diff --git a/.clang-format b/.clang-format new file mode 100644 index 00000000..048ae5f7 --- /dev/null +++ b/.clang-format @@ -0,0 +1,26 @@ +Language: Cpp +MaxEmptyLinesToKeep: 1 +SpaceBeforeParens: ControlStatements +SpaceInEmptyParentheses: false +SpacesInContainerLiterals: true +BasedOnStyle: LLVM +ContinuationIndentWidth: 8 +IndentCaseLabels: false +IndentFunctionDeclarationAfterType: false +IndentWidth: 8 +UseTab: ForContinuationAndIndentation +ColumnLimit: 0 +BreakBeforeBraces: Attach +BreakBeforeTernaryOperators: true +AllowShortIfStatementsOnASingleLine: false +AllowShortCaseLabelsOnASingleLine: true +AllowShortFunctionsOnASingleLine: Inline +AllowShortLoopsOnASingleLine: false +AlignAfterOpenBracket: DontAlign +AlignEscapedNewlines: DontAlign +AlignConsecutiveMacros: true +AlignTrailingComments: false +AlignOperands: false +Cpp11BracedListStyle: false +ForEachMacros: ['rz_list_foreach', 'rz_list_foreach_safe', 'rz_pvector_foreach', 'rz_rbtree_foreach', 'rz_interval_tree_foreach', 'ls_foreach', 'rz_skiplist_foreach', 'graph_foreach_anode'] +SortIncludes: false diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..7fb75358 --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ +__pycache__ +.idea +rz_hexagon.egg-info/ +Hexagon.json diff --git a/.reuse/dep5 b/.reuse/dep5 new file mode 100644 index 00000000..044bce81 --- /dev/null +++ b/.reuse/dep5 @@ -0,0 +1,52 @@ +Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ +Upstream-Name: Rizin +Upstream-Contact: RizinOrg +Source: https://github.com/rizinorg/rizin + +Files: rizin/test/db/** +Copyright: 2021 Rot127 +License: LGPL-3.0-only + +Files: .github/** +Copyright: 2021 RizinOrg +License: LGPL-3.0-only + +Files: .clang-format +Copyright: 2021 RizinOrg +License: LGPL-3.0-only + +Files: .gitattributes +Copyright: 2021 RizinOrg +License: LGPL-3.0-only + +Files: .gitignore +Copyright: 2021 RizinOrg +License: LGPL-3.0-only + +Files: .pylintrc +Copyright: 2021 RizinOrg +License: LGPL-3.0-only + +Files: *.yml +Copyright: 2021 RizinOrg +License: LGPL-3.0-only + +Files: *.md +Copyright: 2021 RizinOrg +License: LGPL-3.0-only + +Files: requirements.txt +Copyright: 2021 Rot127 +License: CC0-1.0 + +Files: optional_requirements.txt +Copyright: 2021 Rot127 +License: CC0-1.0 + +Files: handwritten/*-tests/* +Copyright: 2021 Rot127 +License: LGPL-3.0-only + +Files: test-bins/* +Copyright: 2021 Rot127 +License: LGPL-3.0-only diff --git a/80-n2040-36_b_hexagon_v62_prog_ref_manual.txt b/80-n2040-36_b_hexagon_v62_prog_ref_manual.txt deleted file mode 100644 index 41d381bc..00000000 --- a/80-n2040-36_b_hexagon_v62_prog_ref_manual.txt +++ /dev/null @@ -1,35440 +0,0 @@ -Qualcomm Technologies, Inc. - - - - -Hexagon V62 Programmer's -Reference Manual - -80-N2040-36 B -December 19, 2016 - - - - -Qualcomm Hexagon is a product of Qualcomm Technologies, Inc. Other Qualcomm products referenced herein are products of Qualcomm -Technologies, Inc. or its subsidiaries. - -Qualcomm and Hexagon are trademarks of Qualcomm Incorporated, registered in the United States and other countries. Other product and -brand names may be trademarks or registered trademarks of their respective owners. - -This technical data may be subject to U.S. and international export, re-export, or transfer ("export"80-N2040-36 B) laws. Diversion contrary to -U.S. and international law is strictly prohibited. - - Qualcomm Technologies, Inc. - 5775 Morehouse Drive - San Diego, CA 92121 - U.S.A. - - © 2016 Qualcomm Technologies, Inc. All rights reserved. - Contents - - Figures .............................................................................................................................. 14 - Tables ................................................................................................................................ 15 - - 1 Introduction......................................................................................... 17 - 1.1 Features....................................................................................................................... 17 - 1.2 Functional units .......................................................................................................... 19 - 1.2.1 Memory............................................................................................................. 20 - 1.2.2 Registers............................................................................................................ 20 - 1.2.3 Sequencer.......................................................................................................... 20 - 1.2.4 Execution units.................................................................................................. 20 - 1.2.5 Load/store units................................................................................................. 20 - 1.3 Instruction set ............................................................................................................. 21 - 1.3.1 Addressing modes............................................................................................. 21 - 1.3.2 Scalar operations............................................................................................... 22 - 1.3.3 Vector operations .............................................................................................. 22 - 1.3.4 Floating-point operations .................................................................................. 23 - 1.3.5 Program flow .................................................................................................... 24 - 1.3.6 Instruction packets ............................................................................................ 24 - 1.3.7 Dot-new instructions......................................................................................... 25 - 1.3.8 Compound instructions ..................................................................................... 25 - 1.3.9 Duplex instructions ........................................................................................... 25 - 1.3.10 Instruction classes ........................................................................................... 25 - 1.3.11 Instruction intrinsics........................................................................................ 26 - 1.4 Processor versions ...................................................................................................... 27 - 1.5 Notation ...................................................................................................................... 27 - 1.5.1 Instruction syntax.............................................................................................. 27 - 1.5.2 Register operands.............................................................................................. 28 - 1.5.3 Numeric operands ............................................................................................. 30 - 1.6 Terminology ............................................................................................................... 31 - 1.7 Technical assistance.................................................................................................... 31 - - 2 Registers ............................................................................................. 32 - 2.1 General registers......................................................................................................... 33 - 2.2 Control registers ......................................................................................................... 35 - 2.2.1 Program counter................................................................................................ 37 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 2 - Hexagon V62 Programmer's Reference Manual Contents - - - - 2.2.2 Loop registers.................................................................................................... 38 - 2.2.3 User status register............................................................................................ 38 - 2.2.4 Modifier registers.............................................................................................. 41 - 2.2.5 Predicate registers ............................................................................................. 42 - 2.2.6 Circular start registers ....................................................................................... 43 - 2.2.7 User general pointer register............................................................................. 43 - 2.2.8 Global pointer ................................................................................................... 43 - 2.2.9 Cycle count registers......................................................................................... 44 - 2.2.10 Frame limit register......................................................................................... 44 - 2.2.11 Frame key register........................................................................................... 45 - 2.2.12 Packet count registers ..................................................................................... 45 - 2.2.13 Qtimer registers............................................................................................... 46 - - 3 Instructions ......................................................................................... 47 - 3.1 Instruction syntax ....................................................................................................... 47 - 3.2 Instruction classes....................................................................................................... 49 - 3.3 Instruction packets...................................................................................................... 50 - 3.3.1 Packet execution semantics............................................................................... 51 - 3.3.2 Sequencing semantics ....................................................................................... 51 - 3.3.3 Resource constraints ......................................................................................... 52 - 3.3.4 Grouping constraints......................................................................................... 53 - 3.3.5 Dependency constraints .................................................................................... 54 - 3.3.6 Ordering constraints.......................................................................................... 54 - 3.3.7 Alignment constraints ....................................................................................... 55 - 3.4 Instruction intrinsics ................................................................................................... 55 - 3.5 Compound instructions............................................................................................... 56 - 3.6 Duplex instructions..................................................................................................... 56 - - 4 Data Processing ................................................................................. 57 - 4.1 Data types ................................................................................................................... 58 - 4.1.1 Fixed-point data ................................................................................................ 58 - 4.1.2 Floating-point data ............................................................................................ 58 - 4.1.3 Complex data .................................................................................................... 58 - 4.1.4 Vector data ........................................................................................................ 58 - 4.2 Instruction options ...................................................................................................... 60 - 4.2.1 Fractional scaling .............................................................................................. 60 - 4.2.2 Saturation .......................................................................................................... 60 - 4.2.3 Arithmetic rounding.......................................................................................... 61 - 4.2.4 Convergent rounding ........................................................................................ 61 - 4.2.5 Scaling for divide and square-root.................................................................... 61 - 4.3 XTYPE operations...................................................................................................... 62 - 4.3.1 ALU .................................................................................................................. 62 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 3 - Hexagon V62 Programmer's Reference Manual Contents - - - - 4.3.2 Bit manipulation................................................................................................ 63 - 4.3.3 Complex............................................................................................................ 63 - 4.3.4 Floating point .................................................................................................... 64 - 4.3.5 Multiply............................................................................................................. 65 - 4.3.6 Permute ............................................................................................................. 67 - 4.3.7 Predicate............................................................................................................ 67 - 4.3.8 Shift................................................................................................................... 68 - 4.4 ALU32 operations ...................................................................................................... 69 - 4.5 Vector operations ........................................................................................................ 70 - 4.6 CR operations ............................................................................................................. 72 - 4.7 Compound operations................................................................................................. 72 - 4.8 Special operations....................................................................................................... 72 - 4.8.1 H.264 CABAC processing................................................................................ 73 - 4.8.1.1 CABAC implementation ......................................................................... 74 - 4.8.1.2 Code example .......................................................................................... 75 - 4.8.2 IP internet checksum......................................................................................... 76 - 4.8.2.1 Code example .......................................................................................... 77 - 4.8.3 Software-defined radio...................................................................................... 78 - 4.8.3.1 Rake despreading .................................................................................... 78 - 4.8.3.2 Polynomial operations............................................................................. 79 - - 5 Memory................................................................................................ 81 - 5.1 Memory model ........................................................................................................... 82 - 5.1.1 Address space.................................................................................................... 82 - 5.1.2 Byte order.......................................................................................................... 82 - 5.1.3 Alignment ......................................................................................................... 82 - 5.2 Memory loads............................................................................................................. 83 - 5.3 Memory stores ............................................................................................................ 84 - 5.4 Dual stores .................................................................................................................. 84 - 5.5 New-value stores ........................................................................................................ 85 - 5.6 Mem-ops..................................................................................................................... 85 - 5.7 Addressing modes ...................................................................................................... 86 - 5.7.1 Absolute ............................................................................................................ 86 - 5.7.2 Absolute-set ...................................................................................................... 86 - 5.7.3 Absolute with register offset ............................................................................. 87 - 5.7.4 Global pointer relative ...................................................................................... 87 - 5.7.5 Indirect .............................................................................................................. 88 - 5.7.6 Indirect with offset ............................................................................................ 88 - 5.7.7 Indirect with register offset ............................................................................... 89 - 5.7.8 Indirect with auto-increment immediate........................................................... 89 - 5.7.9 Indirect with auto-increment register................................................................ 89 - 5.7.10 Circular with auto-increment immediate ........................................................ 90 - 5.7.11 Circular with auto-increment register ............................................................. 92 - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 4 - Hexagon V62 Programmer's Reference Manual Contents - - - - 5.7.12 Bit-reversed with auto-increment register ...................................................... 93 - 5.8 Conditional load/stores............................................................................................... 94 - 5.9 Cache memory............................................................................................................ 95 - 5.9.1 Uncached memory ............................................................................................ 96 - 5.9.2 Tightly coupled memory ................................................................................... 96 - 5.9.3 Cache maintenance operations.......................................................................... 97 - 5.9.4 L2 cache operations .......................................................................................... 98 - 5.9.5 Cache line zero.................................................................................................. 98 - 5.9.6 Cache prefetch .................................................................................................. 99 - 5.10 Memory ordering.................................................................................................... 102 - 5.11 Atomic operations................................................................................................... 103 - - 6 Conditional Execution..................................................................... 105 - 6.1 Scalar predicates....................................................................................................... 105 - 6.1.1 Generating scalar predicates ........................................................................... 106 - 6.1.2 Consuming scalar predicates........................................................................... 108 - 6.1.3 Auto-AND predicates ..................................................................................... 109 - 6.1.4 Dot-new predicates ......................................................................................... 110 - 6.1.5 Dependency constraints .................................................................................. 111 - 6.2 Vector predicates ...................................................................................................... 111 - 6.2.1 Vector compare ............................................................................................... 111 - 6.2.2 Vector mux instruction.................................................................................... 113 - 6.2.3 Using vector conditionals ............................................................................... 114 - 6.3 Predicate operations.................................................................................................. 115 - - 7 Program Flow.....................................................................................116 - 7.1 Conditional instructions............................................................................................ 116 - 7.2 Hardware loops......................................................................................................... 117 - 7.2.1 Loop setup....................................................................................................... 118 - 7.2.2 Loop end ......................................................................................................... 119 - 7.2.3 Loop execution................................................................................................ 120 - 7.2.4 Pipelined hardware loops................................................................................ 121 - 7.2.5 Loop restrictions ............................................................................................. 124 - 7.3 Software branches .................................................................................................... 124 - 7.3.1 Jumps .............................................................................................................. 125 - 7.3.2 Calls ................................................................................................................ 125 - 7.3.3 Returns ............................................................................................................ 126 - 7.3.4 Extended branches .......................................................................................... 127 - 7.3.5 Branches to and from packets ......................................................................... 127 - 7.4 Speculative jumps..................................................................................................... 128 - 7.5 Compare jumps......................................................................................................... 129 - 7.5.1 New-value compare jumps ............................................................................. 130 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 5 - Hexagon V62 Programmer's Reference Manual Contents - - - - 7.6 Register transfer jumps............................................................................................. 131 - 7.7 Dual jumps................................................................................................................ 132 - 7.8 Hint indirect jump target .......................................................................................... 133 - 7.9 Pauses ....................................................................................................................... 134 - 7.10 Exceptions .............................................................................................................. 134 - - 8 Software Stack .................................................................................. 138 - 8.1 Stack structure .......................................................................................................... 138 - 8.2 Stack frames ............................................................................................................. 140 - 8.3 Stack protection ........................................................................................................ 140 - 8.3.1 Stack bounds checking.................................................................................... 140 - 8.3.2 Stack smashing protection .............................................................................. 141 - 8.4 Stack registers........................................................................................................... 141 - 8.5 Stack instructions...................................................................................................... 142 - - 9 PMU Events....................................................................................... 143 - 9.1 V62 processor event symbols................................................................................... 144 - - 10 Instruction Encoding...................................................................... 151 - 10.1 Instructions ............................................................................................................. 152 - 10.2 Sub-instructions...................................................................................................... 153 - 10.3 Duplexes ................................................................................................................. 156 - 10.4 Instruction classes................................................................................................... 158 - 10.5 Instruction packets.................................................................................................. 159 - 10.6 Loop packets........................................................................................................... 160 - 10.7 Immediate values.................................................................................................... 161 - 10.8 Scaled immediates .................................................................................................. 161 - 10.9 Constant extenders.................................................................................................. 162 - 10.10 New-value operands ............................................................................................. 165 - 10.11 Instruction mapping .............................................................................................. 166 - - 11 Instruction Set................................................................................. 167 - 11.0.1 Instruction categories .................................................................................... 168 - 11.1 ALU32 .................................................................................................................... 171 - 11.1.1 ALU32/ALU ................................................................................................. 171 - Add ................................................................................................................. 171 - Logical operations .......................................................................................... 173 - Negate............................................................................................................. 175 - Nop ................................................................................................................. 176 - Subtract........................................................................................................... 177 - Sign extend ..................................................................................................... 179 - Transfer immediate......................................................................................... 180 - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 6 - Hexagon V62 Programmer's Reference Manual Contents - - - - Transfer register ............................................................................................. 182 - Vector add halfwords ..................................................................................... 183 - Vector average halfwords............................................................................... 184 - Vector subtract halfwords .............................................................................. 185 - Zero extend..................................................................................................... 187 - 11.1.2 ALU32/PERM .............................................................................................. 188 - Combine words into doubleword ................................................................... 188 - Mux ................................................................................................................ 191 - Shift word by 16 ............................................................................................. 193 - Pack high and low halfwords ......................................................................... 195 - 11.1.3 ALU32/PRED ............................................................................................... 196 - Conditional add .............................................................................................. 196 - Conditional shift halfword.............................................................................. 198 - Conditional combine ...................................................................................... 200 - Conditional logical operations........................................................................ 201 - Conditional subtract ....................................................................................... 203 - Conditional sign extend.................................................................................. 204 - Conditional transfer ........................................................................................ 206 - Conditional zero extend.................................................................................. 207 - Compare ......................................................................................................... 209 - Compare to general register ........................................................................... 211 - 11.2 CR........................................................................................................................... 212 - End loop instructions...................................................................................... 212 - Corner detection acceleration ......................................................................... 214 - Logical reductions on predicates .................................................................... 215 - Looping instructions....................................................................................... 216 - Add to PC ....................................................................................................... 218 - Pipelined loop instructions ............................................................................. 219 - Logical operations on predicates .................................................................... 221 - User control register transfer .......................................................................... 223 - 11.3 JR ............................................................................................................................ 225 - Call subroutine from register.......................................................................... 225 - Hint an indirect jump address......................................................................... 227 - Jump to address from register ........................................................................ 228 - 11.4 J............................................................................................................................... 229 - Call subroutine ............................................................................................... 229 - Compare and jump ......................................................................................... 231 - Jump to address .............................................................................................. 236 - Jump to address conditioned on new predicate .............................................. 238 - Jump to address condition on register value .................................................. 239 - Transfer and jump .......................................................................................... 241 - 11.5 LD........................................................................................................................... 242 - Load doubleword............................................................................................ 242 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 7 - Hexagon V62 Programmer's Reference Manual Contents - - - - Load doubleword conditionally...................................................................... 244 - Load byte ........................................................................................................ 246 - Load byte conditionally.................................................................................. 248 - Load byte into shifted vector.......................................................................... 250 - Load half into shifted vector .......................................................................... 253 - Load halfword ................................................................................................ 256 - Load halfword conditionally .......................................................................... 258 - Load unsigned byte ........................................................................................ 260 - Load unsigned byte conditionally .................................................................. 262 - Load unsigned halfword ................................................................................. 264 - Load unsigned halfword conditionally........................................................... 266 - Load word....................................................................................................... 268 - Load word conditionally ................................................................................ 270 - Deallocate stack frame ................................................................................... 272 - Deallocate frame and return ........................................................................... 274 - Load and unpack bytes to halfwords .............................................................. 276 - 11.6 MEMOP.................................................................................................................. 285 - Operation on memory byte............................................................................. 286 - Operation on memory halfword ..................................................................... 287 - Operation on memory word ........................................................................... 288 - 11.7 NV .......................................................................................................................... 289 - 11.7.1 NV/J .............................................................................................................. 289 - Jump to address condition on new register value........................................... 289 - 11.7.2 NV/ST ........................................................................................................... 293 - Store new-value byte ...................................................................................... 293 - Store new-value byte conditionally ................................................................ 295 - Store new-value halfword .............................................................................. 298 - Store new-value halfword conditionally ........................................................ 300 - Store new-value word..................................................................................... 303 - Store new-value word conditionally............................................................... 305 - 11.8 ST............................................................................................................................ 308 - Store doubleword ........................................................................................... 308 - Store doubleword conditionally ..................................................................... 310 - Store byte........................................................................................................ 312 - Store byte conditionally.................................................................................. 314 - Store halfword ................................................................................................ 317 - Store halfword conditionally .......................................................................... 320 - Store word ...................................................................................................... 324 - Store word conditionally ................................................................................ 326 - Allocate stack frame ....................................................................................... 329 - 11.9 SYSTEM ................................................................................................................ 331 - 11.9.1 SYSTEM/GUEST ......................................................................................... 331 - Guest control register transfer ........................................................................ 331 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 8 - Hexagon V62 Programmer's Reference Manual Contents - - - - 11.9.2 SYSTEM/MONITOR ................................................................................... 333 - Clear interrupt auto disable ............................................................................ 333 - Swap SGP control register ............................................................................. 334 - Cancel pending interrupts............................................................................... 335 - Data cache kill ................................................................................................ 336 - Data cache maintenance monitor instructions................................................ 337 - Read the interrupt mask for a thread .............................................................. 339 - Acquire hardware lock ................................................................................... 340 - Release hardware lock.................................................................................... 341 - Interrupt to thread assignment read ................................................................ 342 - Interrupt to thread assignment write............................................................... 344 - Instruction cache maintenance supervisor operations .................................... 346 - Instruction cache maintenance operations (single-thread) ............................. 347 - L2 cache operations by index ......................................................................... 348 - L2 cache global operations............................................................................. 349 - L2 cache operations by address...................................................................... 351 - L2 tag read/write ............................................................................................ 353 - Load from physical address............................................................................ 355 - Raise NMI on threads..................................................................................... 356 - Resume from wait mode................................................................................. 357 - Return from exception.................................................................................... 358 - Return from exception and unlock TLB......................................................... 359 - Set the interrupt mask for a thread ................................................................. 360 - Set interrupt auto disable ................................................................................ 361 - Start threads .................................................................................................... 362 - Stop threads .................................................................................................... 363 - Software interrupt........................................................................................... 364 - TLB read/write/probe operations ................................................................... 365 - System control register transfer...................................................................... 368 - Transition threads to wait mode ..................................................................... 370 - 11.9.3 SYSTEM/USER............................................................................................ 371 - Load locked .................................................................................................... 371 - Store conditional............................................................................................. 372 - Zero a cache line............................................................................................. 374 - Memory barrier............................................................................................... 375 - Breakpoint ...................................................................................................... 376 - Data cache prefetch ........................................................................................ 377 - Data cache maintenance user operations........................................................ 378 - Instruction cache maintenance user operations .............................................. 379 - Instruction synchronization ............................................................................ 380 - L2 cache prefetch ........................................................................................... 381 - Pause............................................................................................................... 384 - Memory thread synchronization..................................................................... 385 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 9 - Hexagon V62 Programmer's Reference Manual Contents - - - - Send value to ETM trace ................................................................................ 386 - Trap ................................................................................................................ 387 - 11.10 XTYPE ................................................................................................................. 388 - 11.10.1 XTYPE/ALU .............................................................................................. 388 - Absolute value doubleword............................................................................ 388 - Absolute value word....................................................................................... 389 - Add and accumulate ....................................................................................... 390 - Add doublewords ........................................................................................... 392 - Add halfword.................................................................................................. 394 - Add or subtract doublewords with carry ........................................................ 397 - Logical doublewords ...................................................................................... 398 - Logical-logical doublewords .......................................................................... 400 - Logical-logical words..................................................................................... 401 - Maximum words............................................................................................. 403 - Maximum doublewords.................................................................................. 404 - Minimum words ............................................................................................. 405 - Minimum doublewords .................................................................................. 406 - Modulo wrap .................................................................................................. 407 - Negate............................................................................................................. 408 - Round ............................................................................................................. 409 - Subtract doublewords ..................................................................................... 411 - Subtract and accumulate words ...................................................................... 412 - Subtract halfword ........................................................................................... 413 - Sign extend word to doubleword.................................................................... 416 - Vector absolute value halfwords .................................................................... 417 - Vector absolute value words .......................................................................... 418 - Vector absolute difference bytes .................................................................... 419 - Vector absolute difference halfwords............................................................. 420 - Vector absolute difference words................................................................... 421 - Vector add compare and select maximum bytes ............................................ 422 - Vector add compare and select maximum halfwords .................................... 423 - Vector add halfwords ..................................................................................... 425 - Vector add halfwords with saturate and pack to unsigned bytes ................... 427 - Vector reduce add unsigned bytes.................................................................. 428 - Vector reduce add unsigned halfwords .......................................................... 430 - Vector add bytes ............................................................................................. 432 - Vector add words............................................................................................ 433 - Vector average halfwords............................................................................... 434 - Vector average unsigned bytes....................................................................... 436 - Vector average words ..................................................................................... 437 - Vector conditional negate............................................................................... 439 - Vector maximum bytes .................................................................................. 441 - Vector maximum halfwords ........................................................................... 442 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 10 - Hexagon V62 Programmer's Reference Manual Contents - - - - Vector reduce maximum halfwords ............................................................... 443 - Vector reduce maximum words ..................................................................... 445 - Vector maximum words ................................................................................. 447 - Vector minimum bytes ................................................................................... 448 - Vector minimum halfwords............................................................................ 450 - Vector reduce minimum halfwords ................................................................ 451 - Vector reduce minimum words ...................................................................... 453 - Vector minimum words.................................................................................. 455 - Vector sum of absolute differences unsigned bytes ....................................... 456 - Vector subtract halfwords .............................................................................. 458 - Vector subtract bytes ...................................................................................... 460 - Vector subtract words..................................................................................... 461 - 11.10.2 XTYPE/BIT ................................................................................................ 462 - Count leading ................................................................................................. 462 - Count population ............................................................................................ 465 - Count trailing.................................................................................................. 466 - Extract bitfield ................................................................................................ 467 - Insert bitfield .................................................................................................. 470 - Interleave/deinterleave ................................................................................... 472 - Linear feedback-shift iteration ....................................................................... 473 - Masked parity ................................................................................................. 474 - Bit reverse....................................................................................................... 475 - Set/clear/toggle bit.......................................................................................... 476 - Split bitfield .................................................................................................... 478 - Table index ..................................................................................................... 480 - 11.10.3 XTYPE/COMPLEX.................................................................................... 483 - Complex add/sub halfwords ........................................................................... 483 - Complex add/sub words ................................................................................. 486 - Complex multiply........................................................................................... 488 - Complex multiply real or imaginary .............................................................. 491 - Complex multiply with round and pack ......................................................... 493 - Complex multiply 32x16................................................................................ 495 - Vector complex multiply real or imaginary ................................................... 497 - Vector complex conjugate.............................................................................. 500 - Vector complex rotate .................................................................................... 501 - Vector reduce complex multiply real or imaginary........................................ 503 - Vector reduce complex multiply by scalar..................................................... 506 - Vector reduce complex multiply by scalar with round and pack ................... 509 - Vector reduce complex rotate......................................................................... 512 - 11.10.4 XTYPE/FP .................................................................................................. 515 - Floating point addition ................................................................................... 516 - Classify floating-point value .......................................................................... 517 - Compare floating-point value......................................................................... 519 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 11 - Hexagon V62 Programmer's Reference Manual Contents - - - - Convert floating-point value to other format ................................................. 521 - Convert integer to floating-point value .......................................................... 522 - Convert floating-point value to integer .......................................................... 524 - Floating point extreme value assistance ......................................................... 527 - Floating point fused multiply-add .................................................................. 528 - Floating point fused multiply-add with scaling.............................................. 529 - Floating point reciprocal square root approximation ..................................... 530 - Floating point fused multiply-add for library routines ................................... 531 - Create floating-point constant ........................................................................ 533 - Floating point maximum ................................................................................ 534 - Floating point minimum ................................................................................. 535 - Floating point multiply ................................................................................... 536 - Floating point reciprocal approximation ........................................................ 537 - Floating point subtraction............................................................................... 538 - 11.10.5 XTYPE/MPY .............................................................................................. 539 - Multiply and use lower result ......................................................................... 539 - Vector multiply word by signed half (32x16) ................................................ 542 - Vector multiply word by unsigned half (32x16) ............................................ 546 - Multiply signed halfwords.............................................................................. 550 - Multiply unsigned halfwords.......................................................................... 558 - Polynomial multiply words ............................................................................ 563 - Vector reduce multiply word by signed half (32x16) .................................... 565 - Multiply and use upper result ......................................................................... 567 - Multiply and use full result ............................................................................ 570 - Vector dual multiply....................................................................................... 572 - Vector dual multiply with round and pack ..................................................... 575 - Vector reduce multiply bytes ......................................................................... 577 - Vector dual multiply signed by unsigned bytes ............................................. 580 - Vector multiply even halfwords ..................................................................... 582 - Vector multiply halfwords.............................................................................. 584 - Vector multiply halfwords with round and pack............................................ 586 - Vector multiply halfwords, signed by unsigned............................................. 588 - Vector reduce multiply halfwords .................................................................. 590 - Vector multiply bytes ..................................................................................... 592 - Vector polynomial multiply halfwords .......................................................... 594 - 11.10.6 XTYPE/PERM............................................................................................ 597 - CABAC decode bin........................................................................................ 597 - Saturate ........................................................................................................... 599 - Swizzle bytes .................................................................................................. 601 - Vector align .................................................................................................... 602 - Vector round and pack ................................................................................... 604 - Vector saturate and pack ................................................................................ 606 - Vector saturate without pack .......................................................................... 609 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 12 - Hexagon V62 Programmer's Reference Manual Contents - - - - Vector shuffle ................................................................................................. 611 - Vector splat bytes ........................................................................................... 613 - Vector splat halfwords.................................................................................... 614 - Vector splice................................................................................................... 615 - Vector sign extend.......................................................................................... 616 - Vector truncate ............................................................................................... 618 - Vector zero extend.......................................................................................... 621 - 11.10.7 XTYPE/PRED ............................................................................................ 623 - Bounds check ................................................................................................. 623 - Compare byte ................................................................................................. 625 - Compare half .................................................................................................. 627 - Compare doublewords.................................................................................... 629 - Compare bit mask........................................................................................... 630 - Mask generate from predicate ........................................................................ 632 - Check for TLB match..................................................................................... 633 - Predicate transfer ............................................................................................ 634 - Test bit ............................................................................................................ 635 - Vector compare halfwords ............................................................................. 636 - Vector compare bytes for any match.............................................................. 638 - Vector compare bytes ..................................................................................... 639 - Vector compare words.................................................................................... 641 - Viterbi pack even and odd predicate bits ....................................................... 643 - Vector mux ..................................................................................................... 644 - 11.10.8 XTYPE/SHIFT............................................................................................ 645 - Shift by immediate ......................................................................................... 645 - Shift by immediate and accumulate ............................................................... 647 - Shift by immediate and add............................................................................ 650 - Shift by immediate and logical....................................................................... 651 - Shift right by immediate with rounding ......................................................... 655 - Shift left by immediate with saturation .......................................................... 657 - Shift by register .............................................................................................. 658 - Shift by register and accumulate .................................................................... 661 - Shift by register and logical............................................................................ 664 - Shift by register with saturation ..................................................................... 668 - Vector shift halfwords by immediate ............................................................. 670 - Vector arithmetic shift halfwords with round ................................................ 672 - Vector arithmetic shift halfwords with saturate and pack .............................. 674 - Vector shift halfwords by register .................................................................. 676 - Vector shift words by immediate ................................................................... 678 - Vector shift words by register ........................................................................ 680 - Vector shift words with truncate and pack ..................................................... 682 - Instruction Index ............................................................................................................. 684 - Intrinsics Index ............................................................................................................... 699 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 13 - Hexagon V62 Programmer's Reference Manual Figures - - - - Figures - Figure 1-1 Hexagon V62 processor architecture ................................................... 19 - Figure 1-2 Vector instruction example .................................................................. 23 - Figure 1-3 Instruction classes and combinations................................................... 26 - Figure 1-4 Register field symbols.......................................................................... 29 - Figure 2-1 General registers .................................................................................. 33 - Figure 2-2 Control registers................................................................................... 35 - Figure 3-1 Packet grouping combinations ............................................................. 52 - Figure 4-1 Vector byte operation........................................................................... 59 - Figure 4-2 Vector halfword operation ................................................................... 59 - Figure 4-3 Vector word operation ......................................................................... 60 - Figure 4-4 64-bit shift and add/sub/logical............................................................ 68 - Figure 4-5 Vector halfword shift right................................................................... 71 - Figure 5-1 Hexagon processor byte order ............................................................. 82 - Figure 5-2 L2FETCH instruction ........................................................................ 100 - Figure 6-1 Vector byte compare .......................................................................... 112 - Figure 6-2 Vector halfword compare .................................................................. 112 - Figure 6-3 Vector mux instruction ...................................................................... 113 - Figure 8-1 Stack structure.................................................................................... 139 - Figure 10-1 Instruction packet encoding ............................................................... 159 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 14 - Hexagon V62 Programmer's Reference Manual Tables - - - - Tables - Table 1-1 Register symbols .................................................................................. 28 - Table 1-2 Register bit field symbols .................................................................... 29 - Table 1-3 Instruction operands............................................................................. 30 - Table 1-4 Data symbols........................................................................................ 31 - Table 2-1 General register aliases ........................................................................ 34 - Table 2-2 General register pairs ........................................................................... 34 - Table 2-3 Aliased control registers ...................................................................... 36 - Table 2-4 Control register pairs............................................................................ 37 - Table 2-5 Loop registers....................................................................................... 38 - Table 2-6 User status register ............................................................................... 39 - Table 2-7 Modifier registers (indirect auto-increment addressing)...................... 41 - Table 2-8 Modifier registers (circular addressing)............................................... 41 - Table 2-9 Modifier registers (bit-reversed addressing) ........................................ 42 - Table 2-10 Predicate registers ................................................................................ 42 - Table 2-11 Circular start registers .......................................................................... 43 - Table 2-12 User general pointer register ................................................................ 43 - Table 2-13 Global pointer register ......................................................................... 43 - Table 2-14 Cycle count registers............................................................................ 44 - Table 2-15 Frame limit register.............................................................................. 44 - Table 2-16 Frame key register................................................................................ 45 - Table 2-17 Packet count registers .......................................................................... 45 - Table 2-18 Qtimer registers.................................................................................... 46 - Table 3-1 Instruction symbols .............................................................................. 47 - Table 3-2 Instruction classes ................................................................................ 49 - Table 4-1 Single-precision multiply options ........................................................ 66 - Table 4-2 Double precision multiply options....................................................... 66 - Table 4-3 Control register transfer instructions ................................................... 72 - Table 5-1 Memory alignment restrictions ............................................................ 83 - Table 5-2 Load instructions.................................................................................. 83 - Table 5-3 Store instructions.................................................................................. 84 - Table 5-4 Mem-ops .............................................................................................. 85 - Table 5-5 Addressing modes ................................................................................ 86 - Table 5-6 Offset ranges (Global pointer relative) ................................................ 88 - Table 5-7 Offset ranges (Indirect with offset) ...................................................... 88 - Table 5-8 Increment ranges (Indirect with auto-inc immediate).......................... 89 - Table 5-9 Increment ranges (Circular with auto-inc immediate) ......................... 91 - Table 5-10 Increment ranges (Circular with auto-inc register) .............................. 92 - Table 5-11 Addressing modes (Conditional load/store)......................................... 94 - Table 5-12 Conditional offset ranges (Indirect with offset) ................................... 95 - Table 5-13 Hexagon processor cache size ............................................................. 96 - Table 5-14 Cache instructions (User-level)............................................................ 97 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 15 - Hexagon V62 Programmer's Reference Manual Tables - - - - Table 5-15 Memory ordering instructions............................................................ 102 - Table 5-16 Atomic instructions ............................................................................ 103 - Table 6-1 Scalar predicate-generating instructions ............................................ 106 - Table 6-2 Vector mux instruction ....................................................................... 113 - Table 6-3 Predicate register instructions ............................................................ 115 - Table 7-1 Loop instructions ............................................................................... 118 - Table 7-2 Software pipelined loop ..................................................................... 122 - Table 7-3 Software pipelined loop (using spNloop0) ........................................ 123 - Table 7-4 Software branch instructions.............................................................. 124 - Table 7-5 Jump instructions ............................................................................... 125 - Table 7-6 Call instructions ................................................................................. 125 - Table 7-7 Return instructions ............................................................................. 126 - Table 7-8 Speculative jump instructions ............................................................ 128 - Table 7-9 Compare jump instructions ................................................................ 130 - Table 7-10 New-value compare jump instructions .............................................. 131 - Table 7-11 Register transfer jump instructions .................................................... 132 - Table 7-12 Dual jump instructions ....................................................................... 132 - Table 7-13 Jump hint instruction.......................................................................... 133 - Table 7-14 Pause instruction ................................................................................ 134 - Table 7-15 V60/61 exceptions ............................................................................. 135 - Table 8-1 Stack registers .................................................................................... 141 - Table 8-2 Stack instructions ............................................................................... 142 - Table 9-1 V62 processor event symbols ............................................................ 144 - Table 10-1 Instruction fields ................................................................................ 152 - Table 10-2 Sub-instructions ................................................................................. 153 - Table 10-3 Sub-instruction registers .................................................................... 155 - Table 10-4 Duplex instruction.............................................................................. 156 - Table 10-5 Duplex ICLASS field......................................................................... 156 - Table 10-6 Instruction class encoding.................................................................. 158 - Table 10-7 Loop packet encoding ........................................................................ 160 - Table 10-8 Scaled immediate encoding (indirect offsets) .................................... 161 - Table 10-9 Constant extender encoding ............................................................... 162 - Table 10-10 Constant extender instructions ........................................................... 163 - Table 10-11 Instruction mapping ........................................................................... 166 - Table 11-1 Instruction syntax symbols ................................................................ 169 - Table 11-2 Instruction operand symbols .............................................................. 169 - Table 11-3 Instruction behavior symbols ............................................................. 170 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 16 - 1 Introduction - - - The Qualcomm Hexagon™ processor is a general-purpose digital signal processor - designed for high performance and low power across a wide variety of multimedia and - modem applications. V62 is a member of the sixth version of the Hexagon processor - architecture. - - - 1.1 Features - ■ Memory - Program code and data are stored in a unified 32-bit address space. The load/store - architecture supports a complete set of addressing modes for both compiler code - generation and DSP application programming. - ■ Registers - Thirty two 32-bit general purpose registers can be accessed as single registers or - as 64-bit register pairs. The general registers hold all data including scalar, - pointer, and packed vector data. - ■ Data types - Instructions can perform a wide variety of operations on fixed-point or floating- - point data. The fixed-point operations support scalar and vector data in a variety - of sizes. The floating-point operations support single-precision data. - ■ Parallel execution - Instructions can be grouped into very long instruction word (VLIW) packets for - parallel execution, with each packet containing from one to four instructions. - Vector instructions operate on single instruction multiple data (SIMD) vectors. - ■ Program flow - Nestable zero-overhead hardware loops are supported. Conditional/unconditional - jumps and subroutine calls support both PC-relative and register indirect - addressing. Two program flow instructions can be grouped into one packet. - ■ Instruction pipeline - Pipeline hazards are resolved by the hardware: instruction scheduling is not - constrained by pipeline restrictions. - ■ Code compression - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 17 - Hexagon V62 Programmer's Reference Manual Introduction - - - - Compound instructions merge certain common operation sequences (add- - accumulate, shift-add, etc.) into a single instruction. Duplex encodings express - two parallel instructions in a single 32-bit word. - ■ Cache memory - Memory accesses can be cached or uncached. Separate L1 instruction and data - caches exist for program code and data. A unified L2 cache can be partly or - wholly configured as tightly-coupled memory (TCM). - ■ Virtual memory - Memory is addressed virtually, with virtual-to-physical memory mapping handled - by a resident OS. Virtual memory supports the implementation of memory - management and memory protection in a hardware-independent manner. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 18 - Hexagon V62 Programmer's Reference Manual Introduction - - - - 1.2 Functional units - Figure 1-1 shows the major functional units of the Hexagon V62 processor architecture: - - ■ Memory and registers - ■ Instruction sequencer - ■ Execution units - ■ Load/store units - - - Memory - (unified address space) - - Load/ Load/ - 64 - 4x32 bit Store 64 Store - 128 Instructions S3: X Unit - XTYPE Instructions - ALU32 Instructions - J Instructions - Sequencer CR Instructions - - Packets of - 1-4 instructions - S2: X Unit - XTYPE Instructions - ALU32 Instructions - J Instructions - JR Instructions - General - Control Registers - Hardware Loop Regs - Registers - Modifier Registers S1: Load/Store - Status Register Unit R0-R31 - Program Counter LD Instructions - Predicate Registers ST Instructions - User General Pointer ALU32 Instructions - Global Pointer - Circular Start Registers - - S0: Load/Store - Unit - LD Instructions - ST Instructions - ALU32 Instructions - MEMOP Instructions - NV Instructions - SYSTEM Instructions - - - - - Figure 1-1 Hexagon V62 processor architecture - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 19 - Hexagon V62 Programmer's Reference Manual Introduction - - - - 1.2.1 Memory - The Hexagon processor features a unified byte-addressable memory. This memory has a - single 32-bit virtual address space which holds both instructions and data. It operates in - little-endian mode. - - - 1.2.2 Registers - The Hexagon processor has two sets of registers: general registers and control registers. - - The general registers include thirty-two 32-bit registers (named R0 through R31) which - can be accessed either as single registers or as aligned 64-bit register pairs. The general - registers are used to contain all pointer, scalar, vector, and accumulator data. - - The control registers include special-purpose registers such as program counter, status - register, loop registers, etc. - - - 1.2.3 Sequencer - The instruction sequencer processes packets of one to four instructions in each cycle. If a - packet contains more than one instruction, the instructions are executed in parallel. - - The instruction combinations allowed in a packet are limited to the instruction types that - can be executed in parallel in the four execution units (as shown in Figure 1-1). - - - 1.2.4 Execution units - The dual execution units are identical: each includes a 64-bit shifter and a vector - multiply/accumulate unit with four 16x16 multipliers to support both scalar and vector - instructions. - - These units also perform 32- and 64-bit ALU instructions, and jump and loop instructions. - - NOTE Each execution unit supports floating-point instructions. - - - 1.2.5 Load/store units - The two load/store units can operate on signed or unsigned bytes, halfwords (16-bit), - words (32-bit), or double words (64-bit). - - To increase the number of instruction combinations allowed in packets, the load units also - support 32-bit ALU instructions. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 20 - Hexagon V62 Programmer's Reference Manual Introduction - - - - 1.3 Instruction set - In order for the Hexagon processor to achieve large amounts of work per cycle, the - instruction set was designed with the following properties: - - ■ Static grouping (VLIW) architecture - ■ Static fusing of simple dependent instructions - ■ Extensive compound instructions - ■ A large set of SIMD and application-specific instructions - - To support efficient compilation, the instruction set is designed to be orthogonal with - respect to registers, addressing modes, and load/store access size. - - - 1.3.1 Addressing modes - The Hexagon processor supports the following memory addressing modes: - ■ 32-bit absolute - - ■ 32-bit absolute-set - ■ Absolute with register offset - ■ Global pointer relative - ■ Indirect - ■ Indirect with offset - ■ Indirect with register offset - ■ Indirect with auto-increment (immediate or register) - ■ Circular with auto-increment (immediate or register) - ■ Bit-reversed with auto-increment register - - For example: - R2 = memw(##myvariable) - R2 = memw(R3=##myvariable) - R2 = memw(R4<<#3+##myvariable) - R2 = memw(GP+#200) - R2 = memw(R1) - R2 = memw(R3+#100) - R2 = memw(R3+R4<<#2) - R2 = memw(R3++#4) - R2 = memw(R0++M1) - R0 = memw(R2++#8:circ(M0)) - R0 = memw(R2++I:circ(M0)) - R2 = memw(R0++M1:brev) - - Auto-increment with register addressing uses one of the two dedicated address-modify - registers M0 and M1 (which are part of the control registers). - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 21 - Hexagon V62 Programmer's Reference Manual Introduction - - - - NOTE Atomic memory operations (load locked/store conditional) are supported to - implement multi-thread synchronization. - - - 1.3.2 Scalar operations - The Hexagon processor includes the following scalar operations on fixed-point data: - ■ Multiplication of 16-bit, 32-bit, and complex data - - ■ Addition and subtraction of 16-, 32-, and 64-bit data (with and without saturation) - ■ Logical operations on 32- and 64-bit data (AND, OR, XOR, NOT) - ■ Shifts on 32- and 64-bit data (arithmetic and logical) - ■ Min/max, negation, absolute value, parity, norm, swizzle - ■ Compares of 8-, 16-, 32-, and 64-bit data - ■ Sign and zero extension (8- and 16- to 32-bit, 32- to 64-bit) - ■ Bit manipulation - ■ Predicate operations - - - 1.3.3 Vector operations - The Hexagon processor includes the following vector operations on fixed-point data: - ■ Multiplication (halfwords, word by half, vector reduce, dual multiply) - - ■ Addition and subtraction of word and halfword data - ■ Shifts on word and halfword data (arithmetic and logical) - ■ Min/max, average, negative average, absolute difference, absolute value - ■ Compares of word, halfword, and byte data - ■ Reduce, sum of absolute differences on unsigned bytes - ■ Special-purpose data arrangement (such as pack, splat, shuffle, align, saturate, - splice, truncate, complex conjugate, complex rotate, zero extend) - - NOTE Certain vector operations support automatic scaling, saturation, and rounding. - - For example, the following instruction performs a vector operation: - R1:0 += vrmpyh(R3:2,R5:4) - - It is defined to perform the following operations in one cycle: - R1:0 += ((R2.L * R4.L) + - (R2.H * R4.H) + - (R3.L * R5.L) + - (R3.H * R5.H) - ) - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 22 - Hexagon V62 Programmer's Reference Manual Introduction - - - - Figure 1-2 shows a schematic of this instruction type. - - - Rss - - - Rtt - - - - - * * * * - 32 32 - 32 32 - - - - - Add - - 64 - - Rdd - 64-bit Register Pair - - Figure 1-2 Vector instruction example - - - 1.3.4 Floating-point operations - The Hexagon processor includes the following operations on floating-point data: - ■ Addition and subtraction - - ■ Multiplication (with optional scaling) - ■ Min/max/compare - ■ Reciprocal/square root approximation - ■ Format conversion - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 23 - Hexagon V62 Programmer's Reference Manual Introduction - - - - 1.3.5 Program flow - The Hexagon processor supports zero-overhead hardware loops. For example: - loop0(start,#3) // loop 3 times - start: - { R0 = mpyi(R0,R0) } :endloop0 - - The loop instructions support nestable loops, with few restrictions on their use. - - Software branches use a predicated branch mechanism. Explicit compare instructions - generate a predicate bit, which is then tested by conditional branch instructions. For - example: - P1 = cmp.eq(R2, R3) - if (P1) jump end - - Jumps and subroutine calls can be conditional or unconditional, and support both PC- - relative and register indirect addressing modes. For example: - jump end - jumpr R1 - call function - callr R2 - - The subroutine call instructions store the return address in register R31. Subroutine - returns are performed using a jump indirect instruction through this register. For example: - jumpr R31 // subroutine return - - - - 1.3.6 Instruction packets - Sequences of instructions can be explicitly grouped into packets for parallel execution. - For example: - { - R8 = memh(R3++#2) - R12 = memw(R1++#4) - R = mpy(R10,R6):<<1:sat - R7 = add(R9,#2) - } - - Brace characters are used to delimit the start and end of an instruction packet. - - Packets can be from one to four instructions long. Packets of varying length can be freely - mixed in a program. - - Packets have various restrictions on the allowable instruction combinations. The primary - restriction is determined by the instruction class of the instructions in a packet. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 24 - Hexagon V62 Programmer's Reference Manual Introduction - - - - 1.3.7 Dot-new instructions - In many cases, a predicate or general register can be both generated and used in the same - instruction packet. This feature is expressed in assembly language by appending the suffix - “.new” to the specified register. For example: - { - P0 = cmp.eq(R2,#4) - if (P0.new) R3 = memw(R4) - if (!P0.new) R5 = #5 - } - - { - R2 = memh(R4+#8) - memw(R5) = R2.new - } - - - - 1.3.8 Compound instructions - Certain common operation pairs (add-accumulate, shift-add, deallocframe-return, etc.) can - be performed by compound instructions. Using compound instructions reduces code size - and improves code performance. - - - 1.3.9 Duplex instructions - A subset of the most common instructions (load, store, branch, ALU) can be packed - together in pairs into single 32-bit instructions known as duplex instructions. Duplex - instructions reduce code size. - - - 1.3.10 Instruction classes - The instructions are assigned to specific instruction classes. Classes are important for two - reasons: - ■ Only certain combinations of instructions can be written in parallel (as shown in - Figure 1-1), and the allowable combinations are specified by instruction class. - ■ Instruction classes logically correspond with instruction types, so they serve as - mnemonics for looking up specific instructions. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 25 - Hexagon V62 Programmer's Reference Manual Introduction - - - - Figure 1-3 presents an overview of the instruction classes and how they can be grouped - together. - - - Slot 0 Slot 1 Slot 2 Slot 3 - LD Instructions LD Instructions - XTYPE Instructions XTYPE Instructions - ST Instructions ST Instructions - ALU32 Instructions ALU32 Instructions - ALU32 Instructions ALU32 Instructions - J Instructions J Instructions - MEMOP Instructions Some J Instructions - JR Instructions CR Instructions - NV Instructions - SYSTEM Instructions - Some J Instructions - - - - XTYPE Instructions (32/64 bit) J Instructions - Arithmetic, Logical, Bit Manipulation Jump/Call PC-relative - Multiply (Integer, Fractional, Complex) - Floating-point Operations - JR Instructions - Permute / Vector Permute Operations - Predicate Operations Jump/Call Register - Shift / Shift with Add/Sub/Logical - Vector Byte ALU LD Instructions - Vector Halfword (ALU, Shift, Multiply) Loads (8/16/32/64 bit) - Vector Word (ALU, Shift) Deallocframe - - ALU32 Instructions ST Instructions - Arithmetic / Logical (32 bit) Stores (8/16/32/64 bit) - Vector Halfword Allocframe - - CR Instructions MEMOP Instructions - Control-Register Transfers Operation on memory (8/16/32 bit) - Hardware Loop Setup - Predicate Logicals & Reductions SYSTEM Instructions - Prefetch - NV Instructions Cache Maintenance - New-value Jumps Bus Operations - New-value Stores - - Figure 1-3 Instruction classes and combinations - - - 1.3.11 Instruction intrinsics - To support efficient coding of the time-critical sections of a program (without resorting to - assembly language), the C compilers support intrinsics which are used to directly express - Hexagon processor instructions from within C code. For example: - int main() - { - long long v1 = 0xFFFF0000FFFF0000; - long long v2 = 0x0000FFFF0000FFFF; - long long result; - - // find the minimum for each half-word in 64-bit vector - result = Q6_P_vminh_PP(v1,v2); - } - - Intrinsics are defined for most of the Hexagon processor instructions. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 26 - Hexagon V62 Programmer's Reference Manual Introduction - - - - 1.4 Processor versions - The V62 Hexagon processor is a member of the sixth version of the Hexagon processor - architecture. While remaining functionally equivalent to V51 at the user level, V62 adopts - a new micro-architecture, which provides higher performance for modem and audio - applications. - - V62 extends the V61 architecture with the following features: - - ■ Dual-cluster micro-architecture - ■ Simultaneous multi-threading (SMT) - - For more information on V61, see the Hexagon V60/V61 Programmer's Reference - Manual. - - - 1.5 Notation - This section presents the notational conventions used in this document to describe - Hexagon processor instructions: - ■ Instruction syntax - - ■ Register operands - ■ Numeric operands - - NOTE The notation described here does not appear in actual assembly language - instructions. It is used only to specify the instruction syntax and behavior. - - - 1.5.1 Instruction syntax - The following notation is used to describe the syntax of instructions: - ■ Monospaced font is used for instructions - ■ Square brackets enclose optional items (e.g., [:sat], means that saturation is - optional) - ■ Braces indicate a choice of items (e.g., {Rs,#s16}, means that either Rs or a - signed 16-bit immediate can be used) - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 27 - Hexagon V62 Programmer's Reference Manual Introduction - - - - 1.5.2 Register operands - The following notation describes register operands in the syntax and behavior of - instructions: - Rds[.elst] - - The ds field indicates the register operand type and bit size (as defined in Table 1-1). - - Table 1-1 Register symbols - Symbol Operand Type Size (in Bits) - d Destination 32 - dd 64 - s First source 32 - ss 64 - t Second source 32 - tt 64 - u Third source 32 - uu 64 - x Source and destination 32 - xx 64 - - - Examples of ds field (describing instruction syntax): - Rd = neg(Rs) // Rd -> 32-bit dest, Rs 32-bit source - Rd = xor(Rs,Rt) // Rt -> 32-bit second source - Rx = insert(Rs,Rtt) // Rx -> both source and dest - - Examples of ds field (describing instruction behavior): - Rdd = Rss + Rtt // Rdd, Rss, Rtt -> 64-bit registers - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 28 - Hexagon V62 Programmer's Reference Manual Introduction - - - - The optional elst field (short for “element size and type”) specifies parts of a register when - the register is used as a vector. It can specify the following values: - ■ A signed or unsigned byte, halfword, or word within the register (as defined in - Figure 1-4) - ■ A bit-field within the register (as defined in Table 1-2) - - - Rds.elst - s, t, u = 32-bit source register - d = 32-bit register destination - x = 32-bit register source/destination - ss, tt, uu = 64-bit source register pair - dd = 64-bit register destination - xx = 64-bit register source/destination - Rds.elst - - .b[7] .b[6] .b[5] .b[4] .b[3] .b[2] .b[1] .b[0] Signed Bytes - - .ub[7] .ub[6] .ub[5] .ub[4] .ub[3] .ub[2] .ub[1] .ub[0] Unsigned Bytes - - .h[3] .h[2] .h[1] .h[0] Signed Halfwords - - .uh[3] .uh[2] .uh[1] .uh[0] Unsigned Halfwords - - .w[1] .w[0] Signed Words - - .uw[1] .uw[0] Unsigned Words - - - Figure 1-4 Register field symbols - - Table 1-2 Register bit field symbols - Symbol Meaning - .sN Bits [N-1:0] are treated as a N-bit signed number. - For example, R0.s16 means that the least significant 16-bits of R0 - are treated as a 16-bit signed number. - .uN Bits [N-1:0] are treated as a N-bit unsigned number. - .H The most-significant 16 bits of a 32-bit register. - .L The least-significant 16 bits of a 32-bit register. - - - Examples of elst field: - EA = Rt.h[1] // .h[1] -> bit field 31:16 in Rt - Pd = (Rss.u64 > Rtt.u64) // .u64 -> unsigned 64-bit value - Rd = mpyu(Rs.L,Rt.H) // .L/.H -> low/high 16-bit fields - - NOTE The control and predicate registers use the same notation as the general - registers, but are written as Cx and Px (respectively) instead of Rx. - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 29 - Hexagon V62 Programmer's Reference Manual Introduction - - - - 1.5.3 Numeric operands - Table 1-3 lists the notation used to describe numeric operands in the syntax and behavior - of instructions: - - Table 1-3 Instruction operands - Symbol Meaning Min Max - #uN Unsigned N-bit immediate value 0 2N-1 - #sN Signed N-bit immediate value -2N-1 2N-1-1 - #mN Signed N-bit immediate value -(2N-1-1) 2N-1-1 - #uN:S Unsigned N-bit immediate value representing 0 (2N-1)  2S - integral multiples of 2S in specified range - #sN:S Signed N-bit immediate value representing (-2N-1)  2S (2N-1-1)  2S - integral multiples of 2S in specified range - #rN:S Same as #sN:S, but value is offset from PC (-2N-1)  2S (2N-1-1)  2S - of current packet - ## Same as #, but associated value (u,s,m,r) – – - is 32 bits - usatN Saturate value to unsigned N-bit number 0 2N-1 - satN Saturate value to signed N-bit number -2N-1 2N-1-1 - - #uN, #sN, and #mN specify immediate operands in instructions. The # symbol appears in - the actual instruction to indicate the immediate operand. - - #rN specifies loop and branch destinations in instructions. In this case the # symbol does - not appear in the actual instruction; instead, the entire #rN symbol (including its :S suffix) - is expressed as a loop or branch symbol whose numeric value is determined by the - assembler and linker. For example: - call my_proc // instruction example - - The :S suffix indicates that the S least-significant bits in a value are implied zero bits and - therefore not encoded in the instruction. The implied zero bits are called scale bits. - - For example, #s4:2 denotes a signed immediate operand represented by four bits encoded - in the instruction, and two scale bits. The possible values for this operand are -32, -28, -24, - -20, -16, -12, -8, -4, 0, 4, 8, 12, 16, 20, 24, and 28. - - ## specifies a 32-bit immediate operand in an instruction (including a loop or branch - destination). The ## symbol appears in the actual instruction to indicate the operand. - - Examples of operand symbols: - Rd = add(Rs,#s16) // #s16 -> signed 16-bit imm value - Rd = memw(Rs++#s4:2) // #s4:2 -> scaled signed 4-bit imm value - call #r22:2 // #r22:2 -> scaled 22-bit PC-rel addr value - Rd = ##u32 // ##u32 -> unsigned 32-bit imm value - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 30 - Hexagon V62 Programmer's Reference Manual Introduction - - - - NOTE When an instruction contains more than one immediate operand, the operand - symbols are specified in upper and lower case (e.g., #uN and #UN) to indicate - where they appear in the instruction encodings - - - 1.6 Terminology - Table 1-4 lists the symbols used in Hexagon processor instruction names to specify the - supported data types. - - Table 1-4 Data symbols - Size Symbol Type - 8-bit B Byte - 8-bit UB Unsigned Byte - 16-bit H Half word - 16-bit UH Unsigned Half word - 32-bit W Word - 32-bit UW Unsigned Word - 64-bit D Double word - - - - - 1.7 Technical assistance - For assistance or clarification on information in this document, submit a case to - Qualcomm Technologies at https://support.cdmatech.com. - - If you do not have access to the CDMATech Support website, register for access or send - email to support.cdmatech@qti.qualcomm.com. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 31 - 2 Registers - - - This chapter describes the Hexagon processor registers: - -  General registers -  Control registers - - General registers are used for all general-purpose computation including address - generation and scalar and vector arithmetic. - - Control registers support special-purpose processor features such as hardware loops and - predicates. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 32 - Hexagon V62 Programmer's Reference Manual Registers - - - - 2.1 General registers - The Hexagon processor has thirty-two 32-bit general-purpose registers (named R0 through - R31). These registers are used to store operands in virtually all the instructions: - -  Memory addresses for load/store instructions -  Data operands for arithmetic/logic instructions -  Vector operands for vector instructions - - For example: - R1 = memh(R0) // Load from address R0 - R4 = add(R2,R3) // Add - R28 = vaddh(R11,R10) // Vector add halfword - - Figure 2-1 shows the general registers. - - - R3 R2 R1 R0 - - - - R3:2 R1:0 - - .. - . - R31 R30 R29 R28 - - - - R31:30 R29:28 - - Figure 2-1 General registers - - Aliased registers - - Three of the general registers – R29 through R31 – are used to support subroutines - (Section 7.3.2) and the software stack (Chapter 8). These registers are modified implicitly - by the subroutine and stack instructions. They have symbol aliases which are used to - indicate when these registers are being accessed as subroutine and stack registers. - - For example: - SP = add(SP, #-8) // SP is alias of R29 - allocframe // Modifies SP (R29) and FP (R30) - call init // Modifies LR (R31) - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 33 - Hexagon V62 Programmer's Reference Manual Registers - - - - Table 2-1 defines the aliased general registers. - - Table 2-1 General register aliases - Register Alias Name Description - R29 SP Stack pointer Points to topmost element of stack in memory. - R30 FP Frame pointer Points to current procedure frame on stack. - - Used by external debuggers to examine the stack - and determine call sequence, parameters, local - variables, etc. - R31 LR Link register Stores return address of a subroutine call. - - - Register pairs - - The general registers can be specified as register pairs which represent a single 64-bit - register. For example: - R1:0 = memd(R3) // Load doubleword - R7:6 = valignb(R9:8,R7:6, #2) // Vector align - - NOTE The first register in a register pair must always be odd-numbered, and the - second must be the next lower register. - - Table 2-2 lists the general register pairs. - - Table 2-2 General register pairs - Register Register Pair - R0 R1:0 - R1 - R2 R3:2 - R3 - R4 R5:4 - R5 - R6 R7:6 - R7 - … - R24 R25:24 - R25 - R26 R27:26 - R27 - R28 R29:28 - R29 (SP) - R30 (FP) R31:30 (LR:FP) - R31 (LR) - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 34 - Hexagon V62 Programmer's Reference Manual Registers - - - - 2.2 Control registers - The Hexagon processor includes a set of 32-bit control registers which provide access to - processor features such as the program counter, hardware loops, and vector predicates. - - Unlike general registers, control registers can be used as instruction operands only in the - following cases: - -  Instructions that require a specific control register as an operand -  Register transfer instructions - - For example: - R2 = memw(R0++M1) // Auto-increment addressing mode (M1) - R9 = PC // Get program counter (PC) - LC1 = R3 // Set hardware loop count (LC1) - - NOTE When a control register is used in a register transfer, the other operand must - be a general register. - - Figure 2-2 shows the control registers. - - - LC0 SA0 UPCYCLELO - Loop Registers Cycle Count Registers - LC1 SA1 UPCYCLEHI - - - PC Program Counter FRAMELIMIT Stack Bounds Register - - - USR User Status Register FRAMEKEY Stack Smash Register - - - M0 PKTCOUNTLO - Modifier Registers Packet Count Registers - M1 PKTCOUNTHI - - - P3:0 Predicate Registers UTIMERLO - Qtimer Registers - UGP User General Pointer UTIMERHI - - - GP Global Pointer - - - CS0 = V61 or greater - Circular Start Registers - CS1 - - - - Figure 2-2 Control registers - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 35 - Hexagon V62 Programmer's Reference Manual Registers - - - - Aliased registers - - The control registers have numeric aliases (C0 through C31). - - Table 2-3 lists the aliased control registers. - - - Table 2-3 Aliased control registers - Register Alias Name - SA0 C0 Loop start address register 0 - LC0 C1 Loop count register 0 - SA1 C2 Loop start address register 1 - LC1 C3 Loop count register 1 - P3:0 C4 Predicate registers 3:0 - reserved C5 – - M0 C6 Modifier register 0 - M1 C7 Modifier register 1 - USR C8 User status register - PC C9 Program counter - UGP C10 User general pointer - GP C11 Global pointer - CS0 C12 Circular start register 0 - CS1 C13 Circular start register 1 - UPCYCLELO C14 Cycle count register (low) - UPCYCLEHI C15 Cycle count register (high) - UPCYCLE C15:14 Cycle count register - FRAMELIMIT C16 Frame limit register - FRAMEKEY C17 Frame key register - PKTCOUNTLO C18 Packet count register (low) - PKTCOUNTHI C19 Packet count register (high) - PKTCOUNT C19:18 Packet count register - reserved C20-29 – - UTIMERLO C30 Qtimer register (low) - UTIMERHI C31 Qtimer register (high) - UTIMER C31:30 Qtimer register - - - NOTE The control register numbers (0-31) are used to specify the control registers in - instruction encodings (Chapter 10). - - The registers shown in gray are supported only in processor versions V61 or - greater. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 36 - Hexagon V62 Programmer's Reference Manual Registers - - - - Register pairs - - The control registers can be specified as register pairs which represent a single 64-bit - register. Control registers specified as pairs must use their numeric aliases. For example: - C1:0 = R5:4 // C1:0 specifies the LC0/SA0 register pair - - NOTE The first register in a control register pair must always be odd-numbered, and - the second must be the next lower register. - - Table 2-4 lists the control register pairs. - - - Table 2-4 Control register pairs - Register Register Pair - C0 C1:0 - C1 - C2 C3:2 - C3 - C4 C5:4 - C5 - C6 C7:6 - C7 - … - C30 C31:30 - C31 - - - - 2.2.1 Program counter - The Program Counter (PC) register points to the next instruction packet to execute - (Section 3.3). It is modified implicitly by instruction execution, but can be read directly. - For example: - R7 = PC // Get program counter - - NOTE The PC register is read-only: writing to it has no effect. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 37 - Hexagon V62 Programmer's Reference Manual Registers - - - - 2.2.2 Loop registers - The Hexagon processor includes two sets of loop registers to support nested hardware - loops (Section 7.2). Each hardware loop is implemented with a pair of registers containing - the loop count and loop start address. The loop registers are modified implicitly by the - loop instruction, but can also be accessed directly. For example: - loop0(start, R4) // Modifies LC0 and SA0 (LC0=R4, SA0=&start) - LC1 = R22 // Set loop1 count - R9 = SA1 // Get loop1 start address - - Table 2-5 defines the loop registers. - - Table 2-5 Loop registers - Register Name Description - LC0, LC1 Loop count Number of loop iterations to execute. - - SA0, SA1 Loop start address Address of first instruction in loop. - - - - 2.2.3 User status register - The user status register (USR) stores processor status and control bits that are accessible - by user programs. The status bits contain the status results of certain instructions, while - the control bits contain user-settable processor modes for hardware prefetching. For - example: - R9:8 = vaddw(R9:8, R3:2):sat // Vector add words - R6 = USR // Get saturation status - - USR stores the following status and control values: -  Cache prefetch enable (Section 5.9.6) -  Cache prefetch status (Section 5.9.6) -  Floating point modes (Section 4.3.4) -  Floating point status (Section 4.3.4) -  Hardware loop configuration (Section 7.2) -  Sticky saturation overflow (Section 4.2.2) - - NOTE A user control register transfer to USR cannot be grouped in an instruction - packet with a floating point instruction (Section 4.3.4). - - Whenever a transfer to USR changes the Enable trap bits [29:25], an isync - instruction (Section 5.10) must be executed before the new exception - programming can take effect. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 38 - Hexagon V62 Programmer's Reference Manual Registers - - - - Table 2-6 defines the user status register. - - Table 2-6 User status register - Name R/W Bits Field Description - USR 32 User Status Register - R 31 PFA L2 Prefetch Active. - 1: l2fetch instruction in progress - 0: l2fetch finished (or inactive) - Set when non-blocking l2fetch instruction is prefetching - requested data. - Remains set until l2fetch prefetch operation is completed - (or not active). - R 30 reserved Return 0 if read. - Reserved for future expansion. To remain compatible - with future processor versions, software should always - write this field with the same value read from the field. - R/W 29 FPINEE Enable trap on IEEE Inexact. - R/W 28 FPUNFE Enable trap on IEEE Underflow. - R/W 27 FPOVFE Enable trap on IEEE Overflow. - R/W 26 FPDBZE Enable trap on IEEE Divide-By-Zero. - R/W 25 FPINVE Enable trap on IEEE Invalid. - R 24 reserved Reserved - R/W 23:22 FPRND Rounding Mode for Floating-Point Instructions. - 00: Round to nearest, ties to even (default) - 01: Toward zero - 10: Downward (toward negative infinity) - 11: Upward (toward positive infinity) - R 21:20 reserved Return 0 if read. - Reserved for future expansion. To remain compatible - with future processor versions, software should always - write this field with the same value read from the field. - R 19:18 reserved Reserved - R 17 reserved Return 0 if read. - Reserved for future expansion. To remain compatible - with future processor versions, software should always - write this field with the same value read from the field. - R/W 16:15 HFI L1 Instruction Prefetch. - 00: Disable - 01: Enable (1 line) - 10: Enable (2 lines) - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 39 - Hexagon V62 Programmer's Reference Manual Registers - - - - Table 2-6 User status register (Continued) - Name R/W Bits Field Description - R/W 14:13 HFD L1 Data Cache Prefetch. - Four levels are defined from disabled to Aggressive. It is - implementation-defined how these levels should be - interpreted. - 00: Disable - 01: Conservative - 10: Moderate - 11: Aggressive - R/W 12 PCMME Enable packet counting in Monitor mode. - R/W 11 PCGME Enable packet counting in Guest mode. - R/W 10 PCUME Enable packet counting in User mode. - R/W 9:8 LPCFGE Hardware Loop Configuration. - Number of loop iterations (0-3) remaining before pipeline - predicate should be set. - R 7:6 reserved Return 0 if read. - Reserved for future expansion. To remain compatible - with future processor versions, software should always - write this field with the same value read from the field. - R/W 5 FPINPF Floating-point IEEE Inexact Sticky Flag. - R/W 4 FPUNFF Floating-point IEEE Underflow Sticky Flag. - R/W 3 FPOVFF Floating-point IEEE Overflow Sticky Flag. - R/W 2 FPDBZF Floating-point IEEE Divide-By-Zero Sticky Flag. - R/W 1 FPINVF Floating-point IEEE Invalid Sticky Flag. - R/W 0 OVF Sticky Saturation Overflow. - 1: Saturation occurred - 0: No saturation - Set when saturation occurs while executing instruction - that specifies optional saturation. - Remains set until explicitly cleared by a USR = Rs - instruction. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 40 - Hexagon V62 Programmer's Reference Manual Registers - - - - 2.2.4 Modifier registers - The modifier registers (M0-M1) are used in the following addressing modes: - -  Indirect auto-increment register addressing -  Circular addressing -  Bit-reversed addressing - - Indirect auto-increment - - In indirect auto-increment register addressing (Section 5.7.9) the modifier registers store a - signed 32-bit value which specifies the increment (or decrement) value. For example: - M1 = R0 // Set modifier register - R3 = memw(R2++M1) // Load word - - Table 2-7 defines the modifier registers as used in auto-increment register addressing. - - Table 2-7 Modifier registers (indirect auto-increment addressing) - Register Name Description - M0, M1 Increment Signed auto-increment value. - - - Circular - - In circular addressing (Section 5.7.10) the modifier registers store the circular buffer - length and related “K” and “I” values. For example: - M0 = R7 // Set modifier register - R0 = memb(R2++#4:circ(M0)) // Load from circ buffer pointed - // to by R2 with size/K vals in M0 - - R0 = memb(R7++I:circ(M1)) // Load from circ buffer pointed - // to by R7 with size/K/I vals in M1 - - Table 2-8 defines the modifier registers as used in circular addressing. - - Table 2-8 Modifier registers (circular addressing) - Name R/W Bits Field Description - M0, M1 32 Circular buffer specifier. - - R/W 31:28 I[10:7] I value (MSB - see Section 5.7.11) - R/W 27:24 K K value (Section 5.7.10) - R/W 23:17 I[6:0] I value (LSB) - R/W 16:0 Length Circular buffer length - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 41 - Hexagon V62 Programmer's Reference Manual Registers - - - - Bit-reversed - - In bit-reversed addressing (Section 5.7.12) the modifier registers store a signed 32-bit - value which specifies the increment (or decrement) value. For example: - M1 = R7 // Set modifier register - R2 = memub(R0++M1:brev) // The address is (R0.H | bitrev(R0.L)) - // The orginal R0 (not reversed) is added - // to M1 and written back to R0 - - Table 2-9 defines the modifier registers as used in bit-reversed addressing. - - Table 2-9 Modifier registers (bit-reversed addressing) - Register Name Description - M0, M1 Increment Signed auto-increment value. - - - - 2.2.5 Predicate registers - The predicate registers (P0-P3) store the status results of the scalar and vector compare - instructions (Chapter 6). For example: - P1 = cmp.eq(R2, R3) // Scalar compare - if (P1) jump end // Jump to address (conditional) - R8 = P1 // Get compare status (P1 only) - P3:0 = R4 // Set compare status (P0-P3) - - The four predicate registers can be specified as a register quadruple (P3:0) which - represents a single 32-bit register. - - NOTE Unlike the other control registers, the predicate registers are only 8 bits wide - because vector compares return a maximum of 8 status results. - - Table 2-10 defines the predicate registers. - - Table 2-10 Predicate registers - Register Bits Description - P0, P1,P2, P3 8 Compare status results. - P3:0 32 Compare status results. - 31:24 P3 register - 23:16 P2 register - 15:8 P1 register - 7:0 P0 register - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 42 - Hexagon V62 Programmer's Reference Manual Registers - - - - 2.2.6 Circular start registers - The circular start registers (CS0 - CS1) store the start address of a circular buffer in - circular addressing (Section 5.7.10). For example: - CS0 = R5 // Set circ start register - M0 = R7 // Set modifier register - R0 = memb(R2++#4:circ(M0)) // Load from circ buffer pointed - // to by CS0 with size/K vals in M0 - - Table 2-11 defines the circular start registers. - - Table 2-11 Circular start registers - Register Name Description - CS0, CS1 Circular Start Circular buffer start address. - - - - 2.2.7 User general pointer register - The user general pointer (UGP) register is a general-purpose control register. For example: - R9 = UGP // Get UGP - UGP = R3 // Set UGP - - NOTE UGP is typically used to store the address of thread local storage. - - Table 2-12 defines the user general pointer register. - - Table 2-12 User general pointer register - Register Name Description - UGP User General Pointer General-purpose control register. - - - - 2.2.8 Global pointer - The Global Pointer (GP) is used in GP-relative addressing. For example: - GP = R7 // Set GP - R2 = memw(GP+#200) // GP-relative load - - Table 2-13 defines the global pointer register. - - Table 2-13 Global pointer register - Name R/W Bits Field Description - GP 32 Global Pointer Register - R/W 31:7 GDP Global Data Pointer (Section 5.7.4). - R 6:0 reserved Return 0 if read. - Reserved for future expansion. To remain forward- - compatible with future processor versions, software - should always write this field with the same value - read from the field. - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 43 - Hexagon V62 Programmer's Reference Manual Registers - - - - 2.2.9 Cycle count registers - The cycle count registers (UPCYCLELO - UPCYCLEHI) store a 64-bit value containing the - current number of processor cycles executed since the Hexagon processor was last reset. - For example: - R5 = UPCYCLEHI // Get cycle count (high) - R4 = UPCYCLELO // Get cycle count (low) - R5:4 = UPCYCLE // Get cycle count - - NOTE The RTOS must grant permission to access these registers. Without this - permission, reading these registers from user code always returns zero. - - Table 2-14 defines the cycle count registers. - - Table 2-14 Cycle count registers - Register Name Description - UPCYCLELO Cycle count (low) Processor cycle count (low 32 bits) - - UPCYCLEHI Cycle count (high) Processor cycle count (high 32 bits) - - UPCYCLE Cycle count Processor cycle count (64 bits) - - - - 2.2.10 Frame limit register - The frame limit register (FRAMELIMIT) stores the low address of the memory area - reserved for the software stack (Section 8.3.1). For example: - R9 = FRAMELIMIT // Get frame limit register - FRAMELIMIT = R3 // Set frame limit register - - Table 2-15 defines the frame limit register. - - Table 2-15 Frame limit register - Register Name Description - FRAMELIMIT Frame Limit Low address of software stack area. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 44 - Hexagon V62 Programmer's Reference Manual Registers - - - - 2.2.11 Frame key register - The frame key register (FRAMEKEY) stores the key value that is used to XOR-scramble - return addresses when they are stored on the software stack (Section 8.3.2). For example: - R2 = FRAMEKEY // Get frame key register - FRAMEKEY = R1 // Set frame key register - - Table 2-16 defines the frame key register. - - Table 2-16 Frame key register - Register Name Description - FRAMEKEY Frame Key Key used to scramble return addresses - stored on software stack. - - - - 2.2.12 Packet count registers - The packet count registers (PKTCOUNTLO - PKTCOUNTHI) store a 64-bit value - containing the current number of instruction packets executed since a PKTCOUNT register - was last written to. For example: - R9 = PKTCOUNTHI // Get packet count (high) - R8 = PKTCOUNTLO // Get packet count (low) - R9:8 = PKTCOUNT // Get packet count - - Packet counting can be configured to operate only in specific sets of processor modes - (e.g., user mode only, or guest and monitor modes only). The configuration for each mode - is controlled by bits [12:10] in the user status register (Section 2.2.3). - - Packets with exceptions are not counted as committed packets. - - NOTE Each hardware thread has its own set of packet count registers. - - The RTOS must grant permission to access these registers. Without this - permission, reading these registers from user code always returns zero. - - When a value is written to a PKTCOUNT register, the 64-bit packet count - value is incremented before the value is stored in the register. - - Table 2-17 defines the packet count registers. - - Table 2-17 Packet count registers - Register Name Description - PKTCOUNTLO Packet count (low) Processor packet count (low 32 bits) - - PKTCOUNTHI Packet count (high) Processor packet count (high 32 bits) - - PKTCOUNT Cycle count Processor packet count (64 bits) - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 45 - Hexagon V62 Programmer's Reference Manual Registers - - - - 2.2.13 Qtimer registers - The Qtimer registers (UTIMERLO - UTIMERHI) provide access to the Qtimer global - reference count value. They enable Hexagon software to read the 64-bit time value - without having to perform an expensive AHB load. For example: - R5 = UTIMERHI // Get Qtimer reference count (high) - R4 = UTIMERLO // Get Qtimer reference count (low) - R5:4 = UTIMER // Get Qtimer reference count - - These registers are read-only – they are automatically updated by hardware to always - contain the current Qtimer value. - - NOTE The RTOS must grant permission to access these registers. Without this - permission, reading these registers from user code always returns zero. - - Table 2-18 defines the packet count registers. - - Table 2-18 Qtimer registers - Register Name Description - UTIMERLO Qtimer (low) Qtimer global reference count (low 32 bits) - - UTIMERHI Qtimer (high) Qtimer global reference count (high 32 bits) - - UTIMER Qtimer Qtimer global reference count (64 bits) - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 46 - 3 Instructions - - - This chapter covers the following topics: -  Instruction syntax - -  Instruction classes -  Instruction packets -  Instruction intrinsics -  Compound instructions -  Duplex instructions - - The instruction encoding is described in Chapter 10. - - For detailed descriptions of the Hexagon processor instructions see Chapter 11. - - - 3.1 Instruction syntax - Most Hexagon processor instructions have the following syntax: - dest = instr_name(source1,source2,...)[:option1][:option2]... - - The item specified on the left-hand side (LHS) of the equation is assigned the value - specified by the right-hand side (RHS). For example: - R2 = add(R3,R1) // Add R3 and R1, assign result to R2 - - Table 3-1 lists symbols commonly used in Hexagon processor instructions. - -Table 3-1 Instruction symbols - Symbol Example Meaning -= R2 = R3 Assignment of RHS to LHS -# R1 = #1 Immediate value -0x 0xBABE Hexadecimal number prefix -memXX R2 = memub(R3) Memory access - XX specifies access size and type - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 47 - Hexagon V62 Programmer's Reference Manual Instructions - - - -Table 3-1 Instruction symbols (Continued) - Symbol Example Meaning -; R2 = R3; R4 = R5; Instruction delimiter, or end of instruction -{…} {R2 = R3; R5 = R6} Instruction packet delimiter -(…) R2 = memw(R0 + #100) Source list delimiter -:endloopX :endloop0 Loop end - X specifies loop instruction (0 or 1) -:t if (P0.new) jump:t target Direction hint (jump taken) -:nt if (!P1.new) jump:nt target Direction hint (jump not taken) -:sat R2 = add(R1,R2):sat Saturate result -:rnd R2 = mpy(R1.H,R2.H):rnd Round result -:carry R5:4=add(R1:0,R3:2,P1):carry Predicate used as carry input and output -:<<16 R2 = add(R1.L,R2.L):<<16 Shift result left by halfword - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 48 - Hexagon V62 Programmer's Reference Manual Instructions - - - - 3.2 Instruction classes - The Hexagon processor instructions are assigned to specific instruction classes. Classes - determine what combinations of instructions can be written in parallel (Section 3.3). - - Instruction classes logically correspond with instruction types. For instance, the ALU32 - class contains ALU instructions which operate on 32-bit operands. - - Table 3-2 lists the instruction classes and subclasses. - -Table 3-2 Instruction classes - Class Subclass Description Section -XTYPE – Various operations Section 11.10 - ALU 64-bit ALU operations Section 11.10.1 - Bit Bit operations Section 11.10.2 - Complex Complex math (using real and Section 11.10.3 - imaginary numbers) - Floating point Floating point operations Section 11.10.4 - Multiply Multiply operations Section 11.10.5 - Permute Vector permute and format conversion Section 11.10.6 - (pack, splat, swizzle) - Predicate Predicate operations Section 11.10.7 - Shift Shift operations Section 11.10.8 - (with optional ALU operations) -ALU32 – 32-bit ALU operations Section 11.1 - ALU Arithmetic and logical Section 11.1.1 - Permute Permute Section 11.1.2 - Predicate Predicate operations Section 11.1.3 -CR – Control register access, loops Section 11.2 -JR – Jumps (register indirect addressing mode) Section 11.3 -J – Jumps (PC-relative addressing mode) Section 11.4 -LD – Memory load operations Section 11.5 -MEMOP – Memory operations Section 11.6 -NV – New-value operations Section 11.7 - Jump New-value jumps Section 11.7.1 - Store New-value stores Section 11.7.2 -ST – Memory store operations; Section 11.8 - alloc stack frame -SYSTEM – Operating system access Section 11.9 - USER Application-level access Section 11.9.3 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 49 - Hexagon V62 Programmer's Reference Manual Instructions - - - - 3.3 Instruction packets - Instructions can be grouped together to form packets of independent instructions which - are executed together in parallel. The packets can contain 1, 2, 3, or 4 instructions. - - Instruction packets must be explicitly specified in software. They are expressed in - assembly language by enclosing groups of instructions in curly braces. For example: - { R0 = R1; R2 = R3 } - - Various rules and restrictions exist on what types of instructions can be grouped together, - and in what order they can appear in the packet. In particular, packet formation is subject - to the following constraints: - -  Resource constraints determine how many instructions of a specific type can - appear in a packet. The Hexagon processor has a fixed number of execution units: - each instruction is executed on a particular type of unit, and each unit can process - at most one instruction at a time. Thus, for example, because the Hexagon - processor contains only two load units, an instruction packet with three load - instructions is invalid. The resource constraints are described in Section 3.3.3 -  Grouping constraints are a small set of rules that apply above and beyond the - resource constraints. These rules are described in Section 3.3.4. -  Dependency constraints ensure that no write-after-write hazards exist in a packet. - These rules are described in Section 3.3.5. -  Ordering constraints dictate the ordering of instructions within a packet. These - rules are described in Section 3.3.6. -  Alignment constraints dictate the placement of packets in memory. These rules are - described in Section 3.3.7. - - NOTE Individual instructions (which are not explicitly grouped in packets) are - executed by the Hexagon processor as packets containing a single instruction. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 50 - Hexagon V62 Programmer's Reference Manual Instructions - - - - 3.3.1 Packet execution semantics - Packets are defined to have parallel execution semantics. Specifically, the execution - behavior of a packet is defined as follows: - -  First, all instructions in the packet read their source registers in parallel. -  Next, all instructions in the packet execute. -  Finally, all instructions in the packet write their destination registers in parallel. - - For example, consider the following packet: - { R2 = R3; R3 = R2; } - - In the first phase, registers R3 and R2 are read from the register file. Then, after execution, - R2 is written with the old value of R3 and R3 is written with the old value of R2. In effect, - the result of this packet is that the values of R2 and R3 are swapped. - - NOTE Dual stores (Section 5.4), dual jumps (Section 7.7), new-value stores - (Section 5.5), new-value compare jumps (Section 7.5.1), and dot-new - predicates (Section 6.1.4) have non-parallel execution semantics. - - - 3.3.2 Sequencing semantics - Packets of any length can be freely mixed in code. A packet is considered an atomic unit: - in essence, a single large “instruction”. From the program perspective a packet either - executes to completion or not at all; it never executes only partially. For example, if a - packet causes a memory exception, the exception point is established before the packet. - - A packet containing multiple load/store instructions may require service from the external - system. For instance, consider the case of a packet which performs two load operations - that both miss in the cache. The packet requires the data to be supplied by the memory - system: - -  From the memory system perspective the two resulting load requests are - processed serially. -  From the program perspective, however, both load operations must complete - before the packet can complete. - - Thus, the packet is atomic from the program perspective. - - Packets have a single PC address which is the address of the start of the packet. Branches - cannot be performed into the middle of a packet. - - Architecturally, packets execute to completion – including updating all registers and - memory – before the next packet begins. As a result, application programs are not exposed - to any pipeline artifacts. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 51 - Hexagon V62 Programmer's Reference Manual Instructions - - - - 3.3.3 Resource constraints - A packet cannot use more hardware resources than are physically available on the - processor. For instance, because the Hexagon processor has only two load units, a packet - with three load instructions is invalid. The behavior of such a packet is undefined. The - assembler automatically rejects packets that oversubscribe the hardware resources. - - The processor supports up to four parallel instructions. The instructions are executed in - four parallel pipelines which are referred to as slots.The four slots are named Slot 0, - Slot 1, Slot 2, and Slot 3. (For more information see Section 1.2.) - - NOTE endloopN instructions (Section 7.2.2) do not use any slots. - - Each instruction belongs to a specific instruction class (Section 3.2). For example, jumps - belong to instruction class J, while loads belong to instruction class LD. An instruction’s - class determines which slot it can execute in. - - Figure 3-1 shows which instruction classes can be assigned to each of the four slots. - - - Slot 0 Slot 1 Slot 2 Slot 3 - LD Instructions LD Instructions - XTYPE Instructions XTYPE Instructions - ST Instructions ST Instructions - ALU32 Instructions ALU32 Instructions - ALU32 Instructions ALU32 Instructions - J Instructions J Instructions - MEMOP Instructions Some J Instructions - JR Instructions CR Instructions - NV Instructions - SYSTEM Instructions - Some J Instructions - - - - XTYPE Instructions (32/64 bit) J Instructions - Arithmetic, Logical, Bit Manipulation Jump/Call PC-relative - Multiply (Integer, Fractional, Complex) - Floating-point Operations - JR Instructions - Permute / Vector Permute Operations - Predicate Operations Jump/Call Register - Shift / Shift with Add/Sub/Logical - Vector Byte ALU LD Instructions - Vector Halfword (ALU, Shift, Multiply) Loads (8/16/32/64 bit) - Vector W ord (ALU, Shift) Deallocframe - - ALU32 Instructions ST Instructions - Arithmetic / Logical (32 bit) Stores (8/16/32/64 bit) - Vector Halfword Allocfram e - - CR Instructions MEMOP Instructions - Control-Register Transfers Operation on memory (8/16/32 bit) - Hardware Loop Setup - Predicate Logicals & Reductions SYSTEM Instructions - Prefetch - NV Instructions Cache Maintenance - New-value Jumps Bus Operations - New-value Stores - - - Figure 3-1 Packet grouping combinations - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 52 - Hexagon V62 Programmer's Reference Manual Instructions - - - - 3.3.4 Grouping constraints - A small number of restrictions determines what constitutes a valid packet. The assembler - ensures that all packets follow valid grouping rules. If a packet is executed which violates - a grouping rule, the behavior is undefined. The following rules must be followed: - -  Dot-new conditional instructions (Section 6.1.4) must be grouped in a packet with - an instruction that generates dot-new predicates. -  ST-class instructions can be placed in Slot 1. In this case Slot 0 normally must - contain a second ST-class instruction (Section 5.4). -  J-class instructions can be placed in Slots 2 or 3. However, only certain - combinations of program flow instructions (J or JR) can be grouped together in a - packet (Section 7.7). Otherwise, at most one program flow instruction is allowed - in a packet. Some Jump and Compare-Jump instructions can execute on slots 0 or - 1, excluding calls, such as the following: -  Instructions of the form “Pd=cmp.xx(); if(Pd.new)jump:hint ” -  Instructions of the form “If(Pd[.new]) jump[:hint] ” -  The “jump” instruction -  JR-class instructions can be placed in Slot 2. However, when encoded in a duplex - jumpr R31 can be placed in Slot 0 (Section 10.3). - -  Restrictions exist which limit the instructions that can appear in a packet at the - setup or end of a hardware loop (Section 7.2.4). -  A user control register transfer to the control register USR cannot be grouped with - a floating point instruction (Section 2.2.3). -  The SYSTEM-class instructions include prefetch, cache operations, bus - operations, load locked, and store conditional instructions (Section 5.9). These - instructions have the following grouping rules: -  brkpt, trap, pause, icinva, isync, and syncht are solo instructions. They - must not be grouped with other instructions in a packet. -  memw_locked, memd_locked, l2fetch, and trace must execute on Slot 0. - They must be grouped only with ALU32 or (non-FP) XTYPE instructions. -  dccleana, dcinva, dccleaninva, and dczeroa must execute on Slot 0. Slot - 1 must be empty or an ALU32 instruction. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 53 - Hexagon V62 Programmer's Reference Manual Instructions - - - - 3.3.5 Dependency constraints - Instructions in a packet cannot write to the same destination register. The assembler - automatically flags such packets as invalid. If the processor executes a packet with two - writes to the same general register, an error exception is raised. - - If the processor executes a packet which performs multiple writes to the same predicate or - control register, the behavior is undefined. Three special cases exist for this rule: - -  Conditional writes are allowed to target the same destination register only if at - most one of the writes is actually performed (Section 6.1.5). -  The overflow flag in the status register has defined behavior when multiple - instructions write to it (Section 2.2.3). Note that instructions that write to the - entire user status register (for example, USR=R2) are not allowed to be grouped in - a packet with any instruction that writes to a bit in the user status register. -  Multiple compare instructions are allowed to target the same predicate register in - order to perform a logical AND of the results (Section 6.1.3). - - - 3.3.6 Ordering constraints - In assembly code, instructions can appear in a packet in any order (with the exception of - dual jumps – Section 7.7). The assembler automatically encodes instructions in the packet - in the proper order. - - In the binary encoding of a packet, the instructions must be ordered from Slot 3 down to - Slot 0. If the packet contains less than four instructions, any unused slot is skipped – a - NOP is unnecessary as the hardware handles the proper spacing of the instructions. - - In memory, instructions in a packet must appear in strictly decreasing slot order. - Additionally, if an instruction can go in a higher-numbered slot, and that slot is empty, - then it must be moved into the higher-numbered slot. - - For example, if a packet contains three instructions and Slot 1 is not used, the instructions - should be encoded in the packet as follows: - -  Slot 3 instruction at lowest address -  Slot 2 instruction follows Slot 3 instruction -  Slot 0 instructions at the last (highest) address - - If a packet contains a single load or store instruction, that instruction must go in Slot 0, - which is the highest address. As an example, a packet containing both LD and ALU32 - instructions must be ordered so the LD is in Slot 0 and the ALU32 in another slot. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 54 - Hexagon V62 Programmer's Reference Manual Instructions - - - - 3.3.7 Alignment constraints - Packets have the following constraints on their placement or alignment in memory: -  Packets must be word-aligned (32-bit). If the processor executes an improperly - aligned packet, it will raise an error exception (Section 7.10). -  Packets should not wrap the 4GB address space. If address wraparound occurs, - the processor behavior is undefined. - - No other core-based restrictions exist for code placement or alignment. - - If the processor branches to a packet which crosses a 16-byte address boundary, the - resulting instruction fetch will stall for one cycle. Packets that are jump targets or loop - body entries can be explicitly aligned to ensure this does not occur (Section 9.5.2). - - - 3.4 Instruction intrinsics - To support efficient coding of the time-critical sections of a program (without resorting to - assembly language), the C compilers support intrinsics which are used to directly express - Hexagon processor instructions from within C code. - - The following example shows how an instruction intrinsic is used to express the XTYPE - instruction “Rdd = vminh(Rtt,Rss)”: - #include - - int main() - { - long long v1 = 0xFFFF0000FFFF0000LL; - long long v2 = 0x0000FFFF0000FFFFLL; - long long result; - - // find the minimum for each half-word in 64-bit vector - result = Q6_P_vminh_PP(v1,v2); - } - - Intrinsics are provided for instructions in the following classes: - -  ALU32 -  XTYPE -  CR (predicate operations only) -  SYSTEM (dcfetch only) - - For more information on intrinsics see Chapter 11. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 55 - Hexagon V62 Programmer's Reference Manual Instructions - - - - 3.5 Compound instructions - The Hexagon processor supports compound instructions, which encode pairs of - commonly-used operations in a single instruction. For example, each of the following is a - single compound instruction: - dealloc_return // deallocate frame and return - R2 &= and(R1, R0) // and and and - R7 = add(R4, sub(#15, R3)) // subtract and add - R3 = sub(#20, asl(R3, #16)) // shift and subtract - R5 = add(R2, mpyi(#8, R4)) // multiply and add - { // compare and jump - P0 = cmp.eq (R2, R5) - if (P0.new) jump:nt target - } - { // register transfer and jump - R2 = #15 - jump target - } - - Using compound instructions reduces code size and improves code performance. - - NOTE Compound instructions (with the exception of X-and-jump, as shown above) - have distinct assembly syntax from the instructions they are composed of. - - - 3.6 Duplex instructions - To reduce code size the Hexagon processor supports duplex instructions, which encode - pairs of commonly-used instructions in a 32-bit instruction container. - - Unlike compound instructions (Section 3.5), duplex instructions do not have distinctive - syntax – in assembly code they appear identical to the instructions they are composed of. - The assembler is responsible for recognizing when a pair of instructions can be encoded as - a single duplex rather than a pair of regular instruction words. - - In order to fit two instructions into a single 32-bit word, duplexes are limited to a subset of - the most common instructions (load, store, branch, ALU), and the most common register - operands. - - For more information on duplexes, see Section 10.2 and Section 10.3. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 56 - 4 Data Processing - - - The Hexagon processor provides a rich set of operations for processing scalar and vector - data. - - This chapter presents an overview of the operations provided by the following Hexagon - processor instruction classes: - -  XTYPE – General-purpose data operations -  ALU32 – Arithmetic/logical operations on 32-bit data - - NOTE For detailed descriptions of these instruction classes see Chapter 11. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 57 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.1 Data types - The Hexagon processor provides operations for processing the following data types: - -  Fixed-point data -  Floating-point data -  Complex data -  Vector data - - - 4.1.1 Fixed-point data - The Hexagon processor provides operations to process 8-, 16-, 32-, or 64-bit fixed-point - data. The data can be either integer or fractional, and in signed or unsigned format. - - - 4.1.2 Floating-point data - The Hexagon processor provides operations to process 32-bit floating-point numbers. The - numbers are stored in IEEE single-precision floating-point format. - - Per the IEEE standard, certain floating-point values are defined to represent positive or - negative infinity, as well as "Not-a-Number" (NaN), which represents values that have no - mathematical meaning. - - Floating-point numbers can be held in a general register. - - - 4.1.3 Complex data - The Hexagon processor provides operations to process 32- or 64-bit complex data. - - Complex numbers include a signed real portion and a signed imaginary portion. Given - two complex numbers (a+bi) and (c+di), the complex multiply operations computes both - the real portion (ac-bd) and the imaginary portion (ad+bc) in a single instruction. - - Complex numbers can be packed in a general register or register pair. When packed, the - imaginary portion occupies the most-significant portion of the register or register pair. - - - 4.1.4 Vector data - The Hexagon processor provides operations to process 64-bit vector data. - - Vector data types pack multiple data items – bytes, halfwords, or words – into 64-bit - registers. Vector data operations are common in video and image processing. - - Eight 8-bit bytes can be packed into a 64-bit register. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 58 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - Figure 4-1 shows an example of a vector byte operation. - - - Rss - - - Rtt - - - Op Op Op Op Op Op Op Op - - - - - Rdd - - Figure 4-1 Vector byte operation - - Four 16-bit halfword values can be packed in a single 64-bit register pair. - - Figure 4-2 shows an example of a vector halfword operation. - - - Rss - - - Rtt - - - - Op Op Op Op - - - - - Rdd - - Figure 4-2 Vector halfword operation - - Two 32-bit word values can be packed in a single 64-bit register pair. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 59 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - Figure 4-3 shows an example of a vector word operation. - - - Rss - - - Rtt - - - - Op Op - - - - - Rdd - - Figure 4-3 Vector word operation - - - - 4.2 Instruction options - Some instructions support optional scaling, saturation, and rounding. There are no mode - bits controlling these options – instead, they are explicitly specified as part of the - instruction name. The options are described in this section. - - - 4.2.1 Fractional scaling - In fractional data format, data is treated as fixed-point fractional values whose range is - determined by the word length and radix point position. - - Fractional scaling is specified in an instruction by adding the :<<1 specifier. For - example: - R3:2 = cmpy(R0,R1):<<1:sat - - When two fractional numbers are multiplied, the product must be scaled to restore the - original fractional data format. The Hexagon processor allows fractional scaling of the - product to be specified in the instruction for shifts of 0 and 1. A shift of 1 should be done - for Q1.15 numbers, while a shift of 0 should be done for integer multiplication. - - - 4.2.2 Saturation - Certain instructions are available in saturating form. If a saturating arithmetic instruction - has a result which is smaller than the minimum value, then the result is set to the minimum - value. Similarly, if the operation has a result which is greater than the maximum value, - then the result is set to the maximum value. - - Saturation is specified in an instruction by adding the :sat specifier. For example: - R2 = abs(R1):sat - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 60 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - The OVF bit in the user status register (Section 2.2.3) is set whenever a saturating - operation saturates to the maximum or minimum value. It remains set until explicitly - cleared by a control register transfer to USR. For vector-type saturating operations, if any - of the individual elements of the vector saturate, then OVF is set. - - - 4.2.3 Arithmetic rounding - Certain signed multiply instructions support optional arithmetic rounding (also known as - biased rounding). The arithmetic rounding operation takes a double precision fractional - value and adds 0x8000 to the low 16-bits (least significant 16-bit halfword). - - Rounding is specified in an instruction by adding the :rnd specifier. For example: - R2 = mpy(R1.h,R2.h):rnd - - NOTE Arithmetic rounding can accumulate numerical errors, especially when the - number to be rounded is exactly 0.5. This happens most frequently when - dividing by 2 or averaging. - - - 4.2.4 Convergent rounding - To address the problem of error accumulation in arithmetic rounding (Section 4.2.3), the - Hexagon processor includes four instructions that support positive and negative averaging - with a convergent rounding option. - - These instructions work as follows: - - 1. Compute (A+B) or (A-B) for AVG and NAVG respectively. - 2. Based on the two least-significant bits of the result, add a rounding constant as - follows: -  If the two LSBs are 00, add 0 - -  If the two LSBs are 01, add 0 -  If the two LSBs are 10, add 0 -  If the two LSBs are 11, add 1 - 3. Shift the result right by one bit. - - - 4.2.5 Scaling for divide and square-root - On the Hexagon processor, floating point divide and square-root operations are - implemented in software using library functions. To enable the efficient implementation of - these operations, the processor supports special variants of the multiply-accumulate - instruction. These are named scale FMA. - - Scale FMA supports optional scaling of the product generated by the floating-point fused - multiply-add instruction. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 61 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - Scaling is specified in the instruction by adding the :scale specifier and a predicate - register operand. For example: - R3 += sfmpy(R0,R1,P2):scale - - For single precision, the scaling factor is two raised to the power specified by the contents - of the predicate register (which is treated as an 8-bit two's complement value). For double - precision, the predicate register value is doubled before being used as a power of two. - - NOTE Scale FMA instructions should not be used outside of divide and square-root - library routines. No guarantee is provided that future versions of the Hexagon - processor will implement these instructions using the same semantics. Future - versions assume only that compatibility for scale FMA is limited to the needs - of divide and square-root library routines. - - - 4.3 XTYPE operations - The XTYPE instruction class includes most of the data-processing operations performed - by the Hexagon processor. These operations are categorized by their operation type: - -  ALU -  Bit manipulation -  Complex -  Floating point -  Multiply -  Permute -  Predicate -  Shift - - - 4.3.1 ALU - ALU operations modify 8-, 16-, 32-, and 64-bit data. These operations include: - -  Add and subtract with and without saturation -  Add and subtract with accumulate -  Absolute value -  Logical operations -  Min, max, negate instructions -  Register transfers of 64-bit data -  Word to doubleword sign extension -  Comparisons - - For more information see Section 11.1.1 and Section 11.10.1. - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 62 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.3.2 Bit manipulation - Bit manipulation operations modify bit fields in a register or register pair. These - operations include: - -  Bit field insert -  Bit field signed and unsigned extract -  Count leading and trailing bits -  Compare bit masks -  Set / Clear / Toggle bit -  Test bit operation -  Interleave/deinterleave bits -  Bit reverse -  Split bitfield -  Masked parity and Linear Feedback shift -  Table index formation - - For more information see Section 11.10.2. - - - 4.3.3 Complex - Complex operations manipulate complex numbers. These operations include: - -  Complex add and subtract -  Complex multiply with optional round and pack -  Vector complex multiply -  Vector complex conjugate -  Vector complex rotate -  Vector reduce complex multiply real or imaginary - - For more information see Section 11.10.3. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 63 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.3.4 Floating point - Floating-point operations manipulate single-precision floating point numbers. These - operations include: - -  Addition and subtraction -  Multiplication (with optional scaling) -  Min/max/compare -  Format conversion - - The Hexagon floating-point operations are defined to support the IEEE floating-point - standard. However, certain IEEE-required operations – such as divide and square root – - are not supported directly. Instead, special instructions are defined to support the - implementation of the required operations as library routines. These instructions include: - -  A special version of the fused multiply-add instruction (designed specifically for - use in library routines) -  Reciprocal/square root approximations (which compute the approximate initial - values used in reciprocal and reciprocal-square-root routines) -  Extreme value assistance (which adjusts input values if they cannot produce - correct results using convergence algorithms) - - For more information see Section 11.10.4. - - NOTE The special floating-point instructions are not intended for use directly in user - code – they should be used only in the floating point library. - - Format conversion - - The floating-point conversion instructions sfmake and dfmake convert an unsigned 10-bit - immediate value into the corresponding floating-point value. - - The immediate value must be encoded so bits [5:0] contain the significand, and bits [9:6] - the exponent. The exponent value is added to the initial exponent value (bias - 6). - - For example, to generate the single-precision floating point value 2.0, bits [5:0] must be - set to 0, and bits [9:6] set to 7. Performing sfmake on this immediate value yields the - floating point value 0x40000000, which is 2.0. - - NOTE The conversion instructions are designed to handle common floating point - values, including most integers and many basic fractions (1/2, 3/4, etc.). - - Rounding - - The Hexagon user status register (Section 2.2.3) includes the FPRND field, which is used - to specify the IEEE-defined floating-point rounding mode. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 64 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - Exceptions - - The Hexagon user status register (Section 2.2.3) includes five status fields, which work as - sticky flags for the five IEEE-defined exception conditions: inexact, overflow, underflow, - divide by zero, and invalid. A sticky flag is set when the corresponding exception occurs, - and remains set until explicitly cleared. - - The user status register also includes five mode fields which are used to specify whether - an operating-system trap should be performed if one of the floating-point exceptions - occur. For every instruction packet containing a floating-point operation, if a floating- - point sticky flag and the corresponding trap-enable bit are both set, then a floating-point - trap is generated. After the packet commits, the Hexagon processor then automatically - traps to the operating system. - - NOTE Non-floating-point instructions never generate a floating-point trap, - regardless of the state of the sticky flag and trap-enable bits. - - - 4.3.5 Multiply - Multiply operations support fixed-point multiplication, including both single- and double- - precision multiplication, and polynomial multiplication. - - Single precision - - In single-precision arithmetic a 16-bit value is multiplied by another 16-bit value. These - operands can come from the high portion or low portion of any register. Depending on the - instruction, the result of the 16  16 operation can optionally be accumulated, saturated, - rounded, or shifted left by 0-1 bits. - - The instruction set supports operations on signed  signed, unsigned  unsigned, and - signed  unsigned data. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 65 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - Table 4-1 summarizes the options available for 16  16 single precision multiplications. - The symbols used in the table are as follows: - -  SS – Perform signed  signed multiply -  UU – Perform unsigned  unsigned multiply -  SU – Perform signed  unsigned multiply -  A+ – Result added to accumulator -  A- – Result subtracted from accumulator -  0 – Result not added to accumulator - - Table 4-1 Single-precision multiply options - Multiply Result Sign Accumulate Sat Rnd Scale - 16  16 32 SS A+, A- Yes No 0-1 - 16  16 32 SS 0 Yes Yes 0-1 - 16  16 64 SS A+, A- No No 0-1 - 16  16 64 SS 0 No Yes 0-1 - 16  16 32 UU A+, A-, 0 No No 0-1 - 16  16 64 UU A+, A-, 0 No No 0-1 - 16  16 32 SU A+, 0 Yes No 0-1 - - - Double precision - - Double precision instructions are available for both 32  32 and 32  16 multiplication: - -  For 32  32 multiplication the result can be either 64 or 32 bits. The 32-bit result - can be either the high or low portion of the 64-bit product. -  For 32  16 multiplication the result is always taken as the upper 32 bits. - - The operands can be either signed or unsigned. - - Table 4-2 summarizes the options available in double precision multiply. - - Table 4-2 Double precision multiply options - Multiply Result Sign Accumulate Sat Rnd Scale - 32 32 64 SS, UU A+, A-, 0 No No 0 - - 32 32 32 (upper) SS, UU 0 No Yes 0 - - 32 32 32 (low) SS, UU A+, 0 No No 0 - - 32 16 32 (upper) SS, UU A+, 0 Yes Yes 0-1 - - 32 32 32 (upper) SU 0 No No 0 - - - Polynomial - - Polynomial multiply instructions are available for both words and vector halfwords. - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 66 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - These instructions are useful for many algorithms including scramble code generation, - cryptographic algorithms, convolutional, and Reed Solomon code. - - For more information on multiply operations, see Section 11.10.5. - - - 4.3.6 Permute - Permute operations perform various operations on vector data, including arithmetic, - format conversion, and rearrangement of vector elements. Many types of conversions are - supported: - -  Swizzle bytes -  Vector shuffle -  Vector align -  Vector saturate and pack -  Vector splat bytes -  Vector splice -  Vector sign extend halfwords -  Vector zero extend bytes -  Vector zero extend halfwords -  Scalar saturate to byte, halfword, word -  Vector pack high and low halfwords -  Vector round and pack -  Vector splat halfwords - - For more information, see Section 11.1.2 and Section 11.10.6. - - - 4.3.7 Predicate - Predicate operations modify predicate source data. The categories of instructions available - include: - -  Vector mask generation -  Predicate transfers -  Viterbi packing - - For more information, see Section 11.1.3 and Section 11.10.7. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 67 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.3.8 Shift - Scalar shift operations perform a variety of 32 and 64-bit shifts followed by an optional - add/sub or logical operation. Figure 4-4 shows the general operation. - - - Rss - - - # / Rt - - Shift - amount - - - 64-bit Shifter - - - - - 64-bit Add/Sub/Logical - - - - - Rxx - - - Figure 4-4 64-bit shift and add/sub/logical - - Four shift types are supported: - -  ASR – Arithmetic shift right -  ASL – Arithmetic shift left -  LSR – Logical shift right -  LSL – Logical shift left - - In register-based shifts, the Rt register is a signed two’s-complement number. If this value - is positive, then the instruction opcode tells the direction of shift (right or left). If this - value is negative, then the shift direction indicated by the opcode is reversed. - - When arithmetic right shifts are performed, the sign bit is shifted in, whereas logical right - shifts shift in zeros. Left shifts always shift in zeros. - - Some shifts are available with saturation and rounding options. - - For more information see Section 11.10.8. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 68 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.4 ALU32 operations - The ALU32 instruction class includes general arithmetic/logical operations on 32-bit data: - -  Add, subtract, negate without saturation on 32-bit data -  Logical operations such as AND, OR, XOR, AND with immediate, and OR with - immediate -  Scalar 32-bit compares -  Combine halfwords, combine words, combine with immediates, shift halfwords, - and Mux -  Conditional add, combine, logical, subtract, and transfer. -  NOP -  Sign and zero-extend bytes and halfwords -  Transfer immediates and registers -  Vector add, subtract, and average halfwords - - For more information see Section 11.1. - - NOTE ALU32 instructions can be executed on any slot (Section 3.3.3). - - Chapter 6 describes the conditional execution and compare instructions. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 69 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.5 Vector operations - Vector operations support arithmetic operations on vectors of bytes, halfwords, and words. - - The vector operations belong to the XTYPE instruction class (except for vector add, - subtract, and average halfwords, which are ALU32). - - Vector byte operations - - The vector byte operations process packed vectors of signed or unsigned bytes. They - include the following operations: - -  Vector add and subtract signed or unsigned bytes -  Vector min and max signed or unsigned bytes -  Vector compare signed or unsigned bytes -  Vector average unsigned bytes -  Vector reduce add unsigned bytes -  Vector sum of absolute differences unsigned bytes - - Vector halfword operations - - The vector halfword operations process packed 16-bit halfwords. They include the - following operations: - -  Vector add and subtract halfwords -  Vector average halfwords -  Vector compare halfwords -  Vector min and max halfwords -  Vector shift halfwords -  Vector dual multiply -  Vector dual multiply with round and pack -  Vector multiply even halfwords with optional round and pack -  Vector multiply halfwords -  Vector reduce multiply halfwords - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 70 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - For example, Figure 4-5 shows the operation of the vector arithmetic shift right halfword - (vasrh) instruction. In this instruction, each 16-bit half-word is shifted right by the same - amount which is specified in a register or with an immediate value. Because the shift is - arithmetic, the bits shifted in are copies of the sign bit. - - - Shift Amount Rt / #u4 - - - lost lost lost lost Rss - - - - - s/z ext s/z ext s/z ext s/z ext Rdd - - Figure 4-5 Vector halfword shift right - - Vector word operations - - The vector word operations process packed vectors of two words. They include the - following operations: - -  Vector add and subtract words -  Vector average words -  Vector compare words -  Vector min and max words -  Vector shift words with optional truncate and pack - - For more information on vector operations see Section 11.1.1 and Section 11.10.1. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 71 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.6 CR operations - The CR instruction class includes operations that access the control registers (Section 2.2). - - Table 4-3 lists the instructions that access the control registers. - - Table 4-3 Control register transfer instructions - Syntax Operation - Rd = Cs Move control register to / from a general register. - Cd = Rs - NOTE - PC is not a valid destination register. - Rdd = Css Move control register pair to / from a general register pair. - Cdd = Rss - NOTE - PC is not a valid destination register. - - - NOTE In register-pair transfers, control registers must be specified using their - numeric alias names – see Section 2.2 for details. - - For more information see Section 11.2. - - - 4.7 Compound operations - The instruction set includes a number of instructions which perform multiple logical or - arithmetic operations in a single instruction. They include the following operations: - -  And/Or with inverted input -  Compound logical register -  Compound logical predicate -  Compound add-subtract with immediates -  Compound shift-operation with immediates (arithmetic or logical) -  Multiply-add with immediates - - For more information see Section 11.10.1. - - - 4.8 Special operations - The instruction set includes a number of special-purpose instructions to support specific - applications: - -  H.264 CABAC processing -  IP internet checksum -  Software-defined radio - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 72 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.8.1 H.264 CABAC processing - H.264/AVC is adopted in a diverse range of multimedia applications: - -  HD-DVDs -  HDTV broadcasting -  Internet video streaming - - Context Adaptive Binary Arithmetic Coding (CABAC) is one of the two alternative - entropy coding methods specified in the H.264 main profile. CABAC offers superior - coding efficiency at the expense of greater computational complexity. The Hexagon - processor includes a dedicated instruction (decbin) to support CABAC decoding. - - Binary arithmetic coding is based on the principle of recursive interval subdivision, and its - state is characterized by two quantities: - -  The current interval range -  The current offset in the current code interval - - The offset is read from the encoded bit stream. When decoding a bin, the interval range is - subdivided in two intervals based on the estimation of the probability pLPS of LPS: one - interval with width of rLPS = range x pLPS, and another with width of rMPS = range x - pMPS = range -rLPS, where LPS stands for Least Probable Symbol, and MPS for Most - Probable Symbol. - - Depending on which subinterval the offset falls into, the decoder decides whether the bin - is decoded as MPS or LPS, after which the two quantities are iteratively updated, as shown - in Figure 4-1. - - - MPS occurs LPS occurs - - - rLPS rLPS - range - - - - - range - - - - - rMPS rMPS - offset - - - - - offset - - - - - rangeNew = rMPS rangeNew = rLPS - offsetNew = offset offsetNew = offset-rMPS - - - - - Figure 4-1 Arithmetic decoding for one bin - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 73 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.8.1.1 CABAC implementation - In H.264 range is a 9-bit quantity, and offset is 9-bits in regular mode and 10-bits in bypass - mode during the whole decoding process. The calculation of rLPS is approximated by a - 64×4 table of 256 bytes, where the range and the context state (selected for the bin to be - decoded) are used to address the lookup table. To maintain the precision of the whole - decoding process, the new range must be renormalized to ensure that the most significant - bit is always 1, and that the offset is synchronously refilled from the bit stream. - - To simplify the renormalization/refilling process, the decoding scheme shown in - Figure 4-2 was created to significantly reduce the frequency of renormalization and - refilling bits from the bit-stream, while also being suitable for DSP implementation. - - - range: 32 bit register 18=29-bitpos - 0000 0000 0001 xxxx xxxx 0000 0000 0000 - bitpos=11 9 12=23-bitpos - offset: 32 bit register - 0000 0000 000x xxxx xxxx xxxx xxxx xxxx - Decode Decision - (ctxIdx, range, offset) - - - bitpos=Count_leading_zeros(range) - rLPS=lutLPS[ctxIdx->state][(range>>(29-bitpos))&3]<<(23-bitpos) - rMPS=range-rLPS - - - Yes offset >= rMPS No - - - bin = !ctxIdx->valMPS - bin = ctxIdx->valMPS - range = rLPS - range = rMPS - offset = offset - rMPS - - - ctxIdx->state == 0 Yes - - - ctxIdx->valMPS=!ctxIdx->valMPS - No - - ctxIdx->state = ctxIdx->state = - TransIndexLPS(ctxIdx->state) TransIndexMPS(ctxIdx->state) - - - - Renormalization1 - (range, offset) - - Done - - Figure 4-2 CABAC decoding engine for regular bin - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 74 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - By using the decbin instruction, the Hexagon processor is able to decode one regular bin - in 2 cycles (not counting the bin refilling process). - - For more information on the decbin instruction see Section 11.10.6. - - For example: - Rdd = decbin(Rss,Rtt) - - INPUT: Rss and Rtt register pairs as: - Rtt.w1[5:0] = state - Rtt.w1[8] = valMPS - Rtt.w0[4:0] = bitpos - Rss.w0 = range - Rss.w1 = offset - - OUTPUT: Rdd register pair is packed as - Rdd.w0[5:0] = state - Rdd.w0[8] = valMPS - Rdd.w0[31:23] = range - Rdd.w0[22:16] = '0' - Rdd.w1 = offset (normalized) - - OUTPUT: P0 - P0 = (bin) - - - 4.8.1.2 Code example - H264CabacGetBinNC: - /**************************************************************** - * Non-conventional call: - * Input: R1:0 = offset : range , R2 = dep, R3 = ctxIdx, - * R4 = (*ctxIdx), R5 = bitpos - * - * Return: - * R1: 0 - offset : range - * P0 - (bin) - *****************************************************************/ - - // Cycle #1 - { R1:0= decbin(R1:0,R5:4) // decoding one bin - R6 = asl(R22,R5) // where R22 = 0x100 - } - - // Cycle #2 - { memb(R3) = R0 // save context to *ctxIdx - R1:0 = vlsrw(R1:0,R5) // re-align range and offset - P1 = cmp.gtu(R6,R1) // need refill? i.e., P1= (range<0x100) - IF (!P1.new) jumpr:t LR // return - } - RENORM_REFILL: - ... - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 75 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.8.2 IP internet checksum - The key features of the internet checksum1 include: - -  The checksum can be summed in any order -  Carries may be accumulated using an accumulator larger than size being added, and - added back in at any time - - Using standard data-processing instructions, the internet checksum can be computed at 8 - bytes per cycle in the main loop, by loading words and accumulating into doublewords. - After the loop, the upper word is added to the lower word; then the upper halfword is - added to the lower halfword, and any carries are added back in. - - The Hexagon processor supports a dedicated instruction (vradduh) which enables the - internet checksum to be computed at a rate of 16 bytes per cycle. - - The vradduh instruction accepts the halfwords of the two input vectors, adds them all - together, and places the result in a 32-bit destination register. This operation can be used - for both computing the sum of 16 bytes of input while preserving the carries, and also - accumulating carries at the end of computation. - - For more information on the vradduh instruction see Section 11.10.1. - - NOTE This operation utilizes the maximum load bandwidth available in the - Hexagon processor. - - - - - 1 See RFC 1071 (http://www.faqs.org/rfcs/rfc1071.html) - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 76 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.8.2.1 Code example - .text - .global fast_ip_check - // Assumes data is 8-byte aligned - // Assumes data is padded at least 16 bytes afterwords with 0's. - // input R0 points to data - // input R1 is length of data - // returns IP checksum in R0 - - fast_ip_check: - { - R1 = lsr(R1,#4) // 16-byte chunks, rounded down, +1 - R9:8 = combine(#0,#0) - R3:2 = combine(#0,#0) - } - { - loop0(1f,R1) - R7:6 = memd(R0+#8) - R5:4 = memd(R0++#16) - } - .falign - 1: - { - R7:6 = memd(R0+#8) - R5:4 = memd(R0++#16) - R2 = vradduh(R5:4,R7:6) // accumulate 8 halfwords - R8 = vradduh(R3:2,R9:8) // accumulate carries - }:endloop0 - // drain pipeline - { - R2 = vradduh(R5:4,R7:6) - R8 = vradduh(R3:2,R9:8) - R5:4 = combine(#0,#0) - } - { - R8 = vradduh(R3:2,R9:8) - R1 = #0 - } - // may have some carries to add back in - { - R0 = vradduh(R5:4,R9:8) - } - // possible for one more to pop out - { - R0 = vradduh(R5:4,R1:0) - } - { - R0 = not(R0) - jumpr LR - } - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 77 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - 4.8.3 Software-defined radio - The Hexagon processor includes six special-purpose instructions which support the - implementation of software-defined radio. The instructions greatly accelerate the - following algorithms: - -  Rake despreading -  Scramble code generation -  Polynomial field processing - - - 4.8.3.1 Rake despreading - A fundamental operation in despreading is the PN multiply operation. In this operation the - received complex chips are compared against a pseudo-random sequence of QAM - constellation points and accumulated. - - Figure 4-3 shows the vrcrotate instruction, which is used to perform this operation. The - products are summed to form a soft 32-bit complex symbol. The instruction has both - accumulating and non-accumulating versions. - - - Rxx += vrcrotate(Rss,Rt,#0) - - - - Rt - - - - - 1 j -1 -j 1 j -1 -j 1 j -1 -j 1 j -1 -j - - mux mux mux mux - - - - - Im3 Re3 Im2 Re2 Im1 Re1 Im0 Re0 Rs - - - - - * * * * - - + + - - - I R Rxx - - - Figure 4-3 Vector reduce complex rotate - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 78 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - For more information on the vrcrotate instruction, see Section 11.10.3. - - NOTE Using this instruction the Hexagon processor can process 5.3 chips per cycle, - and a 12-finger WCDMA user requires only 15 MHz. - - - 4.8.3.2 Polynomial operations - The polynomial multiply instructions support the following operations: - -  Scramble code generation (at a rate of 8 symbols per cycle for WCDMA) -  Cryptographic algorithms (such as Elliptic Curve) -  CRC checks (at a rate of 21bits per cycle) -  Convolutional encoding -  Reed Solomon codes - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 79 - Hexagon V62 Programmer's Reference Manual Data Processing - - - - The four versions of this instruction support 32 x 32 and vector 16 x 16 multiplication both - with and without accumulation, as shown in Figure 4-4. - - For more information on the pmpy instructions see Section 11.10.5. - - Rxx += vpmpyh(Rs,Rt) - Rxx += pmpyw(Rs,Rt) - - - Rs - - Rs - - Rt - - Rt - 16x16 - Carryless 16x16 - Carryless - 32x32 - Carryless - Polynomial - Mpy * * Polynomial - Mpy - Polynomial - mpy * - XOR XOR - - XOR - - - - - Rxx Rxx - - Figure 4-4 Polynomial multiply - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 80 - 5 Memory - - - The Hexagon processor features a load/store architecture, where numeric and logical - instructions operate on registers. Explicit load instructions move operands from memory - to registers, while store instructions move operands from registers to memory. A small - number of instructions (known as mem-ops) perform numeric and logical operations - directly on memory. - - The address space is unified: all accesses target the same linear address space, which - contains both instructions and data. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 81 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.1 Memory model - This section describes the memory model for the Hexagon processor. - - - 5.1.1 Address space - The Hexagon processor has a 32-bit byte-addressable memory address space. The entire - 4G linear address space is addressable by the user application. A virtual-to-physical - address translation mechanism is provided. - - - 5.1.2 Byte order - The Hexagon processor is a little-endian machine: the lowest address byte in memory is - held in the least significant byte of a register, as shown in Figure 5-1. - - - Address Contents - - 0 A Register Contents - 1 B - 31 0 - 2 C - Load byte - - - - A - 3 D - - 4 E - - B A Load Halfword - - 5 F - D C B A Load word - 6 G 63 - - 7 H H G F E D C B A Load doubleword - - - Figure 5-1 Hexagon processor byte order - - - 5.1.3 Alignment - Even though the Hexagon processor memory is byte-addressable, instructions and data - must be aligned in memory on specific address boundaries: -  Instructions and instruction packets must be 32-bit aligned - -  Data must be aligned to its native access size. - - Any unaligned memory access will cause a memory-alignment exception. - - The permute instructions (Section 4.3.6) can be used in applications that need to reference - unaligned vector data. The loads and stores still must be memory-aligned; however, the - permute instructions enable the data to be easily rearranged in registers. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 82 - Hexagon V62 Programmer's Reference Manual Memory - - - - Table 5-1 summarizes the alignment restrictions. - . - - - Table 5-1 Memory alignment restrictions - Data Type Size (bits) Exception When - Byte 8 Never - Unsigned byte - Halfword 16 LSB[0] != 0 1 - Unsigned halfword - Word 32 LSB[1:0] != 00 - Unsigned word - Doubleword 64 LSB[2:0] != 000 - Instruction 32 LSB[1:0] != 00 - Instruction packet - 1 LSB = Least significant bits of address - - - - - 5.2 Memory loads - Memory can be loaded in byte, halfword, word, or doubleword sizes. The data types - supported are signed or unsigned. The syntax used is memXX, where XX denotes the data - type. - - Table 5-2 summarizes the supported load instructions. - -Table 5-2 Load instructions - Source Destination - Size Data - Syntax Size Comment - Placement - (bits) (bits) -Rd = memub(Rs) 8 32 Low 8 bits Zero-extend 8 to 32 bits -Rd = memb(Rs) 8 32 Low 8 bits Sign-extend 8 to 32 bits -Rd = memuh(Rs) 16 32 Low 16 bits Zero-extend 16 to 32 bits -Rd = memh(Rs) 16 32 Low 16 bits Sign-extend 16 to 32 bits -Rd = memubh(Rs) 16 32 Bytes 0 and 2 Bytes 1 and 3 zeroed 1 -Rd = membh(Rs) 16 32 Bytes 0 and 2 Bytes 1 and 3 sign-extended -Rd = memw(Rs) 32 32 All 32 bits Load word -Rdd = memubh(Rs) 32 64 Bytes 0,2,4,6 Bytes 1,3,5,7 zeroed -Rdd = membh(Rs) 32 64 Bytes 0,2,4,6 Bytes 1,3,5,7 sign-extended -Rdd = memd(Rs) 64 64 All 64 bits Load doubleword -Ryy = memh_fifo(Rs) 16 64 High 16 bits Shift vector and load halfword -deallocframe 64 64 All 64 bits See Chapter 8 -dealloc_return 64 64 All 64 bits See Chapter 8 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 83 - Hexagon V62 Programmer's Reference Manual Memory - - - -1 The memubh and membh instructions load contiguous bytes from memory (either 2 or 4 bytes) and unpack these bytes into a - vector of halfwords. The instructions are useful when bytes are used as input into halfword vector operations, which is common in - video and image processing.. - - - NOTE The memory load instructions belong to instruction class LD, and can execute - only in Slots 0 or 1. - - - 5.3 Memory stores - Memory can be stored in byte, halfword, word, or doubleword sizes. The syntax used is - memX, where X denotes the data type. - - Table 5-3 summarizes the supported store instructions. - - Table 5-3 Store instructions - Source Destination - Syntax Size Size Comment - (bits) (bits) - memb(Rs) = Rt 32 8 Store byte (bits 7:0) - memb(Rs) = #s8 8 8 Store byte - memh(Rs) = Rt 32 16 Store lower half (bits 15:0) - memh(Rs) = Rt.H 32 16 Store upper half (bits 31:16) - memh(Rs) = #s8 8 16 Sign-extend 8 to 16 bits - memw(Rs) = Rt 32 32 Store word - memw(Rs) = #s8 8 32 Sign-extend 8 to 32 bits - memd(Rs) = Rtt 64 64 Store doubleword - allocframe(#u11) 64 64 See Chapter 8 - - - NOTE The memory store instructions belong to instruction class ST, and can execute - only in slot 0 or – when part of a dual store (Section 5.4) – slot 1. - - - 5.4 Dual stores - Two memory store instructions can appear in the same instruction packet. The resulting - operation is considered a dual store. For example: - { - memw(R5) = R2 // dual store - memh(R6) = R3 - } - - Unlike most packetized operations, dual stores are not executed in parallel (Section 3.3.1). - Instead, the store instruction in Slot 1 effectively executes first, followed by the store - instruction in Slot 0. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 84 - Hexagon V62 Programmer's Reference Manual Memory - - - - NOTE The store instructions in a dual store must belong to instruction class ST - (Section 5.3), and can execute only in Slots 0 and 1. - - - 5.5 New-value stores - A memory store instruction can store a register that is assigned a new value in the same - instruction packet (Section 3.3). This feature is expressed in assembly language by - appending the suffix “.new” to the source register. For example: - { - R2 = memh(R4+#8) // load halfword - memw(R5) = R2.new // store newly-loaded value - } - - New-value store instructions have the following restrictions: - -  If an instruction uses auto-increment or absolute-set addressing mode - (Section 5.7), its address register cannot be used as the new-value register. -  If an instruction produces a 64-bit result, its result registers cannot be used as the - new-value register. -  If the instruction that sets a new-value register is conditional (Section 6.1.2), it - must always be executed. - - NOTE The new-value store instructions belong to instruction class NV, and can - execute only in Slot 0. - - - 5.6 Mem-ops - Mem-ops perform basic arithmetic, logical, and bit operations directly on memory - operands, without the need for a separate load or store. Mem-ops can be performed on - byte, halfword, or word sizes. Table 5-4 lists the mem-ops. - - Table 5-4 Mem-ops - Syntax Operation - memXX(Rs+#u6) [+-|&] = Rt Arithmetic/logical on memory - memXX(Rs+#u6) [+-] = #u5 Arithmetic on memory - memXX(Rs+#u6) = clrbit(#u5) Clear bit in memory - memXX(Rs+#u6) = setbit(#u5) Set bit in memory - - - NOTE The mem-op instructions belong to instruction class MEMOP, and can - execute only in Slot 0. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 85 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.7 Addressing modes - Table 5-5 summarizes the supported addressing modes. - -Table 5-5 Addressing modes - - Mode Syntax Operation 1 -Absolute memXX(##address) EA = address -Absolute-set memXX(Re=##address) EA = address - Re = address -Absolute with register offset memXX(Ru<<#u2+##U32) EA = imm + (Ru << #u2) -Global-pointer-relative memXX(GP+#immediate) EA = GP + immediate - memXX(#immediate) -Indirect memXX(Rs) EA = Rs -Indirect with offset memXX(Rs+#s11) EA = Rs + imm -Indirect with register offset memXX(Rs+Ru<<#u2) EA = Rs + (Ru << #u2) -Indirect memXX(Rx++#s4) EA = Rx; -with auto-increment immediate Rx += (imm) - -Indirect memXX(Rx++Mu) EA = Rx; -with auto-increment register Rx += Mu - -Circular memXX(Rx++#s4:circ(Mu)) EA = Rx; -with auto-increment immediate Rx = circ_add(Rx,imm,Mu) - -Circular memXX(Rx++I:circ(Mu)) EA = Rx; -with auto-increment register Rx = circ_add(Rx,I,Mu) - -Bit-reversed memXX(Rx++Mu:brev) EA = Rx.H + bit_reverse(Rx.L) -with auto-increment register Rx += Mu -1 EA (Effective Address) is equivalent to VA (Virtual Address). - - - - 5.7.1 Absolute - The absolute addressing mode uses a 32-bit constant value as the effective memory - address. For example: - R2 = memw(##100000) // load R2 with word from addr 100000 - memw(##200000) = R4 // store R4 to word at addr 200000 - - - - 5.7.2 Absolute-set - The absolute-set addressing mode assigns a 32-bit constant value to the specified general - register, then uses the assigned value as the effective memory address. For example: - R2 = memw(R1=##400000) // load R2 with word from addr 400000 - // and load R1 with value 400000 - memw(R3=##600000) = R4 // store R4 to word at addr 600000 - // and load R3 with value 600000 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 86 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.7.3 Absolute with register offset - The absolute with register offset addressing mode performs an arithmetic left shift of a 32- - bit general register value by the amount specified in a 2-bit unsigned immediate value, and - then adds the shifted result to an unsigned 32-bit constant value to create the 32-bit - effective memory address. For example: - R2 = memh(R3 << #3 + ##100000) // load R2 with signed halfword - // from addr [100000 + (R3 << 3)] - - The 32-bit constant value is the base address, and the shifted result is the byte offset. - - NOTE This addressing mode is useful for loading an element from a global table, - where the immediate value is the name of the table, and the register holds the - index of the element. - - - 5.7.4 Global pointer relative - The global pointer relative addressing mode adds an unsigned offset value to the Hexagon - processor global data pointer GP to create the 32-bit effective memory address. This - addressing mode is used to access global and static data in C. - - Global pointer relative addresses can be expressed two ways in assembly language: - -  By explicitly adding an unsigned offset value to register GP -  By specifying only an immediate value as the instruction operand - - For example: - R2 = memh(GP+#100) // load R2 with signed halfword - // from [GP + 100 bytes] - - R3 = memh(#2000) // load R3 with signed halfword - // from [GP + #2000 - _SDA_BASE] - - Specifying only an immediate value causes the assembler and linker to automatically - subtract the value of the special symbol _SDA_BASE_ from the immediate value, and use - the result as the effective offset from GP. - - The global data pointer is programmed in the GDP field of register GP (Section 2.2.8). - This field contains an unsigned 26-bit value which specifies the most significant 26 bits of - the 32-bit global data pointer. (The least significant 6 bits of the pointer are defined to - always be zero.) - - The memory area referenced by the global data pointer is known as the global data area. It - can be up to 512 KB in length, and – because of the way the global data pointer is - defined – must be aligned to a 64-byte boundary in virtual memory. - - When expressed in assembly language, the offset values used in global pointer relative - addressing always specify byte offsets from the global data pointer. Note that the offsets - must be integral multiples of the size of the instruction data type. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 87 - Hexagon V62 Programmer's Reference Manual Memory - - - - Table 5-6 lists the offset ranges for global pointer relative addressing. - - Table 5-6 Offset ranges (Global pointer relative) - Offset Must Be - Data Type Offset Range - Multiple Of - doubleword 0 ... 524280 8 - word 0 ... 262140 4 - halfword 0 ... 131070 2 - byte 0 ... 65535 1 - - - NOTE When using global pointer relative addressing, the immediate operand should - be a symbol in the .sdata or .sbss section to ensure that the offset is valid. - - - 5.7.5 Indirect - The indirect addressing mode uses a 32-bit value stored in a general register as the - effective memory address. For example: - R2 = memub(R1) // load R2 with unsigned byte from addr R1 - - - - 5.7.6 Indirect with offset - The indirect with offset addressing mode adds a signed offset value to a general register - value to create the 32-bit effective memory address. For example: - R2 = memh(R3 + #100) // load R2 with signed halfword - // from [R3 + 100 bytes] - - When expressed in assembly language, the offset values always specify byte offsets from - the general register value. Note that the offsets must be integral multiples of the size of the - instruction data type. - - Table 5-7 lists the offset ranges for indirect with offset addressing. - - Table 5-7 Offset ranges (Indirect with offset) - Offset Must Be - Data Type Offset Range - Multiple Of - doubleword -8192 ... 8184 8 - word -4096 ... 4092 4 - halfword -2048 ... 2046 2 - byte -1024 ... 1023 1 - - - NOTE The offset range is smaller for conditional instructions (Section 5.8). - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 88 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.7.7 Indirect with register offset - The indirect with register offset addressing mode adds a 32-bit general register value to - the result created by performing an arithmetic left shift of a second 32-bit general register - value by the amount specified in a 2-bit unsigned immediate value, forming the 32-bit - effective memory address. For example: - R2 = memh(R3+R4<<#1) // load R2 with signed halfword - // from [R3 + (R4 << 1)] - - The register values always specify byte addresses. - - - 5.7.8 Indirect with auto-increment immediate - The indirect with auto-increment immediate addressing mode uses a 32-bit value stored in - a general register to specify the effective memory address. However, after the address is - accessed, a signed value (known as the increment) is added to the register so it specifies a - different memory address (which will be accessed in a subsequent instruction). For - example: - R2 = memw(R3++#4) // R3 contains the effective address - // R3 is then incremented by 4 - - When expressed in assembly language, the increment values always specify byte offsets - from the general register value. Note that the offsets must be integral multiples of the size - of the instruction data type. - - Table 5-8 lists the increment ranges for indirect with auto-increment immediate - addressing. - - Table 5-8 Increment ranges (Indirect with auto-inc immediate) - Increment Increment Must Be - Data Type - Range Multiple Of - doubleword -64 ... 56 8 - word -32 ... 28 4 - halfword -16 ... 14 2 - byte -8 ... 7 1 - - - - 5.7.9 Indirect with auto-increment register - The indirect with auto-increment register addressing mode is functionally equivalent to - indirect with auto-increment immediate, but uses a modifier register Mx (Section 2.2.4) - instead of an immediate value to hold the increment. For example: - R2 = memw(R0++M1) // The effective addr is the value of R0. - // Next, M1 is added to R0 and the result - // is stored in R0. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 89 - Hexagon V62 Programmer's Reference Manual Memory - - - - When auto-incrementing with a modifier register, the increment is a signed 32-bit value - which is added to the general register. This offers two advantages over auto-increment - immediate: - -  A larger increment range -  Variable increments (since the modifier register can be programmed at runtime) - - The increment value always specifies a byte offset from the general register value. - - NOTE The signed 32-bit increment range is identical for all instruction data types - (doubleword, word, halfword, byte). - - - 5.7.10 Circular with auto-increment immediate - The circular with auto-increment immediate addressing mode is a variant of indirect with - auto-increment addressing – it accesses data buffers in a modulo wrap-around fashion. - Circular addressing is commonly used in data stream processing. - - Circular addressing is expressed in assembly language with the address modifier - “:circ(Mx)”, where Mx specifies a modifier register which is programmed to specify - the circular buffer (Section 2.2.4). For example: - R0 = memb(R2++#4:circ(M0)) // load from R2 in circ buf specified - // by M0 - memw(R2++#8:circ(M1)) = R0 // store to R2 in circ buf specified - // by M1 - - Circular addressing is set up by programming the following elements: -  The Length field of the Mx register is set to the length (in bytes) of the circular - buffer to be accessed. A circular buffer can be from 4 to (128K-1) bytes long. -  The K field of the Mx register is always set to 0. -  The circular start register CSx that corresponds to Mx (CS0 for M0, CS1 for M1) - is set to the start address of the circular buffer. - - In circular addressing, after memory is accessed at the address specified in the general - register, the general register is incremented by the immediate increment value and then - modulo’d by the circular buffer length to implement wrap-around access of the buffer. - - When expressed in assembly language, the increment values always specify byte offsets - from the general register value. Note that the offsets must be integral multiples of the size - of the instruction data type. - - Table 5-9 lists the increment ranges for circular with auto-increment immediate - addressing. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 90 - Hexagon V62 Programmer's Reference Manual Memory - - - - Table 5-9 Increment ranges (Circular with auto-inc immediate) - Increment Increment Must Be - Data Type - Range Multiple Of - doubleword -64 ... 56 8 - word -32 ... 28 4 - halfword -16 ... 14 2 - byte -8 ... 7 1 - - - When programming a circular buffer the following rules apply: -  The start address must be aligned to the native access size of the buffer elements. - -  ABS(Increment) < Length. The absolute value of the increment must be less than - the buffer length. -  Access size < (Length-1). The memory access size (1 for byte, 2 for halfword, 4 - for word, 8 for doubleword) must be less than (Length-1). -  Buffers must not wrap around in the 32-bit address space. - - NOTE If any of these rules are not followed the execution result is undefined. - - For example, a 150-byte circular buffer can be set up and accessed as follows: - R4.H = #0 // K = 0 - R4.L = #150 // length = 150 - M0 = R4 - R2 = ##cbuf // start addr = cbuf - CS0 = R2 - R0 = memb(R2++#4:circ(M0)) // Load byte from circ buf - // specified by M0/CS0 - // inc R2 by 4 after load - // wrap R2 around if >= 150 - - The following C function precisely describes the behavior of the circular add function: - unsigned int - fcircadd(unsigned int pointer, int offset, - unsigned int M_reg, unsigned int CS_reg) - { - unsigned int length; - int new_pointer, start_addr, end_addr; - - length = (M_reg&0x01ffff); // lower 17-bits gives buffer size - new_pointer = pointer+offset; - start_addr = CS_reg; - end_addr = CS_reg + lenth; - if (new_pointer >= end_addr) { - new_pointer -= length; - } else if (new_pointer < start_addr) { - new_pointer += length; - } - return (new_pointer); - } - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 91 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.7.11 Circular with auto-increment register - The circular with auto-increment register addressing mode is functionally equivalent to - circular with auto-increment immediate, but uses a register instead of an immediate value - to hold the increment. - - Register increments are specified in circular addressing instructions by using the symbol I - as the increment (instead of an immediate value). For example: - R0 = memw(R2++I:circ(M1)) // load byte with incr of I*4 from - // circ buf specified by M1/CS1 - - When auto-incrementing with a register, the increment is a signed 11-bit value which is - added to the general register. This offers two advantages over circular addressing with - immediate increments: - -  Larger increment ranges -  Variable increments (since the increment register can be programmed at runtime) - - The circular register increment value is programmed in the I field of the modifier register - Mx (Section 2.2.4) as part of setting up the circular data access. This register field holds the - signed 11-bit increment value. - - Increment values are expressed in units of the buffer element data type, and are - automatically scaled at runtime to the proper data access size. - - Table 5-10 lists the increment ranges for circular with auto-increment register addressing. - - Table 5-10 Increment ranges (Circular with auto-inc register) - Increment Increment Must Be - Data Type - Range Multiple Of - doubleword -8192 ... 8184 8 - word -4096 ... 4092 4 - halfword -2048 ... 2046 2 - byte -1024 ... 1023 1 - - - When programming a circular buffer (with either a register or immediate increment), all - the rules that apply to circular addressing must be followed – for details see - Section 5.7.10. - - NOTE If any of these rules are not followed the execution result is undefined. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 92 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.7.12 Bit-reversed with auto-increment register - The bit-reversed with auto-increment register addressing mode is a variant of indirect with - auto-increment addressing – it accesses data buffers using an address value which is the - bit-wise reversal of the value stored in the general register. Bit-reversed addressing is used - in fast Fourier transforms (FFT) and Viterbi encoding. - - The bit-wise reversal of a 32-bit address value is defined as follows: - -  The lower 16 bits are transformed by exchanging bit 0 with bit 15, bit 1 with bit - 14, and so on. -  The upper 16 bits remain unchanged. - - Bit-reversed addressing is expressed in assembly language with the address modifier - “:brev”. For example: - R2 = memub(R0++M1:brev) // The address is (R0.H | bitrev(R0.L)) - // The orginal R0 (not reversed) is added - // to M1 and written back to R0 - - The initial values for the address and increment must be set in bit-reversed form, with the - hardware bit-reversing the bit-reversed address value to form the effective address. - - The buffer length for a bit-reversed buffer must be an integral power of 2, with a - maximum length of 64K bytes. - - To support bit-reversed addressing, buffers must be properly aligned in memory. A bit- - reversed buffer is properly aligned when its starting byte address is aligned to a power of 2 - greater than or equal to the buffer size (in bytes). For example: - int bitrev_buf[256] __attribute__((aligned(1024))); - - The bit-reversed buffer declared above is aligned to 1024 bytes because the buffer size is - 1024 bytes (256 integer words  4 bytes), and 1024 is an integral power of 2. - - The buffer location pointer for a bit-reversed buffer must be initialized so the least- - significant 16 bits of the address value are bit-reversed. - - The increment value must be initialized to the following value: - bitreverse(buffer_size_in_bytes / 2) - - ...where bitreverse is defined as bit-reversing the least-significant 16 bits while leaving - the remaining bits unchanged. - - NOTE To simplify the initialization of the bit-reversed pointer, bit-reversed buffers - can be aligned to a 64K byte boundary. This has the advantage of allowing the - bit-reversed pointer to be initialized to the base address of the bit-reversed - buffer, with no bit-reversing required for the least-significant 16 bits of the - pointer value (which are all set to 0 by the 64K alignment). - - Since buffers allocated on the stack only have an alignment of 8 bytes or less, - in most cases bit-reversed buffers should not be declared on the stack. - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 93 - Hexagon V62 Programmer's Reference Manual Memory - - - - After a bit-reversed memory access is completed, the general register is incremented by - the register increment value. Note that the value in the general register is never affected by - the bit-reversal that is performed as part of the memory access. - - NOTE The Hexagon processor supports only register increments for bit-reversed - addressing – it does not support immediate increments. - - - 5.8 Conditional load/stores - Some load and store instructions can be executed conditionally based on predicate values - which were set in a previous instruction. The compiler generates conditional loads and - stores to increase instruction-level parallelism. - - Conditional loads and stores are expressed in assembly language with the instruction - prefix “if (pred_expr)”, where pred_expr specifies a predicate register expression - (Section 6.1). For example: - if (P0) R0 = memw(R2) // conditional load - if (!P2) memh(R3 + #100) = R1 // conditional store - if (P1.new) R3 = memw(R3++#4) // conditional load - - Not all addressing modes are supported in conditional loads and stores. Table 5-11 shows - which modes are supported. - - Table 5-11 Addressing modes (Conditional load/store) - Addressing Mode Conditional - Absolute Yes - Absolute-set No - Absolute with register offset No - Global pointer relative No - Indirect Yes - Indirect with offset Yes - Indirect with register offset Yes - Indirect with auto-increment immediate Yes - Indirect with auto-increment register No - Circular with auto-increment immediate No - Circular with auto-increment register No - Bit-reversed with auto-increment register No - - - When a conditional load or store instruction uses indirect-with-offset addressing mode, - note that the offset range is smaller than the range normally defined for indirect-with- - offset addressing (Section 5.7.6). - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 94 - Hexagon V62 Programmer's Reference Manual Memory - - - - Table 5-12 lists the conditional and normal offset ranges for indirect-with-offset - addressing. - - Table 5-12 Conditional offset ranges (Indirect with offset) - Offset Range Offset Range Offset Must Be - Data Type - (Conditional) (Normal) Multiple Of - doubleword 0 ... 504 -8192 ... 8184 8 - word 0 ... 252 -4096 ... 4092 4 - halfword 0 ... 126 -2048 ... 2046 2 - byte 0 ... 63 -1024 ... 1023 1 - - - NOTE For more information on conditional execution see Chapter 6. - - - 5.9 Cache memory - The Hexagon processor has a cache-based memory architecture: - -  A level 1 instruction cache holds recently-fetched instructions. -  A level 1 data cache holds recently-accessed data memory. - - Load/store operations that access memory through the level 1 caches are referred to as - cached accesses. - - Load/stores that bypass the level 1 caches are referred to as uncached accesses. - - Specific memory areas can be configured so they perform cached or uncached accesses. - This configuration is performed by the Hexagon processor’s memory management unit - (MMU). The operating system is responsible for programming the MMU. - - Two types of caching are supported (as cache modes): - -  Write-through caching keep the cache data consistent with external memory by - always writing to the memory any data that is stored in the cache. -  Write-back caching allows data to be stored in the cache without being - immediately written to external memory. Cached data that is inconsistent with - external memory is referred to as dirty. - - The Hexagon processor includes dedicated cache maintenance instructions which can be - used to push dirty data out to external memory. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 95 - Hexagon V62 Programmer's Reference Manual Memory - - - - Table 5-13 lists the cache sizes for the V6x processor versions. - - Table 5-13 Hexagon processor cache size - Processor L1 instruction L1 data L2 - version cache cache cache - V60 16KB 32KB 256KB - V61 32KB 32KB 768KB 1 - 1 512K L2$ + 256K TCM - - - - - 5.9.1 Uncached memory - In some cases load/store operations need to bypass the cache memories and be serviced - externally (for example, when accessing memory-mapped I/O, registers, and peripheral - devices, or other system defined entities). The operating system is responsible for - configuring the MMU to generate uncached memory accesses. - - Uncached memory is categorized into two distinct types: - -  Device-type is for accessing memory that has side-effects (such as a memory- - mapped FIFO peripheral). The hardware ensures that interrupts do not cancel a - pending device access. The hardware does not re-order device accesses. - Peripheral control registers should be marked as device-type. -  Uncached-type is for memory-like memory. No side effects are associated with an - access. The hardware can load from uncached memory multiple times. The - hardware can re-order uncached accesses. - - For instruction accesses, device-type memory is functionally identical to uncached-type - memory. For data accesses, they are different. - - Code can be executed directly from the L2 cache, bypassing the L1 cache. - - - 5.9.2 Tightly coupled memory - The Hexagon processor supports tightly-coupled instruction memory at Level 1, which is - defined as memory with similar access properties to the instruction cache. - - Tightly-coupled memory is also supported at level 2, which is defined as backing store to - the primary caches. - - For more information see Chapter 9. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 96 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.9.3 Cache maintenance operations - The Hexagon processor includes dedicated cache maintenance instructions which can be - used to invalidate cache data or push dirty data out to external memory. - - The cache maintenance instructions operate on specific memory addresses. If the - instruction causes an address error (due to a privilege violation), the processor raises an - exception. - - NOTE The exception to this rule is dcfetch, which never causes a processor - exception. - - Whenever maintenance operations are performed on the instruction cache, the isync - instruction (Section 5.10) must be executed immediately afterwards. This instruction - ensures that the maintenance operations will be observed by subsequent instructions. - - Table 5-14 lists the cache maintenance instructions. - - Table 5-14 Cache instructions (User-level) - Permitted In - Syntax Operation - Packet - icinva(Rs) Solo 1 Instruction cache invalidate. - Look up instruction cache at address Rs. - If address is in cache, invalidate it. - dccleaninva(Rs) Slot 1 Data cache clean and invalidate. - empty or Look up data cache at address Rs. - ALU32 only If address is in cache and has dirty data, flush that - data out to memory. The cache line is then - invalidated, whether or not dirty data was written. - dccleana(Rs) Slot 1 Data cache clean. - empty or Look up data cache at address Rs. - ALU32 only If address is in cache and has dirty data, flush that - data out to memory. - dcinva(Rs) Slot 1 Equivalent to dccleaninva(Rs). - empty or - ALU32 only - dcfetch(Rs) Normal 2 Data cache prefetch. - Prefetch data at address Rs into data cache. - NOTE - This instruction will not cause an exception. - l2fetch(Rs,Rt) ALU32 or L2 cache prefetch. - XTYPE only Prefetch data from memory specified by Rs and Rt - into L2 cache. - 1 Solo means that the instruction must not be grouped with other instructions in a packet. - 2 Normal means that the normal instruction-grouping constraints apply. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 97 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.9.4 L2 cache operations - The cache maintenance operations (Section 5.9.3) operate on both the L1 and L2 caches. - - The data cache coherency operations (including clean, invalidate, and clean and - invalidate) affect both the L1 and L2 caches, and ensure that the memory hierarchy - remains coherent. - - However, the instruction cache invalidate operation affects only the L1 cache. Therefore, - invalidating instructions that may be in the L1 or L2 caches requires a two-step procedure: - - 1. Use icinva to invalidate instructions from the L1 cache. - 2. Use dcinva separately to invalidate instructions from the L2 cache. - - - 5.9.5 Cache line zero - The Hexagon processor includes the instruction dczeroa. This instruction allocates a line - in the L1 data cache and clears it (by storing all zeros). The behavior is as follows: - -  The Rs register value must be 32-byte aligned. If it is unaligned, the processor will - raise an unaligned error exception. -  In the case of a cache hit, the specified cache line is cleared (i.e., written with all - zeros) and made dirty. -  In the case of a cache miss, the specified cache line is not fetched from external - memory. Instead, the line is allocated in the data cache, cleared, and made dirty. - - This instruction is useful in optimizing write-only data. It allows for the use of write-back - pages – which are the most power and performance efficient – without the need to initially - fetch the line to be written. This removes unnecessary read bandwidth and latency. - - NOTE dczeroa has the same exception behavior as write-back stores. - - A packet with dczeroa must have Slot 1 either empty or containing an - ALU32 instruction. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 98 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.9.6 Cache prefetch - The Hexagon processor supports the following types of cache prefetching: - -  Hardware-based instruction cache prefetching -  Software-based data cache prefetching -  Software-based L2FETCH -  Hardware-based data cache prefetching - - Hardware-based instruction cache prefetching - - L1 and L2 instruction cache prefetching can be enabled or disabled on a per-thread basis – - this is done by setting the HFI field in the user status register (Section 2.2.3). - - Software-based data cache prefetching - - The Hexagon processor includes the instruction dcfetch. This instruction queries the L1 - data cache based on the address specified in the instruction: - -  If the address is present in the cache, no action is taken. -  If the cache line for the address is missing, the processor attempts to fill the cache - line from the next level of memory. Note that the thread does not stall, but rather - continues executing while the cache line fill occurs in the background. -  If the address is invalid, no exception is generated and the dcfetch instruction is - treated as a NOP. - - Software-based L2FETCH - - More powerful L2 prefetching – of data or instructions – is provided by the l2fetch - instruction, which specifies an area of memory that is prefetched by the Hexagon - processor’s hardware prefetch engine. l2fetch specifies two registers (Rs and Rt) as - operands. Rs contains the 32-bit virtual start address of the memory area to be prefetched. - Rt contains three bit fields which further specify the memory area: - -  Rt[15:8] – Width, which specifies the width (in bytes) of a block of memory to - fetch. -  Rt[7:0] – Height, which specifies the number of Width-sized blocks to fetch. -  Rt[31:16] – Stride, which specifies an unsigned byte offset that is used to - increment the pointer after each Width-sized block is fetched. - - The l2fetch instruction is non-blocking: it initiates a prefetch operation which is - performed in the background by the prefetch engine while the thread continues to execute - Hexagon processor instructions. - - The prefetch engine requests all lines in the specified memory area. If the line(s) of - interest are already resident in the L2 cache, the prefetch engine performs no action. If the - lines are not in the L2 cache, the prefetch engine attempts to fetch them. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 99 - Hexagon V62 Programmer's Reference Manual Memory - - - - The prefetch engine makes a best effort to prefetch the requested data, and attempts to - perform prefetching at a lower priority than demand fetches. This prevents the prefetch - engine from adding bus traffic when the system is under a heavy load. - - If a program executes an l2fetch instruction while the prefetch operation from a - previous l2fetch is still active, the prefetch engine halts the current prefetch operation. - - NOTE Executing l2fetch with any bit field operand programmed to zero will - cancel all prefetch activity. - - The status of the current prefetch operation is maintained in the PFA field of the user - status register (Section 2.2.3). This field can be used to determine whether or not a - prefetch operation has completed. - - With respect to MMU permissions and error checking, the l2fetch instruction behaves - similarly to a load instruction. If the virtual address causes a processor exception, the - exception will be taken. (Note that this differs from the dcfetch instruction, which is - treated as a NOP in the presence of a translation/protection error.) - - NOTE Prefetches are dropped when the generated prefetch address resides on a - different page than the start address. The programmer must use sufficiently - large pages to ensure this does not occur. - - Figure 5-2 shows two examples of using the l2fetch instruction. The first shows a ‘box’ - prefetch, where a 2-D range of memory is defined within a larger frame. The second - example shows a prefetch for a large linear memory area of size (Lines * 128). - - - L2FETCH for box prefetch L2FETCH for large linear prefetch - - 31 31 16 15 8 7 0 - 16 15 8 7 0 - - Rt Stride Width Height Rt 128 128 Lines - - - - Rs Start Address Rs Start Address - - - - Stride - - - - Width - - - Prefetch - Height 128* Lines - Area - - - - - Figure 5-2 L2FETCH instruction - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 100 - Hexagon V62 Programmer's Reference Manual Memory - - - - Hardware-based data cache prefetching - - L1 data cache prefetching can be enabled or disabled on a per-thread basis – this is done - by setting the HFD field in the user status register (Section 2.2.3). - - When data cache prefetching is enabled, the Hexagon processor observes patterns of data - cache misses, and attempts to predict future misses based on any recurring patterns of - misses where the addresses are separated by a constant stride. If such patterns are found, - the processor attempts to automatically prefetch future cache lines. - - Data cache prefetching can be user-enabled at four levels of aggressiveness: - -  HFD = 00: No prefetching -  HFD = 01: Prefetch up to 4 lines for misses originating from a load, with a post- - update addressing mode that occurs within a hardware loop -  HFD = 10: Prefetch up to 4 lines for misses originating from loads that occur - within a hardware loop -  HFD = 11: Prefetch up to 8 lines for misses originating from loads - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 101 - Hexagon V62 Programmer's Reference Manual Memory - - - - 5.10 Memory ordering - Some devices may require synchronization of stores and loads when they are accessed. In - this case a set of processor instructions enable programmer control of the synchronization - and ordering of memory accesses. - - Table 5-15 lists the memory-ordering instructions. - - Table 5-15 Memory ordering instructions - Syntax Operation - isync Instruction synchronize. - This instruction should be executed after any instruction cache maintenance - operation. - syncht Synchronize transactions. - Perform “heavyweight” synchronization. Ensure that all previous program - transactions (e.g., memw_locked, cached and uncached load/store) have - completed before execution resumes past this instruction. - - - NOTE - In V61 syncht ensures that outstanding memory operations from all - threads are complete before the syncht instruction is committed. - barrier Set memory barrier. - Ensure proper ordering between the program accesses performed before the - instruction and those performed after the instruction. - All accesses before the barrier will be globally observable before any access - occurring after the barrier can be observed. - - - NOTE - In V61 barrier ensures that all outstanding memory operations from the - thread executing the barrier are complete before the instruction is committed. - - - Data memory accesses and program memory accesses are treated separately and held in - separate caches. Software should ensure coherency between data and program code if - necessary. - - For example, with generated or self-modified code, the modified code will be placed in the - data cache and may be inconsistent with program cache. The software must explicitly - force modified data cache lines to memory (either by using a write-through policy, or - through explicit cache clean instructions). A barrier instruction should then be used to - ensure completion of the stores. Finally, relevant instruction cache contents should be - invalidated so the new instructions can be re-fetched. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 102 - Hexagon V62 Programmer's Reference Manual Memory - - - - Here is the recommended code sequence to change and then execute an instruction: - ICINVA(R1) // clear code from instruction cache - ISYNC // ensure that ICINVA is finished - MEMW(R1)=R0 // write the new instruction - DCCLEANINVA(R1) // force data out of data cache - SYNCHT // ensure that it’s in memory - JUMPR R1 // can now execute code at R1 - - NOTE The memory-ordering instructions must not be grouped with other - instructions in a packet, otherwise the behavior is undefined. - - This code sequence differs from the one used in previous processor versions. - - - 5.11 Atomic operations - The Hexagon processor includes an LL/SC (Load Locked / Store Conditional) mechanism - to provide the atomic read-modify-write operation that is necessary to implement - synchronization primitives such as semaphores and mutexes. - - These primitives are used to synchronize the execution of different software programs - running concurrently on the Hexagon processor. They can also be used to provide atomic - memory support between the Hexagon processor and external blocks. - - Table 5-16 describes the atomic instructions. - - Table 5-16 Atomic instructions - Syntax Description - Rd = memw_locked(Rs) Load locked word. - Reserve lock on word at address Rs. - memw_locked(Rs,Pd) = Rt Store conditional word. - If no other atomic operation has been performed at - the address (i.e., atomicity is ensured), perform the - store to the word at address Rs and return TRUE in - Pd; otherwise return FALSE. - TRUE indicates that the LL and SC operations have - been performed atomically. - Rdd = memd_locked(Rs) Load locked doubleword. - Reserve lock on doubleword at address Rs. - memd_locked(Rs,Pd) = Rtt Store conditional doubleword. - If no other atomic operation has been performed at - the address (i.e., atomicity is ensured), perform the - store to the doubleword at address Rs and return - TRUE in Pd; otherwise return FALSE. - TRUE indicates that the LL and SC operations have - been performed atomically. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 103 - Hexagon V62 Programmer's Reference Manual Memory - - - - Here is the recommended code sequence to acquire a mutex: - // assume mutex address is held in R0 - // assume R1,R3,P0,P1 are scratch - - lockMutex: - R3 = #1 - lock_test_spin: - R1 = memw_locked(R0) // do normal test to wait - P1 = cmp.eq(R1,#0) // for lock to be available - if (!P1) jump lock_test_spin - memw_locked(R0,P0) = r3 // do store conditional (SC) - if (!P0) jump lock_test_spin // was LL and SC done atomically? - - Here is the recommended code sequence to release a mutex: - // assume mutex address is held in R0 - // assume R1 is scratch - - R1 = #0 - memw(R0) = R1 - - Atomic memX_locked operations are supported for external accesses that use the AXI bus - and support atomic operations. To perform load-locked operations with external memory, - the operating system must define the memory page as uncacheable, otherwise the - processor behavior is undefined. - - If a load locked operation is performed on an address that does not support atomic - operations, the behavior is undefined. - - For atomic operations on cacheable memory, the page attributes must be set to cacheable - and write-back, otherwise the behavior is undefined. Cacheable memory must be used - when threads need to synchronize with each other. - - NOTE External memX_locked operations are not supported on the AHB bus. If they - are performed on the AHB bus, the behavior is undefined. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 104 - 6 Conditional Execution - - - The Hexagon processor uses a conditional execution model based on compare instructions - that set predicate bits in one of four 8-bit predicate registers (P0-P3). These predicate bits - can be used to conditionally execute certain instructions. - - Conditional scalar operations examine only the least-significant bit in a predicate register, - while conditional vector operations examine multiple bits in the register. - - Branch instructions are the main consumers of the predicate registers. - - - 6.1 Scalar predicates - Scalar predicates are 8-bit values which are used in conditional instructions to represent - truth values: - -  0xFF represents true -  0x00 represents false - - The Hexagon processor provides the four 8-bit predicate registers P0-P3 to hold scalar - predicates (Section 2.2.5). These registers are assigned values by the predicate-generating - instructions, and examined by the predicate-consuming instructions. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 105 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - 6.1.1 Generating scalar predicates - The following instructions generate scalar predicates: - -  Compare byte, halfword, word, doubleword -  Compare single- and double-precision floating point -  Classify floating-point value -  Compare bitmask -  Bounds check -  TLB match -  Store conditional - - Table 6-1 lists the scalar predicate-generating instructions. - - Table 6-1 Scalar predicate-generating instructions - Syntax Operation - Pd = cmpb.eq(Rs,{Rt,#u8}) Equal (signed). - Pd = cmph.eq(Rs,{Rt,#s8}) Compare register Rs to Rt or a signed immediate for - Pd = [!]cmp.eq(Rs,{Rt,#s10}) equality. Assign Pd the resulting truth value. - Pd = cmp.eq(Rss,Rtt) - Pd = sfcmp.eq(Rs,Rt) - Pd = dfcmp.eq(Rss,Rtt) - Pd = cmpb.gt(Rs,{Rt,#s8} Greater than (signed). - Pd = cmph.gt(Rs,{Rt,#s8}) Compare register Rs to Rt or a signed immediate for - Pd = [!]cmp.gt(Rs,{Rt,#s10}) signed greater than. Assign Pd the resulting truth - Pd = cmp.gt(Rss,Rtt) value. - Pd = sfcmp.gt(Rs,Rt) - Pd = dfcmp.gt(Rss,Rtt) - Pd = cmpb.gtu(Rs,{Rt,#u7}) Greater than (unsigned). - Pd = cmph.gtu(Rs,{Rt,#u7}) Compare register Rs to Rt or an unsigned immediate - Pd = [!]cmp.gtu(Rs,{Rt,#u9}) for unsigned greater than. Assign Pd the resulting - Pd = cmp.gtu(Rss,Rtt) truth value. - Pd = cmp.ge(Rs,#s8) Greater than or equal (signed). - Pd = sfcmp.ge(Rs,Rt) Compare register Rs to Rt or a signed immediate for - Pd = dfcmp.ge(Rss,Rtt) signed greater than or equal. Assign Pd the resulting - truth value. - Pd = cmp.geu(Rs,#u8) Greater than or equal (unsigned). - Compare register Rs to an unsigned immediate for - unsigned greater than or equal. Assign Pd the - resulting truth value. - Pd = cmp.lt(Rs,Rt) Less than (signed). - Compare register Rs to Rt for signed less than. - Assign Pd the resulting truth value. - Pd = cmp.ltu(Rs,Rt) Less than (unsigned). - Compare register Rs to Rt for unsigned less than. - Assign Pd the resulting truth value. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 106 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - Table 6-1 Scalar predicate-generating instructions (Continued) - Pd = sfcmp.uo(Rs,Rt) Unordered (signed). - Pd = dfcmp.uo(Rss,Rtt) Determine if register Rs or Rt is set to the value NaN. - Assign Pd the resulting truth value. - Pd=sfclass(Rs,#u5) Classify value (signed). - Pd=dfclass(Rss,#u5) Determine if register Rs is set to any of the specified - classes. Assign Pd the resulting truth value. - Pd = [!]tstbit(Rs,{Rt,#u5}) Test if bit set. - Rt or an unsigned immediate specifies a bit position. - Test if the bit in Rs that is specified by the bit position - is set. Assign Pd the resulting truth value. - Pd = [!]bitsclr(Rs,{Rt,#u6}) Test if bits clear. - Rt or an unsigned immediate specifies a bitmask. - Test if the bits in Rs that are specified by the bitmask - are all clear. Assign Pd the resulting truth value. - Pd = [!]bitsset(Rs,Rt) Test if bits set. - Rt specifies a bitmask. - Test if the bits in Rs that are specified by the bitmask - are all set. Assign Pd the resulting truth value. - memw_locked(Rs,Pd) = Rt Store conditional. - memd_locked(Rs,Pd) = Rtt If no other atomic operation has been performed at - the address (i.e., atomicity is ensured), perform the - store to the word at address Rs. Assign Pd the - resulting truth value. - Pd = boundscheck(Rs,Rtt) Bounds check. - Determine if Rs falls in the numeric range defined by - Rtt. Assign Pd the resulting truth value. - Pd = tlbmatch(Rss,Rt) Determine if TLB entry in Rss matches the ASID:PPN - specified in Rt. Assign Pd the resulting truth value. - - - NOTE One of the compare instructions (cmp.eq) includes a variant which stores a - binary predicate value (0 or 1) in a general register not a predicate register. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 107 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - 6.1.2 Consuming scalar predicates - Certain instructions can be conditionally executed based on the value of a scalar predicate - (or alternatively specify a scalar predicate as an input to their operation). - - The conditional instructions that consume scalar predicates examine only the least- - significant bit of the predicate value. In the simplest case, this bit value directly determines - whether the instruction is executed: - -  1 indicates that the instruction is executed -  0 indicates that the instruction is not executed - - If a conditional instruction includes the operator ! in its predicate expression, then the - logical negation of the bit value determines whether the instruction is executed. - - Conditional instructions are expressed in assembly language with the instruction prefix - “if (pred_expr)”, where pred_expr specifies the predicate expression. For example: - if (P0) jump target // jump if P0 is true - if (!P2) R2 = R5 // assign register if !P2 is true - if (P1) R0 = sub(R2,R3) // conditionally subtract if P1 - if (P2) R0 = memw(R2) // conditionally load word if P2 - - The following instructions can be used as conditional instructions: - -  Jumps and calls (Section 7.3) -  Many load and store instructions (Section 5.8) -  Logical instructions (including AND/OR/XOR) -  Shift halfword -  32-bit add/subtract by register or short immediate -  Sign and zero extend -  32-bit register transfer and 64-bit combine word -  Register transfer immediate -  Deallocate frame and return - - When a conditional load or store is executed and the predicate expression is false, the - instruction is cancelled (including any exceptions that might occur). For example, if a - conditional load uses an address with a memory permission violation, and the predicate - expression is false, then the load does not execute and the exception is not raised. - - The mux instruction accepts a predicate as one of its basic operands: - Rd = mux(Ps,Rs,Rt) - - mux selects either Rs or Rt based on the least significant bit in Ps. If the least-significant - bit in Ps is a 1, then Rd is set to Rs, otherwise it is set to Rt. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 108 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - 6.1.3 Auto-AND predicates - If multiple compare instructions in a packet write to the same predicate register, the result - is the logical AND of the individual compare results. For example: - { - P0 = cmp(A) // if A && B then jump - P0 = cmp(B) - if (P0.new) jump:T taken_path - } - - To perform the corresponding OR operation, the following instructions can be used to - compute the negation of an existing compare (using De Morgan’s law): -  Pd = !cmp.{eq,gt}(Rs, {#s10,Rt} ) -  Pd = !cmp.gtu(Rs, {#u9,Rt} ) -  Pd = !tstbit(Rs, {#u5,Rt} ) -  Pd = !bitsclr(Rs, {#u6,Rt} ) -  Pd = !bitsset(Rs,Rt) - - Auto-AND predicates have the following restrictions: - -  If a packet contains endloopN, it cannot perform an auto-AND with predicate - register P3. -  If a packet contains a register transfer from a general register to a predicate - register, then no other instruction in the packet can write to the same predicate - register. (As a result, a register transfer to P3:0 or C5:4 cannot be grouped with - any other predicate-writing instruction.) -  The instructions spNloop0, decbin, tlbmatch, memw_locked, memd_locked, - add:carry, sub:carry, sfcmp, and dfcmp cannot be grouped with another - instruction that sets the same predicate register. - - NOTE A register transfer from a predicate register to a predicate register has the - same auto-AND behavior as a compare instruction. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 109 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - 6.1.4 Dot-new predicates - The Hexagon processor can generate and use a scalar predicate in the same instruction - packet (Section 3.3). This feature is expressed in assembly language by appending the - suffix “.new” to the specified predicate register. For example: - if (P0.new) R3 = memw(R4) - - To see how dot-new predicates are used, consider the following C statement and the - corresponding assembly code that is generated from it by the compiler: - - C statement - if (R2 == 4) - R3 = *R4; - else - R5 = 5; - - Assembly code - { - P0 = cmp.eq(R2,#4) - if (P0.new) R3 = memw(R4) - if (!P0.new) R5 = #5 - } - - In the assembly code a scalar predicate is generated and then consumed twice within the - same instruction packet. - - The following conditions apply to using dot-new predicates: - -  The predicate must be generated by an instruction in the same packet. The - assembler normally enforces this restriction, but if the processor executes a packet - that violates this restriction, the execution result is undefined. -  A single packet can contain both the dot-new and normal forms of predicates. The - normal form examines the old value in the predicate register, rather than the - newly-generated value. For example: - { - P0 = cmp.eq(R2,#4) - if (P0.new) R3 = memw(R4) // use newly-generated P0 value - if (P0) R5 = #5 // use previous P0 value - } - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 110 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - 6.1.5 Dependency constraints - Two instructions in an instruction packet should not write to the same destination register - (Section 3.3.5). An exception to this rule is if the two instructions are conditional, and - only one of them ever has the predicate expression value true when the packet is - executed. - - For example, the following packet is valid as long as P2 and P3 never both evaluate to - true when the packet is executed: - - { - if (P2) R3 = #4 // P2, P3, or both must be false - if (P3) R3 = #7 - } - - Because predicate values change at runtime, the programmer is responsible for ensuring - that such packets are always valid during program execution. If they are invalid, the - processor takes the following actions: - -  When writing to general registers, an error exception is raised. -  When writing to predicate or control registers, the result is undefined. - - - 6.2 Vector predicates - The predicate registers are also used for conditional vector operations. Unlike scalar - predicates, vector predicates contain multiple truth values which are generated by vector - predicate-generating operations. - - For example, a vector compare instruction compares each element of a vector and assigns - the compare results to a predicate register. Each bit in the predicate vector contains a truth - value indicating the outcome of a separate compare performed by the vector instruction. - - The vector mux instruction uses a vector predicate to selectively merge elements from two - separate vectors into a single destination vector. This operation is useful for enabling the - vectorization of loops with control flow (i.e., branches). - - The vector instructions that use predicates are described in the following sections. - - - 6.2.1 Vector compare - A vector compare instruction inputs two 64-bit vectors, performs separate compares for - each pair of vector elements, and generates a predicate value which contains a bit vector of - truth values. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 111 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - Figure 6-1 shows an example of a vector byte compare. - - - Rss - - - Rtt - - - cmp cmp cmp cmp cmp cmp cmp cmp - - - - - 1 0 1 0 1 0 1 0 Pd - 7 0 - - Figure 6-1 Vector byte compare - - In Figure 6-1 two 64-bit vectors of bytes (contained in Rss and Rtt) are being compared. - The result is assigned as a vector predicate to the destination register Pd. - - In the example vector predicate shown in Figure 6-1, note that every other compare result - in the predicate is true (i.e., 1). - - Figure 6-2 shows how a vector halfword compare generates a vector predicate. - - - Rss - - - Rtt - - - - - cmp cmp cmp cmp - - - - - 1 1 0 0 1 1 0 0 Pd - 7 0 - - Figure 6-2 Vector halfword compare - - In Figure 6-2 two 64-bit vectors of halfwords are being compared. The result is assigned - as a vector predicate to the destination register Pd. - - Because a vector halfword compare yields only four truth values, each truth value is - encoded as two bits in the generated vector predicate. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 112 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - 6.2.2 Vector mux instruction - A vector mux instruction is used to conditionally select the elements from two vectors. - The instruction takes as input two source vectors and a predicate register. For each byte in - the vector, the corresponding bit in the predicate register is used to choose from one of the - two input vectors. The combined result is written to the destination register. - - Figure 6-3 shows the operation of the vector mux instruction. - - - Rss - - - Rtt - - - mux mux mux mux mux mux mux mux - P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] - - - Rdd - - Figure 6-3 Vector mux instruction - - Table 6-2 defines the vector mux instruction. - - Table 6-2 Vector mux instruction - Syntax Operation - Rdd = vmux(Ps,Rss,Rtt) Select bytes from Rss and Rtt - - - Changing the order of the source operands in a mux instruction enables both senses of the - result to be formed. For example: - R1:0 = vmux(P0,R3:2,R5:4) // choose bytes from R3:2 if true - R1:0 = vmux(P0,R5:4,R3:2) // choose bytes from R3:2 if false - - NOTE By replicating the predicate bits generated by word or halfword compares, the - vector mux instruction can be used to select words or halfwords. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 113 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - 6.2.3 Using vector conditionals - Vector conditional support is used to vectorize loops with conditional statements. - - Consider the following C statement: - for (i=0; i<8; i++) { - if (A[i]) { - B[i] = C[i]; - } - } - - Assuming arrays of bytes, this code can be vectorized as follows: - R1:0 = memd(R_A) // R1:0 holds A[7]-A[0] - R3 = #0 // clear R3:2 - R2 = #0 - P0 = vcmpb.eq(R1:0,R3:2) // compare bytes in A to zero - R5:4 = memd(R_B) // R5:4 holds B[7]-B[0] - R7:6 = memd(R_C) // R7:6 holds C[7]-C[0] - R3:2 = vmux(P0,R7:6,R5:4) // if (A[i]) B[i]=C[i] - memd(R_B) = R3:2 // store B[7]-B[0] - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 114 - Hexagon V62 Programmer's Reference Manual Conditional Execution - - - - 6.3 Predicate operations - The Hexagon processor provides a set of operations for manipulating and moving - predicate registers. - - Table 6-3 lists the predicate register instructions. - - Table 6-3 Predicate register instructions - Syntax Operation - Pd = Ps Transfer predicate Ps to Pd - Pd = Rs Transfer register Rs to predicate Pd - Rd = Ps Transfer predicate Ps to register Rd - Pd = and(Ps,[!]Pt) Set Pd to bitwise AND of Ps and [NOT] Pt - Pd = or(Ps,[!]Pt) Set Pd to bitwise OR of Ps and [NOT] Pt - Pd = and(Ps, and(Pt,[!]Pu) Set Pd to AND of Ps and (AND of Pt and [NOT] Pu) - Pd = and(Ps, or(Pt,[!]Pu) Set Pd to AND of Ps and (OR of Pt and [NOT] Pu) - Pd = or(Ps, and(Pt,[!]Pu) Set Pd to OR of Ps and (AND of Pt and [NOT] Pu) - Pd = or(Ps, or(Pt,[!]Pu) Set Pd to OR of Ps and (OR of Pt and [NOT] Pu) - Pd = not(Ps) Set Pd to bitwise inversion of Ps - Pd = xor(Ps,Pt) Set Pd to bitwise exclusive OR of Ps and Pt - Pd = any8(Ps) Set Pd to 0xFF if any bit in Ps is 1, 0x00 otherwise - Pd = all8(Ps) Set Pd to 0x00 if any bit in Ps is 0, 0xFF otherwise - - - NOTE These instructions belong to instruction class CR. - - Predicate registers can be transferred to and from the general registers either - individually or as register quadruples (Section 2.2.5). - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 115 - 7 Program Flow - - - The Hexagon processor supports the following program flow facilities: - -  Conditional instructions -  Hardware loops -  Software branches -  Pauses -  Exceptions - - Software branches include jumps, calls, and returns. Several types of jumps are supported: - -  Speculative jumps -  Compare jumps -  Register transfer jumps -  Dual jumps - - - 7.1 Conditional instructions - Many Hexagon processor instructions can be conditionally executed. For example: - if (P0) R0 = memw(R2) // conditionally load word if P0 - if (!P1) jump label // conditionally jump if not P1 - - The following instructions can be specified as conditional: - -  Jumps and calls -  Many load and store instructions -  Logical instructions (including AND/OR/XOR) -  Shift halfword -  32-bit add/subtract by register or short immediate -  Sign and zero extend -  32-bit register transfer and 64-bit combine word -  Register transfer immediate -  Deallocate frame and return - - For more information, see Section 5.8 and Chapter 6. - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 116 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - 7.2 Hardware loops - The Hexagon processor includes hardware loop instructions which can perform loop - branches with zero overhead. For example: - loop0(start,#3) // loop 3 times - start: - { R0 = mpyi(R0,R0) } :endloop0 - - Two sets of hardware loop instructions are provided – loop0 and loop1 – to enable - hardware loops to be nested one level deep. For example: - // Sum the rows of a 100x200 matrix. - - loop1(outer_start,#100) - outer_start: - R0 = #0 - loop0(inner_start,#200) - inner_start: - R3 = memw(R1++#4) - { R0 = add(R0,R3) }:endloop0 - { memw(R2++#4) = R0 }:endloop1 - - The hardware loop instructions are used as follows: - -  For non-nested loops, loop0 is used. -  For nested loops, loop0 is used for the inner loop, and loop1 for the outer loop. - - NOTE If a program needs to create loops nested more than one level deep, the two - innermost loops can be implemented as hardware loops, with the remaining - outer loops implemented as software branches. - - Each hardware loop is associated with a pair of dedicated loop registers: - -  The loop start address register SAn is set to the address of the first instruction in - the loop (which is typically expressed in assembly language as a label). -  The loop count register LCn is set to a 32-bit unsigned value which specifies the - number of loop iterations to perform. When the PC reaches the end of the loop, - LCn is examined to determine whether the loop should repeat or exit. - - The hardware loop setup instruction sets both of these registers at once – typically there is - no need to set them individually. However, because the loop registers completely specify - the hardware loop state, they can be saved and restored (either automatically by a - processor interrupt or manually by the programmer), enabling a suspended hardware loop - to be resumed normally once its loop registers are reloaded with the saved values. - - The Hexagon processor provides two sets of loop registers for the two hardware loops: - -  SA0 and LC0 are used by loop0 - -  SA1 and LC1 are used by loop1 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 117 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - Table 7-1 lists the hardware loop instructions. - - Table 7-1 Loop instructions - Syntax Description - loopN(start, Rs) Hardware loop with register loop count. - Set registers SAn and LCn for hardware loop N: -  SAn is assigned the specified start address of the loop. -  LCn is assigned the value of general register Rs. - NOTE - The loop start operand is encoded as a PC-relative - immediate value. - loopN(start, #count) Hardware loop with immediate loop count. - Set registers SAn and LCn for hardware loop N: -  SAn is assigned the specified start address of the loop. -  LCn is assigned the specified immediate value (0-1023). - NOTE - The loop start operand is encoded as a PC-relative - immediate value. - :endloopN Hardware loop end instruction. - Performs the following operation: - if (LCn > 1) {PC = SAn; LCn = LCn-1} - - NOTE - This instruction appears in assembly as a suffix appended to - the last packet in the loop. It is encoded in the last packet. - SAn = Rs Set loop start address to general register Rs - LCn = Rs Set loop count to general register Rs - - - NOTE The loop instructions are assigned to instruction class CR. - - - 7.2.1 Loop setup - To set up a hardware loop, the loop registers SAn and LCn must be set to the proper values. - This can be done in two ways: - -  A loopN instruction -  Register transfers to SAn and LCn - - The loopN instruction performs all the work of setting SAn and LCn. For example: - loop0(start,#3) // SA0=&start, LC0=3 - start: - { R0 = mpyi(R0,R0) } :endloop0 - - In this example the hardware loop (consisting of a single multiply instruction) is executed - three times. The loop0 instruction sets register SA0 to the address value of label start, - and LC0 to 3. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 118 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - Loop counts are limited to the range 0-1023 when they are expressed as immediate values - in loopN. If the desired loop count exceeds this range, it must be specified as a register - value. For example: - - Using loopN: - R1 = #20000; - loop0(start,R1) // LC0=20000, SA0=&start - start: - { R0 = mpyi(R0,R0) } :endloop0 - - Using register transfers: - R1 = #20000 - LC0 = R1 // LC0=20000 - R1 = #start - SA0 = R1 // SA0=&start - start: - { R0 = mpyi(R0,R0) } :endloop0 - - If a loopN instruction is located too far from its loop start address, the PC-relative offset - value that is used to specify the start address can exceed the maximum range of the - instruction’s start-address operand. If this occurs, either move the loopN instruction closer - to the loop start, or specify the loop start address as a 32-bit constant (Section 10.9). For - example: - - Using 32-bit constants: - R1 = #20000; - loop0(##start,R1) // LC0=20000, SA0=&start - ... - - - - 7.2.2 Loop end - The loop end instruction indicates the last packet in a hardware loop. It is expressed in - assembly language by appending the packet with the symbol “:endloopN”, where N - specifies the hardware loop (0 or 1). For example: - loop0(start,#3) - start: - { R0 = mpyi(R0,R0) } :endloop0 // last packet in loop - - The last instruction in the loop must always be expressed in assembly language as a packet - (using curly braces), even if it is the only instruction in the packet. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 119 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - Nested hardware loops can specify the same instruction as the end of both the inner and - outer loops. For example: - // Sum the rows of a 100x200 matrix. - // Software pipeline the outer loop. - - p0 = cmp.gt(R0,R0) // p0 = false - loop1(outer_start,#100) - outer_start: - { if (p0) memw(R2++#4) = R0 - p0 = cmp.eq(R0,R0) // p0 = true - R0 = #0 - loop0(inner_start,#200) } - inner_start: - R3 = memw(R1++#4) - { R0 = add(R0,R3) }:endloop0:endloop1 - memw(R2++#4) = R0 - - Though endloopN behaves like a regular instruction (by implementing the loop test and - branch), note that it does not execute in any instruction slot, and does not count as an - instruction in the packet. Therefore a single instruction packet which is marked as a loop - end can perform up to six operations: - -  Four regular instructions (the normal limit for an instruction packet) -  The endloop0 test and branch -  The endloop1 test and branch - - NOTE The endloopN instruction is encoded in the instruction packet (Section 10.6). - - - 7.2.3 Loop execution - After a hardware loop is set up, the loop body always executes at least once regardless of - the specified loop count (because the loop count is not examined until the last instruction - in the loop). Therefore, if a loop needs to be optionally executed zero times, it must be - preceded with an explicit conditional branch. For example: - loop0(start,R1) - P0 = cmp.eq(R1,#0) - if (P0) jump skip - start: - { R0 = mpyi(R0,R0) } :endloop0 - skip: - - In this example a hardware loop is set up with the loop count in R1, but if the value in R1 - is zero a software branch skips over the loop body. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 120 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - After the loop end instruction of a hardware loop is executed, the Hexagon processor - examines the value in the corresponding loop count register: - -  If the value is greater than 1, the processor decrements the loop count register and - performs a zero-cycle branch to the loop start address. -  If the value is less than or equal to 1, the processor resumes program execution at - the instruction immediately following the loop end instruction. - - NOTE Because nested hardware loops can share the same loop end instruction, the - processor may examine both loop count registers in a single operation. - - - 7.2.4 Pipelined hardware loops - Software pipelined loops are common for VLIW architectures such as the Hexagon - processor. They offer increased code performance in loops by overlapping multiple loop - iterations. - - A software pipeline has three sections: - -  A prologue in which the loop is primed -  A kernel (or steady-state) portion -  An epilogue which drains the pipeline - - This is best illustrated with a simple example, as shown in Table 7-2. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 121 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - Table 7-2 Software pipelined loop - - - int foo(int *A, int *result) - { - int i; - for (i=0;i<100;i++) { - result[i]= A[i]*A[i]; - } - } - - - - foo: - { R3 = R1 - loop0(.kernel,#98) // Decrease loop count by 2 - } - R1 = memw(R0++#4) // 1st prologue stage - { R1 = memw(R0++#4) // 2nd prologue stage - R2 = mpyi(R1,R1) - } - .falign - .kernel: - { R1 = memw(R0++#4) // kernel - R2 = mpyi(R1,R1) - memw(R3++#4) = R2 - }:endloop0 - { R2 = mpyi(R1,R1) // 1st epilogue stage - memw(R3++#4) = R2 - } - memw(R3++#4) = R2 // 2nd epilogue stage - jumpr lr - - - - In Table 7-2 the kernel section of the pipelined loop performs three iterations of the loop - in parallel: - -  The load for iteration N+2 -  The multiply for iteration N+1 -  The store for iteration N - - One drawback to software pipelining is the extra code necessary for the prologue and - epilogue sections of a pipelined loop. - - To address this issue the Hexagon processor provides the spNloop0 instruction, where the - “N” in the instruction name indicates a digit in the range 1-3. For example: - P3 = sp2loop0(start,#10) // Set up pipelined loop - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 122 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - spNloop0 is a variant of the loop0 instruction: it sets up a normal hardware loop using - SA0 and LC0, but also performs the following additional operations: - -  When the spNloop0 instruction is executed, it assigns the truth value false to the - predicate register P3. -  After the associated loop has executed N times, P3 is automatically set to true. - - This feature (which is known as automatic predicate control) enables the store instructions - in the kernel section of a pipelined loop to be conditionally executed by P3 and thus – - because of the way spNloop0 controls P3 – not be executed during the pipeline warm-up. - This can reduce the code size of many software pipelined loops by eliminating the need - for prologue code. - - spNloop0 cannot be used to eliminate the epilogue code from a pipelined loop; however, - in some cases it is possible to do this through the use of programming techniques. - - Typically, the issue affecting the removal of epilogue code is load safety. If the kernel - section of a pipelined loop can safely access past the end of its arrays – either because it is - known to be safe, or because the arrays have been padded at the end – then epilogue code - is unnecessary. However, if load safety cannot be ensured, then explicit epilogue code is - required to drain the software pipeline. - - Table 7-3 shows how spNloop0 and load safety simplify the code shown in Table 7-2. - - Table 7-3 Software pipelined loop (using spNloop0) - - - int foo(int *A, int *result) - { - int i; - for (i=0;i<100;i++) { - result[i]= A[i]*A[i]; - } - } - - - - foo: - { // load safety assumed - P3 = sp2loop0(.kernel,#102) // set up pipelined loop - R3 = R1 - } - .falign - .kernel: - { R1 = memw(R0++#4) // kernel - R2 = mpyi(R1,R1) - if (P3) memw(R3++#4) = R2 - }:endloop0 - - jumpr lr - - - - NOTE The count value that spNloop0 uses to control the P3 setting is stored in the - user status register USR.LPCFG. - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 123 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - 7.2.5 Loop restrictions - Hardware loops have the following restrictions: - -  The loop setup packet in loopN or spNloop0 (Section 7.2.4) cannot contain a - speculative indirect jump, new-value compare jump, or dealloc_return. -  The last packet in a hardware loop cannot contain any program flow instructions - (including jumps or calls). -  The loop end packet in loop0 cannot contain any instruction that changes SA0 or - LC0. Similarly, the loop end packet in loop1 cannot contain any instruction that - changes SA1 or LC1. -  The loop end packet in spNloop0 cannot contain any instruction that changes P3. - - NOTE SA1 and LC1 can be changed at the end of loop0, while SA0 and LC0 can be - changed at the end of loop1. - - - 7.3 Software branches - Unlike hardware loops, software branches use an explicit instruction to perform a branch - operation. Software branches include the following instructions: - -  Jumps -  Calls -  Returns - - The target address for branch instructions can be specified as register indirect or PC- - relative offsets. PC-relative offsets are normally less than 32 bits, but can be specified as - 32 bits by using the appropriate syntax in the target operand (Section 7.3.4). - - Branch instructions can be unconditional or conditional, with the execution of conditional - instructions controlled by a predicate expression. - - Table 7-4 summarizes the software branch instructions. - - Table 7-4 Software branch instructions - Syntax Operation - [if (pred_expr)] jump label Branch to address specified by register Rs or PC-relative offset. - [if (pred_expr)] jumpr Rs Can be conditionally executed. - - [if (pred_expr)] call label Branch to address specified by register Rs or PC-relative offset. - [if (pred_expr)] callr Rs Store subroutine return address in link register LR. - Can be conditionally executed. - [if (pred_expr)] jumpr LR Branch to subroutine return address contained in link register LR. - Can be conditionally executed. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 124 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - 7.3.1 Jumps - Jump instructions change the program flow to a target address which can be specified by - either a register or a PC-relative immediate value. Jump instructions can be conditional - based on the value of a predicate expression. - - Table 7-5 lists the jump instructions. - - Table 7-5 Jump instructions - Syntax Operation - jump label Direct jump. - Branch to address specified by label. - Label is encoded as PC-relative signed immediate value. - jumpr Rs Indirect jump. - Branch to address contained in general register Rs. - if ([!]Ps) jump label Conditional jump. - if ([!]Ps) jumpr Rs Perform jump if predicate expression evaluates to true. - - - NOTE Conditional jumps can be specified as speculative (Section 7.4). - - - 7.3.2 Calls - Call instructions are used to jump to subroutines. The instruction performs a jump to the - target address and also stores the return address in the link register LR. - - The forms of call are functionally similar to jump instructions and include both PC- - relative and register indirect in both unconditional and conditional forms. - - Table 7-6 lists the call instructions. - - Table 7-6 Call instructions - Syntax Operation - call label Direct subroutine call. - Branch to address specified by label, and store return address in register - LR. Label is encoded as PC-relative signed immediate value. - callr Rs Indirect subroutine call. - Branch to address contained in general register Rs, and store return - address in register LR. - if ([!]Ps) call label Conditional call. - if ([!]Ps) callr Rs If predicate expression evaluates to true, perform subroutine call to - specified target address. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 125 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - 7.3.3 Returns - Return instructions are used to return from a subroutine. The instruction performs an - indirect jump to the subroutine return address stored in link register LR. - - Returns are implemented as jump register indirect instructions, and support both - unconditional and conditional forms. - - Table 7-7 lists the return instructions. - - Table 7-7 Return instructions - Syntax Operation - jumpr LR Subroutine return. - Branch to subroutine return address contained in link register - LR. - if ([!]Ps) jumpr LR Conditional subroutine return. - If predicate expression evaluates to true, perform subroutine - return to specified target address. - dealloc_return Subroutine return with stack frame deallocate. - Perform deallocframe operation (Section 8.5) and then - perform subroutine return to the target address loaded by - deallocframe from the link register. - if ([!]Ps) dealloc_return Conditional subroutine return with stack frame deallocate. - If predicate expression evaluates to true, perform - deallocframe and then subroutine return to the target - address loaded by deallocframe from the link register. - - - NOTE The link register LR is an alias of general register R31. Therefore subroutine - returns can be performed with the instruction jumpr R31. - - The conditional subroutine returns (including dealloc_return) can be - specified as speculative (Section 7.4). - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 126 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - 7.3.4 Extended branches - When a jump or call instruction specifies a PC-relative offset as the branch target, the - offset value is normally encoded in significantly less than 32 bits. This can limit the ability - for programs to specify “long” branches which span a large range of the processor’s - memory address space. - - To support long branches, the jump and call instructions have special versions which - encode a full 32-bit value as the PC-relative offset. - - NOTE Such instructions use an extra word to store the 32-bit offset (Section 10.9). - - The size of a PC-relative branch offset is expressed in assembly language by optionally - prefixing the target label with the symbol “##” or “#”: - -  “##” specifies that the assembler must use a 32-bit offset -  “#” specifies that the assembler must not use a 32-bit offset -  No “#” specifies that the assembler use a 32-bit offset only if necessary - - For example: - jump ##label // 32-bit offset - call #label // non 32-bit offset - jump label // offset size determined by assembler - - - - 7.3.5 Branches to and from packets - Instruction packets are atomic: even if they contain multiple instructions, they can be - referenced only by the address of the first instruction in the packet. Therefore, branches to - a packet can target only the packet’s first instruction. - - Packets can contain up to two branches (Section 7.7). The branch destination can target - the current packet or the beginning of another packet. - - A branch does not interrupt the execution of the current packet: all the instructions in the - packet are executed, even if they appear in the assembly source after the branch - instruction. - - If a packet is at the end of a hardware loop, it cannot contain a branch instruction. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 127 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - 7.4 Speculative jumps - Conditional instructions normally depend on predicates that are generated in a previous - instruction packet. However, dot-new predicates (Section 6.1.4) enable conditional - instructions to use a predicate generated in the same packet that contains the conditional - instruction. - - When dot-new predicates are used with a conditional jump, the resulting instruction is - called a speculative jump. For example: - { - P0 = cmp.eq(R9,#16) // single-packet compare-and-jump - IF (P0.new) jumpr:t R11 // ... enabled by use of P0.new - } - - Speculative jumps require the programmer to specify a direction hint in the jump - instruction, which indicates whether the conditional jump is expected to be taken or not. - - The hint is used to initialize the Hexagon processor’s dynamic branch predictor. Whenever - the predictor is wrong, the speculative jump instruction takes two cycles to execute instead - of one (due to a pipeline stall). - - Hints can improve program performance by indicating how speculative jumps are - expected to execute over the course of a program: the more often the specified hint - indicates how the instruction actually executes, the better the performance. - - Hints are expressed in assembly language by appending the suffix “:t” or “:nt” to the - jump instruction symbol. For example: - -  jump:t – The jump instruction will most often be taken - -  jump:nt – The jump instruction will most often be not taken - - In addition to dot-new predicates, speculative jumps also accept conditional arithmetic - expressions (=0, !=0, >=0, <=0) involving the general register Rs. - - Table 7-8 lists the speculative jump instructions. - - Table 7-8 Speculative jump instructions - Syntax Operation - if ([!]Ps.new) jump:t label Speculative direct jump. - if ([!]Ps.new) jump:nt label If predicate expression evaluates to true, jump to address - specified by label. - if ([!]Ps.new) jumpr:t Rs Speculative indirect jump. - if ([!]Ps.new) jumpr:nt Rs If predicate expression evaluates to true, jump to address in - register Rs. - if (Rs == #0) jump:t label Speculative direct jump. - if (Rs == #0) jump:nt label If predicate Rs = 0 is true, jump to address specified by label. - if (Rs != #0) jump:t label Speculative direct jump. - if (Rs != #0) jump:nt label If predicate Rs != 0 is true, jump to address specified by label. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 128 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - Table 7-8 Speculative jump instructions (Continued) - Syntax Operation - if (Rs >= #0) jump:t label Speculative direct jump. - if (Rs >= #0) jump:nt label If predicate Rs >= 0 is true, jump to address specified by - label. - if (Rs <= #0) jump:t label Speculative direct jump. - if (Rs <= #0) jump:nt label If predicate Rs <= 0 is true, jump to address specified by - label. - - - NOTE The hints :t and :nt interact with the predicate value to determine the - instruction cycle count. - - Speculative indirect jumps are not supported with register Rs predicates. - - - 7.5 Compare jumps - To reduce code size the Hexagon processor supports a compound instruction which - combines a compare with a speculative jump in a single 32-bit instruction. - - For example: - { - p0 = cmp.eq (R2,R5) // single-instr compare-and-jump - if (p0.new) jump:nt target // enabled by compound instr - } - - The register operands used in a compare jump are limited to R0-R7 or R16-R23 - (Table 10-3). - - The compare and jump instructions that can be used in a compare jump are limited to the - instructions listed in Table 7-9. The compare can use predicate P0 or P1, while the jump - must specify the same predicate that is set in the compare. - - A compare jump instruction is expressed in assembly source as two independent compare - and jump instructions in a packet. The assembler translates the two instructions into a - single compound instruction. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 129 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - - Table 7-9 Compare jump instructions - Compare Instruction Jump Instruction - Pd = cmp.eq (Rs, Rt) IF (Pd.new) jump:t label - Pd = cmp.gt (Rs, Rt) IF (Pd.new) jump:nt label - Pd = cmp.gtu (Rs, Rt) IF (!Pd.new) jump:t label - Pd = cmp.eq (Rs,#U5) IF (!Pd.new) jump:nt label - Pd = cmp.gt (Rs,#U5) - Pd = cmp.gtu (Rs,#U5) - Pd = cmp.eq (Rs,#-1) - Pd = cmp.gt (Rs,#-1) - Pd = tstbit (Rs, #0) - - - - 7.5.1 New-value compare jumps - A compare jump instruction can access a register that is assigned a new value in the same - instruction packet (Section 3.3). This feature is expressed in assembly language by the - following changes: - -  Appending the suffix “.new” to the new-value register in the compare -  Rewriting the compare jump so its constituent compare and jump operations - appear as a single conditional instruction - - For example: - // load-compare-and-jump packet enabled by new-value compare jump - - { - R0 = memw(R2+#8) - if (cmp.eq(R0.new,#0)) jump:nt target - } - - New-value compare jump instructions have the following restrictions: - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 130 - Hexagon V62 Programmer's Reference Manual Program Flow - - - -  They are limited to the instruction forms listed in Table 7-10. -  They cannot be combined with another jump instruction in the same packet. -  If an instruction produces a 64-bit result or performs a floating-point operation - (Section 1.3.4), its result registers cannot be used as the new-value register. -  If an instruction uses auto-increment or absolute-set addressing mode - (Section 5.7), its address register cannot be used as the new-value register. -  If the instruction that sets a new-value register is conditional (Section 6.1.2), it - must always be executed. - - If the specified jump direction hint is wrong (Section 7.4), a new-value compare jump - takes three cycles to execute instead of one. While this penalty is one cycle longer than in - a regular speculative jump, the overall performance is still better than using a regular - speculative jump (which must execute an extra packet in all cases). - - NOTE New-value compare jump instructions are assigned to instruction class NV, - which can execute only in Slot 0. The instruction that assigns the new value - must execute in Slot 1, 2, or 3. - - - - Table 7-10 New-value compare jump instructions - if ([!]cmp.eq (Rs.new, Rt)) jump:[hint] label - if ([!]cmp.gt (Rs.new, Rt)) jump:[hint] label - if ([!]cmp.gtu (Rs.new, Rt)) jump:[hint] label - - if ([!]cmp.gt (Rs, Rt.new)) jump:[hint] label - if ([!]cmp.gtu (Rs, Rt.new)) jump:[hint] label - if ([!]cmp.eq (Rs.new, #u5)) jump:[hint] label - if ([!]cmp.gt (Rs.new, #u5)) jump:[hint] label - if ([!]cmp.gtu (Rs.new ,#u5)) jump:[hint] label - - if ([!]cmp.eq (Rs.new, #-1)) jump:[hint] label - if ([!]cmp.gt (Rs.new, #-1)) jump:[hint] label - - if ([!]tstbit (Rs.new, #0)) jump:[hint] label - - - - 7.6 Register transfer jumps - To reduce code size the Hexagon processor supports a compound instruction which - combines a register transfer with an unconditional jump in a single 32-bit instruction. - - For example: - { - jump target // jump to label “target” - R1 = R2 // assign contents of reg R2 to R1 - } - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 131 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - The source and target register operands in the register transfer are limited to R0-R7 or - R16-R23 (Table 10-3). - - The target address in the jump is a scaled 9-bit PC-relative address value (as opposed to - the 22-bit value in the regular unconditional jump instruction). - - A register transfer jump instruction is expressed in assembly source as two independent - instructions in a packet. The assembler translates the instructions into a single compound - instruction. - - Table 7-11 lists the register transfer jump instructions. - - Table 7-11 Register transfer jump instructions - Syntax Operation - jump label; Rd=Rs Register transfer jump. - - Perform register transfer and branch to address specified by label. - Label is encoded as PC-relative 9-bit signed immediate value. - jump label; Rd=#u6 Register transfer immediate jump. - - Perform register transfer (of 6-bit unsigned immediate value) and - branch to address specified by label. - Label is encoded as PC-relative 9-bit signed immediate value. - - - - - 7.7 Dual jumps - Two software branch instructions (referred to here as “jumps”) can appear in the same - instruction packet, under the conditions listed in Table 7-12. - - The first jump is defined as the jump instruction at the lower address, and the second jump - as the jump instruction at the higher address. - - Unlike most packetized operations, dual jumps are not executed in parallel (Section 3.3.1). - Instead, the two jumps are processed in a well-defined order in a packet: - - 1. The predicate in the first jump is evaluated. - 2. If the first jump is taken, the second jump is ignored. - 3. If the first jump is not taken, the second jump is performed. - - - Table 7-12 Dual jump instructions - First jump Second jump - Instruction Description - in packet? in packet? - jump Direct jump No Yes - if ([!]Ps[.new]) jump Conditional jump Yes Yes - call Direct calls No Yes - if ([!]Ps) call - Pd=cmp.xx ; if ([!]Pd.new) jump Compare jump Yes Yes - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 132 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - Table 7-12 Dual jump instructions - First jump Second jump - Instruction Description - in packet? in packet? - if ([!]cmp.xx(Rs.new, Rt)) jump New-value compare jump No No - jumpr Indirect jumps No No - if ([!]Ps[.new]) jumpr Indirect calls - callr dealloc_return - if ([!]Ps) callr - dealloc_return - if ([!]Ps[.new]) dealloc_return - endloopN Hardware loop end No No - - - NOTE If a call is ignored in a dual jump, the link register LR is not changed. - - - 7.8 Hint indirect jump target - Because it obtains the jump target address from a register, the jumpr instruction - (Section 7.3.1) normally causes the processor to stall for one cycle. - - To avoid the stall penalty caused by a jumpr instruction, the Hexagon processor supports - the jump hint instruction hintjr, which can be specified before the jumpr instruction. - - The hintjr instruction indicates that the program is about to execute a jumpr to the - address contained in the specified register. - - Table 7-13 lists the speculative jump instructions. - - Table 7-13 Jump hint instruction - Syntax Operation - hintjr(Rs) Inform processor that jumpr(Rs) instruction is about to be - performed. - - - NOTE In order to prevent a stall, the hintjr instruction must be executed at least 2 - packets before the corresponding jumpr instruction. - - The hintjr instruction is not needed for jumpr instructions used as returns - (Section 7.3.3), because in this case the Hexagon processor automatically - predicts the jump targets based on the most recent nested call instructions. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 133 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - 7.9 Pauses - Pauses suspend the execution of a program for a period of time, and put it into low-power - mode. The program remains suspended for the duration specified in the instruction. - - The pause instruction accepts an unsigned 8-bit immediate operand which specifies the - pause duration in terms of cycles. The maximum possible duration is 263 cycles (255+8). - - Hexagon processor interrupts cause a program to exit the paused state before its specified - duration has elapsed. - - The pause instruction is useful for implementing user-level low-power synchronization - operations (such as spin locks). - - Table 7-14 lists the pause instruction. - - Table 7-14 Pause instruction - Syntax Operation - pause(#u8) Suspend program in low-power mode for specified cycle - duration. - - - - - 7.10 Exceptions - Exceptions are internally-generated disruptions to the program flow. - - The Hexagon processor OS handles fatal exceptions by terminating the execution of the - application system. The user is responsible for fixing the problem and recompiling their - applications. - - The error messages generated by exceptions include the following information to assist in - locating the problem: - -  Cause code – Hexadecimal value indicating the type of exception that occurred -  User IP – PC value indicating the instruction executed when exception occurred -  Bad VA – Virtual address indicating the data accessed when exception occurred - - NOTE The cause code, user IP, and Bad VA values are stored in the Hexagon - processor system control registers SSR[7:0], ELR, and BADVA respectively. - - If multiple exceptions occur simultaneously, the exception with the lowest error code - value has the highest exception priority. - - If a packet contains multiple loads, or a load and a store, and both operations have an - exception of any type, then all Slot 1 exceptions are processed before any Slot 0 exception - is processed. - - NOTE The exceptions defined for processor versions V60 and V61 are identical, - with one exception: V61 defines an additional event (with cause code 0x27) - to indicate stack overflow. - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 134 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - Table 7-15 lists the exceptions for the V60 and V61 processor versions. - - Table 7-15 V60/61 exceptions - Cause - Event Type Event Description Notes - Code - 0x0 Reset Software thread reset. Non-maskable, - Highest Priority - 0x01 Precise, Unrecoverable BIU error (bus error, timeout, L2 Non-maskable - Unrecoverable parity error, etc.). - 0x03 Precise, Double exception (exception occurs while Non-maskable - Unrecoverable SSR[EX]=1). - 0x11 Precise Privilege violation: User/Guest mode execute to Non-maskable - page with no execute permissions (X=0). - 0x12 Precise Privilege violation: User mode execute to a Non-maskable - page with no user permissions (X=1, U=0). - 0x15 Precise Invalid packet. Non-maskable - 0x16 Precise Illegal Execution of Coprocessor Instruction. Non-maskable - 0x1A Precise Privilege violation: Executing a guest mode Non-maskable - instruction in user mode. - 0x1B Precise Privilege violation: Executing a supervisor Non-maskable - instruction in user/guest mode. - 0x1D Precise, Packet with multiple writes to the same Non-maskable - Unrecoverable destination register. - 0x1E Precise, Program counter values that are not properly Non-maskable - Unrecoverable aligned. - 0x20 Precise Load to misaligned address. Non-maskable - 0x21 Precise Store to misaligned address. Non-maskable - 0x22 Precise Privilege violation: User/Guest mode Read to Non-maskable - page with no read permission (R=0). - 0x23 Precise Privilege violation: User/Guest mode Write to Non-maskable - page with no write permissions (W=0). - 0x24 Precise Privilege violation: User mode Read to page Non-maskable - with no user permission (R=1, U=0). - 0x25 Precise Privilege violation: User mode Write to page Non-maskable - with no user permissions (W=1, U=0). - 0x26 Precise Coprocessor VMEM address error. Non-maskable - 0x27 Precise Stack overflow: Allocframe instruction exceeded Non-maskable, - FRAMELIMIT. V61 and greater - 0x42 Imprecise Data abort. Non-maskable - 0x43 Imprecise NMI. Non-maskable - 0x44 Imprecise Multiple TLB match. Non-maskable - 0x45 Imprecise Livelock exception. Non-maskable - 0x60 TLB miss-X Due to missing Fetch address on PC-page. Non-maskable - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 135 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - Table 7-15 V60/61 exceptions (Continued) - Cause - Event Type Event Description Notes - Code - 0x61 TLB miss-X Due to missing Fetch on second page from Non-maskable - packet that spans pages. - 0x62 TLB miss-X Due to icinva. Non-maskable - Reserved - 0x70 TLB miss-RW Due to memory read. Non-maskable - 0x71 TLB miss-RW Due to memory write. Non-maskable - Reserved - #u8 Trap0 Software Trap0 instruction. Non-maskable - #u8 Trap1 Software Trap1 instruction. Non-maskable - Reserved - 0x80 Debug Single-step debug exception. - Reserved - 0xBF Floating-Point Execution of Floating-Point instruction resulted Non-maskable - in exception. - 0xC0 Interrupt0 General external interrupt. Maskable, highest - priority general - interrupt - 0xC1 Interrupt 1 General external interrupt Maskable - 0xC2 Interrupt 2 - 0xC3 Interrupt 3 - 0xC4 Interrupt 4 - 0xC5 Interrupt 5 - 0xC6 Interrupt 6 - 0xC7 Interrupt 7 - 0xC8 Interrupt 8 - 0xC9 Interrupt 9 - 0xCA Interrupt 10 - 0xCB Interrupt 11 - 0xCC Interrupt 12 - 0xCD Interrupt 13 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 136 - Hexagon V62 Programmer's Reference Manual Program Flow - - - - Table 7-15 V60/61 exceptions (Continued) - Cause - Event Type Event Description Notes - Code - 0xCE Interrupt 14 General external interrupt Maskable - 0xCF Interrupt 15 - 0xD0 Interrupt 16 - 0xD1 Interrupt 17 - 0xD2 Interrupt 18 - 0xD3 Interrupt 19 - 0xD4 Interrupt 20 - 0xD5 Interrupt 21 - 0xD6 Interrupt 22 - 0xD7 Interrupt 23 - 0xD8 Interrupt 24 - 0xD9 Interrupt 25 - 0xDA Interrupt 26 - 0xDB Interrupt 27 - 0xDC Interrupt 28 - 0xDD Interrupt 29 - 0xDE Interrupt 30 General external interrupt. Maskable, lowest - priority internal - interrupt - 0xDF Interrupt 31 General external interrupt. Maskable, lowest - priority interrupt - reserved for L2 - Vectored Interrupt - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 137 - 8 Software Stack - - - The Hexagon processor includes dedicated registers and instructions to support a call - stack for subroutine execution. - - The stack structure follows standard C conventions. - - - 8.1 Stack structure - The stack is defined to grow from high addresses to low addresses. The stack pointer - register SP points to the data element that is currently on the top of the stack. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 138 - Hexagon V62 Programmer's Reference Manual Software Stack - - - - Figure 8-1 shows the stack structure. - - Stack in Memory - - Saved LR - Saved FP - - - - - Higher Address - Procedure Local - Data on Stack - - Stack frame - - - - Saved LR - Saved FP FP register - - - - Procedure Local - Data on Stack - - SP register - Lower Address - - - - - Unallocated Stack - - - - - Figure 8-1 Stack structure - - NOTE The Hexagon processor supports three dedicated stack instructions: - allocframe, deallocframe, and dealloc_return (Section 8.5). - - The SP address must always remain 8-byte aligned for the stack instructions - to work properly. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 139 - Hexagon V62 Programmer's Reference Manual Software Stack - - - - 8.2 Stack frames - The stack is used to store stack frames, which are data structures that store state - information on the active subroutines in a program (i.e., those that were called but have - not yet returned). Each stack frame corresponds to an active subroutine in the program. - - A stack frame contains the following elements: - -  The local variables and data used by the subroutine -  The return address for the subroutine call (pushed from the link register LR) -  The address of the previous stack frame allocated on the stack (pushed from the - frame pointer register FP) - - The frame pointer register FP always contains the address of the saved frame pointer in - the current stack frame. It facilitates debugging by enabling a debugger to examine the - stack in memory and easily determine the call sequence, function parameters, etc. - - NOTE For leaf functions it is often unnecessary to save FP and LR. In this case FP - contains the frame pointer of the calling function, not the current function. - - - 8.3 Stack protection - The Hexagon V6x processor supports the following features to protect the integrity of the - software stack: - -  Stack bounds checking -  Stack smashing protection - - - 8.3.1 Stack bounds checking - Stack bounds checking prevents a stack frame from being allocated past the lower - boundary of the software stack. - - FRAMELIMIT is a 32-bit control register which stores a memory address that specifies the - lower bound of the memory area reserved for the software stack. When the allocframe - instruction allocates a new stack frame, it compares the new stack pointer value in SP with - the stack bound value in FRAMELIMIT. If SP is less than FRAMELIMIT, the Hexagon - processor raises exception 0x27 (Section 7.10). - - NOTE Stack bounds checking is performed when the processor is in user and guest - modes, but not in monitor mode. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 140 - Hexagon V62 Programmer's Reference Manual Software Stack - - - - 8.3.2 Stack smashing protection - Stack smashing is a technique used by malicious code to gain control over an executing - program. Malicious code causes buffer overflows to occur in a procedure’s local data, with - the goal of modifying the subroutine return address stored in a stack frame so it points to - the malicious code instead of the intended return code. - - Stack smashing protection prevents this from happening by scrambling the subroutine - return address whenever a new stack frame is allocated, and then unscrambling the return - address when the frame is deallocated. Because the value in FRAMEKEY changes regularly - and varies from device to device, it becomes difficult to pre-calculate a malicious return - address. - - FRAMEKEY is a 32-bit control register which is used to scramble return addresses stored on - the stack: - -  In the allocframe instruction, the 32-bit return address in link register LR is - XOR-scrambled with the value in FRAMEKEY before it is stored in the new stack - frame. -  In deallocframe and dealloc_return, the return address loaded from the stack - frame is unscrambled with the value in FRAMEKEY before it is stored in LR. - - After a processor reset, the default value of FRAMEKEY is 0. If this value is not changed, - stack smashing protection is effectively disabled. - - NOTE Each hardware thread has its own instance of the FRAMEKEY register. - - - 8.4 Stack registers - Table 8-1 lists the stack registers. - - - Table 8-1 Stack registers - Register Name Description Alias - SP Stack pointer Points to topmost stack element in memory R29 - FP Frame pointer Points to previous stack frame on stack R30 - LR Link register Contains return address of subroutine call R31 - FRAMELIMIT Frame limit register Contains lowest address of stack area C16 - FRAMEKEY Frame key register Contains scrambling key for return addresses C17 - - - NOTE SP, FP, and LR are aliases of three general registers (Section 2.1). These - general registers are conventionally dedicated for use as stack registers. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 141 - Hexagon V62 Programmer's Reference Manual Software Stack - - - - 8.5 Stack instructions - The Hexagon processor includes the instructions allocframe and deallocframe to - efficiently allocate and deallocate stack frames on the call stack. - - Table 8-2 describes these instructions. - - Table 8-2 Stack instructions - Syntax Operation - allocframe(#u11:3) Allocate stack frame. - This instruction is used after a call. It first XORs the values in LR - and FRAMEKEY, and pushes the resulting scrambled return - address and FP to the top of stack. - Next, it subtracts an unsigned immediate from SP in order to - allocate room for local variables. If the resulting SP is less than - FRAMELIMIT, the processor raises exception 0x27. Otherwise, - SP is set to the new value, and FP is set to the address of the - old frame pointer on the stack. - The immediate operand as expressed in assembly syntax - specifies the byte offset. This value must be 8-byte aligned. The - valid range is from 0 to 16 KB. - deallocframe Deallocate stack frame. - This instruction is used before a return in order to free a stack - frame. It first loads the saved FP and LR values from the - address at FP, and XORs the restored LR with the value in - FRAMEKEY to unscramble the return address. SPis then - pointed back to the previous frame. - dealloc_return Subroutine return with stack frame deallocate. - Perform deallocframe operation, and then perform - subroutine return (Section 7.3.3) to the target address loaded - from LR by deallocframe. - - - NOTE allocframe and deallocframe load and store the LR and FP registers on the - stack as a single aligned 64-bit register pair (i.e., LR:FP). - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 142 - 9 PMU Events - - The Hexagon processor can collect execution statistics on the applications it executes. The - statistics summarize the various types of Hexagon processor events that occurred while - the application was running. - - Execution statistics can be collected in hardware or software: - -  Statistics can be collected in hardware with the Performance Monitor Unit (PMU), - which is defined as part of the Hexagon processor architecture. -  Statistics can be collected in software using the Hexagon simulator. The simulator - statistics are presented in the same format used by the PMU. - - Execution statistics are expressed in terms of processor events. This chapter defines the - event symbols, along with their associated numeric codes. - - NOTE Because the types of execution events vary across the Hexagon processor - versions, different types of statistics are collected for each version. This - chapter lists the event symbols defined for version V62. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 143 - Hexagon V62 Programmer's Reference Manual PMU Events - - - - 9.1 V62 processor event symbols - Table 9-1 defines the symbols that are used to represent processor events for the V62 - Hexagon processor. - -Table 9-1 V62 processor event symbols - Event Symbol Definition - 0x00 No Do nothing. This event never causes a counter update. - 0x01 COUNTER0_OVERFLOW Counter0 overflow. This can be used as the event detected by - counter1 to build an effective 64-bit counter. - 0x02 COUNTER2_OVERFLOW Counter2 overflow. This can be used as the event detected by - counter3 to build an effective 64-bit counter. - 0x03 COMMITTED_PKT_ANY Thread committed a packet. Packets executed. - 0x04 COMMITTED_PKT_BSB Packet committed 2 cycles after previous packet in same thread. - 0x05 COUNTER4_OVERFLOW Counter4 overflow. This can be used as the event detected by - counter5 to build an effective 64-bit counter. - 0x06 COUNTER6_OVERFLOW Counter6 overflow. This can be used as the event detected by - counter7 to build an effective 64-bit counter. - 0x07 COMMITTED_PKT_B2B Packet committed 1 cycle after previous packet in same thread. - 0x08 COMMITTED_PKT_SMT 2 packets committed in the same cycle. - 0x12 ICACHE_DEMAND_MISS Icache demand miss. Includes secondary miss and dczero. - Excludes uncacheables, prefetch initiated misses, and predicate- - killed operations. - 0x13 DCACHE_DEMAND_MISS Dcache cacheable demand primary or secondary miss. Includes - dczero stall. Excludes uncacheables, prefetches, and no allocate - store misses. - 0x14 DCACHE_STORE_MISS Dcache cacheable store miss. - 0x17 CU_PKT_READY_NOT_DISPATCHED Packet ready at scheduler but not scheduled because a) its thread - was not picked or b) an intercluster resource conflict occurred. - 0x20 ANY_IU_REPLAY Any IU stall other than icache miss. Includes jump register stall, - fetchcross stall, itlb miss stall, etc. Excludes CU replay. - 0x21 ANY_DU_REPLAY Any DU replay. Bank conflict, dTLB miss, etc. Excludes stalls due - to cache misses. - 0x22 CU_REDISPATCH Any case where a packet is redispatched. Commonly a replay - requested for a non-replayable instruction or forwarding bus - resource conflict. - 0x25 COMMITTED_PKT_1_THREAD_ Committed packets with 1 thread running. Not in stop/wait. - RUNNING - 0x26 COMMITTED_PKT_2_THREAD_ Committed packets with 2 threads running. Not in stop/wait. - RUNNING - 0x27 COMMITTED_PKT_3_THREAD_ Committed packets with 3 threads running. Not in stop/wait. - RUNNING - 0x2a COMMITTED_INSTS Committed instructions. Increments by up to 8 per cycle. Duplex - counts as two instructions. Does not include endloops. - 0x2b COMMITTED_TC1_INSTS Committed tc1 class instructions. Increments by up to 8 per cycle. - Duplex of two tc1 instructions counts as two tc1 instructions. - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 144 - Hexagon V62 Programmer's Reference Manual PMU Events - - - -Table 9-1 V62 processor event symbols - Event Symbol Definition - 0x2c COMMITTED_PRIVATE_INSTS Committed instructions that have per-cluster (private) execution - resources. Increments by up to 8 per cycle. Duplex of two private - instructions counts as two private instructions. - 0x2f COMMITTED_PKT_4_THREAD_ Committed packets with 4 threads running. Not in stop/wait. - RUNNING - 0x30 COMMITTED_LOADS Committed load instructions. Includes cached and uncached. - Increments by 2 for dual loads. Excludes prefetches, memops. - 0x31 COMMITTED_STORES Committed store instructions. Includes cached and uncached. - Increments by 2 for dual stores. Excludes memops. - 0x32 COMMITTED_MEMOPS Committed memop instructions. Cached or uncached. - 0x37 COMMITTED_PROGRAM_FLOW_ Committed packet contains program flow inst. Includes cr jumps, - INSTS endloop, j, jr, dealloc_return, system/trap, superset of event 0x38. - Dual jumps count as two. - 0x38 COMMITTED_PKT_CHANGED_ Committed packet resulted in change-of-flow. Any taken jump, - FLOW includes endloop. - 0x39 COMMITTED_PKT_ENDLOOP Committed packet contains an endloop which was taken. - 0x3b CYCLES_1_THREAD_RUNNING Processor cycles that 1 thread is running. Not in wait or stop. - 0x3c CYCLES_2_THREAD_RUNNING Processor cycles that 2 threads are running. Not in wait or stop. - 0x3d CYCLES_3_THREAD_RUNNING Processor cycles that 3 threads are running. Not in wait or stop. - 0x3e CYCLES_4_THREAD_RUNNING Processor cycles that 4 threads are running. Not in wait or stop. - 0x40 AXI_READ_REQUEST All read requests issued by primary AXI master. Includes full line - and partial line. - 0x41 AXI_LINE32_READ_REQUEST 32-byte line read requests issued by primary AXI master. - 0x42 AXI_WRITE_REQUEST All write requests issued by primary AXI master. Includes full line - and partial line. - 0x43 AXI_LINE32_WRITE_REQUEST 32-byte line write requests issued by primary AXI master, all bytes - valid. - 0x44 AHB_READ_REQUEST Read requests issued by AHB master. - 0x45 AHB_WRITE_REQUEST Write requests issued by AHB master. - 0x47 AXI_SLAVE_MULTI_BEAT_ACCESS AXI slave multi-beat access. - 0x48 AXI_SLAVE_SINGLE_BEAT_ AXI slave single-beat access. - ACCESS - 0x49 AXI2_READ_REQUEST All read requests issued by secondary AXI master. Includes full - line and partial line. - 0x4a AXI2_LINE32_READ_REQUEST 32-byte line read requests issued by secondary AXI master - 0x4b AXI2_WRITE_REQUEST All write requests issued by secondary AXI master. Includes full - line and partial line. - 0x4c AXI2_LINE32_WRITE_REQUEST 32-byte line write requests issued by secondary AXI master. - 0x4d AXI2_CONGESTION Secondary AXI command or data queue is full and an operation is - stuck at the head of the secondary AXI master command queue. - 0x50 COMMITTED_FPS Committed floating point instructions. Increments by 2 for dual FP - ops. Excludes conversions. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 145 - Hexagon V62 Programmer's Reference Manual PMU Events - - - -Table 9-1 V62 processor event symbols - Event Symbol Definition - 0x51 BRANCH_MISPREDICT_DIRECTION Branch mispredict direction. Includes new-predicate, old- - predicate, low loop count, new-value, and dealloc_return direction - mispredicts. Only counts once if both jumps in a dual jump - mispredict. Excludes target mispredicts. - 0x52 BRANCH_MISPREDICT_TARGET Branch mispredict target. Includes RAS mispredict. Excludes - indirect jumps and calls other than JUMPR R31 returns. Excludes - direction mispredicts. - 0x58 JTLB_MISS Instruction or data address translation request missed in JTLB. - 0x5a COMMITTED_PKT_RETURN Committed a return instruction. Includes canceled returns. - 0x5b COMMITTED_PKT_INDIRECT_JUMP Committed an indirect jump or call instruction. Includes canceled - instructions. Does not include JUMPR R31 returns. - 0x5c COMMITTED_BIMODAL_ Committed bimodal branch. Includes .old and .new. Increments by - BRANCH_INSTS 2 for dual jumps. - 0x65 IU_DEMAND_SECONDARY_MISS Icache secondary miss. - 0x6b IU_PREFETCHES_SENT_TO_L2 IU prefetches sent to L2. Counts cachelines not dropped by L2. - Excludes replayed prefetches and only counts ones L2 accepts. - 0x6c ITLB_MISS ITLB miss. One per thread maximum. - 0x76 L2_IU_ACCESS L2 access from IU. Any access to L2 cache that was the result of - an IU command, either demand or L1 prefetch access. Excludes - L2 prefetches, TCM accesses, and uncacheables. - 0x77 L2_IU_MISS L2 misses from IU. Of the events qualified by 0x76, the ones that - resulted in an L2 miss (demand miss or L1 prefetch miss). - Includes hitting a reserved line. - 0x78 L2_IU_PREFETCH_ACCESS Pre-fetch from the IU to L2. Any IU pre-fetch access sent to the L2 - cache. Access must be L2 cacheable and target primary AXI. This - does not include L2Fetch generated accesses. - 0x79 L2_IU_PREFETCH_MISS L2 prefetch from IU miss. Of the events qualified by 0x78, the - ones that resulted in an L2 miss. - 0x7c L2_DU_READ_ACCESS L2 read access from DU. Any read access from DU that may - cause a lookup in the L2 cache. includes loads, L1 prefetch, - dcfetch. excludes initial L2fetch command, uncacheables. - 0x7d L2_DU_READ_MISS L2 read miss from DU. Of the events qualified by 0x7c, the ones - that resulted in a miss and were attempts to load data. Includes - prefetches. Excludes TCM. - 0x7e L2FETCH_ACCESS L2fetch access from DU. Any access to the L2 cache from the L2 - prefetch engine that was initiated by programing the L2Fetch - engine. Includes only the cache inquire and fetch if not present - commands. - 0x7f L2FETCH_MISS L2fetch miss from a programed inquiry. Of the events qualified by - 0x7e, the ones that resulted in L2 miss. i.e. the line was not - previously allocated in the L2 cache and will be fetched from - backing memory. - 0x81 L2_ACCESS All requests to the L2. Does not include internally generated - accesses like L2Fetch, however the programing of the L2Fetch - engine would be counted. Accesses target odd or even interleave, - and may be L2 cacheable or TCM. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 146 - Hexagon V62 Programmer's Reference Manual PMU Events - - - -Table 9-1 V62 processor event symbols - Event Symbol Definition - 0x82 L2_PIPE_CONFLICT Request not taken by the L2 due to a pipe conflict. The conflict - may be a tag bank, data bank, or other pipeline conflict. - 0x83 L2_TAG_ARRAY_CONFLICT Tag array conflict. Triggers when L2 tag has a conflict i.e., two - operations collide. - 0x87 TCM_DU_ACCESS TCM access from DU. DU access to the L2 TCM space. - 0x88 TCM_DU_READ_ACCESS TCM read access from DU. DU read access to the L2 TCM space. - 0x89 TCM_IU_ACCESS TCM access from IU. IU access to the L2 TCM space. - 0x8a L2_CASTOUT L2 castout. Triggers when L2 evicts a dirty line due to an - allocation. Not triggered on cache ops. - 0x8b L2_DU_STORE_ACCESS L2 cacheable store access from DU. Any store access from DU - that may cause a lookup in the L2 cache. Excludes cache ops, - uncacheables, TCM. Must target primary AXI. - 0x8c L2_DU_STORE_MISS L2 miss from DU. Of the events qualified by 0x8b, the ones that - resulted in a miss. Specifically the cases where the line is not in - cache or a coalesce buffer. - 0x8d L2_DU_PREFETCH_ACCESS L2 prefetch access from DU. Dcfetch and dhwprefetch access to - the L2. - 0x8e L2_DU_PREFETCH_MISS L2 prefetch miss from DU. Of the events qualified by 0x8d, which - ones missed the L2. - 0x90 L2_DU_LOAD_SECONDARY_MISS L2 load secondary miss from DU. Hit busy line in the scoreboard - which prevented a return. Busy condition may include pipeline - bubbles caused by back to back loads, as may be seen on L1UC - loads. - 0x91 L2FETCH_COMMAND L2fetch command. Excludes stop command. - 0x92 L2FETCH_COMMAND_KILLED L2fetch command killed because a stop command was issued. - Increments once for each L2fetch commands that is killed. If - multiple commands are queued to the L2Fetch engine, the kill of - each one will be recorded. - 0x93 L2FETCH_COMMAND_OVERWRITE L2fetch command overwrite. Kills old L2fetch and replaces with - new one. - 0x94 L2FETCH_ACCESS_CREDIT_FAIL L2fetch access could not get a credit. L2fetch blocked because of - missing L2fetch or L2evict credit. - 0x97 L2_ACCESS_EVEN Of the events in 0x81, the number of accesses made to the even - L2 cache. - 0xa0 ANY_DU_STALL Any DU stall. Increments once when the thread has any DU stall - (dcache miss or dTLB miss). - 0xa1 DU_BANK_CONFLICT_REPLAY DU bank conflict replay. Dual mem access to same bank but - different lines. Banks are determined by bits 11,5,4,3. - 0xa2 DU_CREDIT_REPLAY Number of times packet took a replay because insufficient QoS - DU credits were available. - 0xa3 L2_FIFO_FULL_REPLAY Counts L2 even/odd FIFO full replays. - 0xa4 DU_STORE_BUFFER_FULL_ First packet puts access in DU store buffer (memop, store.new, - REPLAY load/store bank conflict, store/store bank conflict). Any later - packet tries to use store buffer before the first one evicts, and so - must replay so the store buffer can drain. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 147 - Hexagon V62 Programmer's Reference Manual PMU Events - - - -Table 9-1 V62 processor event symbols - Event Symbol Definition - 0xa7 DU_SNOOP_REQUEST Number of DU snoop requests that were accepted. - 0xa8 DU_FILL_REPLAY A fill has a index conflict with an instruction from the same thread - in pipeline. Fills and demands might be from different threads if (1) - prefetch from deferral queue, (2) store from store buffer, or (3) fill - has not be ack'ed for too long and forces itself in to the pipeline. - 0xac DU_READ_TO_L2 DU read to L2. Total of everything that brings data from L2. - Includes prefetches (dcfetch and hwprefetch). - 0xad DU_WRITE_TO_L2 DU write to L2. Total of everything that is written out of DU to the - L2 array. Includes cleaninv. Excludes tag writes. - 0xaf DCZERO_COMMITTED Committed a dczeroa instruction. - 0xb3 DTLB_MISS DTLB miss which goes to JTLB. When both slots miss to different - pages, increments by 2. When both slots miss to the same page, - only counts S1, since S1 goes first and fills for S0. - 0xb6 STORE_BUFFER_HIT_REPLAY Store buffer hit replay due to a packet with 2 stores going to the - same bank but different cachelines, followed by a load from an - address that was pushed into the store buffer. - 0xb7 STORE_BUFFER_FORCE_REPLAY The store buffer must drain, forcing the current packet to replay. - This usually happens on a cache index match between the current - packet and store buffer. Could also a store buffer timeout. - 0xb9 SMT_BANK_CONFLICT Counts inter-thread SMT bank conflicts. - 0xba PORT_CONFLICT_REPLAY Counts all port conflict replays, including the same cluster replays - that were caused by high-priority fills and store buffer force drains - (and intercluster ones as well). - 0xbd PAGE_CROSS_REPLAY Page cross replay. Page cross from valid packet that caused - replay. Excludes pdkill packets. Counts twice if both slots cause a - page cross. - 0xbe DU_DEALLOC_SECURITY_REPLAY Replay caused by executing the instructions deallocframe or - dealloc_return when FRAMEKEY is not equal to zero. - 0xbf DU_DEMAND_SECONDARY_MISS DU demand secondary miss. - 0xc3 DCFETCH_COMMITTED Dcfetch committed. Includes hit and dropped. Does not include - convert-to-prefetches. - 0xc4 DCFETCH_HIT Dcfetch hit in dcache. Includes hit valid or reserved line. - 0xc5 DCFETCH_MISS Dcfetch missed in L1. Counts the dcfetch issued to L2 FIFO. - 0xc8 DU_LOAD_UNCACHEABLE Uncacheable load in L1 cache. Counts twice for dual uncacheable - loads. - 0xc9 DU_DUAL_LOAD_UNCACHEABLE Dual uncacheable loads in L1 cache. - 0xca DU_STORE_UNCACHEABLE Uncacheable store in L1 cache. Counts twice for dual - uncacheable stores. - 0xce AXI_LINE64_READ_REQUEST 64-byte line read requests issued by primary AXI master. - 0xcf AXI_LINE64_WRITE_REQUEST 64-byte line write requests issued by primary AXI master. All bytes - valid. - 0xd1 AHB_8_READ_REQUEST An 8-byte AHB read was made. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 148 - Hexagon V62 Programmer's Reference Manual PMU Events - - - -Table 9-1 V62 processor event symbols - Event Symbol Definition - 0xd3 L2FETCH_COMMAND_PAGE_ L2fetch command terminated because it could not get a page - TERMINATION translation from VA to PA. Includes termination dues to permission - errors. i.e. address translation could fail because the VA to PA is - not in the TLB, or the properties in the translation are not - acceptable and the command terminates. - 0xd5 L2_DU_STORE_COALESCE Events from 0x8b that were coalesced. - 0xd6 L2_STORE_LINK Number of times a new store links to something else in the - scoreboard. - 0xd7 L2_SCOREBOARD_70_PERCENT_ Increments by 1 every cycle that the L2 scoreboard is at least 70% - FULL full. For a 32-entry scoreboard, this indicates that 23 or more - entries are consumed. This event continues to count even if the - scoreboard is more than 80% full. For more than one interleave, - this event considers only the scoreboard with the most entries - consumed. - 0xd8 L2_SCOREBOARD_80_PERCENT_ Increments by 1 every cycle that the L2 scoreboard is at least 80% - FULL full. For a 32-entry scoreboard, this indicates that 26 or more - entries are consumed. This event continues to count even if the - scoreboard is more than 90% full. For more than one interleave, - this event considers only the scoreboard with the most entries - consumed. - 0xd9 L2_SCOREBOARD_90_PERCENT_ Increments by 1 every cycle that the L2 scoreboard is at least 90% - FULL full. For a 32-entry scoreboard, this indicates that 29 or more - entries are consumed. For more than one interleave, this event - considers only the scoreboard with the most entries consumed. - 0xda L2_SCOREBOARD_FULL_REJECT L2 scoreboard is too full to accept a selector request, and the - selector has a request. - 0xdc L2_EVICTION_BUFFERS_FULL Counts every cycle when all eviction buffers in any interleave are - occupied. - 0xdd AHB_MULTI_BEAT_READ_ A 32-byte multi-beat AHB read was made. - REQUEST - 0xdf L2_DU_LOAD_SECONDARY_MISS_ Of the events in 0x90, the ones where the primary miss was a - ON_SW_PREFETCH DCFETCH or L2FETCH. - 0xe6 ARCH_LOCK_PVIEW_CYCLES Cycles cluster could not dispatch due to kernel lock or TLB lock. - 0xe7 IU_BRANCH_MISS_PVIEW_CYCLES Packets in-flight killed due to branch mispredict, and cycles cluster - could not dispatch due to IQ being empty because of branch - mispredict. - 0xe8 IU_NO_PKT_PVIEW_CYCLES Cycles cluster could not dispatch due to IQ being empty. - 0xe9 DU_CACHE_MISS_PVIEW_CYCLES Cycles cluster could not dispatch due to D-cache miss or - uncached access. - 0xea DU_BUSY_OTHER_PVIEW_CYCLES Packets in flight killed due to DU replay and cycles cluster could - not dispatch due to DU busy because of stall or replay. - 0xeb CU_BUSY_PVIEW_CYCLES Cycles cluster could not dispatch due to register interlock, register - port conflict, bubbles due to timing class such as tc_3stall, no B2B - HVX, or HVX FIFO full. - 0xec SMT_DU_CONFLICT_PVIEW_ Cycles cluster could not dispatch even though the thread was - CYCLES ready due to DU resource conflict. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 149 - Hexagon V62 Programmer's Reference Manual PMU Events - - - -Table 9-1 V62 processor event symbols - Event Symbol Definition - 0xed SMT_XU_CONFLICT_PVIEW_ Cycles cluster could not dispatch even though the cluster was - CYCLES ready due to an XU resource conflict or other non-DU reason. - oxf0 COPROC_PKT_THREAD Committed packets on a thread with XE bit set, whether executed - in core or coprocessor. - oxf1 COPROC_PKT_COUNT Packets with HVX instructions. - oxf2 COPROC_POWER_THROTTLING_ Stall cycles due to HVX engine being throttled for power reasons. - STALL_CYCLES - oxf3 COPROC_REGISTER_STALL_ Stall cycles due to interlocks. - CYCLES - oxf4 COPROC_LOAD_STALL_CYCLES Stall cycles due to load pending. - oxf5 COPROC_STORE_STALL_CYCLES Stall cycles due to store not yet allocated in L2. - oxf6 COPROC_BUSY_STALL_CYCLES Stall cycles due to multi-issue packet. - oxf7 COPROC_FREEZE_STALL_CYCLES Stall cycles due to L2 vector store data FIFO full. - oxf8 COPROC_CORE_VFIFO_FULL_ Number of times a thread had to stall due to VFIFO being full. - STALL - oxf9 COPROC_L2_STORE_ACCESS L2 cacheable store access from HVX. Any store access from HVX - that may cause a lookup in L2 cache. Excludes cache ops, - uncacheables, scalar stores. - oxfa COPROC_L2_STORE_MISS L2 cacheable miss from HVX. Of the events qualified by 0xf9, the - ones that resulted in a miss. Specifically the cases where line is - not in cache or a coalesce buffer. DCZero does not count as a - miss, if it allocates without a backing store fetch. - oxfb COPROC_L2_LOAD_ACCESS L2 cacheable load access from HVX. Any load access from HVX - that may cause a lookup in the L2 cache. Excludes cache ops, - uncacheables, scalars. - oxfc COPROC_L2_LOAD_MISS L2 cacheable miss from HVX. Of the events qualified by 0xFB, the - ones that resulted in a miss i.e. the line was not previously - allocated in the L2 cache and will be fetched from backing - memory. - oxfd COPROC_TCM_STORE_ACCESS TCM store access for HVX. HVX store to L2 TCM space. - oxfe COPROC_TCM_LOAD_ACCESS TCM load access for HVX. HVX load from L2 TCM space - oxff COPROC_L2_LOAD_SECONDARY_ Of the events in 0xfb, the ones where the load could not be - MISS returned due to the immediately prior access for the line being a - pending load or pending L2Fetch. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 150 - 10 Instruction Encoding - - - This chapter describes the binary encoding of Hexagon processor instructions and - instruction packets. It covers the following topics: - -  Instructions -  Sub-instructions -  Duplex instructions -  Instruction classes -  Instruction packets -  Loop packets -  Immediate operands -  Scaled immediate operands -  Constant extenders -  New-value operands -  Instruction mapping - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 151 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - 10.1 Instructions - All Hexagon processor instructions are encoded in a 32-bit instruction word. The - instruction word format varies according to the instruction type. - - The instruction words contain two types of bit fields: - -  Common fields appear in every processor instruction, and are defined the same in - all instructions. -  Instruction-specific fields appear only in some instructions, or vary in definition - across the instruction set. - - Table 10-1 lists the instruction bit fields. - - Table 10-1 Instruction fields - Name Description Type - ICLASS Instruction class Common - Parse Packet / loop bits - MajOp Major opcode Instruction- - Maj specific - MinOp Minor opcode - Min - RegType Register type (32-bit, 64-bit) - Type Operand type (byte, halfword, etc.) - Amode Addressing mode - dn Destination register operand - sn Source register operand - tn Source register operand #2 - xn Source and destination register operand - un Predicate or modifier register operand - sH Source register bit field (Rs.H or Rs.L) - tH Source register #2 bit field (Rt.H or Rt.L) - UN Unsigned operand - Rs No source register read - P Predicate expression - PS Predicate sense (Pu or !Pu) - DN Dot-new predicate - PT Predict taken - sm Supervisor mode only - - - NOTE In some cases instruction-specific fields are used to encode instruction - attributes other than the ones described for the fields in Table 10-1. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 152 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - Reserved bits - - Some instructions contain reserved bits which are not currently used to encode instruction - attributes. These bits should always be set to 0 to ensure compatibility with any future - changes in the instruction encoding. - - NOTE Reserved bits appear as ‘-’ characters in the instruction encoding tables. - - - 10.2 Sub-instructions - To reduce code size the Hexagon processor supports the encoding of certain pairs of - instructions in a single 32-bit container. Instructions encoded this way are called sub- - instructions, and the containers are called duplexes (Section 10.3). - - Sub-instructions are limited to certain commonly-used instructions: - -  Arithmetic and logical operations -  Register transfer -  Loads and stores -  Stack frame allocation/deallocation -  Subroutine return - - Table 10-2 lists the sub-instructions along with the group identifiers that are used to - encode them in duplexes. - - Sub-instructions can access only a subset of the general registers (R0-R7, R16-R23). - Table 10-3 lists the sub-instruction register encodings. - - NOTE Certain sub-instructions implicitly access registers such as SP (R29). - -Table 10-2 Sub-instructions - Group Instruction Description - L1 Rd = memw(Rs+#u4:2) Word load - L1 Rd = memub(Rs+#u4:0) Unsigned byte load - Group Instruction Instruction - L2 Rd = memh/memuh(Rs+#u3:1) Halfword loads - L2 Rd = memb(Rs+#u3:0) Signed byte load - L2 Rd = memw(r29+#u5:2) Load word from stack - L2 Rdd = memd(r29+#u5:3) Load pair from stack - L2 deallocframe Dealloc stack frame - L2 if ([!]P0) dealloc_return Dealloc stack frame and return - if ([!]P0.new) dealloc_return:nt - L2 jumpr R31 Return - if ([!]P0) jumpr R31 - if ([!]P0.new) jumpr:nt R31 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 153 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - -Table 10-2 Sub-instructions (Continued) - Group Instruction Description - Group Instruction Instruction - S1 memw(Rs+#u4:2) = Rt Store word - S1 memb(Rs+#u4:0) = Rt Store byte - Group Instruction Instruction - S2 memh(Rs+#u3:1) = Rt Store halfword - S2 memw(r29+#u5:2) = Rt Store word to stack - S2 memd(r29+#s6:3) = Rtt Store pair to stack - S2 memw(Rs+#u4:2) = #U1 Store immediate word #0 or #1 - S2 memb(Rs+#u4) = #U1 Store immediate byte #0 or #1 - S2 allocframe(#u5:3) Allocate stack frame - Group Instruction Instruction - A Rx = add(Rx,#s7) Add immediate - A Rd = Rs Transfer - A Rd = #u6 Set to unsigned immediate - A Rd = #-1 Set to -1 - A if ([!]P0[.new]) Rd = #0 Conditional clear - A Rd = add(r29,#u6:2) Add immediate to stack pointer - A Rx = add(Rx,Rs) Register add - A P0 = cmp.eq(Rs,#u2) Compare register equal immed - A Rdd = combine(#0,Rs) Combine zero and register into pair - A Rdd = combine(Rs,#0) Combine register and zero into pair - A Rdd = combine(#u2,#U2) Combine immediates into pair - A Rd = add(Rs,#1) Add and Subtract 1 - Rd = add(Rs,#-1) - A Rd = sxth/sxtb/zxtb/zxth(Rs) Sign- and zero-extends - A Rd = and(Rs,#1) And with 1 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 154 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - - Table 10-3 Sub-instruction registers - Register Encoding - Rs,Rt,Rd,Rx 0000 = R0 - 0001 = R1 - 0010 = R2 - 0011 = R3 - 0100 = R4 - 0101 = R5 - 0110 = R6 - 0111 = R7 - 1000 = R16 - 1001 = R17 - 1010 = R18 - 1011 = R19 - 1100 = R20 - 1101 = R21 - 1110 = R22 - 1111 = R23 - Rdd,Rtt 000 = R1:0 - 001 = R3:2 - 010 = R5:4 - 011 = R7:6 - 100 = R17:16 - 101 = R19:18 - 110 = R21:20 - 111 = R23:22 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 155 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - 10.3 Duplexes - A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00. The sub-instructions - (Section 10.2) that comprise a duplex are encoded as 13-bit fields in the duplex. - - Table 10-4 shows the encoding details for a duplex. - - An instruction packet can contain one duplex and up to two other (non-duplex) - instructions. The duplex must always appear as the last word in a packet. - - The sub-instructions in a duplex are always executed in Slot 0 and Slot 1. - - Table 10-4 Duplex instruction - Bits Name Description - 15:14 Parse Bits 00 = Duplex type, ends the packet and indicates that - word contains two sub-instructions - 12:0 Sub-insn low Encodes Slot 0 sub-instruction - 28:16 Sub-insn high Encodes Slot 1 sub-instruction - 31:29, 13 4-bit ICLASS Indicates which group the low and high sub-instructions - below to. - - Table 10-5 lists the duplex ICLASS field values, which specify the group of each sub- - instruction in a duplex. - - Table 10-5 Duplex ICLASS field - ICLASS Low Slot 0 subinsn type High Slot 1 subinsn type - 0x0 L1-type L1-type - 0x1 L2-type L1-type - 0x2 L2-type L2-type - 0x3 A-type A-type - 0x4 L1-type A-type - 0x5 L2-type A-type - 0x6 S1-type A-type - 0x7 S2-type A-type - 0x8 S1-type L1-type - 0x9 S1-type L2-type - 0xA S1-type S1-type - 0xB S2-type S1-type - 0xC S2-type L1-type - 0xD S2-type L2-type - 0xE S2-type S2-type - 0xF Reserved Reserved - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 156 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - Duplexes have the following grouping constraints: - -  Constant extenders enable the range of an instruction’s immediate operand to be - expanded to 32 bits (Section 10.9). The following sub-instructions can be - expanded with a constant extender: - • Rx = add(Rx,#s7) - • Rd = #u6 - Note that a duplex can contain only one constant-extended instruction, and it must - appear in the Slot 1 position. -  If a duplex contains two instructions with the same sub-instruction group, the - instructions must be ordered in the duplex as follows: when the sub-instructions - are treated as 13-bit unsigned integer values, the instruction corresponding to the - numerically smaller value must be encoded in the Slot 1 position of the duplex.1 -  Sub-instructions must conform to any slot assignment grouping rules that apply to - the individual instructions, even if a duplex pattern exists which violates those - assignments. One exception to this rule exists: - • jumpr R31 must appear in the Slot 0 position - - - - - 1 Note that the sub-instruction register and immediate fields are assumed to be 0 when performing - this comparison. - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 157 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - 10.4 Instruction classes - The instruction class (Section 3.2) is encoded in the four most-significant bits of the - instruction word (31:28). These bits are referred to as the instruction’s ICLASS field. - - Table 10-6 lists the encoding values for the instruction classes. The Slots column indicates - which slots can receive the instruction class. - - Table 10-6 Instruction class encoding - Encoding Instruction Class Slots - 0000 Constant extender (Section 10.9) – - 0001 J 2,3 - 0010 J 2,3 - 0011 LD 0,1 - ST - 0100 LD 0,1 - ST - (conditional or GP-relative) - 0101 J 2,3 - 0110 CR 3 - 0111 ALU32 0,1,2,3 - 1000 XTYPE 2,3 - 1001 LD 0,1 - 1010 ST 0 - 1011 ALU32 0,1,2,3 - 1100 XTYPE 2,3 - 1101 XTYPE 2,3 - 1110 XTYPE 2,3 - 1111 ALU32 0,1,2,3 - - - For details on encoding the individual class types see Chapter 11. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 158 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - 10.5 Instruction packets - Instruction packets are encoded using two bits of the instruction word (15:14), which are - referred to as the instruction word’s Parse field. The field values have the following - definitions: - -  ‘11’ indicates that an instruction is the last instruction in a packet (i.e., the - instruction word at the highest address). -  ‘01’ or ‘10’ indicate that an instruction is not the last instruction in a packet. -  ‘00’indicates a duplex (Section 10.3) - - If any sequence of four consecutive instructions occurs without one of them containing - ‘11’ or ‘00’, the processor will raise an error exception (illegal opcode). - - Figure 10-1 shows the location of the Parse field in an instruction word. - - - 31 16 - - - - 15 0 - P P - - - - - Packet / Loop Parse Bits: - 01, 10 = not end of packet - 11 = end of packet - 00 = duplex - - - - Figure 10-1 Instruction packet encoding - - The following examples show how the Parse field is used to encode instruction packets: - { A ; B} - 01 11 // Parse fields of instrs A,B - - { A ; B ; C} - 01 01 11 // Parse fields of instrs A,B,C - - { A ; B ; C ; D} - 01 01 01 11 // Parse fields of instrs A,B,C,D - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 159 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - 10.6 Loop packets - In addition to encoding the last instruction in a packet, the instruction word’s Parse field - (Section 10.5) is used to encode the last packet in a hardware loop. - - The Hexagon processor supports two hardware loops, labelled 0 and 1 (Section 7.2). The - last packet in these loops is subject to the following restrictions: - -  The last packet in a hardware loop 0 must contain two or more instruction words. -  The last packet in a hardware loop 1 must contain three or more instruction words. - - If the last packet in a loop is expressed in assembly language with fewer than the required - number of words, the assembler automatically adds one or two NOP instructions to the - encoded packet so it contains the minimum required number of instruction words. - - The Parse fields in a packet’s first and second instruction words (i.e., the words at the - lowest addresses) encode whether or not the packet is the last packet in a hardware loop. - - Table 10-7 shows how the Parse fields are used to encode loop packets. - Table 10-7 Loop packet encoding - Parse Field in Parse Field in - Packet - First Instruction Second Instruction - Not last in loop 01 or 11 01 or 11 1 - Last in loop 0 10 01 or 11 - Last in loop 1 01 10 - Last in loops 0 & 1 10 10 - 1 Not applicable for single-instruction packets. - - - The following examples show how the Parse field is used to encode loop packets: - { A B}:endloop0 - 10 11 // Parse fields of instrs A,B - - { A B C}:endloop0 - 10 01 11 // Parse fields of instrs A,B,C - - { A B C D}:endloop0 - 10 01 01 11 // Parse fields of instrs A,B,C,D - - { A B C}:endloop1 - 01 10 11 // Parse fields of instrs A,B,C - - { A B C D}:endloop1 - 01 10 01 11 // Parse fields of instrs A,B,C,D - - { A B C}:endloop0:endloop1 - 10 10 11 // Parse fields of instrs A,B,C - - { A B C D}:endloop0:endloop1 - 10 10 01 11 // Parse fields of instrs A,B,C,D - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 160 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - 10.7 Immediate values - To conserve encoding space, the Hexagon processor often stores immediate values in - instruction fields that are smaller (in bit size) than the values actually needed in the - instruction operation. - - When an instruction operates on one of its immediate operands, the processor - automatically extends the immediate value to the bit size required by the operation: - -  Signed immediate values are sign-extended -  Unsigned immediate values are zero-extended - - - 10.8 Scaled immediates - To minimize the number of bits used in instruction words to store certain immediate - values, the Hexagon processor stores the values as scaled immediates. Scaled immediate - values are used when an immediate value must represent integral multiples of a power of 2 - in a specific range. - - For example, consider an instruction operand whose possible values are the following: - - -32, -28, -24, -20, -16, -12, -8, -4, 0, 4, 8, 12, 16, 20, 24, 28 - - Encoding the full range of integers -32..28 would normally require 6 bits. However, if the - operand is stored as a scaled immediate, it can first be shifted right by two bits, with only - the four remaining bits being stored in the instruction word. When the operand is fetched - from the instruction word, the processor automatically shifts the value left by two bits to - recreate the original operand value. - - NOTE The scaled immediate value in the example above is represented notationally - as #s4:2. For more information see Section 1.5. - - Scaled immediate values are commonly used to encode address offsets which apply to - data types of varying size. For example, Table 10-8 shows how the byte offsets used in - immediate-with-offset addressing mode are stored as 11-bit scaled immediate values. This - enables the offsets to span the same range of data elements regardless of the data type. - - Table 10-8 Scaled immediate encoding (indirect offsets) - Offset Size Scale Offset Size Offset Range Offset Range - Data Type - (Stored) Bits (Effective) (Bytes) (Elements) - byte 11 0 11 -1024 ... 1023 -1024 ... 1023 - halfword 11 1 12 -2048 ... 2046 -1024 ... 1023 - word 11 2 13 -4096 ... 4092 -1024 ... 1023 - doubleword 11 3 14 -8192 ... 8184 -1024 ... 1023 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 161 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - 10.9 Constant extenders - To support the use of 32-bit operands in a number of instructions, the Hexagon processor - defines an instruction word which exists solely to extend the bit range of an immediate or - address operand that is contained in an adjacent instruction in a packet. These instruction - words are called constant extenders. - - For example, the absolute addressing mode specifies a 32-bit constant value as the - effective address. Instructions using this addressing mode are encoded in a single packet - containing both the normal instruction word and a second word with a constant extender - that increases the range of the instruction’s normal constant operand to a full 32 bits. - - NOTE Constant extended operands can encode symbols. - - A constant extender is encoded as a 32-bit instruction with the 4-bit ICLASS field set to 0 - and the 2-bit Parse field set to its usual value (Section 10.5). The remaining 26 bits in the - instruction word store the data bits that are prepended to an operand as small as 6 bits in - order to create a full 32-bit value. - - Table 10-9 shows the encoding details. - - Table 10-9 Constant extender encoding - Bits Name Description - 31:28 ICLASS Instruction class = 0000 - 27:16 Extender high High 12 bits of 26-bit constant extension - 15:14 Parse Parse bits - 13:0 Extender low Low 14 bits of 26-bit constant extension - - Within a packet, a constant extender must be positioned immediately before the - instruction that it extends: in terms of memory addresses, the extender word must reside at - address ( - 4). - - The constant extender effectively serves as a prefix for an instruction: it is not executed in - a slot, nor does it consume any slot resources. All packets must contain four or fewer - words, and the constant extender occupies one word. - - If the instruction operand to be extended is longer than 6 bits, the overlapping bits in the - base instruction must be encoded as zeros. The value in the constant extender always - supplies the upper 26 bits. - - Table 10-10 lists the instructions that work with constant extenders. - - The Regclass field in the table lists the values that bits [27:24] must be set to in the - instruction word to identify the instruction as one that may include a constant extender. - - NOTE In cases where the base instruction encodes two constant operands, the - extended immediate is the one specified in the table. - - Constant extenders appear in disassembly listings as Hexagon instructions - with the name immext. - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 162 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - -Table 10-10 Constant extender instructions - ICLASS Regclass Instructions -LD ---1 Rd = mem{b,ub,h,uh,w,d}(##U32) - if ([!]Pt[.new]) Rd = mem{b,ub,h,uh,w,d} (Rs + ##U32) - // predicated loads -LD ---- Rd = mem{b,ub,h,uh,w,d} (Rs + ##U32) - Rd = mem{b,ub,h,uh,w,d} (Re=##U32) - Rd = mem{b,ub,h,uh,w,d} (Rt<<#u2 + ##U32) - if ([!]Pt[.new]) Rd = mem{b,ub,h,uh,w,d} (##U32) -ST ---0 mem{b,h,w,d}(##U32) = Rs[.new] // GP-stores - if ([!]Pt[.new]) mem{b,h,w,d}(Rs + ##U32) = Rt[.new] - // predicated stores -ST ---- mem{b,h,w,d}(Rs + ##U32) = Rt[.new] - mem{b,h,w,d}(Rd=##U32) = Rt[.new] - mem{b,h,w,d}(Ru<<#u2 + ##U32) = Rt[.new] - if ([!]Pt[.new]) mem{b,h,w,d}(##U32) = Rt[.new] -MEMOP ---- [if [!]Ps] memw(Rs + #u6) = ##U32 // constant store - memw(Rs + Rt<<#u2) = ##U32 // constant store -NV ---- if (cmp.xx(Rs.new,##U32)) jump:hint target -ALU32 ---- Rd = ##u32 - Rdd = combine(Rs,##u32) - Rdd = combine(##u32,Rs) - Rdd = combine(##u32,#s8) - Rdd = combine(#s8,##u32) - Rd = mux (Pu, Rs,##u32) - Rd = mux (Pu, ##u32, Rs) - Rd = mux(Pu,##u32,#s8) - if ([!]Pu[.new]) Rd = add(Rs,##u32) - if ([!]Pu[.new]) Rd = ##u32 - Pd = [!]cmp.eq (Rs,##u32) - Pd = [!]cmp.gt (Rs,##u32) - Pd = [!]cmp.gtu (Rs,##u32) - Rd = [!]cmp.eq(Rs,##u32) - Rd = and(Rs,##u32) - Rd = or(Rs,##u32) - Rd = sub(##u32,Rs) -ALU32 ---- Rd = add(Rs,##s32) -XTYPE 00-- Rd = mpyi(Rs,##u32) - Rd += mpyi(Rs,##u32) - Rd -= mpyi(Rs,##u32) - Rx += add(Rs,##u32) - Rx -= add(Rs,##u32) -ALU32 ---- 1 Rd = ##u32 - Rd = add(Rs,##s32) -J 1--- jump (PC + ##s32) - call (PC + ##s32) - if ([!]Pu) call (PC + ##s32) - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 163 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - -Table 10-10 Constant extender instructions (Continued) - ICLASS Regclass Instructions -CR ---- Pd = spNloop0(PC+##s32,Rs/#U10) - loop0/1 (PC+##s32,#Rs/#U10) -XTYPE 1--- Rd = add(pc,##s32) - Rd = add(##u32,mpyi(Rs,#u6)) - Rd = add(##u32,mpyi(Rs,Rt)) - Rd = add(Rs,add(Rt,##u32)) - Rd = add(Rs,sub(##u32,Rt)) - Rd = sub(##u32,add(Rs,Rt)) - Rd = or(Rs,and(Rt,##u32)) - Rx = add/sub/and/or (##u32,asl/asr/lsr(Rx,#U5)) - Rx = add/sub/and/or (##u32,asl/asr/lsr(Rs,Rx)) - Rx = add/sub/and/or (##u32,asl/asr/lsr(Rx,Rs)) - Pd = cmpb/h.{eq,gt,gtu} (Rs,##u32) -1 Constant extension is only for a Slot 1 sub-instruction. - - - NOTE If a constant extender is encoded in a packet for an instruction that does not - accept a constant extender, the execution result is undefined. The assembler - normally ensures that only valid constant extenders are generated. - - Encoding 32-bit address operands in load/stores - - Two methods exist for encoding a 32-bit absolute address in a load or store instruction: - - 1) For unconditional load/stores, the GP-relative load/store instruction is used. The - assembler encodes the absolute 32-bit address as follows: - -  The upper 26 bits are encoded in a constant extender -  The lower 6 bits are encoded in the 6 operand bits contained in the GP-relative - instruction - - In this case the 32-bit value encoded must be a plain address, and the value stored in the - GP register is ignored. - - NOTE When a constant extender is explicitly specified with a GP-relative load/store, - the processor ignores the value in GP and creates the effective address directly - from the 32-bit constant value. - - 2) For conditional load/store instructions that have their base address encoded only by a 6- - bit immediate operand, a constant extender must be explicitly specified; otherwise, the - execution result is undefined. The assembler ensures that these instructions always include - a constant extender. - - This case applies also to instructions that use the absolute-set addressing mode or - absolute-plus-register-offset addressing mode. - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 164 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - Encoding 32-bit immediate operands - - The immediate operands of certain instructions use scaled immediates (Section 10.8) to - increase their addressable range. When constant extenders are used, scaled immediates are - not scaled by the processor. Instead, the assembler must encode the full 32-bit unscaled - value as follows: - -  The upper 26 bits are encoded in the constant extender -  The lower 6 bits are encoded in the base instruction in the least-significant bit - positions of the immediate operand field. -  Any overlapping bits in the base instruction are encoded as zeros. - - Encoding 32-bit jump/call target addresses - - When a jump/call has a constant extender, the resulting target address is forced to a 32-bit - alignment (i.e., bits 1:0 in the address are cleared by hardware). The resulting jump/call - operation will never cause an alignment violation. - - - 10.10 New-value operands - Instructions that include a new-value register operand specify in their encodings which - instruction in the packet has its destination register accessed as the new-value register. - - New-value consumers include a 3-bit instruction field named Nt which specifies this - information. - -  Nt[0] is reserved and should always be encoded as zero. A non-zero value - produces undefined results. -  Nt[2:1] encodes the distance (in instructions) from the producer to the consumer, - as follows: -  Nt[2:1] = 00 // reserved -  Nt[2:1] = 01 // producer is +1 instruction ahead of consumer -  Nt[2:1] = 10 // producer is +2 instructions ahead of consumer -  Nt[2:1] = 11 // producer is +3 instructions ahead of consumer - - “ahead” is defined here as the instruction encoded at a lower memory address than the - consumer instruction, not counting empty slots or constant extenders. For example, the - following producer/consumer relationship would be encoded with Nt[2:1] set to 01. - ... - - - - ... - - NOTE Instructions with 64-bit register pair destinations cannot produce new-values. - The assembler flags this case with an error, as the result is undefined. - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 165 - Hexagon V62 Programmer's Reference Manual Instruction Encoding - - - - 10.11 Instruction mapping - Some Hexagon processor instructions are encoded by the assembler as variants of other - instructions. This is done for operations that are functionally equivalent to other - instructions, but are still defined as separate instructions because of their programming - utility as common operations. - - Table 10-11 lists some of the instructions that are mapped to other instructions. - Table 10-11 Instruction mapping - Instruction Mapping - Rd = not(Rs) Rd = sub(#-1,Rs) - Rd = neg(Rs) Rd = sub(#0,Rs) - Rdd = Rss Rdd = combine(Rss.H32, Rss.L32) - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 166 - 11 Instruction Set - - - This chapter describes the instruction set for version 6 of the Hexagon processor. - - The instructions are listed alphabetically within instruction categories. The following - information is provided for each instruction: -  Instruction name -  A brief description of the instruction -  A high-level functional description (syntax and behavior) with all possible - operand types -  Instruction class and slot information for grouping instructions in packets -  Notes on miscellaneous issues -  Any C intrinsic functions that provide access to the instruction -  Instruction encoding - - - - -80-N2040-36 B 167 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.0.1 Instruction categories - -  ALU32 — 32-bit ALU operations -  ALU — Arithmetic and Logical -  PERM — Permute -  PRED — Predicate -  CR — Control registers, looping -  JR — Jump from Register -  J — Jump -  LD — Load -  MEMOP — Memory operations -  NV — New-value operations -  J — New-value jumps -  ST — New-value stores -  ST — Store operations -  SYSTEM -  User Instructions -  XTYPE — 32-bit and 64-bit operations -  ALU — Arithmetic and Logical -  BIT — Bit -  COMPLEX — Complex -  FP — Floating point -  MPY — Multiply -  PERM — Permute -  PRED — Predicate -  SHIFT — Shift - - Table 11-1 lists the symbols used to specify the instruction syntax. - - - - -80-N2040-36 B 168 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Table 11-1 Instruction syntax symbols - Symbol Example Meaning - = R2 = R3; Assignment of RHS to LHS - ; R2 = R3; Marks the end of an instruction or group of - instructions - {…} {R2 = R3; R5 = R6;} Indicates a group of parallel instructions. - # #100 Immediate constant value - ## ##2147483647 32-bit immediate constant value - 0x R2 = #0x1fe; Indicates hexadecimal number - MEMxx R2 = MEMxx(R3) Access memory. xx specifies the size and - type of access. - :sat R2 = add(r1,r2):sat Perform optional saturation - :rnd R2 = mpy(r1.h,r2.h):rnd Perform optional rounding - :<<16 R2 = add(r1.l,r2.l):<<16 Shift left by a halfword - - - - - Table 11-2 lists the symbols used to specify instruction operands. - - - Table 11-2 Instruction operand symbols - Symbol Example Meaning - #uN R2 = #u16 Unsigned N-bit immediate value - #sN R2 = add(R3,#s16) Signed N-bit immediate value - #mN Rd = mpyi(Rs,#m9) Signed N-bit immediate value - #uN:S R2 = memh(#u16:1) Unsigned N-bit immediate value representing - integral multiples of 2S in specified range - #sN:S Rd = memw(Rs++#s4:2) Signed N-bit immediate value representing - integral multiples of 2S in specified range - #rN:S call #r22:2 Same as #sN:S, but value is offset from PC of - current packet - ## call ##32 Same as #, but associated value (u,s,m,r) is 32 - bits - - When an instruction contains more than one immediate operand, the operand symbols are - specified in upper and lower case (e.g., #uN and #UN) to indicate where they appear in the - instruction encodings. - - The instruction behavior is specified using a superset of the C language. Table 11-3 lists - symbols not defined in C which are used to specify the instruction behavior. - - - - -80-N2040-36 B 169 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Table 11-3 Instruction behavior symbols - Symbol Example Meaning - usatN usat16(Rs) Saturate a value to an unsigned N-bit - satN sat16(Rs) Saturate a value to a signed N-bit number - sxt x->y sxt32->64(Rs) Sign-extend value from x to y bits - zxt x->y zxt32->64(Rs) Zero-extend value from x to y bits - >>> Rss >>> offset Logical right shift - - - - -80-N2040-36 B 170 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.1 ALU32 - The ALU32 instruction class includes instructions which perform arithmetic and logical - operations on 32-bit data. - - ALU32 instructions are executable on any slot. - - - 11.1.1 ALU32/ALU - The ALU32/ALU instruction subclass includes instructions which perform arithmetic and - logical operations on individual 32-bit items. - -Add - Add a source register either to another source register or to a signed 16-bit immediate - value. Store result in destination register. Source and destination registers are 32 bits. If the - result overflows 32 bits, it wraps around. Optionally saturate result to a signed value - between 0x80000000 and 0x7fffffff. - - For 64-bit versions of this operation, see the XTYPE add instructions. - - Syntax Behavior - Rd=add(Rs,#s16) apply_extension(#s); - Rd=Rs+#s; - Rd=add(Rs,Rt) Rd=Rs+Rt; - Rd=add(Rs,Rt):sat Rd=sat32(Rs+Rt); - - - Class: ALU32 (slots 0,1,2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), then the OVF bit in the Status Register is - set. OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=add(Rs,#s16) Word32 Q6_R_add_RI(Word32 Rs, Word32 Is16) - Rd=add(Rs,Rt) Word32 Q6_R_add_RR(Word32 Rs, Word32 Rt) - Rd=add(Rs,Rt):sat Word32 Q6_R_add_RR_sat(Word32 Rs, Word32 Rt) - - - - -80-N2040-36 B 171 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse d5 -1 0 1 1 i i i i i i i s s s s s P P i i i i i i i i i d d d d d Rd=add(Rs,#s16) - ICLASS P MajOp MinOp s5 Parse t5 d5 -1 1 1 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t - - - d d d d d Rd=add(Rs,Rt) -1 1 1 1 0 1 1 0 0 1 0 s s s s s P P - t t t t t - - - d d d d d Rd=add(Rs,Rt):sat - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 172 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Logical operations - Perform bitwise logical operations (AND, OR, XOR, NOT) either on two source registers - or on a source register and a signed 10-bit immediate value. Store result in destination - register. Source and destination registers are 32 bits. - - For 64-bit versions of these operations, see the XTYPE logical instructions. - - Syntax Behavior - Rd=and(Rs,#s10) apply_extension(#s); - Rd=Rs&#s; - Rd=and(Rs,Rt) Rd=Rs&Rt; - Rd=and(Rt,~Rs) Rd = (Rt & ~Rs); - Rd=not(Rs) Assembler mapped to: "Rd=sub(#-1,Rs)" - Rd=or(Rs,#s10) apply_extension(#s); - Rd=Rs|#s; - Rd=or(Rs,Rt) Rd=Rs|Rt; - Rd=or(Rt,~Rs) Rd = (Rt | ~Rs); - Rd=xor(Rs,Rt) Rd=Rs^Rt; - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - Rd=and(Rs,#s10) Word32 Q6_R_and_RI(Word32 Rs, Word32 Is10) - Rd=and(Rs,Rt) Word32 Q6_R_and_RR(Word32 Rs, Word32 Rt) - Rd=and(Rt,~Rs) Word32 Q6_R_and_RnR(Word32 Rt, Word32 Rs) - Rd=not(Rs) Word32 Q6_R_not_R(Word32 Rs) - Rd=or(Rs,#s10) Word32 Q6_R_or_RI(Word32 Rs, Word32 Is10) - Rd=or(Rs,Rt) Word32 Q6_R_or_RR(Word32 Rs, Word32 Rt) - Rd=or(Rt,~Rs) Word32 Q6_R_or_RnR(Word32 Rt, Word32 Rs) - Rd=xor(Rs,Rt) Word32 Q6_R_xor_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse d5 -0 1 1 1 0 1 1 0 0 0 i s s s s s P P i i i i i i i i i d d d d d Rd=and(Rs,#s10) -0 1 1 1 0 1 1 0 1 0 i s s s s s P P i i i i i i i i i d d d d d Rd=or(Rs,#s10) - ICLASS P MajOp MinOp s5 Parse t5 d5 - - - - -80-N2040-36 B 173 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 1 1 1 0 0 0 1 0 0 0 s s s s s P P - t t t t t - - - d d d d d Rd=and(Rs,Rt) -1 1 1 1 0 0 0 1 0 0 1 s s s s s P P - t t t t t - - - d d d d d Rd=or(Rs,Rt) -1 1 1 1 0 0 0 1 0 1 1 s s s s s P P - t t t t t - - - d d d d d Rd=xor(Rs,Rt) -1 1 1 1 0 0 0 1 1 0 0 s s s s s P P - t t t t t - - - d d d d d Rd=and(Rt,~Rs) -1 1 1 1 0 0 0 1 1 0 1 s s s s s P P - t t t t t - - - d d d d d Rd=or(Rt,~Rs) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 174 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Negate - Perform arithmetic negation on a source register. Store result in destination register. - Source and destination registers are 32 bits. - - For 64-bit and saturating versions of this instruction, see the XTYPE-class negate - instructions. - - Syntax Behavior - Rd=neg(Rs) Assembler mapped to: "Rd=sub(#0,Rs)" - - - Class: N/A - - Intrinsics - - Rd=neg(Rs) Word32 Q6_R_neg_R(Word32 Rs) - - - - -80-N2040-36 B 175 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Nop - Perform no operation. This instruction is used for padding and alignment. - - Within a packet it can be positioned in any slot 0-3. - - Syntax Behavior - nop - - - Class: ALU32 (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp Parse -0 1 1 1 1 1 1 1 - - - - - - - - P P - - - - - - - - - - - - - - nop - - - - - Field name Description - MajOp Major Opcode - Rs No Rs read - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 176 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Subtract - Subtract a source register from either another source register or from a signed 10-bit - immediate value. Store result in destination register. Source and destination registers are - 32 bits. If the result underflows 32 bits, it wraps around. Optionally saturate result to a - signed value between 0x8000_0000 and 0x7fff_ffff. - - For 64-bit versions of this operation, see the XTYPE subtract instructions. - - Syntax Behavior - Rd=sub(#s10,Rs) apply_extension(#s); - Rd=#s-Rs; - Rd=sub(Rt,Rs) Rd=Rt-Rs; - Rd=sub(Rt,Rs):sat Rd=sat32(Rt - Rs); - - - Class: ALU32 (slots 0,1,2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), then the OVF bit in the Status Register is - set. OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=sub(#s10,Rs) Word32 Q6_R_sub_IR(Word32 Is10, Word32 Rs) - Rd=sub(Rt,Rs) Word32 Q6_R_sub_RR(Word32 Rt, Word32 Rs) - Rd=sub(Rt,Rs):sat Word32 Q6_R_sub_RR_sat(Word32 Rt, Word32 - Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse d5 -0 1 1 1 0 1 1 0 0 1 i s s s s s P P i i i i i i i i i d d d d d Rd=sub(#s10,Rs) - ICLASS P MajOp MinOp s5 Parse t5 d5 -1 1 1 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t - - - d d d d d Rd=sub(Rt,Rs) -1 1 1 1 0 1 1 0 1 1 0 s s s s s P P - t t t t t - - - d d d d d Rd=sub(Rt,Rs):sat - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - - - -80-N2040-36 B 177 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 178 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Sign extend - Sign-extend the least-significant byte or halfword from the source register and place the - 32-bit result in the destination register. - - - Rd=sxth(Rs) Rd=sxtb(Rs) - - Rs Rs - - - - - Sign-extend Rd Sign-extend Rd - - - Syntax Behavior - Rd=sxtb(Rs) Rd = sxt8->32(Rs); - Rd=sxth(Rs) Rd = sxt16->32(Rs); - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - - Rd=sxtb(Rs) Word32 Q6_R_sxtb_R(Word32 Rs) - Rd=sxth(Rs) Word32 Q6_R_sxth_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse C d5 -0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 0 - - - - - - - - d d d d d Rd=sxtb(Rs) -0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - - - - d d d d d Rd=sxth(Rs) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - C Conditional - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 179 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Transfer immediate - Assign an immediate value to a 32-bit destination register. - - Two types of assignment are supported. The first sign-extends a 16-bit signed immediate - value to 32 bits. The second assigns a 16-bit unsigned immediate value to either the upper - or lower 16 bits of the destination register, leaving the other 16 bits unchanged. - - - Rd=#s16 - Sign-Extend 16-bit immediate - - Rx.H=#u16 - 16-bit immediate Unchanged - - Rx.L=#u16 - Unchanged 16-bit immediate - - - Syntax Behavior - Rd=#s16 apply_extension(#s); - Rd=#s; - Rdd=#s8 if ("#s8<0") { - Assembler mapped to: "Rdd=combine(#- - 1,#s8)"; - } else { - Assembler mapped to: - "Rdd=combine(#0,#s8)"; - }; - Rx.[HL]=#u16 Rx.h[01]=#u; - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - Rd=#s16 Word32 Q6_R_equals_I(Word32 Is16) - Rdd=#s8 Word64 Q6_P_equals_I(Word32 Is8) - Rx.H=#u16 Word32 Q6_Rh_equals_I(Word32 Rx, Word32 - Iu16) - Rx.L=#u16 Word32 Q6_Rl_equals_I(Word32 Rx, Word32 - Iu16) - - - - -80-N2040-36 B 180 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp x5 Parse -0 1 1 1 0 0 0 1 i i 1 x x x x x P P i i i i i i i i i i i i i i Rx.L=#u16 -0 1 1 1 0 0 1 0 i i 1 x x x x x P P i i i i i i i i i i i i i i Rx.H=#u16 - ICLASS Rs MajOp MinOp Parse d5 -0 1 1 1 1 0 0 0 i i - i i i i i P P i i i i i i i i i d d d d d Rd=#s16 - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - x5 Field to encode register x - - - - -80-N2040-36 B 181 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Transfer register - Transfer a source register to a destination register. Source and destination registers are - either 32 bits or 64 bits. - - Syntax Behavior - Rd=Rs Rd=Rs; - Rdd=Rss Assembler mapped to: - "Rdd=combine(Rss.H32,Rss.L32)" - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - Rd=Rs Word32 Q6_R_equals_R(Word32 Rs) - Rdd=Rss Word64 Q6_P_equals_P(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse C d5 -0 1 1 1 0 0 0 0 0 1 1 s s s s s P P 0 - - - - - - - - d d d d d Rd=Rs - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - C Conditional - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 182 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector add halfwords - Add the two 16-bit halfwords of Rs to the two 16-bit halfwords of Rt. The results are - optionally saturated to signed or unsigned 16-bit values. - - Syntax Behavior - Rd=vaddh(Rs,Rt)[:sat] for (i=0;i<2;i++) { - Rd.h[i]=[sat16](Rs.h[i]+Rt.h[i]); - }; - Rd=vadduh(Rs,Rt):sat for (i=0;i<2;i++) { - Rd.h[i]=usat16(Rs.uh[i]+Rt.uh[i]); - }; - - - Class: ALU32 (slots 0,1,2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), then the OVF bit in the Status Register is - set. OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=vaddh(Rs,Rt) Word32 Q6_R_vaddh_RR(Word32 Rs, Word32 Rt) - Rd=vaddh(Rs,Rt):sat Word32 Q6_R_vaddh_RR_sat(Word32 Rs, Word32 - Rt) - Rd=vadduh(Rs,Rt):sat Word32 Q6_R_vadduh_RR_sat(Word32 Rs, Word32 - Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS P MajOp MinOp s5 Parse t5 d5 -1 1 1 1 0 1 1 0 0 0 0 s s s s s P P - t t t t t - - - d d d d d Rd=vaddh(Rs,Rt) -1 1 1 1 0 1 1 0 0 0 1 s s s s s P P - t t t t t - - - d d d d d Rd=vaddh(Rs,Rt):sat -1 1 1 1 0 1 1 0 0 1 1 s s s s s P P - t t t t t - - - d d d d d Rd=vadduh(Rs,Rt):sat - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 183 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector average halfwords - VAVGH adds the two 16-bit halfwords of Rs to the two 16-bit halfwords of Rd, and shifts - the result right by 1 bit. Optionally, a rounding constant is added before shifting. - - VNAVGH subtracts the two 16-bit halfwords of Rt from the two 16-bit halfwords of Rs, - and shifts the result right by 1 bit. For vector negative average with rounding, see the - XTYPE VNAVGH instruction. - - Syntax Behavior - Rd=vavgh(Rs,Rt) for (i=0;i<2;i++) { - Rd.h[i]=((Rs.h[i]+Rt.h[i])>>1); - }; - Rd=vavgh(Rs,Rt):rnd for (i=0;i<2;i++) { - Rd.h[i]=((Rs.h[i]+Rt.h[i]+1)>>1); - }; - Rd=vnavgh(Rt,Rs) for (i=0;i<2;i++) { - Rd.h[i]=((Rt.h[i]-Rs.h[i])>>1); - }; - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - - Rd=vavgh(Rs,Rt) Word32 Q6_R_vavgh_RR(Word32 Rs, Word32 Rt) - Rd=vavgh(Rs,Rt):rnd Word32 Q6_R_vavgh_RR_rnd(Word32 Rs, Word32 - Rt) - Rd=vnavgh(Rt,Rs) Word32 Q6_R_vnavgh_RR(Word32 Rt, Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS P MajOp MinOp s5 Parse t5 d5 -1 1 1 1 0 1 1 1 - 0 0 s s s s s P P - t t t t t - - - d d d d d Rd=vavgh(Rs,Rt) -1 1 1 1 0 1 1 1 - 0 1 s s s s s P P - t t t t t - - - d d d d d Rd=vavgh(Rs,Rt):rnd -1 1 1 1 0 1 1 1 - 1 1 s s s s s P P - t t t t t - - - d d d d d Rd=vnavgh(Rt,Rs) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 184 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector subtract halfwords - Subtract each of the two halfwords in 32-bit vector Rs from the corresponding halfword in - vector Rt. Optionally saturate each 16-bit addition to either a signed or unsigned 16-bit - value. - - Applying saturation to the VSUBH instruction clamps the result to the signed range - 0x8000 to 0x7fff, whereas applying saturation to VSUBUH ensures that the unsigned - result is in the range 0 to 0xffff. When saturation is not needed, VSUBH should be used. - - Syntax Behavior - Rd=vsubh(Rt,Rs)[:sat] for (i=0;i<2;i++) { - Rd.h[i]=[sat16](Rt.h[i]-Rs.h[i]); - }; - Rd=vsubuh(Rt,Rs):sat for (i=0;i<2;i++) { - Rd.h[i]=usat16(Rt.uh[i]-Rs.uh[i]); - }; - - - Class: ALU32 (slots 0,1,2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), then the OVF bit in the Status Register is - set. OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=vsubh(Rt,Rs) Word32 Q6_R_vsubh_RR(Word32 Rt, Word32 Rs) - Rd=vsubh(Rt,Rs):sat Word32 Q6_R_vsubh_RR_sat(Word32 Rt, Word32 - Rs) - Rd=vsubuh(Rt,Rs):sat Word32 Q6_R_vsubuh_RR_sat(Word32 Rt, Word32 - Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS P MajOp MinOp s5 Parse t5 d5 -1 1 1 1 0 1 1 0 1 0 0 s s s s s P P - t t t t t - - - d d d d d Rd=vsubh(Rt,Rs) -1 1 1 1 0 1 1 0 1 0 1 s s s s s P P - t t t t t - - - d d d d d Rd=vsubh(Rt,Rs):sat -1 1 1 1 0 1 1 0 1 1 1 s s s s s P P - t t t t t - - - d d d d d Rd=vsubuh(Rt,Rs):sat - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - ICLASS Instruction Class - - - -80-N2040-36 B 185 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 186 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Zero extend - Zero-extend the least significant byte or halfword from Rs and place the 32-bit result in - Rd. - - - Rd=zxth(Rs) Rd=zxtb(Rs) - - Rs Rs - - - - - 0x0000 Rd 0x000000 Rd - - - Syntax Behavior - Rd=zxtb(Rs) Assembler mapped to: "Rd=and(Rs,#255)" - Rd=zxth(Rs) Rd = zxt16->32(Rs); - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - - Rd=zxtb(Rs) Word32 Q6_R_zxtb_R(Word32 Rs) - Rd=zxth(Rs) Word32 Q6_R_zxth_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse C d5 -0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 0 - - - - - - - - d d d d d Rd=zxth(Rs) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - C Conditional - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 187 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.1.2 ALU32/PERM - The ALU32/PERM instruction subclass includes instructions which rearrange or perform - format conversion on vector data types. - -Combine words into doubleword - Combine halfwords or words into larger values. - - In a halfword combine, either the high or low halfword of the first source register is - transferred to the most-significant halfword of the destination register, while either the - high or low halfword of the second source register is transferred to the least-significant - halfword of the destination register. Source and destination registers are 32 bits. - - In a word combine, the first source register is transferred to the most-significant word of - the destination register, while the second source register is transferred to the least- - significant word of the destination register. Source registers are 32 bits and the destination - register is 64 bits. - - In a variant of word combine, signed 8-bit immediate values (instead of registers) are - transferred to the most- and least-significant words of the 64-bit destination register. - Optionally one of the immediate values can be 32 bits. - - - Rd=combine(Rt.[HL],Rs.[HL]) - - - Rt.H Rt.L Rs.H Rs.L - Rdd=combine(Rs,Rt) - - Mux Mux Rs Rt - - - - - Rd Rdd - - - Syntax Behavior - Rd=combine(Rt.[HL],Rs.[HL]) Rd = (Rt.uh[01]<<16) | Rs.uh[01]; - - - - -80-N2040-36 B 188 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rdd=combine(#s8,#S8) apply_extension(#s); - Rdd.w[0]=#S; - Rdd.w[1]=#s; - Rdd=combine(#s8,#U6) apply_extension(#U); - Rdd.w[0]=#U; - Rdd.w[1]=#s; - Rdd=combine(#s8,Rs) apply_extension(#s); - Rdd.w[0]=Rs; - Rdd.w[1]=#s; - Rdd=combine(Rs,#s8) apply_extension(#s); - Rdd.w[0]=#s; - Rdd.w[1]=Rs; - Rdd=combine(Rs,Rt) Rdd.w[0]=Rt; - Rdd.w[1]=Rs; - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - - Rd=combine(Rt.H,Rs.H) Word32 Q6_R_combine_RhRh(Word32 Rt, Word32 - Rs) - Rd=combine(Rt.H,Rs.L) Word32 Q6_R_combine_RhRl(Word32 Rt, Word32 - Rs) - Rd=combine(Rt.L,Rs.H) Word32 Q6_R_combine_RlRh(Word32 Rt, Word32 - Rs) - Rd=combine(Rt.L,Rs.L) Word32 Q6_R_combine_RlRl(Word32 Rt, Word32 - Rs) - Rdd=combine(#s8,#S8) Word64 Q6_P_combine_II(Word32 Is8, Word32 - IS8) - Rdd=combine(#s8,Rs) Word64 Q6_P_combine_IR(Word32 Is8, Word32 - Rs) - Rdd=combine(Rs,#s8) Word64 Q6_P_combine_RI(Word32 Rs, Word32 - Is8) - Rdd=combine(Rs,Rt) Word64 Q6_P_combine_RR(Word32 Rs, Word32 - Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse d5 -0 1 1 1 0 0 1 1 - 0 0 s s s s s P P 1 i i i i i i i i d d d d d Rdd=combine(Rs,#s8) -0 1 1 1 0 0 1 1 - 0 1 s s s s s P P 1 i i i i i i i i d d d d d Rdd=combine(#s8,Rs) - ICLASS Rs MajOp MinOp Parse d5 -0 1 1 1 1 1 0 0 0 I I I I I I I P P I i i i i i i i i d d d d d Rdd=combine(#s8,#S8) -0 1 1 1 1 1 0 0 1 - - I I I I I P P I i i i i i i i i d d d d d Rdd=combine(#s8,#U6) - ICLASS P MajOp MinOp s5 Parse t5 d5 - - - - -80-N2040-36 B 189 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 1 1 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t - - - d d d d d Rd=combine(Rt.H,Rs.H) -1 1 1 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t - - - d d d d d Rd=combine(Rt.H,Rs.L) -1 1 1 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t - - - d d d d d Rd=combine(Rt.L,Rs.H) -1 1 1 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t - - - d d d d d Rd=combine(Rt.L,Rs.L) -1 1 1 1 0 1 0 1 0 - - s s s s s P P - t t t t t - - - d d d d d Rdd=combine(Rs,Rt) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 190 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Mux - Select between two source registers based on the least-significant bit of a predicate - register. If the bit is 1, transfer the first source register to the destination register; - otherwise, transfer the second source register. Source and destination registers are 32 bits. - - In a variant of mux, signed 8-bit immediate values can be used instead of registers for - either or both source operands. - - For 64-bit versions of this instruction, see the XTYPE vmux instruction. - - Syntax Behavior - Rd=mux(Pu,#s8,#S8) apply_extension(#s); - (Pu[0]) ? (Rd=#s):(Rd=#S); - Rd=mux(Pu,#s8,Rs) apply_extension(#s); - (Pu[0]) ? (Rd=#s):(Rd=Rs); - Rd=mux(Pu,Rs,#s8) apply_extension(#s); - (Pu[0]) ? (Rd=Rs):(Rd=#s); - Rd=mux(Pu,Rs,Rt) (Pu[0]) ? (Rd=Rs):(Rd=Rt); - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - - Rd=mux(Pu,#s8,#S8) Word32 Q6_R_mux_pII(Byte Pu, Word32 Is8, - Word32 IS8) - Rd=mux(Pu,#s8,Rs) Word32 Q6_R_mux_pIR(Byte Pu, Word32 Is8, - Word32 Rs) - Rd=mux(Pu,Rs,#s8) Word32 Q6_R_mux_pRI(Byte Pu, Word32 Rs, - Word32 Is8) - Rd=mux(Pu,Rs,Rt) Word32 Q6_R_mux_pRR(Byte Pu, Word32 Rs, - Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp u2 s5 Parse d5 -0 1 1 1 0 0 1 1 0 u u s s s s s P P 0 i i i i i i i i d d d d d Rd=mux(Pu,Rs,#s8) -0 1 1 1 0 0 1 1 1 u u s s s s s P P 0 i i i i i i i i d d d d d Rd=mux(Pu,#s8,Rs) - ICLASS Rs u1 Parse d5 -0 1 1 1 1 0 1 u u I I I I I I I P P I i i i i i i i i d d d d d Rd=mux(Pu,#s8,#S8) - ICLASS P MajOp s5 Parse t5 u2 d5 -1 1 1 1 0 1 0 0 - - - s s s s s P P - t t t t t - u u d d d d d Rd=mux(Pu,Rs,Rt) - - - - -80-N2040-36 B 191 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - MajOp Major Opcode - P Predicated - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - u2 Field to encode register u - - - - -80-N2040-36 B 192 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Shift word by 16 - ASLH performs an arithmetic left shift of the 32-bit source register by 16 bits (one - halfword). The lower 16 bits of the destination are zero-filled. - - - Rs - - - - - 0x0000 Rd - - - ASRH performs an arithmetic right shift of the 32-bit source register by 16 bits (one - halfword). The upper 16 bits of the destination are sign-extended. - - - Rs - - - - - Sign-extend Rd - - - Syntax Behavior - Rd=aslh(Rs) Rd=Rs<<16; - Rd=asrh(Rs) Rd=Rs>>16; - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - Rd=aslh(Rs) Word32 Q6_R_aslh_R(Word32 Rs) - Rd=asrh(Rs) Word32 Q6_R_asrh_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse C d5 -0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 0 - - - - - - - - d d d d d Rd=aslh(Rs) -0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 0 - - - - - - - - d d d d d Rd=asrh(Rs) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - C Conditional - - - -80-N2040-36 B 193 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 194 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Pack high and low halfwords - Pack together the most-significant halfwords from Rs and Rt into the most-significant - word of register pair Rdd, and the least-significant halfwords from Rs and Rt into the - least-significant halfword of Rdd. - - - Rs Rt - - - - - Rdd - - - Syntax Behavior - Rdd=packhl(Rs,Rt) Rdd.h[0]=Rt.h[0]; - Rdd.h[1]=Rs.h[0]; - Rdd.h[2]=Rt.h[1]; - Rdd.h[3]=Rs.h[1]; - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - Rdd=packhl(Rs,Rt) Word64 Q6_P_packhl_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS P MajOp MinOp s5 Parse t5 d5 -1 1 1 1 0 1 0 1 1 - - s s s s s P P - t t t t t - - - d d d d d Rdd=packhl(Rs,Rt) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 195 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.1.3 ALU32/PRED - The ALU32/PRED instruction subclass includes instructions which perform conditional - arithmetic and logical operations based on the values stored in a predicate register, and - which produce predicate results. They are executable on any slot. - -Conditional add - If the least-significant bit of predicate Pu is set, then add a 32-bit source register to either - another register or an immediate value. The result is placed in 32-bit destination register. If - the predicate is false, the instruction does nothing. - - Syntax Behavior - if ([!]Pu[.new]) if([!]Pu[.new][0]){ - Rd=add(Rs,#s8) apply_extension(#s); - Rd=Rs+#s; - } else { - NOP; - }; - if ([!]Pu[.new]) if([!]Pu[.new][0]){ - Rd=add(Rs,Rt) Rd=Rs+Rt; - } else { - NOP; - }; - - - Class: ALU32 (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - D - ICLASS Rs MajOp PS u2 s5 Parse N d5 - -0 1 1 1 0 1 0 0 0 u u s s s s s P P 0 i i i i i i i i d d d d d if (Pu) Rd=add(Rs,#s8) -0 1 1 1 0 1 0 0 0 u u s s s s s P P 1 i i i i i i i i d d d d d if (Pu.new) Rd=add(Rs,#s8) -0 1 1 1 0 1 0 0 1 u u s s s s s P P 0 i i i i i i i i d d d d d if (!Pu) Rd=add(Rs,#s8) -0 1 1 1 0 1 0 0 1 u u s s s s s P P 1 i i i i i i i i d d d d d if (!Pu.new) Rd=add(Rs,#s8) - D - ICLASS P MajOp MinOp s5 Parse t5 PS u2 d5 - N -1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 0 t t t t t 0 u u d d d d d if (Pu) Rd=add(Rs,Rt) -1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 0 t t t t t 1 u u d d d d d if (!Pu) Rd=add(Rs,Rt) -1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 1 t t t t t 0 u u d d d d d if (Pu.new) Rd=add(Rs,Rt) -1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 1 t t t t t 1 u u d d d d d if (!Pu.new) Rd=add(Rs,Rt) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - DN Dot-new - PS Predicate sense - - - - -80-N2040-36 B 196 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - DN Dot-new - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - PS Predicate sense - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u2 Field to encode register u - - - - -80-N2040-36 B 197 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Conditional shift halfword - Conditionally shift a halfword. - - ASLH performs an arithmetic left shift of the 32-bit source register by 16 bits (one - halfword). The lower 16 bits of the destination are zero-filled. - - - Rs - - - - - 0x0000 Rd - - - ASRH performs an arithmetic right shift of the 32-bit source register by 16 bits (one - halfword). The upper 16 bits of the destination are sign-extended. - - - Rs - - - - - Sign-extend Rd - - - Syntax Behavior - if ([!]Pu[.new]) Rd=aslh(Rs) if([!]Pu[.new][0]){ - Rd=Rs<<16; - } else { - NOP; - }; - if ([!]Pu[.new]) Rd=asrh(Rs) if([!]Pu[.new][0]){ - Rd=Rs>>16; - } else { - NOP; - }; - - - Class: ALU32 (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse C S dn u2 d5 -0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 0 0 u u - - - d d d d d if (Pu) Rd=aslh(Rs) -0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 0 1 u u - - - d d d d d if (Pu.new) Rd=aslh(Rs) -0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 1 0 u u - - - d d d d d if (!Pu) Rd=aslh(Rs) - - - - -80-N2040-36 B 198 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 1 1 u u - - - d d d d d if (!Pu.new) Rd=aslh(Rs) -0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 0 0 u u - - - d d d d d if (Pu) Rd=asrh(Rs) -0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 0 1 u u - - - d d d d d if (Pu.new) Rd=asrh(Rs) -0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 1 0 u u - - - d d d d d if (!Pu) Rd=asrh(Rs) -0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 1 1 u u - - - d d d d d if (!Pu.new) Rd=asrh(Rs) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - C Conditional - S Predicate sense - dn Dot-new - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - u2 Field to encode register u - - - - -80-N2040-36 B 199 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Conditional combine - If the least-significant bit of predicate Pu is set, then the most-significant word of - destination Rdd is taken from the first source register Rs, while the least-significant word - is taken from the second source register Rt. If the predicate is false, this instruction does - nothing. - - Syntax Behavior - if ([!]Pu[.new]) if ([!]Pu[.new][0]) { - Rdd=combine(Rs,Rt) Rdd.w[0]=Rt; - Rdd.w[1]=Rs; - } else { - NOP; - }; - - - Class: ALU32 (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - ICLASS P MajOp s5 Parse D t5 PS u2 d5 - N -1 1 1 1 1 1 0 1 - - - s s s s s P P 0 t t t t t 0 u u d d d d d if (Pu) Rdd=combine(Rs,Rt) -1 1 1 1 1 1 0 1 - - - s s s s s P P 0 t t t t t 1 u u d d d d d if (!Pu) Rdd=combine(Rs,Rt) -1 1 1 1 1 1 0 1 - - - s s s s s P P 1 t t t t t 0 u u d d d d d if (Pu.new) Rdd=combine(Rs,Rt) -1 1 1 1 1 1 0 1 - - - s s s s s P P 1 t t t t t 1 u u d d d d d if (!Pu.new) Rdd=combine(Rs,Rt) - - - - - Field name Description - DN Dot-new - MajOp Major Opcode - P Predicated - PS Predicate sense - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u2 Field to encode register u - - - - -80-N2040-36 B 200 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Conditional logical operations - If the least-significant bit of predicate Pu is set, then do a logical operation on the source - values. The result is placed in 32-bit destination register. If the predicate is false, the - instruction does nothing. - - Syntax Behavior - if ([!]Pu[.new]) if([!]Pu[.new][0]){ - Rd=and(Rs,Rt) Rd=Rs&Rt; - } else { - NOP; - }; - if ([!]Pu[.new]) if([!]Pu[.new][0]){ - Rd=or(Rs,Rt) Rd=Rs|Rt; - } else { - NOP; - }; - if ([!]Pu[.new]) if([!]Pu[.new][0]){ - Rd=xor(Rs,Rt) Rd=Rs^Rt; - } else { - NOP; - }; - - - Class: ALU32 (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - D - ICLASS P MajOp MinOp s5 Parse N t5 PS u2 d5 - -1 1 1 1 1 0 0 1 - 0 0 s s s s s P P 0 t t t t t 0 u u d d d d d if (Pu) Rd=and(Rs,Rt) -1 1 1 1 1 0 0 1 - 0 0 s s s s s P P 0 t t t t t 1 u u d d d d d if (!Pu) Rd=and(Rs,Rt) -1 1 1 1 1 0 0 1 - 0 0 s s s s s P P 1 t t t t t 0 u u d d d d d if (Pu.new) Rd=and(Rs,Rt) -1 1 1 1 1 0 0 1 - 0 0 s s s s s P P 1 t t t t t 1 u u d d d d d if (!Pu.new) Rd=and(Rs,Rt) -1 1 1 1 1 0 0 1 - 0 1 s s s s s P P 0 t t t t t 0 u u d d d d d if (Pu) Rd=or(Rs,Rt) -1 1 1 1 1 0 0 1 - 0 1 s s s s s P P 0 t t t t t 1 u u d d d d d if (!Pu) Rd=or(Rs,Rt) -1 1 1 1 1 0 0 1 - 0 1 s s s s s P P 1 t t t t t 0 u u d d d d d if (Pu.new) Rd=or(Rs,Rt) -1 1 1 1 1 0 0 1 - 0 1 s s s s s P P 1 t t t t t 1 u u d d d d d if (!Pu.new) Rd=or(Rs,Rt) -1 1 1 1 1 0 0 1 - 1 1 s s s s s P P 0 t t t t t 0 u u d d d d d if (Pu) Rd=xor(Rs,Rt) -1 1 1 1 1 0 0 1 - 1 1 s s s s s P P 0 t t t t t 1 u u d d d d d if (!Pu) Rd=xor(Rs,Rt) -1 1 1 1 1 0 0 1 - 1 1 s s s s s P P 1 t t t t t 0 u u d d d d d if (Pu.new) Rd=xor(Rs,Rt) -1 1 1 1 1 0 0 1 - 1 1 s s s s s P P 1 t t t t t 1 u u d d d d d if (!Pu.new) Rd=xor(Rs,Rt) - - - - - Field name Description - DN Dot-new - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - PS Predicate sense - - - - -80-N2040-36 B 201 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u2 Field to encode register u - - - - -80-N2040-36 B 202 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Conditional subtract - If the least-significant bit of predicate Pu is set, then subtract a 32-bit source register Rt - from register Rs. The result is placed in a 32-bit destination register. If the predicate is - false, the instruction does nothing. - - Syntax Behavior - if ([!]Pu[.new]) if([!]Pu[.new][0]){ - Rd=sub(Rt,Rs) Rd=Rt-Rs; - } else { - NOP; - }; - - - Class: ALU32 (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - D - ICLASS P MajOp MinOp s5 Parse N t5 PS u2 d5 - -1 1 1 1 1 0 1 1 0 - 1 s s s s s P P 0 t t t t t 0 u u d d d d d if (Pu) Rd=sub(Rt,Rs) -1 1 1 1 1 0 1 1 0 - 1 s s s s s P P 0 t t t t t 1 u u d d d d d if (!Pu) Rd=sub(Rt,Rs) -1 1 1 1 1 0 1 1 0 - 1 s s s s s P P 1 t t t t t 0 u u d d d d d if (Pu.new) Rd=sub(Rt,Rs) -1 1 1 1 1 0 1 1 0 - 1 s s s s s P P 1 t t t t t 1 u u d d d d d if (!Pu.new) Rd=sub(Rt,Rs) - - - - - Field name Description - DN Dot-new - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - PS Predicate sense - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u2 Field to encode register u - - - - -80-N2040-36 B 203 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Conditional sign extend - Conditionally sign-extend the least-significant byte or halfword from Rs and put the 32-bit - result in Rd. - - - Rd=sxth(Rs) Rd=sxtb(Rs) - - Rs Rs - - - - - Sign-extend Rd Sign-extend Rd - - - Syntax Behavior - if ([!]Pu[.new]) Rd=sxtb(Rs) if([!]Pu[.new][0]){ - Rd=sxt8->32(Rs); - } else { - NOP; - }; - if ([!]Pu[.new]) Rd=sxth(Rs) if([!]Pu[.new][0]){ - Rd=sxt16->32(Rs); - } else { - NOP; - }; - - - Class: ALU32 (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse C S dn u2 d5 -0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 - 0 0 u u - - - d d d d d if (Pu) Rd=sxtb(Rs) -0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 - 0 1 u u - - - d d d d d if (Pu.new) Rd=sxtb(Rs) -0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 - 1 0 u u - - - d d d d d if (!Pu) Rd=sxtb(Rs) -0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 - 1 1 u u - - - d d d d d if (!Pu.new) Rd=sxtb(Rs) -0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 - 0 0 u u - - - d d d d d if (Pu) Rd=sxth(Rs) -0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 - 0 1 u u - - - d d d d d if (Pu.new) Rd=sxth(Rs) -0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 - 1 0 u u - - - d d d d d if (!Pu) Rd=sxth(Rs) -0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 - 1 1 u u - - - d d d d d if (!Pu.new) Rd=sxth(Rs) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - C Conditional - S Predicate sense - dn Dot-new - - - - -80-N2040-36 B 204 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - u2 Field to encode register u - - - - -80-N2040-36 B 205 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Conditional transfer - If the LSB of predicate Pu is set, transfer register Rs or a signed immediate into - destination Rd. If the predicate is false, this instruction does nothing. - - Syntax Behavior - if ([!]Pu[.new]) Rd=#s12 apply_extension(#s); - if ([!]Pu[.new][0]) Rd=#s; - else NOP; - if ([!]Pu[.new]) Rd=Rs Assembler mapped to: "if ([!]Pu[.new]) - Rd=add(Rs,#0)" - if ([!]Pu[.new]) Rdd=Rss Assembler mapped to: "if ([!]Pu[.new]) - Rdd=combine(Rss.H32,Rss.L32)" - - - Class: ALU32 (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - D - ICLASS Rs MajOp PS u2 Parse d5 - N -0 1 1 1 1 1 1 0 0 u u 0 i i i i P P 0 i i i i i i i i d d d d d if (Pu) Rd=#s12 -0 1 1 1 1 1 1 0 0 u u 0 i i i i P P 1 i i i i i i i i d d d d d if (Pu.new) Rd=#s12 -0 1 1 1 1 1 1 0 1 u u 0 i i i i P P 0 i i i i i i i i d d d d d if (!Pu) Rd=#s12 -0 1 1 1 1 1 1 0 1 u u 0 i i i i P P 1 i i i i i i i i d d d d d if (!Pu.new) Rd=#s12 - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - DN Dot-new - PS Predicate sense - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - u2 Field to encode register u - - - - -80-N2040-36 B 206 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Conditional zero extend - Conditionally zero-extend the least-significant byte or halfword from Rs and put the 32-bit - result in Rd. - - - Rd=zxth(Rs) Rd=zxtb(Rs) - - Rs Rs - - - - - 0x0000 Rd 0x000000 Rd - - - Syntax Behavior - if ([!]Pu[.new]) Rd=zxtb(Rs) if([!]Pu[.new][0]){ - Rd=zxt8->32(Rs); - } else { - NOP; - }; - if ([!]Pu[.new]) Rd=zxth(Rs) if([!]Pu[.new][0]){ - Rd=zxt16->32(Rs); - } else { - NOP; - }; - - - Class: ALU32 (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse C S dn u2 d5 -0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 - 0 0 u u - - - d d d d d if (Pu) Rd=zxtb(Rs) -0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 - 0 1 u u - - - d d d d d if (Pu.new) Rd=zxtb(Rs) -0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 - 1 0 u u - - - d d d d d if (!Pu) Rd=zxtb(Rs) -0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 - 1 1 u u - - - d d d d d if (!Pu.new) Rd=zxtb(Rs) -0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 - 0 0 u u - - - d d d d d if (Pu) Rd=zxth(Rs) -0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 - 0 1 u u - - - d d d d d if (Pu.new) Rd=zxth(Rs) -0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 - 1 0 u u - - - d d d d d if (!Pu) Rd=zxth(Rs) -0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 - 1 1 u u - - - d d d d d if (!Pu.new) Rd=zxth(Rs) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - C Conditional - S Predicate sense - dn Dot-new - - - - -80-N2040-36 B 207 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - u2 Field to encode register u - - - - -80-N2040-36 B 208 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Compare - The register form compares two 32-bit registers for unsigned greater than, greater than, or - equal. - - The immediate form compares a register against a signed or unsigned immediate value. - The 8-bit predicate register Pd is set to all 1's or all 0's depending on the result. For 64-bit - versions of this instruction, see the XTYPE compare instructions. - - Syntax Behavior - Pd=[!]cmp.eq(Rs,#s10) apply_extension(#s); - Pd=Rs[!]=#s ? 0xff : 0x00; - Pd=[!]cmp.eq(Rs,Rt) Pd=Rs[!]=Rt ? 0xff : 0x00; - Pd=[!]cmp.gt(Rs,#s10) apply_extension(#s); - Pd=Rs<=#s ? 0xff : 0x00; - Pd=[!]cmp.gt(Rs,Rt) Pd=Rs<=Rt ? 0xff : 0x00; - Pd=[!]cmp.gtu(Rs,#u9) apply_extension(#u); - Pd=Rs.uw[0]<=#u ? 0xff : 0x00; - Pd=[!]cmp.gtu(Rs,Rt) Pd=Rs.uw[0]<=Rt.uw[0] ? 0xff : 0x00; - Pd=cmp.ge(Rs,#s8) Assembler mapped to: "Pd=cmp.gt(Rs,#s8-1)" - Pd=cmp.geu(Rs,#u8) if ("#u8==0") { - Assembler mapped to: - "Pd=cmp.eq(Rs,Rs)"; - } else { - Assembler mapped to: - "Pd=cmp.gtu(Rs,#u8-1)"; - }; - Pd=cmp.lt(Rs,Rt) Assembler mapped to: "Pd=cmp.gt(Rt,Rs)" - Pd=cmp.ltu(Rs,Rt) Assembler mapped to: "Pd=cmp.gtu(Rt,Rs)" - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - Pd=!cmp.eq(Rs,#s10) Byte Q6_p_not_cmp_eq_RI(Word32 Rs, Word32 - Is10) - Pd=!cmp.eq(Rs,Rt) Byte Q6_p_not_cmp_eq_RR(Word32 Rs, Word32 - Rt) - Pd=!cmp.gt(Rs,#s10) Byte Q6_p_not_cmp_gt_RI(Word32 Rs, Word32 - Is10) - Pd=!cmp.gt(Rs,Rt) Byte Q6_p_not_cmp_gt_RR(Word32 Rs, Word32 - Rt) - Pd=!cmp.gtu(Rs,#u9) Byte Q6_p_not_cmp_gtu_RI(Word32 Rs, Word32 - Iu9) - Pd=!cmp.gtu(Rs,Rt) Byte Q6_p_not_cmp_gtu_RR(Word32 Rs, Word32 - Rt) - - - - -80-N2040-36 B 209 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Pd=cmp.eq(Rs,#s10) Byte Q6_p_cmp_eq_RI(Word32 Rs, Word32 Is10) - Pd=cmp.eq(Rs,Rt) Byte Q6_p_cmp_eq_RR(Word32 Rs, Word32 Rt) - Pd=cmp.ge(Rs,#s8) Byte Q6_p_cmp_ge_RI(Word32 Rs, Word32 Is8) - Pd=cmp.geu(Rs,#u8) Byte Q6_p_cmp_geu_RI(Word32 Rs, Word32 Iu8) - Pd=cmp.gt(Rs,#s10) Byte Q6_p_cmp_gt_RI(Word32 Rs, Word32 Is10) - Pd=cmp.gt(Rs,Rt) Byte Q6_p_cmp_gt_RR(Word32 Rs, Word32 Rt) - Pd=cmp.gtu(Rs,#u9) Byte Q6_p_cmp_gtu_RI(Word32 Rs, Word32 Iu9) - Pd=cmp.gtu(Rs,Rt) Byte Q6_p_cmp_gtu_RR(Word32 Rs, Word32 Rt) - Pd=cmp.lt(Rs,Rt) Byte Q6_p_cmp_lt_RR(Word32 Rs, Word32 Rt) - Pd=cmp.ltu(Rs,Rt) Byte Q6_p_cmp_ltu_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse d2 -0 1 1 1 0 1 0 1 0 0 i s s s s s P P i i i i i i i i i 0 0 0 d d Pd=cmp.eq(Rs,#s10) -0 1 1 1 0 1 0 1 0 0 i s s s s s P P i i i i i i i i i 1 0 0 d d Pd=!cmp.eq(Rs,#s10) -0 1 1 1 0 1 0 1 0 1 i s s s s s P P i i i i i i i i i 0 0 0 d d Pd=cmp.gt(Rs,#s10) -0 1 1 1 0 1 0 1 0 1 i s s s s s P P i i i i i i i i i 1 0 0 d d Pd=!cmp.gt(Rs,#s10) -0 1 1 1 0 1 0 1 1 0 0 s s s s s P P i i i i i i i i i 0 0 0 d d Pd=cmp.gtu(Rs,#u9) -0 1 1 1 0 1 0 1 1 0 0 s s s s s P P i i i i i i i i i 1 0 0 d d Pd=!cmp.gtu(Rs,#u9) - ICLASS P MajOp MinOp s5 Parse t5 d2 -1 1 1 1 0 0 1 0 - 0 0 s s s s s P P - t t t t t - - - 0 0 0 d d Pd=cmp.eq(Rs,Rt) -1 1 1 1 0 0 1 0 - 0 0 s s s s s P P - t t t t t - - - 1 0 0 d d Pd=!cmp.eq(Rs,Rt) -1 1 1 1 0 0 1 0 - 1 0 s s s s s P P - t t t t t - - - 0 0 0 d d Pd=cmp.gt(Rs,Rt) -1 1 1 1 0 0 1 0 - 1 0 s s s s s P P - t t t t t - - - 1 0 0 d d Pd=!cmp.gt(Rs,Rt) -1 1 1 1 0 0 1 0 - 1 1 s s s s s P P - t t t t t - - - 0 0 0 d d Pd=cmp.gtu(Rs,Rt) -1 1 1 1 0 0 1 0 - 1 1 s s s s s P P - t t t t t - - - 1 0 0 d d Pd=!cmp.gtu(Rs,Rt) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 210 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Compare to general register - The register form compares two 32-bit registers for unsigned greater than, greater than, or - equal. The immediate form compares a register against a signed or unsigned immediate - value. The resulting zero or one is placed in a general register. - - Syntax Behavior - Rd=[!]cmp.eq(Rs,#s8) apply_extension(#s); - Rd=(Rs[!]=#s); - Rd=[!]cmp.eq(Rs,Rt) Rd=(Rs[!]=Rt); - - - Class: ALU32 (slots 0,1,2,3) - - Intrinsics - - - Rd=!cmp.eq(Rs,#s8) Word32 Q6_R_not_cmp_eq_RI(Word32 Rs, Word32 - Is8) - Rd=!cmp.eq(Rs,Rt) Word32 Q6_R_not_cmp_eq_RR(Word32 Rs, Word32 - Rt) - Rd=cmp.eq(Rs,#s8) Word32 Q6_R_cmp_eq_RI(Word32 Rs, Word32 - Is8) - Rd=cmp.eq(Rs,Rt) Word32 Q6_R_cmp_eq_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Rs MajOp MinOp s5 Parse d5 -0 1 1 1 0 0 1 1 - 1 0 s s s s s P P 1 i i i i i i i i d d d d d Rd=cmp.eq(Rs,#s8) -0 1 1 1 0 0 1 1 - 1 1 s s s s s P P 1 i i i i i i i i d d d d d Rd=!cmp.eq(Rs,#s8) - ICLASS P MajOp MinOp s5 Parse t5 d5 -1 1 1 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t - - - d d d d d Rd=cmp.eq(Rs,Rt) -1 1 1 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t - - - d d d d d Rd=!cmp.eq(Rs,Rt) - - - - - Field name Description - MajOp Major Opcode - MinOp Minor Opcode - Rs No Rs read - MajOp Major Opcode - MinOp Minor Opcode - P Predicated - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 211 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.2 CR - The CR instruction class includes instructions which manage control registers, including - hardware looping, modulo addressing, and status flags. - - CR instructions are executable on slot 3. - -End loop instructions - The endloop instructions mark the end of a hardware loop. If the Loop Count (LC) register - indicates that a loop should continue to iterate, the LC register is decremented and the - program flow changes to the address in the Start Address (SA) register. - - The endloopN instruction is actually a pseudo-instruction encoded in bits 15:14 of each - instruction. Therefore, no distinct 32-bit encoding exists for this instruction. - - Syntax Behavior - endloop0 if (USR.LPCFG) { - if (USR.LPCFG==1) { - P3=0xff; - }; - USR.LPCFG=USR.LPCFG-1; - }; - if (LC0>1) { - PC=SA0; - LC0=LC0-1; - }; - endloop01 if (USR.LPCFG) { - if (USR.LPCFG==1) { - P3=0xff; - }; - USR.LPCFG=USR.LPCFG-1; - }; - if (LC0>1) { - PC=SA0; - LC0=LC0-1; - } else { - if (LC1>1) { - PC=SA1; - LC1=LC1-1; - }; - }; - endloop1 if (LC1>1) { - PC=SA1; - LC1=LC1-1; - }; - - - Class: N/A - - Notes - -  This instruction cannot be grouped in a packet with any program flow - instructions. - - - - -80-N2040-36 B 212 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -  The Next PC value is the address immediately following the last instruction in the - packet containing this instruction. -  The PC value is the address of the start of the packet - - - - -80-N2040-36 B 213 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Corner detection acceleration - The FASTCORNER9 instruction takes the Ps and Pt values and treats them as a circular - bit string. If any contiguous nine bits are set around the circle, the result is true, false - otherwise. The sense may be optionally inverted. This instruction is used to accelerate - FAST corner detection. - - Syntax Behavior - Pd=[!]fastcorner9(Ps,Pt) tmp.h[0]=(Ps<<8)|Pt; - tmp.h[1]=(Ps<<8)|Pt; - for (i = 1; i < 9; i++) { - tmp &= tmp >> 1; - }; - Pd = tmp == 0 ? 0xff : 0x00; - - - Class: CR (slot 2,3) - - Notes - -  This instruction may execute on either slot2 or slot3, even though it is a CR-type - - Intrinsics - - Pd=!fastcorner9(Ps,Pt) Byte Q6_p_not_fastcorner9_pp(Byte Ps, Byte - Pt) - Pd=fastcorner9(Ps,Pt) Byte Q6_p_fastcorner9_pp(Byte Ps, Byte Pt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s2 Parse t2 d2 -0 1 1 0 1 0 1 1 0 0 0 0 - - s s P P 1 - - - t t 1 - - 1 - - d d Pd=fastcorner9(Ps,Pt) -0 1 1 0 1 0 1 1 0 0 0 1 - - s s P P 1 - - - t t 1 - - 1 - - d d Pd=!fastcorner9(Ps,Pt) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s2 Field to encode register s - t2 Field to encode register t - - - - -80-N2040-36 B 214 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Logical reductions on predicates - The ANY8 instruction sets a destination predicate register to 0xff if any of the low 8 bits - in source predicate register Ps are set. Otherwise, the predicate is set to 0x00. - - The ALL8 instruction sets a destination predicate register to 0xff if all of the low 8 bits in - the source predicate register Ps are set. Otherwise, the predicate is set to 0x00. - - Syntax Behavior - Pd=all8(Ps) (Ps==0xff) ? (Pd=0xff) : (Pd=0x00); - Pd=any8(Ps) Ps ? (Pd=0xff) : (Pd=0x00); - - - Class: CR (slot 2,3) - - Notes - -  This instruction may execute on either slot2 or slot3, even though it is a CR-type - - Intrinsics - - Pd=all8(Ps) Byte Q6_p_all8_p(Byte Ps) - Pd=any8(Ps) Byte Q6_p_any8_p(Byte Ps) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s2 Parse d2 -0 1 1 0 1 0 1 1 1 0 0 0 - - s s P P 0 - - - - - - - - - - - d d Pd=any8(Ps) -0 1 1 0 1 0 1 1 1 0 1 0 - - s s P P 0 - - - - - - - - - - - d d Pd=all8(Ps) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s2 Field to encode register s - - - - -80-N2040-36 B 215 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Looping instructions - loopN is a single instruction which sets up a hardware loop. The N in the instruction name - indicates the set of loop registers to use. Loop0 is the innermost loop, while loop1 is the - outer loop.The loopN instruction first sets the Start Address (SA) register based on a PC- - relative immediate add. The relative immediate is added to the PC and stored in SA. The - Loop Count (LC) register is set to either an unsigned immediate or to a register value. - - Syntax Behavior - loop0(#r7:2,#U10) apply_extension(#r); - #r=#r & ~0x3; - SA0=PC+#r; - LC0=#U; - USR.LPCFG=0; - loop0(#r7:2,Rs) apply_extension(#r); - #r=#r & ~0x3; - SA0=PC+#r; - LC0=Rs; - USR.LPCFG=0; - loop1(#r7:2,#U10) apply_extension(#r); - #r=#r & ~0x3; - SA1=PC+#r; - LC1=#U; - loop1(#r7:2,Rs) apply_extension(#r); - #r=#r & ~0x3; - SA1=PC+#r; - LC1=Rs; - - - Class: CR (slot 3) - - Notes - -  This instruction cannot execute in the last address of a hardware loop. -  The Next PC value is the address immediately following the last instruction in the - packet containing this instruction. -  The PC value is the address of the start of the packet -  A PC-relative address is formed by taking the decoded immediate value and - adding it to the current PC value. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 0 0 0 0 0 0 s s s s s P P - i i i i i - - - i i - - - loop0(#r7:2,Rs) -0 1 1 0 0 0 0 0 0 0 1 s s s s s P P - i i i i i - - - i i - - - loop1(#r7:2,Rs) - ICLASS sm Parse -0 1 1 0 1 0 0 1 0 0 0 I I I I I P P - i i i i i I I I i i - I I loop0(#r7:2,#U10) -0 1 1 0 1 0 0 1 0 0 1 I I I I I P P - i i i i i I I I i i - I I loop1(#r7:2,#U10) - - - - -80-N2040-36 B 216 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 217 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Add to PC - Add an immediate value to the Program Counter (PC) and place the result in a destination - register. This instruction is typically used with a constant extender to add a 32-bit - immediate value to PC. - - Syntax Behavior - Rd=add(pc,#u6) Rd=PC+apply_extension(#u); - - - Class: CR (slot 3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm Parse d5 -0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 P P - i i i i i i - - d d d d d Rd=add(pc,#u6) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - - - - -80-N2040-36 B 218 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Pipelined loop instructions - spNloop0 is a single instruction which sets up a hardware loop with automatic predicate - control. This features saves code size by enabling many software pipelined loops to be - generated without prologue code. Upon executing this instruction, the P3 register is - automatically cleared. After the loop has been executed N times (where N is selectable - from 1-3), the P3 register is set. The intent is that store instructions in the loop are - predicated with P3 and thus not enabled during the pipeline warm-up. - - In the spNloop0 instruction the loop 0 (inner-loop) registers are used. This instruction sets - the Start Address (SA0) register based on a PC-relative immediate add. The relative - immediate is added to the PC and stored in SA0. The Loop Count (LC0) is set to either an - unsigned immediate or to a register value. The predicate P3 is cleared. The USR.LPCFG - bits are set based on the N value. - - Syntax Behavior - p3=sp1loop0(#r7:2,#U10) apply_extension(#r); - #r=#r & ~0x3; - SA0=PC+#r; - LC0=#U; - USR.LPCFG=1; - P3=0; - p3=sp1loop0(#r7:2,Rs) apply_extension(#r); - #r=#r & ~0x3; - SA0=PC+#r; - LC0=Rs; - USR.LPCFG=1; - P3=0; - p3=sp2loop0(#r7:2,#U10) apply_extension(#r); - #r=#r & ~0x3; - SA0=PC+#r; - LC0=#U; - USR.LPCFG=2; - P3=0; - p3=sp2loop0(#r7:2,Rs) apply_extension(#r); - #r=#r & ~0x3; - SA0=PC+#r; - LC0=Rs; - USR.LPCFG=2; - P3=0; - p3=sp3loop0(#r7:2,#U10) apply_extension(#r); - #r=#r & ~0x3; - SA0=PC+#r; - LC0=#U; - USR.LPCFG=3; - P3=0; - p3=sp3loop0(#r7:2,Rs) apply_extension(#r); - #r=#r & ~0x3; - SA0=PC+#r; - LC0=Rs; - USR.LPCFG=3; - P3=0; - - - - -80-N2040-36 B 219 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: CR (slot 3) - - Notes - -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. -  This instruction cannot execute in the last address of a hardware loop. -  The Next PC value is the address immediately following the last instruction in the - packet containing this instruction. -  The PC value is the address of the start of the packet -  A PC-relative address is formed by taking the decoded immediate value and - adding it to the current PC value. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 0 0 0 1 0 1 s s s s s P P - i i i i i - - - i i - - - p3=sp1loop0(#r7:2,Rs) -0 1 1 0 0 0 0 0 1 1 0 s s s s s P P - i i i i i - - - i i - - - p3=sp2loop0(#r7:2,Rs) -0 1 1 0 0 0 0 0 1 1 1 s s s s s P P - i i i i i - - - i i - - - p3=sp3loop0(#r7:2,Rs) - ICLASS sm Parse -0 1 1 0 1 0 0 1 1 0 1 I I I I I P P - i i i i i I I I i i - I I p3=sp1loop0(#r7:2,#U10) -0 1 1 0 1 0 0 1 1 1 0 I I I I I P P - i i i i i I I I i i - I I p3=sp2loop0(#r7:2,#U10) -0 1 1 0 1 0 0 1 1 1 1 I I I I I P P - i i i i i I I I i i - I I p3=sp3loop0(#r7:2,#U10) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 220 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Logical operations on predicates - Perform bitwise logical operations on predicate registers. - - Syntax Behavior - Pd=Ps Assembler mapped to: "Pd=or(Ps,Ps)" - Pd=and(Ps,and(Pt,[!]Pu)) Pd = Ps & Pt & (~Pu); - Pd=and(Ps,or(Pt,[!]Pu)) Pd = Ps & (Pt | (~Pu)); - Pd=and(Pt,[!]Ps) Pd=Pt & (~Ps); - Pd=not(Ps) Pd=~Ps; - Pd=or(Ps,and(Pt,[!]Pu)) Pd = Ps | (Pt & (~Pu)); - Pd=or(Ps,or(Pt,[!]Pu)) Pd = Ps | Pt | (~Pu); - Pd=or(Pt,[!]Ps) Pd=Pt | (~Ps); - Pd=xor(Ps,Pt) Pd=Ps ^ Pt; - - - Class: CR (slot 2,3) - - Notes - -  This instruction may execute on either slot2 or slot3, even though it is a CR-type - - Intrinsics - - Pd=Ps Byte Q6_p_equals_p(Byte Ps) - Pd=and(Ps,and(Pt,!Pu)) Byte Q6_p_and_and_ppnp(Byte Ps, Byte Pt, - Byte Pu) - Pd=and(Ps,and(Pt,Pu)) Byte Q6_p_and_and_ppp(Byte Ps, Byte Pt, - Byte Pu) - Pd=and(Ps,or(Pt,!Pu)) Byte Q6_p_and_or_ppnp(Byte Ps, Byte Pt, - Byte Pu) - Pd=and(Ps,or(Pt,Pu)) Byte Q6_p_and_or_ppp(Byte Ps, Byte Pt, Byte - Pu) - Pd=and(Pt,!Ps) Byte Q6_p_and_pnp(Byte Pt, Byte Ps) - Pd=and(Pt,Ps) Byte Q6_p_and_pp(Byte Pt, Byte Ps) - Pd=not(Ps) Byte Q6_p_not_p(Byte Ps) - Pd=or(Ps,and(Pt,!Pu)) Byte Q6_p_or_and_ppnp(Byte Ps, Byte Pt, - Byte Pu) - Pd=or(Ps,and(Pt,Pu)) Byte Q6_p_or_and_ppp(Byte Ps, Byte Pt, Byte - Pu) - - - - -80-N2040-36 B 221 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Pd=or(Ps,or(Pt,!Pu)) Byte Q6_p_or_or_ppnp(Byte Ps, Byte Pt, Byte - Pu) - Pd=or(Ps,or(Pt,Pu)) Byte Q6_p_or_or_ppp(Byte Ps, Byte Pt, Byte - Pu) - Pd=or(Pt,!Ps) Byte Q6_p_or_pnp(Byte Pt, Byte Ps) - Pd=or(Pt,Ps) Byte Q6_p_or_pp(Byte Pt, Byte Ps) - Pd=xor(Ps,Pt) Byte Q6_p_xor_pp(Byte Ps, Byte Pt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s2 Parse t2 d2 -0 1 1 0 1 0 1 1 0 0 0 0 - - s s P P 0 - - - t t - - - - - - d d Pd=and(Pt,Ps) - ICLASS sm s2 Parse t2 u2 d2 -0 1 1 0 1 0 1 1 0 0 0 1 - - s s P P 0 - - - t t u u - - - - d d Pd=and(Ps,and(Pt,Pu)) - ICLASS sm s2 Parse t2 d2 -0 1 1 0 1 0 1 1 0 0 1 0 - - s s P P 0 - - - t t - - - - - - d d Pd=or(Pt,Ps) - ICLASS sm s2 Parse t2 u2 d2 -0 1 1 0 1 0 1 1 0 0 1 1 - - s s P P 0 - - - t t u u - - - - d d Pd=and(Ps,or(Pt,Pu)) - ICLASS sm s2 Parse t2 d2 -0 1 1 0 1 0 1 1 0 1 0 0 - - s s P P 0 - - - t t - - - - - - d d Pd=xor(Ps,Pt) - ICLASS sm s2 Parse t2 u2 d2 -0 1 1 0 1 0 1 1 0 1 0 1 - - s s P P 0 - - - t t u u - - - - d d Pd=or(Ps,and(Pt,Pu)) - ICLASS sm s2 Parse t2 d2 -0 1 1 0 1 0 1 1 0 1 1 0 - - s s P P 0 - - - t t - - - - - - d d Pd=and(Pt,!Ps) - ICLASS sm s2 Parse t2 u2 d2 -0 1 1 0 1 0 1 1 0 1 1 1 - - s s P P 0 - - - t t u u - - - - d d Pd=or(Ps,or(Pt,Pu)) -0 1 1 0 1 0 1 1 1 0 0 1 - - s s P P 0 - - - t t u u - - - - d d Pd=and(Ps,and(Pt,!Pu)) -0 1 1 0 1 0 1 1 1 0 1 1 - - s s P P 0 - - - t t u u - - - - d d Pd=and(Ps,or(Pt,!Pu)) - ICLASS sm s2 Parse d2 -0 1 1 0 1 0 1 1 1 1 0 0 - - s s P P 0 - - - - - - - - - - - d d Pd=not(Ps) - ICLASS sm s2 Parse t2 u2 d2 -0 1 1 0 1 0 1 1 1 1 0 1 - - s s P P 0 - - - t t u u - - - - d d Pd=or(Ps,and(Pt,!Pu)) - ICLASS sm s2 Parse t2 d2 -0 1 1 0 1 0 1 1 1 1 1 0 - - s s P P 0 - - - t t - - - - - - d d Pd=or(Pt,!Ps) - ICLASS sm s2 Parse t2 u2 d2 -0 1 1 0 1 0 1 1 1 1 1 1 - - s s P P 0 - - - t t u u - - - - d d Pd=or(Ps,or(Pt,!Pu)) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s2 Field to encode register s - t2 Field to encode register t - u2 Field to encode register u - - - - -80-N2040-36 B 222 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -User control register transfer - Move 32- or 64-bit values between a user control register and a general register. The user - control registers include SA, LC, Predicates, M, USR, PC, UGP, GP, and CS, and - UPCYCLE. The figure shows the user control registers and their register field encodings. - - Registers can be moved as singles or as aligned 64-bit pairs. - - Note that the PC register is not writable. A program flow instruction must be used to - change the PC value. - - - 0 SA0 8 USR 16 24 - - - 1 LC0 9 PC - - 2 SA1 10 UGP - - 3 LC1 11 GP - Reserved Reserved - 4 P3:0 12 CS0 - - - 5 Reserved 13 CS1 - - 6 M0 14 UPCYCLELO - - 7 M1 UPCYCLEHI - 15 23 31 - - - - - Syntax Behavior - Cd=Rs Cd=Rs; - Cdd=Rss Cdd=Rss; - Rd=Cs Rd=Cs; - Rdd=Css Rdd=Css; - - - Class: CR (slot 3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse d5 -0 1 1 0 0 0 1 0 0 0 1 s s s s s P P - - - - - - - - - d d d d d Cd=Rs -0 1 1 0 0 0 1 1 0 0 1 s s s s s P P - - - - - - - - - d d d d d Cdd=Rss -0 1 1 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - - - - d d d d d Rdd=Css -0 1 1 0 1 0 1 0 0 0 0 s s s s s P P - - - - - - - - - d d d d d Rd=Cs - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - - - - -80-N2040-36 B 223 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 224 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.3 JR - The JR instruction class includes instructions to change the program flow to a new - location contained in a register. - - JR instructions are executable on slot 2. - -Call subroutine from register - Change the program flow to a subroutine. This instruction first transfers the Next Program - Counter (NPC) value into the Link Register, and then jumps to a target address contained - in a register. - - This instruction can only appear in slot 2. - - Syntax Behavior - callr Rs LR=NPC; - PC=Rs; - ; - if ([!]Pu) callr Rs ; - if ([!]Pu[0]) { - LR=NPC; - PC=Rs; - ; - }; - - - Class: JR (slot 2) - - Notes - -  This instruction can be conditionally executed based on the value of a predicate - register. If the instruction is preceded by 'if Pn', then the instruction only executes - if the least-significant bit of the predicate register is 1. Similarly, if the instruction - is preceded by 'if !Pn', then the instruction is executed only if the least-significant - bit of Pn is 0. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse -0 1 0 1 0 0 0 0 1 0 1 s s s s s P P - - - - - - - - - - - - - - callr Rs - ICLASS s5 Parse u2 -0 1 0 1 0 0 0 1 0 0 0 s s s s s P P - - - - u u - - - - - - - - if (Pu) callr Rs -0 1 0 1 0 0 0 1 0 0 1 s s s s s P P - - - - u u - - - - - - - - if (!Pu) callr Rs - - - - - Field name Description - ICLASS Instruction Class - - - - -80-N2040-36 B 225 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Parse Packet/Loop parse bits - s5 Field to encode register s - u2 Field to encode register u - - - - -80-N2040-36 B 226 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Hint an indirect jump address - Provide a hint indicating that there will soon be an indirect JUMPR to the address - specified in Rs. - - Syntax Behavior - hintjr(Rs) ; - - - Class: JR (slot 2) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse -0 1 0 1 0 0 1 0 1 0 1 s s s s s P P - - - - - - - - - - - - - - hintjr(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 227 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Jump to address from register - Change the program flow to a target address. This instruction changes the Program - Counter to a target address contained in a register. - - This instruction can appear only in slot 2. - - Syntax Behavior - if ([!]Pu) jumpr Rs Assembler mapped to: "if ([!]Pu) - ""jumpr"":nt ""Rs" - if ([!]Pu[.new]) }; - jumpr: Rs { - if([!]Pu[.new][0]){ - PC=Rs; - ; - }; - jumpr Rs PC=Rs; - - - Class: JR (slot 2) - - Notes - -  This instruction can be conditionally executed based on the value of a predicate - register. If the instruction is preceded by 'if Pn', then the instruction only executes - if the least-significant bit of the predicate register is 1. Similarly, if the instruction - is preceded by 'if !Pn', then the instruction is executed only if the least-significant - bit of Pn is 0. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse -0 1 0 1 0 0 1 0 1 0 0 s s s s s P P - - - - - - - - - - - - - - jumpr Rs - ICLASS s5 Parse u2 -0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 0 0 - u u - - - - - - - - if (Pu) jumpr:nt Rs -0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 0 1 - u u - - - - - - - - if (Pu.new) jumpr:nt Rs -0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 1 0 - u u - - - - - - - - if (Pu) jumpr:t Rs -0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 1 1 - u u - - - - - - - - if (Pu.new) jumpr:t Rs -0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 0 0 - u u - - - - - - - - if (!Pu) jumpr:nt Rs -0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 0 1 - u u - - - - - - - - if (!Pu.new) jumpr:nt Rs -0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 1 0 - u u - - - - - - - - if (!Pu) jumpr:t Rs -0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 1 1 - u u - - - - - - - - if (!Pu.new) jumpr:t Rs - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - u2 Field to encode register u - - - -80-N2040-36 B 228 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.4 J - The J instruction class includes branch instructions (jumps and calls) that obtain the target - address from a (PC-relative) immediate address value. - - J instructions are executable on slot 2 and slot 3. - -Call subroutine - Change the program flow to a subroutine. This instruction first transfers the Next Program - Counter (NPC) value into the Link Register, and then jumps to the target address. - - This instruction can appear in slots 2 or 3. - - Syntax Behavior - call #r22:2 apply_extension(#r); - #r=#r & ~0x3; - LR=NPC; - PC=PC+#r; - ; - if ([!]Pu) call #r15:2 apply_extension(#r); - #r=#r & ~0x3; - ; - if ([!]Pu[0]) { - LR=NPC; - PC=PC+#r; - ; - }; - - - Class: J (slots 2,3) - - Notes - -  This instruction can be conditionally executed based on the value of a predicate - register. If the instruction is preceded by 'if Pn', then the instruction only executes - if the least-significant bit of the predicate register is 1. Similarly, if the instruction - is preceded by 'if !Pn', then the instruction is executed only if the least-significant - bit of Pn is 0. -  The Next PC value is the address immediately following the last instruction in the - packet containing this instruction. -  The PC value is the address of the start of the packet -  A PC-relative address is formed by taking the decoded immediate value and - adding it to the current PC value. - - - - -80-N2040-36 B 229 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Parse -0 1 0 1 1 0 1 i i i i i i i i i P P i i i i i i i i i i i i i 0 call #r22:2 - D - ICLASS Parse u2 - N -0 1 0 1 1 1 0 1 i i 0 i i i i i P P i - 0 - u u i i i i i i i - if (Pu) call #r15:2 -0 1 0 1 1 1 0 1 i i 1 i i i i i P P i - 0 - u u i i i i i i i - if (!Pu) call #r15:2 - - - - - Field name Description - ICLASS Instruction Class - DN Dot-new - Parse Packet/Loop parse bits - u2 Field to encode register u - - - - -80-N2040-36 B 230 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Compare and jump - Compare two registers, or a register and immediate value, and write a predicate with the - result. Then use the predicate result to conditionally jump to a PC-relative target address. - - The registers available as operands are restricted to R0-R7 and R16-R23. The predicate - destination is restricted to P0 and P1. - - In assembly syntax, this instruction appears as two instructions in the packet: a compare - and a separate conditional jump. The assembler may convert adjacent compare and jump - instructions into compound compare-jump form. - - Syntax Behavior - p[01]=cmp.eq(Rs,#-1); if P[01]=(Rs==-1) ? 0xff : 0x00 if - ([!]p[01].new) jump: ([!]P[01].new[0]) { - #r9:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - p[01]=cmp.eq(Rs,#U5); if P[01]=(Rs==#U) ? 0xff : 0x00 if - ([!]p[01].new) jump: ([!]P[01].new[0]) { - #r9:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - p[01]=cmp.eq(Rs,Rt); if P[01]=(Rs==Rt) ? 0xff : 0x00 if - ([!]p[01].new) jump: ([!]P[01].new[0]) { - #r9:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - p[01]=cmp.gt(Rs,#-1); if P[01]=(Rs>-1) ? 0xff : 0x00 if - ([!]p[01].new) jump: ([!]P[01].new[0]) { - #r9:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - - - - -80-N2040-36 B 231 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - p[01]=cmp.gt(Rs,#U5); if P[01]=(Rs>#U) ? 0xff : 0x00 if - ([!]p[01].new) jump: ([!]P[01].new[0]) { - #r9:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - p[01]=cmp.gt(Rs,Rt); if P[01]=(Rs>Rt) ? 0xff : 0x00 if - ([!]p[01].new) jump: ([!]P[01].new[0]) { - #r9:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - p[01]=cmp.gtu(Rs,#U5); if P[01]=(Rs.uw[0]>#U) ? 0xff : 0x00 if - ([!]p[01].new) jump: ([!]P[01].new[0]) { - #r9:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - p[01]=cmp.gtu(Rs,Rt); if P[01]=(Rs.uw[0]>Rt) ? 0xff : 0x00 if - ([!]p[01].new) jump: ([!]P[01].new[0]) { - #r9:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - p[01]=tstbit(Rs,#0); if P[01]=(Rs & 1) ? 0xff : 0x00 if - ([!]p[01].new) jump: ([!]P[01].new[0]) { - #r9:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - - - Class: J (slots 0,1,2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s4 Parse -0 0 0 1 0 0 0 1 1 0 i i s s s s P P 0 - - - 0 0 i i i i i i i - p0=cmp.eq(Rs,#-1); if (p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 1 1 0 i i s s s s P P 0 - - - 0 1 i i i i i i i - p0=cmp.gt(Rs,#-1); if (p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 1 1 0 i i s s s s P P 0 - - - 1 1 i i i i i i i - p0=tstbit(Rs,#0); if (p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 1 1 0 i i s s s s P P 1 - - - 0 0 i i i i i i i - p0=cmp.eq(Rs,#-1); if (p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 1 1 0 i i s s s s P P 1 - - - 0 1 i i i i i i i - p0=cmp.gt(Rs,#-1); if (p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 1 1 0 i i s s s s P P 1 - - - 1 1 i i i i i i i - p0=tstbit(Rs,#0); if (p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 1 1 1 i i s s s s P P 0 - - - 0 0 i i i i i i i - p0=cmp.eq(Rs,#-1); if (!p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 1 1 1 i i s s s s P P 0 - - - 0 1 i i i i i i i - p0=cmp.gt(Rs,#-1); if (!p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 1 1 1 i i s s s s P P 0 - - - 1 1 i i i i i i i - p0=tstbit(Rs,#0); if (!p0.new) jump:nt #r9:2 - - - - -80-N2040-36 B 232 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 0 0 1 0 0 0 1 1 1 i i s s s s P P 1 - - - 0 0 i i i i i i i - p0=cmp.eq(Rs,#-1); if (!p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 1 1 1 i i s s s s P P 1 - - - 0 1 i i i i i i i - p0=cmp.gt(Rs,#-1); if (!p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 1 1 1 i i s s s s P P 1 - - - 1 1 i i i i i i i - p0=tstbit(Rs,#0); if (!p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 0 0 0 i i s s s s P P 0 I I I I I i i i i i i i - p0=cmp.eq(Rs,#U5); if (p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 0 0 0 i i s s s s P P 1 I I I I I i i i i i i i - p0=cmp.eq(Rs,#U5); if (p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 0 0 1 i i s s s s P P 0 I I I I I i i i i i i i - p0=cmp.eq(Rs,#U5); if (!p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 0 0 1 i i s s s s P P 1 I I I I I i i i i i i i - p0=cmp.eq(Rs,#U5); if (!p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 0 1 0 i i s s s s P P 0 I I I I I i i i i i i i - p0=cmp.gt(Rs,#U5); if (p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 0 1 0 i i s s s s P P 1 I I I I I i i i i i i i - p0=cmp.gt(Rs,#U5); if (p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 0 1 1 i i s s s s P P 0 I I I I I i i i i i i i - p0=cmp.gt(Rs,#U5); if (!p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 0 1 1 i i s s s s P P 1 I I I I I i i i i i i i - p0=cmp.gt(Rs,#U5); if (!p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 1 0 0 i i s s s s P P 0 I I I I I i i i i i i i - p0=cmp.gtu(Rs,#U5); if (p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 1 0 0 i i s s s s P P 1 I I I I I i i i i i i i - p0=cmp.gtu(Rs,#U5); if (p0.new) jump:t #r9:2 -0 0 0 1 0 0 0 1 0 1 i i s s s s P P 0 I I I I I i i i i i i i - p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:nt #r9:2 -0 0 0 1 0 0 0 1 0 1 i i s s s s P P 1 I I I I I i i i i i i i - p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:t #r9:2 -0 0 0 1 0 0 1 1 1 0 i i s s s s P P 0 - - - 0 0 i i i i i i i - p1=cmp.eq(Rs,#-1); if (p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 1 1 0 i i s s s s P P 0 - - - 0 1 i i i i i i i - p1=cmp.gt(Rs,#-1); if (p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 1 1 0 i i s s s s P P 0 - - - 1 1 i i i i i i i - p1=tstbit(Rs,#0); if (p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 1 1 0 i i s s s s P P 1 - - - 0 0 i i i i i i i - p1=cmp.eq(Rs,#-1); if (p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 1 1 0 i i s s s s P P 1 - - - 0 1 i i i i i i i - p1=cmp.gt(Rs,#-1); if (p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 1 1 0 i i s s s s P P 1 - - - 1 1 i i i i i i i - p1=tstbit(Rs,#0); if (p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 1 1 1 i i s s s s P P 0 - - - 0 0 i i i i i i i - p1=cmp.eq(Rs,#-1); if (!p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 1 1 1 i i s s s s P P 0 - - - 0 1 i i i i i i i - p1=cmp.gt(Rs,#-1); if (!p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 1 1 1 i i s s s s P P 0 - - - 1 1 i i i i i i i - p1=tstbit(Rs,#0); if (!p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 1 1 1 i i s s s s P P 1 - - - 0 0 i i i i i i i - p1=cmp.eq(Rs,#-1); if (!p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 1 1 1 i i s s s s P P 1 - - - 0 1 i i i i i i i - p1=cmp.gt(Rs,#-1); if (!p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 1 1 1 i i s s s s P P 1 - - - 1 1 i i i i i i i - p1=tstbit(Rs,#0); if (!p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 0 0 0 i i s s s s P P 0 I I I I I i i i i i i i - p1=cmp.eq(Rs,#U5); if (p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 0 0 0 i i s s s s P P 1 I I I I I i i i i i i i - p1=cmp.eq(Rs,#U5); if (p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 0 0 1 i i s s s s P P 0 I I I I I i i i i i i i - p1=cmp.eq(Rs,#U5); if (!p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 0 0 1 i i s s s s P P 1 I I I I I i i i i i i i - p1=cmp.eq(Rs,#U5); if (!p1.new) jump:t #r9:2 - - - - -80-N2040-36 B 233 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 0 0 1 0 0 1 0 1 0 i i s s s s P P 0 I I I I I i i i i i i i - p1=cmp.gt(Rs,#U5); if (p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 0 1 0 i i s s s s P P 1 I I I I I i i i i i i i - p1=cmp.gt(Rs,#U5); if (p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 0 1 1 i i s s s s P P 0 I I I I I i i i i i i i - p1=cmp.gt(Rs,#U5); if (!p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 0 1 1 i i s s s s P P 1 I I I I I i i i i i i i - p1=cmp.gt(Rs,#U5); if (!p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 1 0 0 i i s s s s P P 0 I I I I I i i i i i i i - p1=cmp.gtu(Rs,#U5); if (p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 1 0 0 i i s s s s P P 1 I I I I I i i i i i i i - p1=cmp.gtu(Rs,#U5); if (p1.new) jump:t #r9:2 -0 0 0 1 0 0 1 1 0 1 i i s s s s P P 0 I I I I I i i i i i i i - p1=cmp.gtu(Rs,#U5); if (!p1.new) jump:nt #r9:2 -0 0 0 1 0 0 1 1 0 1 i i s s s s P P 1 I I I I I i i i i i i i - p1=cmp.gtu(Rs,#U5); if (!p1.new) jump:t #r9:2 - ICLASS s4 Parse t4 -0 0 0 1 0 1 0 0 0 0 i i s s s s P P 0 0 t t t t i i i i i i i - p0=cmp.eq(Rs,Rt); if (p0.new) jump:nt #r9:2 -0 0 0 1 0 1 0 0 0 0 i i s s s s P P 0 1 t t t t i i i i i i i - p1=cmp.eq(Rs,Rt); if (p1.new) jump:nt #r9:2 -0 0 0 1 0 1 0 0 0 0 i i s s s s P P 1 0 t t t t i i i i i i i - p0=cmp.eq(Rs,Rt); if (p0.new) jump:t #r9:2 -0 0 0 1 0 1 0 0 0 0 i i s s s s P P 1 1 t t t t i i i i i i i - p1=cmp.eq(Rs,Rt); if (p1.new) jump:t #r9:2 -0 0 0 1 0 1 0 0 0 1 i i s s s s P P 0 0 t t t t i i i i i i i - p0=cmp.eq(Rs,Rt); if (!p0.new) jump:nt #r9:2 -0 0 0 1 0 1 0 0 0 1 i i s s s s P P 0 1 t t t t i i i i i i i - p1=cmp.eq(Rs,Rt); if (!p1.new) jump:nt #r9:2 -0 0 0 1 0 1 0 0 0 1 i i s s s s P P 1 0 t t t t i i i i i i i - p0=cmp.eq(Rs,Rt); if (!p0.new) jump:t #r9:2 -0 0 0 1 0 1 0 0 0 1 i i s s s s P P 1 1 t t t t i i i i i i i - p1=cmp.eq(Rs,Rt); if (!p1.new) jump:t #r9:2 -0 0 0 1 0 1 0 0 1 0 i i s s s s P P 0 0 t t t t i i i i i i i - p0=cmp.gt(Rs,Rt); if (p0.new) jump:nt #r9:2 -0 0 0 1 0 1 0 0 1 0 i i s s s s P P 0 1 t t t t i i i i i i i - p1=cmp.gt(Rs,Rt); if (p1.new) jump:nt #r9:2 -0 0 0 1 0 1 0 0 1 0 i i s s s s P P 1 0 t t t t i i i i i i i - p0=cmp.gt(Rs,Rt); if (p0.new) jump:t #r9:2 -0 0 0 1 0 1 0 0 1 0 i i s s s s P P 1 1 t t t t i i i i i i i - p1=cmp.gt(Rs,Rt); if (p1.new) jump:t #r9:2 -0 0 0 1 0 1 0 0 1 1 i i s s s s P P 0 0 t t t t i i i i i i i - p0=cmp.gt(Rs,Rt); if (!p0.new) jump:nt #r9:2 -0 0 0 1 0 1 0 0 1 1 i i s s s s P P 0 1 t t t t i i i i i i i - p1=cmp.gt(Rs,Rt); if (!p1.new) jump:nt #r9:2 -0 0 0 1 0 1 0 0 1 1 i i s s s s P P 1 0 t t t t i i i i i i i - p0=cmp.gt(Rs,Rt); if (!p0.new) jump:t #r9:2 -0 0 0 1 0 1 0 0 1 1 i i s s s s P P 1 1 t t t t i i i i i i i - p1=cmp.gt(Rs,Rt); if (!p1.new) jump:t #r9:2 -0 0 0 1 0 1 0 1 0 0 i i s s s s P P 0 0 t t t t i i i i i i i - p0=cmp.gtu(Rs,Rt); if (p0.new) jump:nt #r9:2 -0 0 0 1 0 1 0 1 0 0 i i s s s s P P 0 1 t t t t i i i i i i i - p1=cmp.gtu(Rs,Rt); if (p1.new) jump:nt #r9:2 -0 0 0 1 0 1 0 1 0 0 i i s s s s P P 1 0 t t t t i i i i i i i - p0=cmp.gtu(Rs,Rt); if (p0.new) jump:t #r9:2 - - -80-N2040-36 B 234 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 0 0 1 0 1 0 1 0 0 i i s s s s P P 1 1 t t t t i i i i i i i - p1=cmp.gtu(Rs,Rt); if (p1.new) jump:t #r9:2 -0 0 0 1 0 1 0 1 0 1 i i s s s s P P 0 0 t t t t i i i i i i i - p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:nt #r9:2 -0 0 0 1 0 1 0 1 0 1 i i s s s s P P 0 1 t t t t i i i i i i i - p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:nt #r9:2 -0 0 0 1 0 1 0 1 0 1 i i s s s s P P 1 0 t t t t i i i i i i i - p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:t #r9:2 -0 0 0 1 0 1 0 1 0 1 i i s s s s P P 1 1 t t t t i i i i i i i - p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:t #r9:2 - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s4 Field to encode register s - t4 Field to encode register t - - - - -80-N2040-36 B 235 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Jump to address - Change the program flow to a target address. This instruction changes the Program - Counter to a target address which is relative to the PC address. The offset from the current - PC address is contained in the instruction encoding. - - A speculated jump instruction includes a hint ("taken" or "not taken") which specifies the - expected value of the conditional expression. If the actual generated value of the predicate - differs from this expected value, the jump instruction incurs a performance penalty. - - This instruction can appear in slots 2 or 3. - - Syntax Behavior - if ([!]Pu) jump #r15:2 Assembler mapped to: "if ([!]Pu) - ""jump"":nt ""#r15:2" - if ([!]Pu) jump: ; - #r15:2 if ([!]Pu[0]) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - ; - }; - jump #r22:2 apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - - - Class: J (slots 0,1,2,3) - - Notes - -  This instruction can be conditionally executed based on the value of a predicate - register. If the instruction is preceded by 'if Pn', then the instruction only executes - if the least-significant bit of the predicate register is 1. Similarly, if the instruction - is preceded by 'if !Pn', then the instruction is executed only if the least-significant - bit of Pn is 0. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Parse -0 1 0 1 1 0 0 i i i i i i i i i P P i i i i i i i i i i i i i - jump #r22:2 - D - ICLASS Parse PT N u2 - -0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 0 - u u i i i i i i i - if (Pu) jump:nt #r15:2 -0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 0 - u u i i i i i i i - if (Pu) jump:t #r15:2 -0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 0 - u u i i i i i i i - if (!Pu) jump:nt #r15:2 -0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 0 - u u i i i i i i i - if (!Pu) jump:t #r15:2 - - - - -80-N2040-36 B 236 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - DN Dot-new - PT Predict-taken - Parse Packet/Loop parse bits - u2 Field to encode register u - - - - -80-N2040-36 B 237 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Jump to address conditioned on new predicate - Perform speculated jump. - - Jump if the LSB of the newly-generated predicate is true. The predicate must be generated - in the same packet as the speculated jump instruction. - - A speculated jump instruction includes a hint ("taken" or "not taken") which specifies the - expected value of the conditional expression. If the actual generated value of the predicate - differs from this expected value, the jump instruction incurs a performance penalty. - - This instruction can appear in slots 2 or 3. - - Syntax Behavior - if ([!]Pu.new) jump: #r15:2 }; - { - if([!]Pu.new[0]){ - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - ; - }; - - - Class: J (slots 0,1,2,3) - - Notes - -  This instruction can be conditionally executed based on the value of a predicate - register. If the instruction is preceded by 'if Pn', then the instruction only executes - if the least-significant bit of the predicate register is 1. Similarly, if the instruction - is preceded by 'if !Pn', then the instruction is executed only if the least-significant - bit of Pn is 0. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - D - ICLASS Parse PT N u2 - -0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 1 - u u i i i i i i i - if (Pu.new) jump:nt #r15:2 -0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 1 - u u i i i i i i i - if (Pu.new) jump:t #r15:2 -0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 1 - u u i i i i i i i - if (!Pu.new) jump:nt #r15:2 -0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 1 - u u i i i i i i i - if (!Pu.new) jump:t #r15:2 - - - - - Field name Description - ICLASS Instruction Class - DN Dot-new - PT Predict-taken - Parse Packet/Loop parse bits - u2 Field to encode register u - - - - -80-N2040-36 B 238 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Jump to address condition on register value - Perform register-conditional jump. - - Jump if the specified register expression is true. - - A register-conditional jump includes a hint ("taken" or "not taken") which specifies the - expected value of the register expression. If the actual generated value of the expression - differs from this expected value, the jump instruction incurs a performance penalty. - - This instruction can appear only in slot 3. - - Syntax Behavior - if (Rs!=#0) jump:nt #r13:2 if (Rs != 0) { - PC=PC+#r; - }; - if (Rs!=#0) jump:t #r13:2 if (Rs != 0) { - PC=PC+#r; - }; - if (Rs<=#0) jump:nt #r13:2 if (Rs<=0) { - PC=PC+#r; - }; - if (Rs<=#0) jump:t #r13:2 if (Rs<=0) { - PC=PC+#r; - }; - if (Rs==#0) jump:nt #r13:2 if (Rs == 0) { - PC=PC+#r; - }; - if (Rs==#0) jump:t #r13:2 if (Rs == 0) { - PC=PC+#r; - }; - if (Rs>=#0) jump:nt #r13:2 if (Rs>=0) { - PC=PC+#r; - }; - if (Rs>=#0) jump:t #r13:2 if (Rs>=0) { - PC=PC+#r; - }; - - - Class: J (slot 3) - - Notes - -  This instruction will be deprecated in a future version. - - - - -80-N2040-36 B 239 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 0 i i i i i i i i i i i - if (Rs!=#0) jump:nt #r13:2 -0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 1 i i i i i i i i i i i - if (Rs!=#0) jump:t #r13:2 -0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 0 i i i i i i i i i i i - if (Rs>=#0) jump:nt #r13:2 -0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 1 i i i i i i i i i i i - if (Rs>=#0) jump:t #r13:2 -0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 0 i i i i i i i i i i i - if (Rs==#0) jump:nt #r13:2 -0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 1 i i i i i i i i i i i - if (Rs==#0) jump:t #r13:2 -0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 0 i i i i i i i i i i i - if (Rs<=#0) jump:nt #r13:2 -0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 1 i i i i i i i i i i i - if (Rs<=#0) jump:t #r13:2 - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 240 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Transfer and jump - Move an unsigned immediate or register value into a destination register and - unconditionally jump. In assembly syntax, this instruction appears as two instructions in - the packet, a transfer and a separate jump. The assembler may convert adjacent transfer - and jump instructions into compound transfer-jump form. - - Syntax Behavior - Rd=#U6 ; jump #r9:2 apply_extension(#r); - #r=#r & ~0x3; - Rd=#U; - PC=PC+#r; - Rd=Rs ; jump #r9:2 apply_extension(#r); - #r=#r & ~0x3; - Rd=Rs; - PC=PC+#r; - - - Class: J (slots 2,3) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS d4 Parse -0 0 0 1 0 1 1 0 - - i i d d d d P P I I I I I I i i i i i i i - Rd=#U6 ; jump #r9:2 - ICLASS s4 Parse d4 -0 0 0 1 0 1 1 1 - - i i s s s s P P - - d d d d i i i i i i i - Rd=Rs ; jump #r9:2 - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d4 Field to encode register d - s4 Field to encode register s - - - - -80-N2040-36 B 241 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.5 LD - The LD instruction class includes load instructions, which are used to load values into - registers. - - LD instructions are executable on slot 0 and slot 1. - -Load doubleword - Load a 64-bit doubleword from memory and place in a destination register pair. - - Syntax Behavior - Rdd=memd(Re=#U6) apply_extension(#U); - EA=#U; - Rdd = *EA; - Re=#U; - Rdd=memd(Rs+#s11:3) apply_extension(#s); - EA=Rs+#s; - Rdd = *EA; - Rdd=memd(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rdd = *EA; - Rdd=memd(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - Rdd = *EA; - Rdd=memd(Rx++#s4:3) EA=Rx; - Rx=Rx+#s; - Rdd = *EA; - Rdd=memd(Rx++#s4:3:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - Rdd = *EA; - Rdd=memd(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<3,MuV); - Rdd = *EA; - Rdd=memd(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - Rdd = *EA; - Rdd=memd(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - Rdd = *EA; - Rdd=memd(gp+#u16:3) apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - Rdd = *EA; - - - - -80-N2040-36 B 242 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 -0 0 1 1 1 0 1 0 1 1 0 s s s s s P P i t t t t t i - - d d d d d Rdd=memd(Rs+Rt<<#u2) - U - ICLASS Type Parse d5 - N -0 1 0 0 1 i i 1 1 1 0 i i i i i P P i i i i i i i i i d d d d d Rdd=memd(gp+#u16:3) - U - ICLASS Amode Type N s5 Parse d5 - -1 0 0 1 0 i i 1 1 1 0 s s s s s P P i i i i i i i i i d d d d d Rdd=memd(Rs+#s11:3) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 0 0 1 1 1 0 x x x x x P P u 0 - - 0 i i i i d d d d d Rdd=memd(Rx++#s4:3:circ(Mu)) - -1 0 0 1 1 0 0 1 1 1 0 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rdd=memd(Rx++I:circ(Mu)) - U - ICLASS Amode Type e5 Parse d5 - N -1 0 0 1 1 0 1 1 1 1 0 e e e e e P P 0 1 I I I I - I I d d d d d Rdd=memd(Re=#U6) - - ICLASS Amode Type U x5 Parse d5 - N -1 0 0 1 1 0 1 1 1 1 0 x x x x x P P 0 0 - - - i i i i d d d d d Rdd=memd(Rx++#s4:3) - - ICLASS Amode Type U t5 Parse d5 - N -1 0 0 1 1 1 0 1 1 1 0 t t t t t P P i 1 I I I I i I I d d d d d Rdd=memd(Rt<<#u2+#U6) - U - ICLASS Amode Type N x5 Parse u1 d5 - -1 0 0 1 1 1 0 1 1 1 0 x x x x x P P u 0 - - - - 0 - - d d d d d Rdd=memd(Rx++Mu) -1 0 0 1 1 1 1 1 1 1 0 x x x x x P P u 0 - - - - 0 - - d d d d d Rdd=memd(Rx++Mu:brev) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - Parse Packet/Loop parse bits - d5 Field to encode register d - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 243 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load doubleword conditionally - Load a 64-bit doubleword from memory and place in a destination register pair. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pt[.new]) Rdd=memd(#u6) if ([!]Pt[.new][0]) { - apply_extension(#u); - EA=#u; - Rdd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) Rdd=memd(Rs+#u6:3) if ([!]Pt[.new][0]) { - apply_extension(#u); - EA=Rs+#u; - Rdd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) Rdd=memd(Rx++#s4:3) if([!]Pt[.new][0]){ - EA=Rx; - Rx=Rx+#s; - Rdd = *EA; - } else { - NOP; - }; - if ([!]Pv[.new]) Rdd=memd(Rs+Rt<<#u2) if ([!]Pv[.new][0]) { - EA=Rs+(Rt<<#u); - Rdd = *EA; - } else { - NOP; - }; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 -0 0 1 1 0 0 0 0 1 1 0 s s s s s P P i t t t t t i v v d d d d d if (Pv) Rdd=memd(Rs+Rt<<#u2) -0 0 1 1 0 0 0 1 1 1 0 s s s s s P P i t t t t t i v v d d d d d if (!Pv) Rdd=memd(Rs+Rt<<#u2) -0 0 1 1 0 0 1 0 1 1 0 s s s s s P P i t t t t t i v v d d d d d if (Pv.new) Rdd=memd(Rs+Rt<<#u2) -0 0 1 1 0 0 1 1 1 1 0 s s s s s P P i t t t t t i v v d d d d d if (!Pv.new) Rdd=memd(Rs+Rt<<#u2) - Pr - Se ed - U - ICLASS ns Ne Type - N s5 Parse t2 d5 - e w - -0 1 0 0 0 0 0 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d if (Pt) Rdd=memd(Rs+#u6:3) - - - - -80-N2040-36 B 244 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 1 0 0 0 0 1 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d if (Pt.new) Rdd=memd(Rs+#u6:3) -0 1 0 0 0 1 0 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt) Rdd=memd(Rs+#u6:3) -0 1 0 0 0 1 1 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt.new) Rdd=memd(Rs+#u6:3) - U - ICLASS Amode Type N x5 Parse t2 d5 - -1 0 0 1 1 0 1 1 1 1 0 x x x x x P P 1 0 0 t t i i i i d d d d d if (Pt) Rdd=memd(Rx++#s4:3) -1 0 0 1 1 0 1 1 1 1 0 x x x x x P P 1 0 1 t t i i i i d d d d d if (!Pt) Rdd=memd(Rx++#s4:3) -1 0 0 1 1 0 1 1 1 1 0 x x x x x P P 1 1 0 t t i i i i d d d d d if (Pt.new) Rdd=memd(Rx++#s4:3) -1 0 0 1 1 0 1 1 1 1 0 x x x x x P P 1 1 1 t t i i i i d d d d d if (!Pt.new) Rdd=memd(Rx++#s4:3) - U - ICLASS Amode Type Parse t2 d5 - N -1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 0 t t i 1 - - d d d d d if (Pt) Rdd=memd(#u6) -1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 1 t t i 1 - - d d d d d if (!Pt) Rdd=memd(#u6) -1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 0 t t i 1 - - d d d d d if (Pt.new) Rdd=memd(#u6) -1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 1 t t i 1 - - d d d d d if (!Pt.new) Rdd=memd(#u6) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t2 Field to encode register t - t5 Field to encode register t - v2 Field to encode register v - x5 Field to encode register x - - - - -80-N2040-36 B 245 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load byte - Load a signed byte from memory. The byte at the effective address in memory is placed in - the least-significant 8 bits of the destination register. The destination register is then sign- - extended from 8 bits to 32. - - Syntax Behavior - Rd=memb(Re=#U6) apply_extension(#U); - EA=#U; - Rd = *EA; - Re=#U; - Rd=memb(Rs+#s11:0) apply_extension(#s); - EA=Rs+#s; - Rd = *EA; - Rd=memb(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rd = *EA; - Rd=memb(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - Rd = *EA; - Rd=memb(Rx++#s4:0) EA=Rx; - Rx=Rx+#s; - Rd = *EA; - Rd=memb(Rx++#s4:0:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - Rd = *EA; - Rd=memb(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<0,MuV); - Rd = *EA; - Rd=memb(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - Rd = *EA; - Rd=memb(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - Rd = *EA; - Rd=memb(gp+#u16:0) apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - Rd = *EA; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 -0 0 1 1 1 0 1 0 0 0 0 s s s s s P P i t t t t t i - - d d d d d Rd=memb(Rs+Rt<<#u2) - U - ICLASS Type Parse d5 - N -0 1 0 0 1 i i 1 0 0 0 i i i i i P P i i i i i i i i i d d d d d Rd=memb(gp+#u16:0) - U - ICLASS Amode Type s5 Parse d5 - N - - - - -80-N2040-36 B 246 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 1 0 i i 1 0 0 0 s s s s s P P i i i i i i i i i d d d d d Rd=memb(Rs+#s11:0) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 0 0 1 0 0 0 x x x x x P P u 0 - - 0 i i i i d d d d d Rd=memb(Rx++#s4:0:circ(Mu)) -1 0 0 1 1 0 0 1 0 0 0 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rd=memb(Rx++I:circ(Mu)) - U - ICLASS Amode Type e5 Parse d5 - N -1 0 0 1 1 0 1 1 0 0 0 e e e e e P P 0 1 I I I I - I I d d d d d Rd=memb(Re=#U6) - - ICLASS Amode Type U x5 Parse d5 - N -1 0 0 1 1 0 1 1 0 0 0 x x x x x P P 0 0 - - - i i i i d d d d d Rd=memb(Rx++#s4:0) - U - ICLASS Amode Type t5 Parse d5 - N -1 0 0 1 1 1 0 1 0 0 0 t t t t t P P i 1 I I I I i I I d d d d d Rd=memb(Rt<<#u2+#U6) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 1 0 1 0 0 0 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memb(Rx++Mu) -1 0 0 1 1 1 1 1 0 0 0 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memb(Rx++Mu:brev) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - Parse Packet/Loop parse bits - d5 Field to encode register d - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 247 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load byte conditionally - Load a signed byte from memory. The byte at the effective address in memory is placed in - the least-significant 8 bits of the destination register. The destination register is then sign- - extended from 8 bits to 32. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pt[.new]) Rd=memb(#u6) if ([!]Pt[.new][0]) { - apply_extension(#u); - EA=#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) Rd=memb(Rs+#u6:0) if ([!]Pt[.new][0]) { - apply_extension(#u); - EA=Rs+#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) Rd=memb(Rx++#s4:0) if([!]Pt[.new][0]){ - EA=Rx; - Rx=Rx+#s; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2) if ([!]Pv[.new][0]) { - EA=Rs+(Rt<<#u); - Rd = *EA; - } else { - NOP; - }; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 -0 0 1 1 0 0 0 0 0 0 0 s s s s s P P i t t t t t i v v d d d d d if (Pv) Rd=memb(Rs+Rt<<#u2) -0 0 1 1 0 0 0 1 0 0 0 s s s s s P P i t t t t t i v v d d d d d if (!Pv) Rd=memb(Rs+Rt<<#u2) -0 0 1 1 0 0 1 0 0 0 0 s s s s s P P i t t t t t i v v d d d d d if (Pv.new) Rd=memb(Rs+Rt<<#u2) -0 0 1 1 0 0 1 1 0 0 0 s s s s s P P i t t t t t i v v d d d d d if (!Pv.new) Rd=memb(Rs+Rt<<#u2) - - - - -80-N2040-36 B 248 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - Pr - Se - ed U - ICLASS ns Type s5 Parse t2 d5 - Ne N - e - w -0 1 0 0 0 0 0 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d if (Pt) Rd=memb(Rs+#u6:0) -0 1 0 0 0 0 1 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d if (Pt.new) Rd=memb(Rs+#u6:0) -0 1 0 0 0 1 0 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt) Rd=memb(Rs+#u6:0) -0 1 0 0 0 1 1 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt.new) Rd=memb(Rs+#u6:0) - U - ICLASS Amode Type x5 Parse t2 d5 - N -1 0 0 1 1 0 1 1 0 0 0 x x x x x P P 1 0 0 t t i i i i d d d d d if (Pt) Rd=memb(Rx++#s4:0) -1 0 0 1 1 0 1 1 0 0 0 x x x x x P P 1 0 1 t t i i i i d d d d d if (!Pt) Rd=memb(Rx++#s4:0) -1 0 0 1 1 0 1 1 0 0 0 x x x x x P P 1 1 0 t t i i i i d d d d d if (Pt.new) Rd=memb(Rx++#s4:0) -1 0 0 1 1 0 1 1 0 0 0 x x x x x P P 1 1 1 t t i i i i d d d d d if (!Pt.new) Rd=memb(Rx++#s4:0) - - ICLASS Amode Type U Parse t2 d5 - N -1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 0 t t i 1 - - d d d d d if (Pt) Rd=memb(#u6) -1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 1 t t i 1 - - d d d d d if (!Pt) Rd=memb(#u6) -1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 0 t t i 1 - - d d d d d if (Pt.new) Rd=memb(#u6) -1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 1 t t i 1 - - d d d d d if (!Pt.new) Rd=memb(#u6) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t2 Field to encode register t - t5 Field to encode register t - v2 Field to encode register v - x5 Field to encode register x - - - - -80-N2040-36 B 249 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load byte into shifted vector - Shift a 64-bit vector right by one byte. Insert a byte from memory into the vacated upper - byte of the vector. - - - Mem - Ryy - - - - - Ryy - - - Syntax Behavior - Ryy=memb_fifo(Re=#U6) apply_extension(#U); - EA=#U; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56); - }; - ; - Re=#U; - Ryy=memb_fifo(Rs) Assembler mapped to: - "Ryy=memb_fifo""(Rs+#0)" - Ryy=memb_fifo(Rs+#s11:0) apply_extension(#s); - EA=Rs+#s; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56); - }; - ; - Ryy=memb_fifo(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56); - }; - ; - - - - -80-N2040-36 B 250 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Ryy=memb_fifo(Rx++#s4:0) EA=Rx; - Rx=Rx+#s; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56); - }; - ; - Ryy=memb_fifo(Rx++#s4:0:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56); - }; - ; - Ryy=memb_fifo(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<0,MuV); - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56); - }; - ; - Ryy=memb_fifo(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56); - }; - ; - Ryy=memb_fifo(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>8)|(tmpV<<56); - }; - ; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse y5 - N -1 0 0 1 0 i i 0 1 0 0 s s s s s P P i i i i i i i i i y y y y y Ryy=memb_fifo(Rs+#s11:0) - U - ICLASS Amode Type x5 Parse u1 y5 - N - -1 0 0 1 1 0 0 0 1 0 0 x x x x x P P u 0 - - 0 i i i i y y y y y Ryy=memb_fifo(Rx++#s4:0:circ(Mu)) -1 0 0 1 1 0 0 0 1 0 0 x x x x x P P u 0 - - 1 - 0 - - y y y y y Ryy=memb_fifo(Rx++I:circ(Mu)) - U - ICLASS Amode Type N e5 Parse y5 - -1 0 0 1 1 0 1 0 1 0 0 e e e e e P P 0 1 I I I I - I I y y y y y Ryy=memb_fifo(Re=#U6) - U - ICLASS Amode Type N - x5 Parse y5 - - - - -80-N2040-36 B 251 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 1 1 0 1 0 1 0 0 x x x x x P P 0 0 - - - i i i i y y y y y Ryy=memb_fifo(Rx++#s4:0) - U - ICLASS Amode Type t5 Parse y5 - N -1 0 0 1 1 1 0 0 1 0 0 t t t t t P P i 1 I I I I i I I y y y y y Ryy=memb_fifo(Rt<<#u2+#U6) - U - ICLASS Amode Type N x5 Parse u1 y5 - -1 0 0 1 1 1 0 0 1 0 0 x x x x x P P u 0 - - - - 0 - - y y y y y Ryy=memb_fifo(Rx++Mu) -1 0 0 1 1 1 1 0 1 0 0 x x x x x P P u 0 - - - - 0 - - y y y y y Ryy=memb_fifo(Rx++Mu:brev) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Parse Packet/Loop parse bits - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - x5 Field to encode register x - y5 Field to encode register y - - - - -80-N2040-36 B 252 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load half into shifted vector - Shift a 64-bit vector right by one halfword. Insert a halfword from memory into the - vacated upper halfword of the vector. - - - Mem - Ryy - - - - - Ryy - - - Syntax Behavior - Ryy=memh_fifo(Re=#U6) apply_extension(#U); - EA=#U; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48); - }; - ; - Re=#U; - Ryy=memh_fifo(Rs) Assembler mapped to: - "Ryy=memh_fifo""(Rs+#0)" - Ryy=memh_fifo(Rs+#s11:1) apply_extension(#s); - EA=Rs+#s; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48); - }; - ; - Ryy=memh_fifo(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48); - }; - ; - - - - -80-N2040-36 B 253 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Ryy=memh_fifo(Rx++#s4:1) EA=Rx; - Rx=Rx+#s; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48); - }; - ; - Ryy=memh_fifo(Rx++#s4:1:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48); - }; - ; - Ryy=memh_fifo(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<1,MuV); - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48); - }; - ; - Ryy=memh_fifo(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48); - }; - ; - Ryy=memh_fifo(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - { - tmpV = *EA; - Ryy = (((size8u_t)Ryy)>>16)|(tmpV<<48); - }; - ; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse y5 - N -1 0 0 1 0 i i 0 0 1 0 s s s s s P P i i i i i i i i i y y y y y Ryy=memh_fifo(Rs+#s11:1) - U - ICLASS Amode Type x5 Parse u1 y5 - N - -1 0 0 1 1 0 0 0 0 1 0 x x x x x P P u 0 - - 0 i i i i y y y y y Ryy=memh_fifo(Rx++#s4:1:circ(Mu)) -1 0 0 1 1 0 0 0 0 1 0 x x x x x P P u 0 - - 1 - 0 - - y y y y y Ryy=memh_fifo(Rx++I:circ(Mu)) - U - ICLASS Amode Type N e5 Parse y5 - -1 0 0 1 1 0 1 0 0 1 0 e e e e e P P 0 1 I I I I - I I y y y y y Ryy=memh_fifo(Re=#U6) - U - ICLASS Amode Type N - x5 Parse y5 - - - - -80-N2040-36 B 254 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 1 1 0 1 0 0 1 0 x x x x x P P 0 0 - - - i i i i y y y y y Ryy=memh_fifo(Rx++#s4:1) - U - ICLASS Amode Type t5 Parse y5 - N -1 0 0 1 1 1 0 0 0 1 0 t t t t t P P i 1 I I I I i I I y y y y y Ryy=memh_fifo(Rt<<#u2+#U6) - U - ICLASS Amode Type N x5 Parse u1 y5 - -1 0 0 1 1 1 0 0 0 1 0 x x x x x P P u 0 - - - - 0 - - y y y y y Ryy=memh_fifo(Rx++Mu) -1 0 0 1 1 1 1 0 0 1 0 x x x x x P P u 0 - - - - 0 - - y y y y y Ryy=memh_fifo(Rx++Mu:brev) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Parse Packet/Loop parse bits - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - x5 Field to encode register x - y5 Field to encode register y - - - - -80-N2040-36 B 255 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load halfword - Load a signed halfword from memory. The 16-bit halfword at the effective address in - memory is placed in the least-significant 16 bits of the destination register. The destination - register is then sign-extended from 16 bits to 32. - - Syntax Behavior - Rd=memh(Re=#U6) apply_extension(#U); - EA=#U; - Rd = *EA; - Re=#U; - Rd=memh(Rs+#s11:1) apply_extension(#s); - EA=Rs+#s; - Rd = *EA; - Rd=memh(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rd = *EA; - Rd=memh(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - Rd = *EA; - Rd=memh(Rx++#s4:1) EA=Rx; - Rx=Rx+#s; - Rd = *EA; - Rd=memh(Rx++#s4:1:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - Rd = *EA; - Rd=memh(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<1,MuV); - Rd = *EA; - Rd=memh(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - Rd = *EA; - Rd=memh(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - Rd = *EA; - Rd=memh(gp+#u16:1) apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - Rd = *EA; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 -0 0 1 1 1 0 1 0 0 1 0 s s s s s P P i t t t t t i - - d d d d d Rd=memh(Rs+Rt<<#u2) - U - ICLASS Type Parse d5 - N -0 1 0 0 1 i i 1 0 1 0 i i i i i P P i i i i i i i i i d d d d d Rd=memh(gp+#u16:1) - U - ICLASS Amode Type s5 Parse d5 - N - - - - -80-N2040-36 B 256 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 1 0 i i 1 0 1 0 s s s s s P P i i i i i i i i i d d d d d Rd=memh(Rs+#s11:1) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 0 0 1 0 1 0 x x x x x P P u 0 - - 0 i i i i d d d d d Rd=memh(Rx++#s4:1:circ(Mu)) -1 0 0 1 1 0 0 1 0 1 0 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rd=memh(Rx++I:circ(Mu)) - U - ICLASS Amode Type e5 Parse d5 - N -1 0 0 1 1 0 1 1 0 1 0 e e e e e P P 0 1 I I I I - I I d d d d d Rd=memh(Re=#U6) - - ICLASS Amode Type U x5 Parse d5 - N -1 0 0 1 1 0 1 1 0 1 0 x x x x x P P 0 0 - - - i i i i d d d d d Rd=memh(Rx++#s4:1) - U - ICLASS Amode Type t5 Parse d5 - N -1 0 0 1 1 1 0 1 0 1 0 t t t t t P P i 1 I I I I i I I d d d d d Rd=memh(Rt<<#u2+#U6) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 1 0 1 0 1 0 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memh(Rx++Mu) -1 0 0 1 1 1 1 1 0 1 0 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memh(Rx++Mu:brev) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - Parse Packet/Loop parse bits - d5 Field to encode register d - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 257 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load halfword conditionally - Load a signed halfword from memory. The 16-bit halfword at the effective address in - memory is placed in the least-significant 16 bits of the destination register. The destination - register is then sign-extended from 16 bits to 32. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pt[.new]) if ([!]Pt[.new][0]) { - Rd=memh(#u6) apply_extension(#u); - EA=#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) if ([!]Pt[.new][0]) { - Rd=memh(Rs+#u6:1) apply_extension(#u); - EA=Rs+#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) if([!]Pt[.new][0]){ - Rd=memh(Rx++#s4:1) EA=Rx; - Rx=Rx+#s; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - Rd=memh(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rd = *EA; - } else { - NOP; - }; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 - -0 0 1 1 0 0 0 0 0 1 0 s s s s s P P i t t t t t i v v d d d d d if (Pv) Rd=memh(Rs+Rt<<#u2) -0 0 1 1 0 0 0 1 0 1 0 s s s s s P P i t t t t t i v v d d d d d if (!Pv) Rd=memh(Rs+Rt<<#u2) -0 0 1 1 0 0 1 0 0 1 0 s s s s s P P i t t t t t i v v d d d d d if (Pv.new) Rd=memh(Rs+Rt<<#u2) -0 0 1 1 0 0 1 1 0 1 0 s s s s s P P i t t t t t i v v d d d d d if (!Pv.new) Rd=memh(Rs+Rt<<#u2) - - - - -80-N2040-36 B 258 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - Pr - Se - ed U - ICLASS ns Type s5 Parse t2 d5 - Ne N - e - w -0 1 0 0 0 0 0 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d if (Pt) Rd=memh(Rs+#u6:1) -0 1 0 0 0 0 1 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d if (Pt.new) Rd=memh(Rs+#u6:1) -0 1 0 0 0 1 0 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt) Rd=memh(Rs+#u6:1) -0 1 0 0 0 1 1 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt.new) Rd=memh(Rs+#u6:1) - U - ICLASS Amode Type x5 Parse t2 d5 - N -1 0 0 1 1 0 1 1 0 1 0 x x x x x P P 1 0 0 t t i i i i d d d d d if (Pt) Pd=memh(Rx++#s4:1) -1 0 0 1 1 0 1 1 0 1 0 x x x x x P P 1 0 1 t t i i i i d d d d d if (!Pt) Rd=memh(Rx++#s4:1) -1 0 0 1 1 0 1 1 0 1 0 x x x x x P P 1 1 0 t t i i i i d d d d d if (Pt.new) Rd=memh(Rx++#s4:1) -1 0 0 1 1 0 1 1 0 1 0 x x x x x P P 1 1 1 t t i i i i d d d d d if (!Pt.new) Rd=memh(Rx++#s4:1) - - ICLASS Amode Type U Parse t2 d5 - N -1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 0 t t i 1 - - d d d d d if (Pt) Rd=memh(#u6) -1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 1 t t i 1 - - d d d d d if (!Pt) Rd=memh(#u6) -1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 0 t t i 1 - - d d d d d if (Pt.new) Rd=memh(#u6) -1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 1 t t i 1 - - d d d d d if (!Pt.new) Rd=memh(#u6) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t2 Field to encode register t - t5 Field to encode register t - v2 Field to encode register v - x5 Field to encode register x - - - - -80-N2040-36 B 259 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load unsigned byte - Load an unsigned byte from memory. The byte at the effective address in memory is - placed in the least-significant 8 bits of the destination register. The destination register is - then zero-extended from 8 bits to 32. - - Syntax Behavior - Rd=memub(Re=#U6) apply_extension(#U); - EA=#U; - Rd = *EA; - Re=#U; - Rd=memub(Rs+#s11:0) apply_extension(#s); - EA=Rs+#s; - Rd = *EA; - Rd=memub(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rd = *EA; - Rd=memub(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - Rd = *EA; - Rd=memub(Rx++#s4:0) EA=Rx; - Rx=Rx+#s; - Rd = *EA; - Rd=memub(Rx++#s4:0:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - Rd = *EA; - Rd=memub(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<0,MuV); - Rd = *EA; - Rd=memub(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - Rd = *EA; - Rd=memub(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - Rd = *EA; - Rd=memub(gp+#u16:0) apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - Rd = *EA; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 -0 0 1 1 1 0 1 0 0 0 1 s s s s s P P i t t t t t i - - d d d d d Rd=memub(Rs+Rt<<#u2) - U - ICLASS Type Parse d5 - N -0 1 0 0 1 i i 1 0 0 1 i i i i i P P i i i i i i i i i d d d d d Rd=memub(gp+#u16:0) - U - ICLASS Amode Type s5 Parse d5 - N - - - - -80-N2040-36 B 260 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 1 0 i i 1 0 0 1 s s s s s P P i i i i i i i i i d d d d d Rd=memub(Rs+#s11:0) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 0 0 1 0 0 1 x x x x x P P u 0 - - 0 i i i i d d d d d Rd=memub(Rx++#s4:0:circ(Mu)) -1 0 0 1 1 0 0 1 0 0 1 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rd=memub(Rx++I:circ(Mu)) - U - ICLASS Amode Type e5 Parse d5 - N -1 0 0 1 1 0 1 1 0 0 1 e e e e e P P 0 1 I I I I - I I d d d d d Rd=memub(Re=#U6) - U - ICLASS Amode Type x5 Parse d5 - N -1 0 0 1 1 0 1 1 0 0 1 x x x x x P P 0 0 - - - i i i i d d d d d Rd=memub(Rx++#s4:0) - U - ICLASS Amode Type t5 Parse d5 - N -1 0 0 1 1 1 0 1 0 0 1 t t t t t P P i 1 I I I I i I I d d d d d Rd=memub(Rt<<#u2+#U6) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 1 0 1 0 0 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memub(Rx++Mu) -1 0 0 1 1 1 1 1 0 0 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memub(Rx++Mu:brev) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - Parse Packet/Loop parse bits - d5 Field to encode register d - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 261 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load unsigned byte conditionally - Load an unsigned byte from memory. The byte at the effective address in memory is - placed in the least-significant 8 bits of the destination register. The destination register is - then zero-extended from 8 bits to 32. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pt[.new]) if ([!]Pt[.new][0]) { - Rd=memub(#u6) apply_extension(#u); - EA=#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) if ([!]Pt[.new][0]) { - Rd=memub(Rs+#u6:0) apply_extension(#u); - EA=Rs+#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) if([!]Pt[.new][0]){ - Rd=memub(Rx++#s4:0) EA=Rx; - Rx=Rx+#s; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - Rd=memub(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rd = *EA; - } else { - NOP; - }; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 - -0 0 1 1 0 0 0 0 0 0 1 s s s s s P P i t t t t t i v v d d d d d if (Pv) Rd=memub(Rs+Rt<<#u2) -0 0 1 1 0 0 0 1 0 0 1 s s s s s P P i t t t t t i v v d d d d d if (!Pv) Rd=memub(Rs+Rt<<#u2) -0 0 1 1 0 0 1 0 0 0 1 s s s s s P P i t t t t t i v v d d d d d if (Pv.new) Rd=memub(Rs+Rt<<#u2) -0 0 1 1 0 0 1 1 0 0 1 s s s s s P P i t t t t t i v v d d d d d if (!Pv.new) Rd=memub(Rs+Rt<<#u2) - - - -80-N2040-36 B 262 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - Pr - Se - ed U - ICLASS ns Type s5 Parse t2 d5 - Ne N - e - w -0 1 0 0 0 0 0 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d if (Pt) Rd=memub(Rs+#u6:0) -0 1 0 0 0 0 1 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d if (Pt.new) Rd=memub(Rs+#u6:0) -0 1 0 0 0 1 0 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt) Rd=memub(Rs+#u6:0) -0 1 0 0 0 1 1 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt.new) Rd=memub(Rs+#u6:0) - U - ICLASS Amode Type x5 Parse t2 d5 - N -1 0 0 1 1 0 1 1 0 0 1 x x x x x P P 1 0 0 t t i i i i d d d d d if (Pt) Rd=memub(Rx++#s4:0) -1 0 0 1 1 0 1 1 0 0 1 x x x x x P P 1 0 1 t t i i i i d d d d d if (!Pt) Rd=memub(Rx++#s4:0) -1 0 0 1 1 0 1 1 0 0 1 x x x x x P P 1 1 0 t t i i i i d d d d d if (Pt.new) Rd=memub(Rx++#s4:0) -1 0 0 1 1 0 1 1 0 0 1 x x x x x P P 1 1 1 t t i i i i d d d d d if (!Pt.new) Rd=memub(Rx++#s4:0) - - ICLASS Amode Type U Parse t2 d5 - N -1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 0 t t i 1 - - d d d d d if (Pt) Rd=memub(#u6) -1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 1 t t i 1 - - d d d d d if (!Pt) Rd=memub(#u6) -1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 0 t t i 1 - - d d d d d if (Pt.new) Rd=memub(#u6) -1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 1 t t i 1 - - d d d d d if (!Pt.new) Rd=memub(#u6) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t2 Field to encode register t - t5 Field to encode register t - v2 Field to encode register v - x5 Field to encode register x - - - - -80-N2040-36 B 263 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load unsigned halfword - Load an unsigned halfword from memory. The 16-bit halfword at the effective address in - memory is placed in the least-significant 16 bits of the destination register. The destination - register is zero-extended from 16 bits to 32. - - Syntax Behavior - Rd=memuh(Re=#U6) apply_extension(#U); - EA=#U; - Rd = *EA; - Re=#U; - Rd=memuh(Rs+#s11:1) apply_extension(#s); - EA=Rs+#s; - Rd = *EA; - Rd=memuh(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rd = *EA; - Rd=memuh(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - Rd = *EA; - Rd=memuh(Rx++#s4:1) EA=Rx; - Rx=Rx+#s; - Rd = *EA; - Rd=memuh(Rx++#s4:1:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - Rd = *EA; - Rd=memuh(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<1,MuV); - Rd = *EA; - Rd=memuh(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - Rd = *EA; - Rd=memuh(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - Rd = *EA; - Rd=memuh(gp+#u16:1) apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - Rd = *EA; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 -0 0 1 1 1 0 1 0 0 1 1 s s s s s P P i t t t t t i - - d d d d d Rd=memuh(Rs+Rt<<#u2) - U - ICLASS Type Parse d5 - N -0 1 0 0 1 i i 1 0 1 1 i i i i i P P i i i i i i i i i d d d d d Rd=memuh(gp+#u16:1) - U - ICLASS Amode Type s5 Parse d5 - N - - - - -80-N2040-36 B 264 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 1 0 i i 1 0 1 1 s s s s s P P i i i i i i i i i d d d d d Rd=memuh(Rs+#s11:1) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 0 0 1 0 1 1 x x x x x P P u 0 - - 0 i i i i d d d d d Rd=memuh(Rx++#s4:1:circ(Mu)) -1 0 0 1 1 0 0 1 0 1 1 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rd=memuh(Rx++I:circ(Mu)) - U - ICLASS Amode Type e5 Parse d5 - N -1 0 0 1 1 0 1 1 0 1 1 e e e e e P P 0 1 I I I I - I I d d d d d Rd=memuh(Re=#U6) - U - ICLASS Amode Type x5 Parse d5 - N -1 0 0 1 1 0 1 1 0 1 1 x x x x x P P 0 0 - - - i i i i d d d d d Rd=memuh(Rx++#s4:1) - U - ICLASS Amode Type t5 Parse d5 - N -1 0 0 1 1 1 0 1 0 1 1 t t t t t P P i 1 I I I I i I I d d d d d Rd=memuh(Rt<<#u2+#U6) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 1 0 1 0 1 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memuh(Rx++Mu) -1 0 0 1 1 1 1 1 0 1 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memuh(Rx++Mu:brev) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - Parse Packet/Loop parse bits - d5 Field to encode register d - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 265 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load unsigned halfword conditionally - Load an unsigned halfword from memory. The 16-bit halfword at the effective address in - memory is placed in the least-significant 16 bits of the destination register. The destination - register is zero-extended from 16 bits to 32. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pt[.new]) if ([!]Pt[.new][0]) { - Rd=memuh(#u6) apply_extension(#u); - EA=#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) if ([!]Pt[.new][0]) { - Rd=memuh(Rs+#u6:1) apply_extension(#u); - EA=Rs+#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) if([!]Pt[.new][0]){ - Rd=memuh(Rx++#s4:1) EA=Rx; - Rx=Rx+#s; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - Rd=memuh(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rd = *EA; - } else { - NOP; - }; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 - -0 0 1 1 0 0 0 0 0 1 1 s s s s s P P i t t t t t i v v d d d d d if (Pv) Rd=memuh(Rs+Rt<<#u2) -0 0 1 1 0 0 0 1 0 1 1 s s s s s P P i t t t t t i v v d d d d d if (!Pv) Rd=memuh(Rs+Rt<<#u2) -0 0 1 1 0 0 1 0 0 1 1 s s s s s P P i t t t t t i v v d d d d d if (Pv.new) Rd=memuh(Rs+Rt<<#u2) -0 0 1 1 0 0 1 1 0 1 1 s s s s s P P i t t t t t i v v d d d d d if (!Pv.new) Rd=memuh(Rs+Rt<<#u2) - - - - -80-N2040-36 B 266 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - Pr - Se - ed U - ICLASS ns Type s5 Parse t2 d5 - Ne N - e - w -0 1 0 0 0 0 0 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d if (Pt) Rd=memuh(Rs+#u6:1) -0 1 0 0 0 0 1 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d if (Pt.new) Rd=memuh(Rs+#u6:1) -0 1 0 0 0 1 0 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt) Rd=memuh(Rs+#u6:1) -0 1 0 0 0 1 1 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt.new) Rd=memuh(Rs+#u6:1) - U - ICLASS Amode Type x5 Parse t2 d5 - N -1 0 0 1 1 0 1 1 0 1 1 x x x x x P P 1 0 0 t t i i i i d d d d d if (Pt) Rd=memuh(Rx++#s4:1) -1 0 0 1 1 0 1 1 0 1 1 x x x x x P P 1 0 1 t t i i i i d d d d d if (!Pt) Rd=memuh(Rx++#s4:1) -1 0 0 1 1 0 1 1 0 1 1 x x x x x P P 1 1 0 t t i i i i d d d d d if (Pt.new) Rd=memuh(Rx++#s4:1) -1 0 0 1 1 0 1 1 0 1 1 x x x x x P P 1 1 1 t t i i i i d d d d d if (!Pt.new) Rd=memuh(Rx++#s4:1) - - ICLASS Amode Type U Parse t2 d5 - N -1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 0 t t i 1 - - d d d d d if (Pt) Rd=memuh(#u6) -1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 1 t t i 1 - - d d d d d if (!Pt) Rd=memuh(#u6) -1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 0 t t i 1 - - d d d d d if (Pt.new) Rd=memuh(#u6) -1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 1 t t i 1 - - d d d d d if (!Pt.new) Rd=memuh(#u6) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t2 Field to encode register t - t5 Field to encode register t - v2 Field to encode register v - x5 Field to encode register x - - - - -80-N2040-36 B 267 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load word - Load a 32-bit word from memory and place in a destination register. - - Syntax Behavior - Rd=memw(Re=#U6) apply_extension(#U); - EA=#U; - Rd = *EA; - Re=#U; - Rd=memw(Rs+#s11:2) apply_extension(#s); - EA=Rs+#s; - Rd = *EA; - Rd=memw(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rd = *EA; - Rd=memw(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - Rd = *EA; - Rd=memw(Rx++#s4:2) EA=Rx; - Rx=Rx+#s; - Rd = *EA; - Rd=memw(Rx++#s4:2:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - Rd = *EA; - Rd=memw(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<2,MuV); - Rd = *EA; - Rd=memw(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - Rd = *EA; - Rd=memw(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - Rd = *EA; - Rd=memw(gp+#u16:2) apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - Rd = *EA; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 -0 0 1 1 1 0 1 0 1 0 0 s s s s s P P i t t t t t i - - d d d d d Rd=memw(Rs+Rt<<#u2) - U - ICLASS Type Parse d5 - N -0 1 0 0 1 i i 1 1 0 0 i i i i i P P i i i i i i i i i d d d d d Rd=memw(gp+#u16:2) - U - ICLASS Amode Type N s5 Parse d5 - -1 0 0 1 0 i i 1 1 0 0 s s s s s P P i i i i i i i i i d d d d d Rd=memw(Rs+#s11:2) - U - ICLASS Amode Type x5 Parse u1 d5 - N - - - - -80-N2040-36 B 268 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 1 1 0 0 1 1 0 0 x x x x x P P u 0 - - 0 i i i i d d d d d Rd=memw(Rx++#s4:2:circ(Mu)) -1 0 0 1 1 0 0 1 1 0 0 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rd=memw(Rx++I:circ(Mu)) - U - ICLASS Amode Type e5 Parse d5 - N -1 0 0 1 1 0 1 1 1 0 0 e e e e e P P 0 1 I I I I - I I d d d d d Rd=memw(Re=#U6) - - ICLASS Amode Type U x5 Parse d5 - N -1 0 0 1 1 0 1 1 1 0 0 x x x x x P P 0 0 - - - i i i i d d d d d Rd=memw(Rx++#s4:2) - U - ICLASS Amode Type N t5 Parse d5 - -1 0 0 1 1 1 0 1 1 0 0 t t t t t P P i 1 I I I I i I I d d d d d Rd=memw(Rt<<#u2+#U6) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 1 0 1 1 0 0 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memw(Rx++Mu) -1 0 0 1 1 1 1 1 1 0 0 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memw(Rx++Mu:brev) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - Parse Packet/Loop parse bits - d5 Field to encode register d - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 269 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load word conditionally - Load a 32-bit word from memory and place in a destination register. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pt[.new]) if ([!]Pt[.new][0]) { - Rd=memw(#u6) apply_extension(#u); - EA=#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) if ([!]Pt[.new][0]) { - Rd=memw(Rs+#u6:2) apply_extension(#u); - EA=Rs+#u; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pt[.new]) if([!]Pt[.new][0]){ - Rd=memw(Rx++#s4:2) EA=Rx; - Rx=Rx+#s; - Rd = *EA; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - Rd=memw(Rs+Rt<<#u2) EA=Rs+(Rt<<#u); - Rd = *EA; - } else { - NOP; - }; - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 d5 -0 0 1 1 0 0 0 0 1 0 0 s s s s s P P i t t t t t i v v d d d d d if (Pv) Rd=memw(Rs+Rt<<#u2) -0 0 1 1 0 0 0 1 1 0 0 s s s s s P P i t t t t t i v v d d d d d if (!Pv) Rd=memw(Rs+Rt<<#u2) -0 0 1 1 0 0 1 0 1 0 0 s s s s s P P i t t t t t i v v d d d d d if (Pv.new) Rd=memw(Rs+Rt<<#u2) -0 0 1 1 0 0 1 1 1 0 0 s s s s s P P i t t t t t i v v d d d d d if (!Pv.new) Rd=memw(Rs+Rt<<#u2) - Pr - Se ed - U - ICLASS ns Ne Type - N s5 Parse t2 d5 - e w - -0 1 0 0 0 0 0 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d if (Pt) Rd=memw(Rs+#u6:2) - - - - -80-N2040-36 B 270 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 1 0 0 0 0 1 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d if (Pt.new) Rd=memw(Rs+#u6:2) -0 1 0 0 0 1 0 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt) Rd=memw(Rs+#u6:2) -0 1 0 0 0 1 1 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d if (!Pt.new) Rd=memw(Rs+#u6:2) - U - ICLASS Amode Type N x5 Parse t2 d5 - -1 0 0 1 1 0 1 1 1 0 0 x x x x x P P 1 0 0 t t i i i i d d d d d if (Pt) Rd=memw(Rx++#s4:2) -1 0 0 1 1 0 1 1 1 0 0 x x x x x P P 1 0 1 t t i i i i d d d d d if (!Pt) Rd=memw(Rx++#s4:2) -1 0 0 1 1 0 1 1 1 0 0 x x x x x P P 1 1 0 t t i i i i d d d d d if (Pt.new) Rd=memw(Rx++#s4:2) -1 0 0 1 1 0 1 1 1 0 0 x x x x x P P 1 1 1 t t i i i i d d d d d if (!Pt.new) Rd=memw(Rx++#s4:2) - U - ICLASS Amode Type Parse t2 d5 - N -1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 0 t t i 1 - - d d d d d if (Pt) Rd=memw(#u6) -1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 1 t t i 1 - - d d d d d if (!Pt) Rd=memw(#u6) -1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 0 t t i 1 - - d d d d d if (Pt.new) Rd=memw(#u6) -1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 1 t t i 1 - - d d d d d if (!Pt.new) Rd=memw(#u6) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Type Type - UN Unsigned - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t2 Field to encode register t - t5 Field to encode register t - v2 Field to encode register v - x5 Field to encode register x - - - - -80-N2040-36 B 271 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Deallocate stack frame - Deallocate a stack frame from the call stack. The instruction first loads the saved FP and - saved LR values from the address at FP. It then points SP back to the previous frame. - - The stack layout is seen in the following figure. - - - Stack in Memory - - Saved LR - Saved FP - - - - - Higher Address - Procedure Local - Data on Stack - - Stack frame - - - - Saved LR - Saved FP FP register - - - - Procedure Local - Data on Stack - - SP register - Lower Address - - - - - Unallocated Stack - - - - - Syntax Behavior - deallocframe EA=FP; - tmp = *EA; - tmp = frame_unscramble(tmp); - LR=tmp.w[1]; - FP=tmp.w[0]; - SP=EA+8; - - - - -80-N2040-36 B 272 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type Parse - N -1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 P P 0 - - - - - - - - 1 1 1 1 0 deallocframe - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 273 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Deallocate frame and return - Return from a function with a stack frame. This instruction is equivalent to deallocframe - followed by jumpr R31. - - Syntax Behavior - dealloc_return EA=FP; - tmp = *EA; - tmp = frame_unscramble(tmp); - LR=tmp.w[1]; - FP=tmp.w[0]; - SP=EA+8; - PC=tmp.w[1]; - if ([!]Ps) dealloc_return ; - ; - if ([!]Ps[0]) { - EA=FP; - tmp = *EA; - tmp = frame_unscramble(tmp); - LR=tmp.w[1]; - FP=tmp.w[0]; - SP=EA+8; - PC=tmp.w[1]; - } else { - NOP; - }; - if ([!]Ps.new) ; - dealloc_return:nt if ([!]Ps.new[0]) { - EA=FP; - tmp = *EA; - tmp = frame_unscramble(tmp); - LR=tmp.w[1]; - FP=tmp.w[0]; - SP=EA+8; - PC=tmp.w[1]; - } else { - NOP; - }; - if ([!]Ps.new) ; - dealloc_return:t if ([!]Ps.new[0]) { - EA=FP; - tmp = *EA; - tmp = frame_unscramble(tmp); - LR=tmp.w[1]; - FP=tmp.w[0]; - SP=EA+8; - PC=tmp.w[1]; - } else { - NOP; - }; - - - - -80-N2040-36 B 274 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: LD (slots 0) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type Parse - N -1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 0 0 - - - - - 1 1 1 1 0 dealloc_return - U - ICLASS Amode Type Parse s2 - N -1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 1 0 s s - - - 1 1 1 1 0 if (Ps.new) dealloc_return:nt -1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 0 0 s s - - - 1 1 1 1 0 if (Ps) dealloc_return -1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 1 0 s s - - - 1 1 1 1 0 if (Ps.new) dealloc_return:t -1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 0 1 0 s s - - - 1 1 1 1 0 if (!Ps.new) dealloc_return:nt -1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 0 0 s s - - - 1 1 1 1 0 if (!Ps) dealloc_return -1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 1 0 s s - - - 1 1 1 1 0 if (!Ps.new) dealloc_return:t - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Parse Packet/Loop parse bits - s2 Field to encode register s - - - - -80-N2040-36 B 275 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load and unpack bytes to halfwords - Load contiguous bytes from memory and vector unpack them into halfwords. - Rdd=memubh(amode) - - mem - - - zero zero zero zero Rdd - - - - Rd=memubh(amode) - - mem - - - zero zero Rdd - - - - -80-N2040-36 B 276 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rd=membh(Re=#U6) apply_extension(#U); - EA=#U; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.b[i]; - }; - }; - ; - Re=#U; - Rd=membh(Rs) Assembler mapped to: "Rd=membh""(Rs+#0)" - Rd=membh(Rs+#s11:1) apply_extension(#s); - EA=Rs+#s; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.b[i]; - }; - }; - ; - Rd=membh(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.b[i]; - }; - }; - ; - Rd=membh(Rx++#s4:1) EA=Rx; - Rx=Rx+#s; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.b[i]; - }; - }; - ; - Rd=membh(Rx++#s4:1:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.b[i]; - }; - }; - ; - Rd=membh(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<1,MuV); - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.b[i]; - }; - }; - ; - - - - -80-N2040-36 B 277 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rd=membh(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.b[i]; - }; - }; - ; - Rd=membh(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.b[i]; - }; - }; - ; - Rd=memubh(Re=#U6) apply_extension(#U); - EA=#U; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.ub[i]; - }; - }; - ; - Re=#U; - Rd=memubh(Rs+#s11:1) apply_extension(#s); - EA=Rs+#s; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rd=memubh(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rd=memubh(Rx++#s4:1) EA=Rx; - Rx=Rx+#s; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.ub[i]; - }; - }; - ; - - - - -80-N2040-36 B 278 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rd=memubh(Rx++#s4:1:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rd=memubh(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<1,MuV); - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rd=memubh(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rd=memubh(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - { - tmpV = *EA; - for (i=0;i<2;i++) { - Rd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rdd=membh(Re=#U6) apply_extension(#U); - EA=#U; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.b[i]; - }; - }; - ; - Re=#U; - Rdd=membh(Rs) Assembler mapped to: "Rdd=membh""(Rs+#0)" - Rdd=membh(Rs+#s11:2) apply_extension(#s); - EA=Rs+#s; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.b[i]; - }; - }; - ; - - - - -80-N2040-36 B 279 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rdd=membh(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.b[i]; - }; - }; - ; - Rdd=membh(Rx++#s4:2) EA=Rx; - Rx=Rx+#s; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.b[i]; - }; - }; - ; - Rdd=membh(Rx++#s4:2:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.b[i]; - }; - }; - ; - Rdd=membh(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<2,MuV); - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.b[i]; - }; - }; - ; - Rdd=membh(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.b[i]; - }; - }; - ; - Rdd=membh(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.b[i]; - }; - }; - ; - - - - -80-N2040-36 B 280 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rdd=memubh(Re=#U6) apply_extension(#U); - EA=#U; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.ub[i]; - }; - }; - ; - Re=#U; - Rdd=memubh(Rs+#s11:2) apply_extension(#s); - EA=Rs+#s; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rdd=memubh(Rt<<#u2+#U6) apply_extension(#U); - EA=#U+(Rt<<#u); - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.ub[i]; - }; - }; - ; - - - - -80-N2040-36 B 281 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rdd=memubh(Rx++#s4:2) EA=Rx; - Rx=Rx+#s; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rdd=memubh(Rx++#s4:2:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rdd=memubh(Rx++I:circ(Mu)) EA=Rx; - Rx=Rx=circ_add(Rx,I<<2,MuV); - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rdd=memubh(Rx++Mu) EA=Rx; - Rx=Rx+MuV; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.ub[i]; - }; - }; - ; - Rdd=memubh(Rx++Mu:brev) EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - { - tmpV = *EA; - for (i=0;i<4;i++) { - Rdd.h[i]=tmpV.ub[i]; - }; - }; - ; - - - - -80-N2040-36 B 282 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: LD (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse d5 - N -1 0 0 1 0 i i 0 0 0 1 s s s s s P P i i i i i i i i i d d d d d Rd=membh(Rs+#s11:1) -1 0 0 1 0 i i 0 0 1 1 s s s s s P P i i i i i i i i i d d d d d Rd=memubh(Rs+#s11:1) -1 0 0 1 0 i i 0 1 0 1 s s s s s P P i i i i i i i i i d d d d d Rdd=memubh(Rs+#s11:2) -1 0 0 1 0 i i 0 1 1 1 s s s s s P P i i i i i i i i i d d d d d Rdd=membh(Rs+#s11:2) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 0 0 0 0 0 1 x x x x x P P u 0 - - 0 i i i i d d d d d Rd=membh(Rx++#s4:1:circ(Mu)) -1 0 0 1 1 0 0 0 0 0 1 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rd=membh(Rx++I:circ(Mu)) -1 0 0 1 1 0 0 0 0 1 1 x x x x x P P u 0 - - 0 i i i i d d d d d Rd=memubh(Rx++#s4:1:circ(Mu)) -1 0 0 1 1 0 0 0 0 1 1 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rd=memubh(Rx++I:circ(Mu)) -1 0 0 1 1 0 0 0 1 0 1 x x x x x P P u 0 - - 0 i i i i d d d d d Rdd=memubh(Rx++#s4:2:circ(Mu)) -1 0 0 1 1 0 0 0 1 0 1 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rdd=memubh(Rx++I:circ(Mu)) -1 0 0 1 1 0 0 0 1 1 1 x x x x x P P u 0 - - 0 i i i i d d d d d Rdd=membh(Rx++#s4:2:circ(Mu)) -1 0 0 1 1 0 0 0 1 1 1 x x x x x P P u 0 - - 1 - 0 - - d d d d d Rdd=membh(Rx++I:circ(Mu)) - - ICLASS Amode Type U e5 Parse d5 - N -1 0 0 1 1 0 1 0 0 0 1 e e e e e P P 0 1 I I I I - I I d d d d d Rd=membh(Re=#U6) - U - ICLASS Amode Type N x5 Parse d5 - -1 0 0 1 1 0 1 0 0 0 1 x x x x x P P 0 0 - - - i i i i d d d d d Rd=membh(Rx++#s4:1) - - ICLASS Amode Type U e5 Parse d5 - N -1 0 0 1 1 0 1 0 0 1 1 e e e e e P P 0 1 I I I I - I I d d d d d Rd=memubh(Re=#U6) - - ICLASS Amode Type U - N x5 Parse d5 - -1 0 0 1 1 0 1 0 0 1 1 x x x x x P P 0 0 - - - i i i i d d d d d Rd=memubh(Rx++#s4:1) - U - ICLASS Amode Type e5 Parse d5 - N -1 0 0 1 1 0 1 0 1 0 1 e e e e e P P 0 1 I I I I - I I d d d d d Rdd=memubh(Re=#U6) - U - ICLASS Amode Type x5 Parse d5 - N -1 0 0 1 1 0 1 0 1 0 1 x x x x x P P 0 0 - - - i i i i d d d d d Rdd=memubh(Rx++#s4:2) - U - ICLASS Amode Type e5 Parse d5 - N -1 0 0 1 1 0 1 0 1 1 1 e e e e e P P 0 1 I I I I - I I d d d d d Rdd=membh(Re=#U6) - U - ICLASS Amode Type x5 Parse d5 - N -1 0 0 1 1 0 1 0 1 1 1 x x x x x P P 0 0 - - - i i i i d d d d d Rdd=membh(Rx++#s4:2) - U - ICLASS Amode Type N - t5 Parse d5 - -1 0 0 1 1 1 0 0 0 0 1 t t t t t P P i 1 I I I I i I I d d d d d Rd=membh(Rt<<#u2+#U6) - U - ICLASS Amode Type N - x5 Parse u1 d5 - - - - -80-N2040-36 B 283 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 1 1 1 0 0 0 0 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=membh(Rx++Mu) - U - ICLASS Amode Type t5 Parse d5 - N -1 0 0 1 1 1 0 0 0 1 1 t t t t t P P i 1 I I I I i I I d d d d d Rd=memubh(Rt<<#u2+#U6) - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 1 0 0 0 1 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memubh(Rx++Mu) - U - ICLASS Amode Type t5 Parse d5 - N -1 0 0 1 1 1 0 0 1 0 1 t t t t t P P i 1 I I I I i I I d d d d d Rdd=memubh(Rt<<#u2+#U6) - U - ICLASS Amode Type N x5 Parse u1 d5 - -1 0 0 1 1 1 0 0 1 0 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rdd=memubh(Rx++Mu) - U - ICLASS Amode Type t5 Parse d5 - N -1 0 0 1 1 1 0 0 1 1 1 t t t t t P P i 1 I I I I i I I d d d d d Rdd=membh(Rt<<#u2+#U6) - - U - ICLASS Amode Type x5 Parse u1 d5 - N -1 0 0 1 1 1 0 0 1 1 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rdd=membh(Rx++Mu) -1 0 0 1 1 1 1 0 0 0 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=membh(Rx++Mu:brev) -1 0 0 1 1 1 1 0 0 1 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rd=memubh(Rx++Mu:brev) -1 0 0 1 1 1 1 0 1 0 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rdd=memubh(Rx++Mu:brev) -1 0 0 1 1 1 1 0 1 1 1 x x x x x P P u 0 - - - - 0 - - d d d d d Rdd=membh(Rx++Mu:brev) - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Parse Packet/Loop parse bits - d5 Field to encode register d - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 284 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.6 MEMOP - The MEMOP instruction class includes simple operations on values in memory. - - MEMOP instructions are executable on slot 0. - - - - -80-N2040-36 B 285 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Operation on memory byte - Perform ALU or bit operation on the memory byte at the effective address. - - Syntax Behavior - memb(Rs+#u6:0)=clrbit(#U5) apply_extension(#u); - EA=Rs+#u; - tmp = *EA; - tmp &= (~(1<<#U)); - *EA = tmp; - memb(Rs+#u6:0)=setbit(#U5) apply_extension(#u); - EA=Rs+#u; - tmp = *EA; - tmp |= (1<<#U); - *EA = tmp; - memb(Rs+#u6:0)[+-]=#U5 apply_extension(#u); - EA=Rs[+-]#u; - tmp = *EA; - tmp [+-]= #U; - *EA = tmp; - memb(Rs+#u6:0)[+-|&]=Rt apply_extension(#u); - EA=Rs+#u; - tmp = *EA; - tmp [+-|&]= Rt; - *EA = tmp; - - - Class: MEMOP (slots 0) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 -0 0 1 1 1 1 1 0 - 0 0 s s s s s P P 0 i i i i i i 0 0 t t t t t memb(Rs+#u6:0)+=Rt -0 0 1 1 1 1 1 0 - 0 0 s s s s s P P 0 i i i i i i 0 1 t t t t t memb(Rs+#u6:0)-=Rt -0 0 1 1 1 1 1 0 - 0 0 s s s s s P P 0 i i i i i i 1 0 t t t t t memb(Rs+#u6:0)&=Rt -0 0 1 1 1 1 1 0 - 0 0 s s s s s P P 0 i i i i i i 1 1 t t t t t memb(Rs+#u6:0)|=Rt - ICLASS s5 Parse -0 0 1 1 1 1 1 1 - 0 0 s s s s s P P 0 i i i i i i 0 0 I I I I I memb(Rs+#u6:0)+=#U5 -0 0 1 1 1 1 1 1 - 0 0 s s s s s P P 0 i i i i i i 0 1 I I I I I memb(Rs+#u6:0)-=#U5 -0 0 1 1 1 1 1 1 - 0 0 s s s s s P P 0 i i i i i i 1 0 I I I I I memb(Rs+#u6:0)=clrbit(#U5) -0 0 1 1 1 1 1 1 - 0 0 s s s s s P P 0 i i i i i i 1 1 I I I I I memb(Rs+#u6:0)=setbit(#U5) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 286 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Operation on memory halfword - Perform ALU or bit operation on the memory halfword at the effective address. - - Syntax Behavior - memh(Rs+#u6:1)=clrbit(#U5) apply_extension(#u); - EA=Rs+#u; - tmp = *EA; - tmp &= (~(1<<#U)); - *EA = tmp; - memh(Rs+#u6:1)=setbit(#U5) apply_extension(#u); - EA=Rs+#u; - tmp = *EA; - tmp |= (1<<#U); - *EA = tmp; - memh(Rs+#u6:1)[+-]=#U5 apply_extension(#u); - EA=Rs[+-]#u; - tmp = *EA; - tmp [+-]= #U; - *EA = tmp; - memh(Rs+#u6:1)[+-|&]=Rt apply_extension(#u); - EA=Rs+#u; - tmp = *EA; - tmp [+-|&]= Rt; - *EA = tmp; - - - Class: MEMOP (slots 0) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 -0 0 1 1 1 1 1 0 - 0 1 s s s s s P P 0 i i i i i i 0 0 t t t t t memh(Rs+#u6:1)+=Rt -0 0 1 1 1 1 1 0 - 0 1 s s s s s P P 0 i i i i i i 0 1 t t t t t memh(Rs+#u6:1)-=Rt -0 0 1 1 1 1 1 0 - 0 1 s s s s s P P 0 i i i i i i 1 0 t t t t t memh(Rs+#u6:1)&=Rt -0 0 1 1 1 1 1 0 - 0 1 s s s s s P P 0 i i i i i i 1 1 t t t t t memh(Rs+#u6:1)|=Rt - ICLASS s5 Parse -0 0 1 1 1 1 1 1 - 0 1 s s s s s P P 0 i i i i i i 0 0 I I I I I memh(Rs+#u6:1)+=#U5 -0 0 1 1 1 1 1 1 - 0 1 s s s s s P P 0 i i i i i i 0 1 I I I I I memh(Rs+#u6:1)-=#U5 -0 0 1 1 1 1 1 1 - 0 1 s s s s s P P 0 i i i i i i 1 0 I I I I I memh(Rs+#u6:1)=clrbit(#U5) -0 0 1 1 1 1 1 1 - 0 1 s s s s s P P 0 i i i i i i 1 1 I I I I I memh(Rs+#u6:1)=setbit(#U5) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 287 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Operation on memory word - Perform ALU or bit operation on the memory word at the effective address. - - Syntax Behavior - memw(Rs+#u6:2)=clrbit(#U5) apply_extension(#u); - EA=Rs+#u; - tmp = *EA; - tmp &= (~(1<<#U)); - *EA = tmp; - memw(Rs+#u6:2)=setbit(#U5) apply_extension(#u); - EA=Rs+#u; - tmp = *EA; - tmp |= (1<<#U); - *EA = tmp; - memw(Rs+#u6:2)[+-]=#U5 apply_extension(#u); - EA=Rs[+-]#u; - tmp = *EA; - tmp [+-]= #U; - *EA = tmp; - memw(Rs+#u6:2)[+-|&]=Rt apply_extension(#u); - EA=Rs+#u; - tmp = *EA; - tmp [+-|&]= Rt; - *EA = tmp; - - - Class: MEMOP (slots 0) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 -0 0 1 1 1 1 1 0 - 1 0 s s s s s P P 0 i i i i i i 0 0 t t t t t memw(Rs+#u6:2)+=Rt -0 0 1 1 1 1 1 0 - 1 0 s s s s s P P 0 i i i i i i 0 1 t t t t t memw(Rs+#u6:2)-=Rt -0 0 1 1 1 1 1 0 - 1 0 s s s s s P P 0 i i i i i i 1 0 t t t t t memw(Rs+#u6:2)&=Rt -0 0 1 1 1 1 1 0 - 1 0 s s s s s P P 0 i i i i i i 1 1 t t t t t memw(Rs+#u6:2)|=Rt - ICLASS s5 Parse -0 0 1 1 1 1 1 1 - 1 0 s s s s s P P 0 i i i i i i 0 0 I I I I I memw(Rs+#u6:2)+=#U5 -0 0 1 1 1 1 1 1 - 1 0 s s s s s P P 0 i i i i i i 0 1 I I I I I memw(Rs+#u6:2)-=#U5 -0 0 1 1 1 1 1 1 - 1 0 s s s s s P P 0 i i i i i i 1 0 I I I I I memw(Rs+#u6:2)=clrbit(#U5) -0 0 1 1 1 1 1 1 - 1 0 s s s s s P P 0 i i i i i i 1 1 I I I I I memw(Rs+#u6:2)=setbit(#U5) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 288 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.7 NV - The NV instruction class includes instructions which take the register source operand from - another instruction in the same packet. - - NV instructions are executable on slot 0. - - - 11.7.1 NV/J - The NV/J instruction subclass includes jump instructions which take the register source - operand from another instruction in the same packet. - -Jump to address condition on new register value - Compare a register or constant against the value produced by a slot 1 instruction. If the - comparison is true, the program counter is changed to a target address, relative to the - current PC. - - This instruction is executable only on slot 0. - - Syntax Behavior - if ([!]cmp.eq(Ns.new,#-1)) ; - jump: #r9:2 if ((Ns.new[!]=(-1))) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - if ([!]cmp.eq(Ns.new,#U5)) ; - jump: #r9:2 if ((Ns.new[!]=(#U))) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - if ([!]cmp.eq(Ns.new,Rt)) ; - jump: #r9:2 if ((Ns.new[!]=Rt)) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - if ([!]cmp.gt(Ns.new,#-1)) ; - jump: #r9:2 if ([!](Ns.new>(-1))) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - if ([!]cmp.gt(Ns.new,#U5)) ; - jump: #r9:2 if ([!](Ns.new>(#U))) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - - - - -80-N2040-36 B 289 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - if ([!]cmp.gt(Ns.new,Rt)) ; - jump: #r9:2 if ([!](Ns.new>Rt)) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - if ([!]cmp.gt(Rt,Ns.new)) ; - jump: #r9:2 if ([!](Rt>Ns.new)) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - if ([!]cmp.gtu(Ns.new,#U5)) ; - jump: #r9:2 if ([!](Ns.new.uw[0]>(#U))) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - if ([!]cmp.gtu(Ns.new,Rt)) ; - jump: #r9:2 if ([!](Ns.new.uw[0]>Rt.uw[0])) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - if ([!]cmp.gtu(Rt,Ns.new)) ; - jump: #r9:2 if ([!](Rt.uw[0]>Ns.new.uw[0])) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - if ([!]tstbit(Ns.new,#0)) ; - jump: #r9:2 if ([!]((Ns.new) & 1)) { - apply_extension(#r); - #r=#r & ~0x3; - PC=PC+#r; - }; - - - Class: NV (slots 0) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s3 Parse t5 -0 0 1 0 0 0 0 0 0 0 i i - s s s P P 0 t t t t t i i i i i i i - if (cmp.eq(Ns.new,Rt)) jump:nt #r9:2 -0 0 1 0 0 0 0 0 0 0 i i - s s s P P 1 t t t t t i i i i i i i - if (cmp.eq(Ns.new,Rt)) jump:t #r9:2 -0 0 1 0 0 0 0 0 0 1 i i - s s s P P 0 t t t t t i i i i i i i - if (!cmp.eq(Ns.new,Rt)) jump:nt #r9:2 -0 0 1 0 0 0 0 0 0 1 i i - s s s P P 1 t t t t t i i i i i i i - if (!cmp.eq(Ns.new,Rt)) jump:t #r9:2 -0 0 1 0 0 0 0 0 1 0 i i - s s s P P 0 t t t t t i i i i i i i - if (cmp.gt(Ns.new,Rt)) jump:nt #r9:2 -0 0 1 0 0 0 0 0 1 0 i i - s s s P P 1 t t t t t i i i i i i i - if (cmp.gt(Ns.new,Rt)) jump:t #r9:2 - - - - -80-N2040-36 B 290 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 0 1 0 0 0 0 0 1 1 i i - s s s P P 0 t t t t t i i i i i i i - if (!cmp.gt(Ns.new,Rt)) jump:nt #r9:2 -0 0 1 0 0 0 0 0 1 1 i i - s s s P P 1 t t t t t i i i i i i i - if (!cmp.gt(Ns.new,Rt)) jump:t #r9:2 -0 0 1 0 0 0 0 1 0 0 i i - s s s P P 0 t t t t t i i i i i i i - if (cmp.gtu(Ns.new,Rt)) jump:nt #r9:2 -0 0 1 0 0 0 0 1 0 0 i i - s s s P P 1 t t t t t i i i i i i i - if (cmp.gtu(Ns.new,Rt)) jump:t #r9:2 -0 0 1 0 0 0 0 1 0 1 i i - s s s P P 0 t t t t t i i i i i i i - if (!cmp.gtu(Ns.new,Rt)) jump:nt #r9:2 -0 0 1 0 0 0 0 1 0 1 i i - s s s P P 1 t t t t t i i i i i i i - if (!cmp.gtu(Ns.new,Rt)) jump:t #r9:2 -0 0 1 0 0 0 0 1 1 0 i i - s s s P P 0 t t t t t i i i i i i i - if (cmp.gt(Rt,Ns.new)) jump:nt #r9:2 -0 0 1 0 0 0 0 1 1 0 i i - s s s P P 1 t t t t t i i i i i i i - if (cmp.gt(Rt,Ns.new)) jump:t #r9:2 -0 0 1 0 0 0 0 1 1 1 i i - s s s P P 0 t t t t t i i i i i i i - if (!cmp.gt(Rt,Ns.new)) jump:nt #r9:2 -0 0 1 0 0 0 0 1 1 1 i i - s s s P P 1 t t t t t i i i i i i i - if (!cmp.gt(Rt,Ns.new)) jump:t #r9:2 -0 0 1 0 0 0 1 0 0 0 i i - s s s P P 0 t t t t t i i i i i i i - if (cmp.gtu(Rt,Ns.new)) jump:nt #r9:2 -0 0 1 0 0 0 1 0 0 0 i i - s s s P P 1 t t t t t i i i i i i i - if (cmp.gtu(Rt,Ns.new)) jump:t #r9:2 -0 0 1 0 0 0 1 0 0 1 i i - s s s P P 0 t t t t t i i i i i i i - if (!cmp.gtu(Rt,Ns.new)) jump:nt #r9:2 -0 0 1 0 0 0 1 0 0 1 i i - s s s P P 1 t t t t t i i i i i i i - if (!cmp.gtu(Rt,Ns.new)) jump:t #r9:2 - ICLASS s3 Parse -0 0 1 0 0 1 0 0 0 0 i i - s s s P P 0 I I I I I i i i i i i i - if (cmp.eq(Ns.new,#U5)) jump:nt #r9:2 -0 0 1 0 0 1 0 0 0 0 i i - s s s P P 1 I I I I I i i i i i i i - if (cmp.eq(Ns.new,#U5)) jump:t #r9:2 -0 0 1 0 0 1 0 0 0 1 i i - s s s P P 0 I I I I I i i i i i i i - if (!cmp.eq(Ns.new,#U5)) jump:nt #r9:2 -0 0 1 0 0 1 0 0 0 1 i i - s s s P P 1 I I I I I i i i i i i i - if (!cmp.eq(Ns.new,#U5)) jump:t #r9:2 -0 0 1 0 0 1 0 0 1 0 i i - s s s P P 0 I I I I I i i i i i i i - if (cmp.gt(Ns.new,#U5)) jump:nt #r9:2 -0 0 1 0 0 1 0 0 1 0 i i - s s s P P 1 I I I I I i i i i i i i - if (cmp.gt(Ns.new,#U5)) jump:t #r9:2 -0 0 1 0 0 1 0 0 1 1 i i - s s s P P 0 I I I I I i i i i i i i - if (!cmp.gt(Ns.new,#U5)) jump:nt #r9:2 -0 0 1 0 0 1 0 0 1 1 i i - s s s P P 1 I I I I I i i i i i i i - if (!cmp.gt(Ns.new,#U5)) jump:t #r9:2 -0 0 1 0 0 1 0 1 0 0 i i - s s s P P 0 I I I I I i i i i i i i - if (cmp.gtu(Ns.new,#U5)) jump:nt #r9:2 -0 0 1 0 0 1 0 1 0 0 i i - s s s P P 1 I I I I I i i i i i i i - if (cmp.gtu(Ns.new,#U5)) jump:t #r9:2 -0 0 1 0 0 1 0 1 0 1 i i - s s s P P 0 I I I I I i i i i i i i - if (!cmp.gtu(Ns.new,#U5)) jump:nt #r9:2 -0 0 1 0 0 1 0 1 0 1 i i - s s s P P 1 I I I I I i i i i i i i - if (!cmp.gtu(Ns.new,#U5)) jump:t #r9:2 -0 0 1 0 0 1 0 1 1 0 i i - s s s P P 0 - - - - - i i i i i i i - if (tstbit(Ns.new,#0)) jump:nt #r9:2 -0 0 1 0 0 1 0 1 1 0 i i - s s s P P 1 - - - - - i i i i i i i - if (tstbit(Ns.new,#0)) jump:t #r9:2 -0 0 1 0 0 1 0 1 1 1 i i - s s s P P 0 - - - - - i i i i i i i - if (!tstbit(Ns.new,#0)) jump:nt #r9:2 -0 0 1 0 0 1 0 1 1 1 i i - s s s P P 1 - - - - - i i i i i i i - if (!tstbit(Ns.new,#0)) jump:t #r9:2 -0 0 1 0 0 1 1 0 0 0 i i - s s s P P 0 - - - - - i i i i i i i - if (cmp.eq(Ns.new,#-1)) jump:nt #r9:2 - - - - -80-N2040-36 B 291 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 0 1 0 0 1 1 0 0 0 i i - s s s P P 1 - - - - - i i i i i i i - if (cmp.eq(Ns.new,#-1)) jump:t #r9:2 -0 0 1 0 0 1 1 0 0 1 i i - s s s P P 0 - - - - - i i i i i i i - if (!cmp.eq(Ns.new,#-1)) jump:nt #r9:2 -0 0 1 0 0 1 1 0 0 1 i i - s s s P P 1 - - - - - i i i i i i i - if (!cmp.eq(Ns.new,#-1)) jump:t #r9:2 -0 0 1 0 0 1 1 0 1 0 i i - s s s P P 0 - - - - - i i i i i i i - if (cmp.gt(Ns.new,#-1)) jump:nt #r9:2 -0 0 1 0 0 1 1 0 1 0 i i - s s s P P 1 - - - - - i i i i i i i - if (cmp.gt(Ns.new,#-1)) jump:t #r9:2 -0 0 1 0 0 1 1 0 1 1 i i - s s s P P 0 - - - - - i i i i i i i - if (!cmp.gt(Ns.new,#-1)) jump:nt #r9:2 -0 0 1 0 0 1 1 0 1 1 i i - s s s P P 1 - - - - - i i i i i i i - if (!cmp.gt(Ns.new,#-1)) jump:t #r9:2 - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s3 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 292 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.7.2 NV/ST - The NV/ST instruction subclass includes store instructions which take the register source - operand from another instruction in the same packet. - -Store new-value byte - Store the least-significant byte in a source register in memory at the effective address. - - Syntax Behavior - memb(Re=#U6)=Nt.new apply_extension(#U); - EA=#U; - *EA = Nt.new&0xff; - Re=#U; - memb(Rs+#s11:0)=Nt.new apply_extension(#s); - EA=Rs+#s; - *EA = Nt.new&0xff; - memb(Rs+Ru<<#u2)=Nt.new EA=Rs+(Ru<<#u); - *EA = Nt.new&0xff; - memb(Ru<<#u2+#U6)=Nt.new apply_extension(#U); - EA=#U+(Ru<<#u); - *EA = Nt.new&0xff; - memb(Rx++#s4:0)=Nt.new EA=Rx; - Rx=Rx+#s; - *EA = Nt.new&0xff; - memb(Rx++#s4:0:circ(Mu))=Nt.new EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - *EA = Nt.new&0xff; - memb(Rx++I:circ(Mu))=Nt.new EA=Rx; - Rx=Rx=circ_add(Rx,I<<0,MuV); - *EA = Nt.new&0xff; - memb(Rx++Mu)=Nt.new EA=Rx; - Rx=Rx+MuV; - *EA = Nt.new&0xff; - memb(Rx++Mu:brev)=Nt.new EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - *EA = Nt.new&0xff; - memb(gp+#u16:0)=Nt.new apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - *EA = Nt.new&0xff; - - - Class: NV (slots 0) - - Notes - -  Forms of this instruction which use a new-value operand produced in the packet - must execute on slot 0. -  This instruction can execute only in slot 0, even though it is an ST instruction. - - - - -80-N2040-36 B 293 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t3 -0 0 1 1 1 0 1 1 1 0 1 s s s s s P P i u u u u u i - - 0 0 t t t memb(Rs+Ru<<#u2)=Nt.new - ICLASS Type Parse t3 -0 1 0 0 1 i i 0 1 0 1 i i i i i P P i 0 0 t t t i i i i i i i i memb(gp+#u16:0)=Nt.new - U - ICLASS Amode Type s5 Parse t3 - N -1 0 1 0 0 i i 1 1 0 1 s s s s s P P i 0 0 t t t i i i i i i i i memb(Rs+#s11:0)=Nt.new - - ICLASS Amode Type U x5 Parse u1 t3 - N -1 0 1 0 1 0 0 1 1 0 1 x x x x x P P u 0 0 t t t 0 - - - - - 1 - memb(Rx++I:circ(Mu))=Nt.new -1 0 1 0 1 0 0 1 1 0 1 x x x x x P P u 0 0 t t t 0 i i i i - 0 - memb(Rx++#s4:0:circ(Mu))=Nt.new - U - ICLASS Amode Type e5 Parse t3 - N -1 0 1 0 1 0 1 1 1 0 1 e e e e e P P 0 0 0 t t t 1 - I I I I I I memb(Re=#U6)=Nt.new - U - ICLASS Amode Type N x5 Parse t3 - -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 0 0 0 t t t 0 i i i i - 0 - memb(Rx++#s4:0)=Nt.new - U - ICLASS Amode Type u5 Parse t3 - N -1 0 1 0 1 1 0 1 1 0 1 u u u u u P P i 0 0 t t t 1 i I I I I I I memb(Ru<<#u2+#U6)=Nt.new - - ICLASS Amode Type U x5 Parse u1 t3 - N -1 0 1 0 1 1 0 1 1 0 1 x x x x x P P u 0 0 t t t 0 - - - - - - - memb(Rx++Mu)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 x x x x x P P u 0 0 t t t 0 - - - - - - - memb(Rx++Mu:brev)=Nt.new - - - - - Field name Description - ICLASS Instruction Class - Type Type - Parse Packet/Loop parse bits - e5 Field to encode register e - s5 Field to encode register s - t3 Field to encode register t - u1 Field to encode register u - u5 Field to encode register u - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 294 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store new-value byte conditionally - Store the least-significant byte in a source register in memory at the effective address. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memb(#u6)=Nt.new apply_extension(#u); - EA=#u; - *EA = Nt[.new]&0xff; - } else { - NOP; - }; - if ([!]Pv[.new]) apply_extension(#u); - memb(Rs+#u6:0)=Nt.new if ([!]Pv[.new][0]) { - EA=Rs+#u; - *EA = Nt[.new]&0xff; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memb(Rs+Ru<<#u2)=Nt.new EA=Rs+(Ru<<#u); - *EA = Nt[.new]&0xff; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memb(Rx++#s4:0)=Nt.new EA=Rx; - Rx=Rx+#s; - *EA = Nt[.new]&0xff; - } else { - NOP; - }; - - - Class: NV (slots 0) - - Notes - -  Forms of this instruction which use a new-value operand produced in the packet - must execute on slot 0. -  This instruction can execute only in slot 0, even though it is an ST instruction. - - - - -80-N2040-36 B 295 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t3 -0 0 1 1 0 1 0 0 1 0 1 s s s s s P P i u u u u u i v v 0 0 t t t if (Pv) memb(Rs+Ru<<#u2)=Nt.new -0 0 1 1 0 1 0 1 1 0 1 s s s s s P P i u u u u u i v v 0 0 t t t if (!Pv) memb(Rs+Ru<<#u2)=Nt.new -0 0 1 1 0 1 1 0 1 0 1 s s s s s P P i u u u u u i v v 0 0 t t t if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new -0 0 1 1 0 1 1 1 1 0 1 s s s s s P P i u u u u u i v v 0 0 t t t if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new - Pr - Se - ed - ICLASS ns Ne Type s5 Parse t3 - e w - -0 1 0 0 0 0 0 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v if (Pv) memb(Rs+#u6:0)=Nt.new -0 1 0 0 0 0 1 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v if (Pv.new) memb(Rs+#u6:0)=Nt.new -0 1 0 0 0 1 0 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v if (!Pv) memb(Rs+#u6:0)=Nt.new -0 1 0 0 0 1 1 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v if (!Pv.new) memb(Rs+#u6:0)=Nt.new - U - ICLASS Amode Type N x5 Parse t3 - -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 0 0 t t t 0 i i i i 0 v v if (Pv) memb(Rx++#s4:0)=Nt.new -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 0 0 t t t 0 i i i i 1 v v if (!Pv) memb(Rx++#s4:0)=Nt.new -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 0 0 t t t 1 i i i i 0 v v if (Pv.new) memb(Rx++#s4:0)=Nt.new -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 0 0 t t t 1 i i i i 1 v v if (!Pv.new) memb(Rx++#s4:0)=Nt.new - - U - ICLASS Amode Type N Parse t3 - -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 0 0 t t t 1 i i i i 0 v v if (Pv) memb(#u6)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 0 0 t t t 1 i i i i 1 v v if (!Pv) memb(#u6)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 0 0 t t t 1 i i i i 0 v v if (Pv.new) memb(#u6)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 0 0 t t t 1 i i i i 1 v v if (!Pv.new) memb(#u6)=Nt.new - - - - - Field name Description - ICLASS Instruction Class - Type Type - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - s5 Field to encode register s - t3 Field to encode register t - u5 Field to encode register u - v2 Field to encode register v - x5 Field to encode register x - - - - -80-N2040-36 B 296 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 297 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store new-value halfword - Store the upper or lower 16-bits of a source register in memory at the effective address. - - Syntax Behavior - memh(Re=#U6)=Nt.new apply_extension(#U); - EA=#U; - *EA = Nt.new.h[0]; - Re=#U; - memh(Rs+#s11:1)=Nt.new apply_extension(#s); - EA=Rs+#s; - *EA = Nt.new.h[0]; - memh(Rs+Ru<<#u2)=Nt.new EA=Rs+(Ru<<#u); - *EA = Nt.new.h[0]; - memh(Ru<<#u2+#U6)=Nt.new apply_extension(#U); - EA=#U+(Ru<<#u); - *EA = Nt.new.h[0]; - memh(Rx++#s4:1)=Nt.new EA=Rx; - Rx=Rx+#s; - *EA = Nt.new.h[0]; - memh(Rx++#s4:1:circ(Mu))=Nt.new EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - *EA = Nt.new.h[0]; - memh(Rx++I:circ(Mu))=Nt.new EA=Rx; - Rx=Rx=circ_add(Rx,I<<1,MuV); - *EA = Nt.new.h[0]; - memh(Rx++Mu)=Nt.new EA=Rx; - Rx=Rx+MuV; - *EA = Nt.new.h[0]; - memh(Rx++Mu:brev)=Nt.new EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - *EA = Nt.new.h[0]; - memh(gp+#u16:1)=Nt.new apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - *EA = Nt.new.h[0]; - - - Class: NV (slots 0) - - Notes - -  Forms of this instruction which use a new-value operand produced in the packet - must execute on slot 0. -  This instruction can execute only in slot 0, even though it is an ST instruction. - - - - -80-N2040-36 B 298 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t3 -0 0 1 1 1 0 1 1 1 0 1 s s s s s P P i u u u u u i - - 0 1 t t t memh(Rs+Ru<<#u2)=Nt.new - ICLASS Type Parse t3 -0 1 0 0 1 i i 0 1 0 1 i i i i i P P i 0 1 t t t i i i i i i i i memh(gp+#u16:1)=Nt.new - U - ICLASS Amode Type s5 Parse t3 - N -1 0 1 0 0 i i 1 1 0 1 s s s s s P P i 0 1 t t t i i i i i i i i memh(Rs+#s11:1)=Nt.new - - ICLASS Amode Type U x5 Parse u1 t3 - N -1 0 1 0 1 0 0 1 1 0 1 x x x x x P P u 0 1 t t t 0 - - - - - 1 - memh(Rx++I:circ(Mu))=Nt.new - -1 0 1 0 1 0 0 1 1 0 1 x x x x x P P u 0 1 t t t 0 i i i i - 0 - memh(Rx++#s4:1:circ(Mu))=Nt.new - U - ICLASS Amode Type e5 Parse t3 - N -1 0 1 0 1 0 1 1 1 0 1 e e e e e P P 0 0 1 t t t 1 - I I I I I I memh(Re=#U6)=Nt.new - U - ICLASS Amode Type N x5 Parse t3 - -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 0 0 1 t t t 0 i i i i - 0 - memh(Rx++#s4:1)=Nt.new - U - ICLASS Amode Type u5 Parse t3 - N -1 0 1 0 1 1 0 1 1 0 1 u u u u u P P i 0 1 t t t 1 i I I I I I I memh(Ru<<#u2+#U6)=Nt.new - - ICLASS Amode Type U x5 Parse u1 t3 - N -1 0 1 0 1 1 0 1 1 0 1 x x x x x P P u 0 1 t t t 0 - - - - - - - memh(Rx++Mu)=Nt.new - -1 0 1 0 1 1 1 1 1 0 1 x x x x x P P u 0 1 t t t 0 - - - - - - - memh(Rx++Mu:brev)=Nt.new - - - - - Field name Description - ICLASS Instruction Class - Type Type - Parse Packet/Loop parse bits - e5 Field to encode register e - s5 Field to encode register s - t3 Field to encode register t - u1 Field to encode register u - u5 Field to encode register u - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 299 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store new-value halfword conditionally - Store the upper or lower 16-bits of a source register in memory at the effective address. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memh(#u6)=Nt.new apply_extension(#u); - EA=#u; - *EA = Nt[.new].h[0]; - } else { - NOP; - }; - if ([!]Pv[.new]) apply_extension(#u); - memh(Rs+#u6:1)=Nt.new if ([!]Pv[.new][0]) { - EA=Rs+#u; - *EA = Nt[.new].h[0]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memh(Rs+Ru<<#u2)=Nt.new EA=Rs+(Ru<<#u); - *EA = Nt[.new].h[0]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memh(Rx++#s4:1)=Nt.new EA=Rx; - Rx=Rx+#s; - *EA = Nt[.new].h[0]; - } else { - NOP; - }; - - - Class: NV (slots 0) - - Notes - -  Forms of this instruction which use a new-value operand produced in the packet - must execute on slot 0. -  This instruction can execute only in slot 0, even though it is an ST instruction. - - - - -80-N2040-36 B 300 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t3 -0 0 1 1 0 1 0 0 1 0 1 s s s s s P P i u u u u u i v v 0 1 t t t if (Pv) memh(Rs+Ru<<#u2)=Nt.new -0 0 1 1 0 1 0 1 1 0 1 s s s s s P P i u u u u u i v v 0 1 t t t if (!Pv) memh(Rs+Ru<<#u2)=Nt.new -0 0 1 1 0 1 1 0 1 0 1 s s s s s P P i u u u u u i v v 0 1 t t t if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new -0 0 1 1 0 1 1 1 1 0 1 s s s s s P P i u u u u u i v v 0 1 t t t if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new - Pr - Se - ed - ICLASS ns Ne Type s5 Parse t3 - e w - -0 1 0 0 0 0 0 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v if (Pv) memh(Rs+#u6:1)=Nt.new -0 1 0 0 0 0 1 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v if (Pv.new) memh(Rs+#u6:1)=Nt.new -0 1 0 0 0 1 0 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v if (!Pv) memh(Rs+#u6:1)=Nt.new -0 1 0 0 0 1 1 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v if (!Pv.new) memh(Rs+#u6:1)=Nt.new - U - ICLASS Amode Type N x5 Parse t3 - -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 0 1 t t t 0 i i i i 0 v v if (Pv) memh(Rx++#s4:1)=Nt.new -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 0 1 t t t 0 i i i i 1 v v if (!Pv) memh(Rx++#s4:1)=Nt.new -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 0 1 t t t 1 i i i i 0 v v if (Pv.new) memh(Rx++#s4:1)=Nt.new -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 0 1 t t t 1 i i i i 1 v v if (!Pv.new) memh(Rx++#s4:1)=Nt.new - U - ICLASS Amode Type N Parse t3 - -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 0 1 t t t 1 i i i i 0 v v if (Pv) memh(#u6)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 0 1 t t t 1 i i i i 1 v v if (!Pv) memh(#u6)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 0 1 t t t 1 i i i i 0 v v if (Pv.new) memh(#u6)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 0 1 t t t 1 i i i i 1 v v if (!Pv.new) memh(#u6)=Nt.new - - - - - Field name Description - ICLASS Instruction Class - Type Type - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - s5 Field to encode register s - t3 Field to encode register t - u5 Field to encode register u - v2 Field to encode register v - x5 Field to encode register x - - - - -80-N2040-36 B 301 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 302 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store new-value word - Store a 32-bit register in memory at the effective address. - - Syntax Behavior - memw(Re=#U6)=Nt.new apply_extension(#U); - EA=#U; - *EA = Nt.new; - Re=#U; - memw(Rs+#s11:2)=Nt.new apply_extension(#s); - EA=Rs+#s; - *EA = Nt.new; - memw(Rs+Ru<<#u2)=Nt.new EA=Rs+(Ru<<#u); - *EA = Nt.new; - memw(Ru<<#u2+#U6)=Nt.new apply_extension(#U); - EA=#U+(Ru<<#u); - *EA = Nt.new; - memw(Rx++#s4:2)=Nt.new EA=Rx; - Rx=Rx+#s; - *EA = Nt.new; - memw(Rx++#s4:2:circ(Mu))=Nt.new EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - *EA = Nt.new; - memw(Rx++I:circ(Mu))=Nt.new EA=Rx; - Rx=Rx=circ_add(Rx,I<<2,MuV); - *EA = Nt.new; - memw(Rx++Mu)=Nt.new EA=Rx; - Rx=Rx+MuV; - *EA = Nt.new; - memw(Rx++Mu:brev)=Nt.new EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - *EA = Nt.new; - memw(gp+#u16:2)=Nt.new apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - *EA = Nt.new; - - - Class: NV (slots 0) - - Notes - -  Forms of this instruction which use a new-value operand produced in the packet - must execute on slot 0. -  This instruction can execute only in slot 0, even though it is an ST instruction. - - - - -80-N2040-36 B 303 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t3 -0 0 1 1 1 0 1 1 1 0 1 s s s s s P P i u u u u u i - - 1 0 t t t memw(Rs+Ru<<#u2)=Nt.new - ICLASS Type Parse t3 -0 1 0 0 1 i i 0 1 0 1 i i i i i P P i 1 0 t t t i i i i i i i i memw(gp+#u16:2)=Nt.new - U - ICLASS Amode Type s5 Parse t3 - N -1 0 1 0 0 i i 1 1 0 1 s s s s s P P i 1 0 t t t i i i i i i i i memw(Rs+#s11:2)=Nt.new - - ICLASS Amode Type U x5 Parse u1 t3 - N -1 0 1 0 1 0 0 1 1 0 1 x x x x x P P u 1 0 t t t 0 - - - - - 1 - memw(Rx++I:circ(Mu))=Nt.new - -1 0 1 0 1 0 0 1 1 0 1 x x x x x P P u 1 0 t t t 0 i i i i - 0 - memw(Rx++#s4:2:circ(Mu))=Nt.new - U - ICLASS Amode Type e5 Parse t3 - N -1 0 1 0 1 0 1 1 1 0 1 e e e e e P P 0 1 0 t t t 1 - I I I I I I memw(Re=#U6)=Nt.new - U - ICLASS Amode Type N x5 Parse t3 - -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 0 1 0 t t t 0 i i i i - 0 - memw(Rx++#s4:2)=Nt.new - U - ICLASS Amode Type u5 Parse t3 - N -1 0 1 0 1 1 0 1 1 0 1 u u u u u P P i 1 0 t t t 1 i I I I I I I memw(Ru<<#u2+#U6)=Nt.new - - ICLASS Amode Type U x5 Parse u1 t3 - N -1 0 1 0 1 1 0 1 1 0 1 x x x x x P P u 1 0 t t t 0 - - - - - - - memw(Rx++Mu)=Nt.new - -1 0 1 0 1 1 1 1 1 0 1 x x x x x P P u 1 0 t t t 0 - - - - - - - memw(Rx++Mu:brev)=Nt.new - - - - - Field name Description - ICLASS Instruction Class - Type Type - Parse Packet/Loop parse bits - e5 Field to encode register e - s5 Field to encode register s - t3 Field to encode register t - u1 Field to encode register u - u5 Field to encode register u - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 304 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store new-value word conditionally - Store a 32-bit register in memory at the effective address. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memw(#u6)=Nt.new apply_extension(#u); - EA=#u; - *EA = Nt[.new]; - } else { - NOP; - }; - if ([!]Pv[.new]) apply_extension(#u); - memw(Rs+#u6:2)=Nt.new if ([!]Pv[.new][0]) { - EA=Rs+#u; - *EA = Nt[.new]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memw(Rs+Ru<<#u2)=Nt.new EA=Rs+(Ru<<#u); - *EA = Nt[.new]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memw(Rx++#s4:2)=Nt.new EA=Rx; - Rx=Rx+#s; - *EA = Nt[.new]; - } else { - NOP; - }; - - - Class: NV (slots 0) - - Notes - -  Forms of this instruction which use a new-value operand produced in the packet - must execute on slot 0. -  This instruction can execute only in slot 0, even though it is an ST instruction. - - - - -80-N2040-36 B 305 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t3 -0 0 1 1 0 1 0 0 1 0 1 s s s s s P P i u u u u u i v v 1 0 t t t if (Pv) memw(Rs+Ru<<#u2)=Nt.new -0 0 1 1 0 1 0 1 1 0 1 s s s s s P P i u u u u u i v v 1 0 t t t if (!Pv) memw(Rs+Ru<<#u2)=Nt.new -0 0 1 1 0 1 1 0 1 0 1 s s s s s P P i u u u u u i v v 1 0 t t t if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new -0 0 1 1 0 1 1 1 1 0 1 s s s s s P P i u u u u u i v v 1 0 t t t if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new - Pr - Se - ed - ICLASS ns Ne Type s5 Parse t3 - e w - -0 1 0 0 0 0 0 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v if (Pv) memw(Rs+#u6:2)=Nt.new -0 1 0 0 0 0 1 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v if (Pv.new) memw(Rs+#u6:2)=Nt.new -0 1 0 0 0 1 0 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v if (!Pv) memw(Rs+#u6:2)=Nt.new -0 1 0 0 0 1 1 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v if (!Pv.new) memw(Rs+#u6:2)=Nt.new - U - ICLASS Amode Type N x5 Parse t3 - -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 1 0 t t t 0 i i i i 0 v v if (Pv) memw(Rx++#s4:2)=Nt.new -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 1 0 t t t 0 i i i i 1 v v if (!Pv) memw(Rx++#s4:2)=Nt.new -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 1 0 t t t 1 i i i i 0 v v if (Pv.new) memw(Rx++#s4:2)=Nt.new -1 0 1 0 1 0 1 1 1 0 1 x x x x x P P 1 1 0 t t t 1 i i i i 1 v v if (!Pv.new) memw(Rx++#s4:2)=Nt.new - - U - ICLASS Amode Type N Parse t3 - -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 1 0 t t t 1 i i i i 0 v v if (Pv) memw(#u6)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 1 0 t t t 1 i i i i 1 v v if (!Pv) memw(#u6)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 1 0 t t t 1 i i i i 0 v v if (Pv.new) memw(#u6)=Nt.new -1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 1 0 t t t 1 i i i i 1 v v if (!Pv.new) memw(#u6)=Nt.new - - - - - Field name Description - ICLASS Instruction Class - Type Type - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - s5 Field to encode register s - t3 Field to encode register t - u5 Field to encode register u - v2 Field to encode register v - x5 Field to encode register x - - - - -80-N2040-36 B 306 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 307 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.8 ST - The ST instruction class includes store instructions, used to store values in memory. - - ST instructions are executable on slot 0 and slot 1. - -Store doubleword - Store a 64-bit register pair in memory at the effective address. - - Syntax Behavior - memd(Re=#U6)=Rtt apply_extension(#U); - EA=#U; - *EA = Rtt; - Re=#U; - memd(Rs+#s11:3)=Rtt apply_extension(#s); - EA=Rs+#s; - *EA = Rtt; - memd(Rs+Ru<<#u2)=Rtt EA=Rs+(Ru<<#u); - *EA = Rtt; - memd(Ru<<#u2+#U6)=Rtt apply_extension(#U); - EA=#U+(Ru<<#u); - *EA = Rtt; - memd(Rx++#s4:3)=Rtt EA=Rx; - Rx=Rx+#s; - *EA = Rtt; - memd(Rx++#s4:3:circ(Mu))=Rtt EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - *EA = Rtt; - memd(Rx++I:circ(Mu))=Rtt EA=Rx; - Rx=Rx=circ_add(Rx,I<<3,MuV); - *EA = Rtt; - memd(Rx++Mu)=Rtt EA=Rx; - Rx=Rx+MuV; - *EA = Rtt; - memd(Rx++Mu:brev)=Rtt EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - *EA = Rtt; - memd(gp+#u16:3)=Rtt apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - *EA = Rtt; - - - - -80-N2040-36 B 308 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: ST (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t5 -0 0 1 1 1 0 1 1 1 1 0 s s s s s P P i u u u u u i - - t t t t t memd(Rs+Ru<<#u2)=Rtt - ICLASS Type Parse t5 -0 1 0 0 1 i i 0 1 1 0 i i i i i P P i t t t t t i i i i i i i i memd(gp+#u16:3)=Rtt - U - ICLASS Amode Type s5 Parse t5 - N -1 0 1 0 0 i i 1 1 1 0 s s s s s P P i t t t t t i i i i i i i i memd(Rs+#s11:3)=Rtt - U - ICLASS Amode Type x5 Parse u1 t5 - N -1 0 1 0 1 0 0 1 1 1 0 x x x x x P P u t t t t t 0 - - - - - 1 - memd(Rx++I:circ(Mu))=Rtt -1 0 1 0 1 0 0 1 1 1 0 x x x x x P P u t t t t t 0 i i i i - 0 - memd(Rx++#s4:3:circ(Mu))=Rtt - U - ICLASS Amode Type e5 Parse t5 - N -1 0 1 0 1 0 1 1 1 1 0 e e e e e P P 0 t t t t t 1 - I I I I I I memd(Re=#U6)=Rtt - U - ICLASS Amode Type N - x5 Parse t5 - -1 0 1 0 1 0 1 1 1 1 0 x x x x x P P 0 t t t t t 0 i i i i - 0 - memd(Rx++#s4:3)=Rtt - U - ICLASS Amode Type N u5 Parse t5 - -1 0 1 0 1 1 0 1 1 1 0 u u u u u P P i t t t t t 1 i I I I I I I memd(Ru<<#u2+#U6)=Rtt - U - ICLASS Amode Type N x5 Parse u1 t5 - -1 0 1 0 1 1 0 1 1 1 0 x x x x x P P u t t t t t 0 - - - - - - - memd(Rx++Mu)=Rtt -1 0 1 0 1 1 1 1 1 1 0 x x x x x P P u t t t t t 0 - - - - - - - memd(Rx++Mu:brev)=Rtt - - - - - Field name Description - ICLASS Instruction Class - Type Type - Parse Packet/Loop parse bits - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - u5 Field to encode register u - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 309 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store doubleword conditionally - Store a 64-bit register pair in memory at the effective address. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memd(#u6)=Rtt apply_extension(#u); - EA=#u; - *EA = Rtt; - } else { - NOP; - }; - if ([!]Pv[.new]) apply_extension(#u); - memd(Rs+#u6:3)=Rtt if ([!]Pv[.new][0]) { - EA=Rs+#u; - *EA = Rtt; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memd(Rs+Ru<<#u2)=Rtt EA=Rs+(Ru<<#u); - *EA = Rtt; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memd(Rx++#s4:3)=Rtt EA=Rx; - Rx=Rx+#s; - *EA = Rtt; - } else { - NOP; - }; - - - Class: ST (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t5 -0 0 1 1 0 1 0 0 1 1 0 s s s s s P P i u u u u u i v v t t t t t if (Pv) memd(Rs+Ru<<#u2)=Rtt -0 0 1 1 0 1 0 1 1 1 0 s s s s s P P i u u u u u i v v t t t t t if (!Pv) memd(Rs+Ru<<#u2)=Rtt -0 0 1 1 0 1 1 0 1 1 0 s s s s s P P i u u u u u i v v t t t t t if (Pv.new) memd(Rs+Ru<<#u2)=Rtt -0 0 1 1 0 1 1 1 1 1 0 s s s s s P P i u u u u u i v v t t t t t if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt - Pr - Se ed - ICLASS ns Ne Type s5 Parse t5 - e w - -0 1 0 0 0 0 0 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v if (Pv) memd(Rs+#u6:3)=Rtt - - - - -80-N2040-36 B 310 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 1 0 0 0 0 1 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v if (Pv.new) memd(Rs+#u6:3)=Rtt -0 1 0 0 0 1 0 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv) memd(Rs+#u6:3)=Rtt -0 1 0 0 0 1 1 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv.new) memd(Rs+#u6:3)=Rtt - U - ICLASS Amode Type N x5 Parse t5 - -1 0 1 0 1 0 1 1 1 1 0 x x x x x P P 1 t t t t t 0 i i i i 0 v v if (Pv) memd(Rx++#s4:3)=Rtt -1 0 1 0 1 0 1 1 1 1 0 x x x x x P P 1 t t t t t 0 i i i i 1 v v if (!Pv) memd(Rx++#s4:3)=Rtt -1 0 1 0 1 0 1 1 1 1 0 x x x x x P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memd(Rx++#s4:3)=Rtt -1 0 1 0 1 0 1 1 1 1 0 x x x x x P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memd(Rx++#s4:3)=Rtt - U - ICLASS Amode Type Parse t5 - N -1 0 1 0 1 1 1 1 1 1 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v if (Pv) memd(#u6)=Rtt -1 0 1 0 1 1 1 1 1 1 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v if (!Pv) memd(#u6)=Rtt -1 0 1 0 1 1 1 1 1 1 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memd(#u6)=Rtt -1 0 1 0 1 1 1 1 1 1 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memd(#u6)=Rtt - - - - - Field name Description - ICLASS Instruction Class - Type Type - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - u5 Field to encode register u - v2 Field to encode register v - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 311 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store byte - Store the least-significant byte in a source register at the effective address. - - Syntax Behavior - memb(Re=#U6)=Rt apply_extension(#U); - EA=#U; - *EA = Rt&0xff; - Re=#U; - memb(Rs+#s11:0)=Rt apply_extension(#s); - EA=Rs+#s; - *EA = Rt&0xff; - memb(Rs+#u6:0)=#S8 EA=Rs+#u; - apply_extension(#S); - *EA = #S; - memb(Rs+Ru<<#u2)=Rt EA=Rs+(Ru<<#u); - *EA = Rt&0xff; - memb(Ru<<#u2+#U6)=Rt apply_extension(#U); - EA=#U+(Ru<<#u); - *EA = Rt&0xff; - memb(Rx++#s4:0)=Rt EA=Rx; - Rx=Rx+#s; - *EA = Rt&0xff; - memb(Rx++#s4:0:circ(Mu))=Rt EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - *EA = Rt&0xff; - memb(Rx++I:circ(Mu))=Rt EA=Rx; - Rx=Rx=circ_add(Rx,I<<0,MuV); - *EA = Rt&0xff; - memb(Rx++Mu)=Rt EA=Rx; - Rx=Rx+MuV; - *EA = Rt&0xff; - memb(Rx++Mu:brev)=Rt EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - *EA = Rt&0xff; - memb(gp+#u16:0)=Rt apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - *EA = Rt&0xff; - - - Class: ST (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t5 -0 0 1 1 1 0 1 1 0 0 0 s s s s s P P i u u u u u i - - t t t t t memb(Rs+Ru<<#u2)=Rt - ICLASS s5 Parse -0 0 1 1 1 1 0 - - 0 0 s s s s s P P I i i i i i i I I I I I I I memb(Rs+#u6:0)=#S8 - ICLASS Type Parse t5 - - - - -80-N2040-36 B 312 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 1 0 0 1 i i 0 0 0 0 i i i i i P P i t t t t t i i i i i i i i memb(gp+#u16:0)=Rt - U - ICLASS Amode Type s5 Parse t5 - N -1 0 1 0 0 i i 1 0 0 0 s s s s s P P i t t t t t i i i i i i i i memb(Rs+#s11:0)=Rt - - ICLASS Amode Type U x5 Parse u1 t5 - N -1 0 1 0 1 0 0 1 0 0 0 x x x x x P P u t t t t t 0 - - - - - 1 - memb(Rx++I:circ(Mu))=Rt -1 0 1 0 1 0 0 1 0 0 0 x x x x x P P u t t t t t 0 i i i i - 0 - memb(Rx++#s4:0:circ(Mu))=Rt - - ICLASS Amode Type U e5 Parse t5 - N -1 0 1 0 1 0 1 1 0 0 0 e e e e e P P 0 t t t t t 1 - I I I I I I memb(Re=#U6)=Rt - U - ICLASS Amode Type x5 Parse t5 - N -1 0 1 0 1 0 1 1 0 0 0 x x x x x P P 0 t t t t t 0 i i i i - 0 - memb(Rx++#s4:0)=Rt - U - ICLASS Amode Type u5 Parse t5 - N -1 0 1 0 1 1 0 1 0 0 0 u u u u u P P i t t t t t 1 i I I I I I I memb(Ru<<#u2+#U6)=Rt - U - ICLASS Amode Type x5 Parse u1 t5 - N -1 0 1 0 1 1 0 1 0 0 0 x x x x x P P u t t t t t 0 - - - - - - - memb(Rx++Mu)=Rt -1 0 1 0 1 1 1 1 0 0 0 x x x x x P P u t t t t t 0 - - - - - - - memb(Rx++Mu:brev)=Rt - - - - - Field name Description - ICLASS Instruction Class - Type Type - Parse Packet/Loop parse bits - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - u5 Field to encode register u - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 313 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store byte conditionally - Store the least-significant byte in a source register at the effective address. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memb(#u6)=Rt apply_extension(#u); - EA=#u; - *EA = Rt&0xff; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memb(Rs+#u6:0)=#S6 EA=Rs+#u; - apply_extension(#S); - *EA = #S; - } else { - NOP; - }; - if ([!]Pv[.new]) apply_extension(#u); - memb(Rs+#u6:0)=Rt if ([!]Pv[.new][0]) { - EA=Rs+#u; - *EA = Rt&0xff; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memb(Rs+Ru<<#u2)=Rt EA=Rs+(Ru<<#u); - *EA = Rt&0xff; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memb(Rx++#s4:0)=Rt EA=Rx; - Rx=Rx+#s; - *EA = Rt&0xff; - } else { - NOP; - }; - - - - -80-N2040-36 B 314 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: ST (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t5 -0 0 1 1 0 1 0 0 0 0 0 s s s s s P P i u u u u u i v v t t t t t if (Pv) memb(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 0 1 0 0 0 s s s s s P P i u u u u u i v v t t t t t if (!Pv) memb(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 1 0 0 0 0 s s s s s P P i u u u u u i v v t t t t t if (Pv.new) memb(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 1 1 0 0 0 s s s s s P P i u u u u u i v v t t t t t if (!Pv.new) memb(Rs+Ru<<#u2)=Rt - ICLASS s5 Parse -0 0 1 1 1 0 0 0 0 0 0 s s s s s P P I i i i i i i v v I I I I I if (Pv) memb(Rs+#u6:0)=#S6 -0 0 1 1 1 0 0 0 1 0 0 s s s s s P P I i i i i i i v v I I I I I if (!Pv) memb(Rs+#u6:0)=#S6 - -0 0 1 1 1 0 0 1 0 0 0 s s s s s P P I i i i i i i v v I I I I I if (Pv.new) memb(Rs+#u6:0)=#S6 -0 0 1 1 1 0 0 1 1 0 0 s s s s s P P I i i i i i i v v I I I I I if (!Pv.new) memb(Rs+#u6:0)=#S6 - Pr - Se ed - ICLASS ns Ne Type s5 Parse t5 - e w - -0 1 0 0 0 0 0 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v if (Pv) memb(Rs+#u6:0)=Rt -0 1 0 0 0 0 1 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v if (Pv.new) memb(Rs+#u6:0)=Rt -0 1 0 0 0 1 0 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv) memb(Rs+#u6:0)=Rt -0 1 0 0 0 1 1 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv.new) memb(Rs+#u6:0)=Rt - U - ICLASS Amode Type N x5 Parse t5 - -1 0 1 0 1 0 1 1 0 0 0 x x x x x P P 1 t t t t t 0 i i i i 0 v v if (Pv) memb(Rx++#s4:0)=Rt -1 0 1 0 1 0 1 1 0 0 0 x x x x x P P 1 t t t t t 0 i i i i 1 v v if (!Pv) memb(Rx++#s4:0)=Rt -1 0 1 0 1 0 1 1 0 0 0 x x x x x P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memb(Rx++#s4:0)=Rt -1 0 1 0 1 0 1 1 0 0 0 x x x x x P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memb(Rx++#s4:0)=Rt - U - ICLASS Amode Type N Parse t5 - -1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v if (Pv) memb(#u6)=Rt -1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v if (!Pv) memb(#u6)=Rt -1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memb(#u6)=Rt -1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memb(#u6)=Rt - - - - - Field name Description - ICLASS Instruction Class - Type Type - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 315 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - s5 Field to encode register s - t5 Field to encode register t - u5 Field to encode register u - v2 Field to encode register v - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 316 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store halfword - Store the upper or lower 16-bits of a source register at the effective address. - - Syntax Behavior - memh(Re=#U6)=Rt.H apply_extension(#U); - EA=#U; - *EA = Rt.h[1]; - Re=#U; - memh(Re=#U6)=Rt apply_extension(#U); - EA=#U; - *EA = Rt.h[0]; - Re=#U; - memh(Rs+#s11:1)=Rt.H apply_extension(#s); - EA=Rs+#s; - *EA = Rt.h[1]; - memh(Rs+#s11:1)=Rt apply_extension(#s); - EA=Rs+#s; - *EA = Rt.h[0]; - memh(Rs+#u6:1)=#S8 EA=Rs+#u; - apply_extension(#S); - *EA = #S; - memh(Rs+Ru<<#u2)=Rt.H EA=Rs+(Ru<<#u); - *EA = Rt.h[1]; - memh(Rs+Ru<<#u2)=Rt EA=Rs+(Ru<<#u); - *EA = Rt.h[0]; - memh(Ru<<#u2+#U6)=Rt.H apply_extension(#U); - EA=#U+(Ru<<#u); - *EA = Rt.h[1]; - memh(Ru<<#u2+#U6)=Rt apply_extension(#U); - EA=#U+(Ru<<#u); - *EA = Rt.h[0]; - memh(Rx++#s4:1)=Rt.H EA=Rx; - Rx=Rx+#s; - *EA = Rt.h[1]; - memh(Rx++#s4:1)=Rt EA=Rx; - Rx=Rx+#s; - *EA = Rt.h[0]; - memh(Rx++#s4:1:circ(Mu))=Rt.H EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - *EA = Rt.h[1]; - memh(Rx++#s4:1:circ(Mu))=Rt EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - *EA = Rt.h[0]; - memh(Rx++I:circ(Mu))=Rt.H EA=Rx; - Rx=Rx=circ_add(Rx,I<<1,MuV); - *EA = Rt.h[1]; - memh(Rx++I:circ(Mu))=Rt EA=Rx; - Rx=Rx=circ_add(Rx,I<<1,MuV); - *EA = Rt.h[0]; - - - - -80-N2040-36 B 317 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - memh(Rx++Mu)=Rt.H EA=Rx; - Rx=Rx+MuV; - *EA = Rt.h[1]; - memh(Rx++Mu)=Rt EA=Rx; - Rx=Rx+MuV; - *EA = Rt.h[0]; - memh(Rx++Mu:brev)=Rt.H EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - *EA = Rt.h[1]; - memh(Rx++Mu:brev)=Rt EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - *EA = Rt.h[0]; - memh(gp+#u16:1)=Rt.H apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - *EA = Rt.h[1]; - memh(gp+#u16:1)=Rt apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - *EA = Rt.h[0]; - - - Class: ST (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t5 -0 0 1 1 1 0 1 1 0 1 0 s s s s s P P i u u u u u i - - t t t t t memh(Rs+Ru<<#u2)=Rt -0 0 1 1 1 0 1 1 0 1 1 s s s s s P P i u u u u u i - - t t t t t memh(Rs+Ru<<#u2)=Rt.H - ICLASS s5 Parse -0 0 1 1 1 1 0 - - 0 1 s s s s s P P I i i i i i i I I I I I I I memh(Rs+#u6:1)=#S8 - ICLASS Type Parse t5 -0 1 0 0 1 i i 0 0 1 0 i i i i i P P i t t t t t i i i i i i i i memh(gp+#u16:1)=Rt -0 1 0 0 1 i i 0 0 1 1 i i i i i P P i t t t t t i i i i i i i i memh(gp+#u16:1)=Rt.H - U - ICLASS Amode Type s5 Parse t5 - N -1 0 1 0 0 i i 1 0 1 0 s s s s s P P i t t t t t i i i i i i i i memh(Rs+#s11:1)=Rt -1 0 1 0 0 i i 1 0 1 1 s s s s s P P i t t t t t i i i i i i i i memh(Rs+#s11:1)=Rt.H - U - ICLASS Amode Type N x5 Parse u1 t5 - -1 0 1 0 1 0 0 1 0 1 0 x x x x x P P u t t t t t 0 - - - - - 1 - memh(Rx++I:circ(Mu))=Rt -1 0 1 0 1 0 0 1 0 1 0 x x x x x P P u t t t t t 0 i i i i - 0 - memh(Rx++#s4:1:circ(Mu))=Rt -1 0 1 0 1 0 0 1 0 1 1 x x x x x P P u t t t t t 0 - - - - - 1 - memh(Rx++I:circ(Mu))=Rt.H -1 0 1 0 1 0 0 1 0 1 1 x x x x x P P u t t t t t 0 i i i i - 0 - memh(Rx++#s4:1:circ(Mu))=Rt.H - U - ICLASS Amode Type N e5 Parse t5 - -1 0 1 0 1 0 1 1 0 1 0 e e e e e P P 0 t t t t t 1 - I I I I I I memh(Re=#U6)=Rt - U - ICLASS Amode Type N x5 Parse t5 - -1 0 1 0 1 0 1 1 0 1 0 x x x x x P P 0 t t t t t 0 i i i i - 0 - memh(Rx++#s4:1)=Rt - - - - -80-N2040-36 B 318 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type e5 Parse t5 - N -1 0 1 0 1 0 1 1 0 1 1 e e e e e P P 0 t t t t t 1 - I I I I I I memh(Re=#U6)=Rt.H - U - ICLASS Amode Type x5 Parse t5 - N -1 0 1 0 1 0 1 1 0 1 1 x x x x x P P 0 t t t t t 0 i i i i - 0 - memh(Rx++#s4:1)=Rt.H - - ICLASS Amode Type U u5 Parse t5 - N -1 0 1 0 1 1 0 1 0 1 0 u u u u u P P i t t t t t 1 i I I I I I I memh(Ru<<#u2+#U6)=Rt - U - ICLASS Amode Type N x5 Parse u1 t5 - -1 0 1 0 1 1 0 1 0 1 0 x x x x x P P u t t t t t 0 - - - - - - - memh(Rx++Mu)=Rt - U - ICLASS Amode Type u5 Parse t5 - N -1 0 1 0 1 1 0 1 0 1 1 u u u u u P P i t t t t t 1 i I I I I I I memh(Ru<<#u2+#U6)=Rt.H - U - ICLASS Amode Type x5 Parse u1 t5 - N -1 0 1 0 1 1 0 1 0 1 1 x x x x x P P u t t t t t 0 - - - - - - - memh(Rx++Mu)=Rt.H -1 0 1 0 1 1 1 1 0 1 0 x x x x x P P u t t t t t 0 - - - - - - - memh(Rx++Mu:brev)=Rt -1 0 1 0 1 1 1 1 0 1 1 x x x x x P P u t t t t t 0 - - - - - - - memh(Rx++Mu:brev)=Rt.H - - - - - Field name Description - ICLASS Instruction Class - Type Type - Parse Packet/Loop parse bits - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - u5 Field to encode register u - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 319 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store halfword conditionally - Store the upper or lower 16-bits of a source register in memory at the effective address. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memh(#u6)=Rt.H apply_extension(#u); - EA=#u; - *EA = Rt.h[1]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memh(#u6)=Rt apply_extension(#u); - EA=#u; - *EA = Rt.h[0]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memh(Rs+#u6:1)=#S6 EA=Rs+#u; - apply_extension(#S); - *EA = #S; - } else { - NOP; - }; - if ([!]Pv[.new]) apply_extension(#u); - memh(Rs+#u6:1)=Rt.H if ([!]Pv[.new][0]) { - EA=Rs+#u; - *EA = Rt.h[1]; - } else { - NOP; - }; - - - - -80-N2040-36 B 320 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - if ([!]Pv[.new]) apply_extension(#u); - memh(Rs+#u6:1)=Rt if ([!]Pv[.new][0]) { - EA=Rs+#u; - *EA = Rt.h[0]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memh(Rs+Ru<<#u2)=Rt.H EA=Rs+(Ru<<#u); - *EA = Rt.h[1]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memh(Rs+Ru<<#u2)=Rt EA=Rs+(Ru<<#u); - *EA = Rt.h[0]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memh(Rx++#s4:1)=Rt.H EA=Rx; - Rx=Rx+#s; - *EA = Rt.h[1]; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memh(Rx++#s4:1)=Rt EA=Rx; - Rx=Rx+#s; - *EA = Rt.h[0]; - } else { - NOP; - }; - - - Class: ST (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t5 - -0 0 1 1 0 1 0 0 0 1 0 s s s s s P P i u u u u u i v v t t t t t if (Pv) memh(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 0 0 0 1 1 s s s s s P P i u u u u u i v v t t t t t if (Pv) memh(Rs+Ru<<#u2)=Rt.H -0 0 1 1 0 1 0 1 0 1 0 s s s s s P P i u u u u u i v v t t t t t if (!Pv) memh(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 0 1 0 1 1 s s s s s P P i u u u u u i v v t t t t t if (!Pv) memh(Rs+Ru<<#u2)=Rt.H -0 0 1 1 0 1 1 0 0 1 0 s s s s s P P i u u u u u i v v t t t t t if (Pv.new) memh(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 1 0 0 1 1 s s s s s P P i u u u u u i v v t t t t t if (Pv.new) memh(Rs+Ru<<#u2)=Rt.H -0 0 1 1 0 1 1 1 0 1 0 s s s s s P P i u u u u u i v v t t t t t if (!Pv.new) memh(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 1 1 0 1 1 s s s s s P P i u u u u u i v v t t t t t if (!Pv.new) memh(Rs+Ru<<#u2)=Rt.H - - - - -80-N2040-36 B 321 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse -0 0 1 1 1 0 0 0 0 0 1 s s s s s P P I i i i i i i v v I I I I I if (Pv) memh(Rs+#u6:1)=#S6 -0 0 1 1 1 0 0 0 1 0 1 s s s s s P P I i i i i i i v v I I I I I if (!Pv) memh(Rs+#u6:1)=#S6 -0 0 1 1 1 0 0 1 0 0 1 s s s s s P P I i i i i i i v v I I I I I if (Pv.new) memh(Rs+#u6:1)=#S6 -0 0 1 1 1 0 0 1 1 0 1 s s s s s P P I i i i i i i v v I I I I I if (!Pv.new) memh(Rs+#u6:1)=#S6 - Pr - Se ed - ICLASS ns Type s5 Parse t5 - Ne - e - w -0 1 0 0 0 0 0 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v if (Pv) memh(Rs+#u6:1)=Rt -0 1 0 0 0 0 0 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v if (Pv) memh(Rs+#u6:1)=Rt.H -0 1 0 0 0 0 1 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v if (Pv.new) memh(Rs+#u6:1)=Rt -0 1 0 0 0 0 1 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v if (Pv.new) memh(Rs+#u6:1)=Rt.H -0 1 0 0 0 1 0 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv) memh(Rs+#u6:1)=Rt -0 1 0 0 0 1 0 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv) memh(Rs+#u6:1)=Rt.H -0 1 0 0 0 1 1 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv.new) memh(Rs+#u6:1)=Rt -0 1 0 0 0 1 1 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv.new) memh(Rs+#u6:1)=Rt.H - U - ICLASS Amode Type N - x5 Parse t5 - -1 0 1 0 1 0 1 1 0 1 0 x x x x x P P 1 t t t t t 0 i i i i 0 v v if (Pv) memh(Rx++#s4:1)=Rt -1 0 1 0 1 0 1 1 0 1 0 x x x x x P P 1 t t t t t 0 i i i i 1 v v if (!Pv) memh(Rx++#s4:1)=Rt -1 0 1 0 1 0 1 1 0 1 0 x x x x x P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memh(Rx++#s4:1)=Rt -1 0 1 0 1 0 1 1 0 1 0 x x x x x P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memh(Rx++#s4:1)=Rt -1 0 1 0 1 0 1 1 0 1 1 x x x x x P P 1 t t t t t 0 i i i i 0 v v if (Pv) memh(Rx++#s4:1)=Rt.H -1 0 1 0 1 0 1 1 0 1 1 x x x x x P P 1 t t t t t 0 i i i i 1 v v if (!Pv) memh(Rx++#s4:1)=Rt.H -1 0 1 0 1 0 1 1 0 1 1 x x x x x P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memh(Rx++#s4:1)=Rt.H -1 0 1 0 1 0 1 1 0 1 1 x x x x x P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memh(Rx++#s4:1)=Rt.H - U - ICLASS Amode Type Parse t5 - N -1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v if (Pv) memh(#u6)=Rt -1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v if (!Pv) memh(#u6)=Rt -1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memh(#u6)=Rt -1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memh(#u6)=Rt -1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 0 t t t t t 1 i i i i 0 v v if (Pv) memh(#u6)=Rt.H -1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 0 t t t t t 1 i i i i 1 v v if (!Pv) memh(#u6)=Rt.H -1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memh(#u6)=Rt.H -1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memh(#u6)=Rt.H - - - -80-N2040-36 B 322 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Type Type - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - u5 Field to encode register u - v2 Field to encode register v - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 323 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store word - Store a 32-bit register in memory at the effective address. - - Syntax Behavior - memw(Re=#U6)=Rt apply_extension(#U); - EA=#U; - *EA = Rt; - Re=#U; - memw(Rs+#s11:2)=Rt apply_extension(#s); - EA=Rs+#s; - *EA = Rt; - memw(Rs+#u6:2)=#S8 EA=Rs+#u; - apply_extension(#S); - *EA = #S; - memw(Rs+Ru<<#u2)=Rt EA=Rs+(Ru<<#u); - *EA = Rt; - memw(Ru<<#u2+#U6)=Rt apply_extension(#U); - EA=#U+(Ru<<#u); - *EA = Rt; - memw(Rx++#s4:2)=Rt EA=Rx; - Rx=Rx+#s; - *EA = Rt; - memw(Rx++#s4:2:circ(Mu))=Rt EA=Rx; - Rx=Rx=circ_add(Rx,#s,MuV); - *EA = Rt; - memw(Rx++I:circ(Mu))=Rt EA=Rx; - Rx=Rx=circ_add(Rx,I<<2,MuV); - *EA = Rt; - memw(Rx++Mu)=Rt EA=Rx; - Rx=Rx+MuV; - *EA = Rt; - memw(Rx++Mu:brev)=Rt EA=Rx.h[1] | brev(Rx.h[0]); - Rx=Rx+MuV; - *EA = Rt; - memw(gp+#u16:2)=Rt apply_extension(#u); - EA=(Constant_extended ? (0) : GP)+#u; - *EA = Rt; - - - Class: ST (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t5 -0 0 1 1 1 0 1 1 1 0 0 s s s s s P P i u u u u u i - - t t t t t memw(Rs+Ru<<#u2)=Rt - ICLASS s5 Parse -0 0 1 1 1 1 0 - - 1 0 s s s s s P P I i i i i i i I I I I I I I memw(Rs+#u6:2)=#S8 - ICLASS Type Parse t5 - - - - -80-N2040-36 B 324 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -0 1 0 0 1 i i 0 1 0 0 i i i i i P P i t t t t t i i i i i i i i memw(gp+#u16:2)=Rt - U - ICLASS Amode Type s5 Parse t5 - N -1 0 1 0 0 i i 1 1 0 0 s s s s s P P i t t t t t i i i i i i i i memw(Rs+#s11:2)=Rt - - ICLASS Amode Type U x5 Parse u1 t5 - N -1 0 1 0 1 0 0 1 1 0 0 x x x x x P P u t t t t t 0 - - - - - 1 - memw(Rx++I:circ(Mu))=Rt -1 0 1 0 1 0 0 1 1 0 0 x x x x x P P u t t t t t 0 i i i i - 0 - memw(Rx++#s4:2:circ(Mu))=Rt - - ICLASS Amode Type U e5 Parse t5 - N -1 0 1 0 1 0 1 1 1 0 0 e e e e e P P 0 t t t t t 1 - I I I I I I memw(Re=#U6)=Rt - U - ICLASS Amode Type x5 Parse t5 - N -1 0 1 0 1 0 1 1 1 0 0 x x x x x P P 0 t t t t t 0 i i i i - 0 - memw(Rx++#s4:2)=Rt - U - ICLASS Amode Type u5 Parse t5 - N -1 0 1 0 1 1 0 1 1 0 0 u u u u u P P i t t t t t 1 i I I I I I I memw(Ru<<#u2+#U6)=Rt - U - ICLASS Amode Type x5 Parse u1 t5 - N -1 0 1 0 1 1 0 1 1 0 0 x x x x x P P u t t t t t 0 - - - - - - - memw(Rx++Mu)=Rt -1 0 1 0 1 1 1 1 1 0 0 x x x x x P P u t t t t t 0 - - - - - - - memw(Rx++Mu:brev)=Rt - - - - - Field name Description - ICLASS Instruction Class - Type Type - Parse Packet/Loop parse bits - e5 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - u1 Field to encode register u - u5 Field to encode register u - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 325 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store word conditionally - Store a 32-bit register in memory at the effective address. - - This instruction is conditional based on a predicate value. If the predicate is true, the - instruction is performed, otherwise it is treated as a NOP. - - Syntax Behavior - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memw(#u6)=Rt apply_extension(#u); - EA=#u; - *EA = Rt; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memw(Rs+#u6:2)=#S6 EA=Rs+#u; - apply_extension(#S); - *EA = #S; - } else { - NOP; - }; - if ([!]Pv[.new]) apply_extension(#u); - memw(Rs+#u6:2)=Rt if ([!]Pv[.new][0]) { - EA=Rs+#u; - *EA = Rt; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]) { - memw(Rs+Ru<<#u2)=Rt EA=Rs+(Ru<<#u); - *EA = Rt; - } else { - NOP; - }; - if ([!]Pv[.new]) if ([!]Pv[.new][0]){ - memw(Rx++#s4:2)=Rt EA=Rx; - Rx=Rx+#s; - *EA = Rt; - } else { - NOP; - }; - - - - -80-N2040-36 B 326 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: ST (slots 0,1) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse u5 t5 -0 0 1 1 0 1 0 0 1 0 0 s s s s s P P i u u u u u i v v t t t t t if (Pv) memw(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 0 1 1 0 0 s s s s s P P i u u u u u i v v t t t t t if (!Pv) memw(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 1 0 1 0 0 s s s s s P P i u u u u u i v v t t t t t if (Pv.new) memw(Rs+Ru<<#u2)=Rt -0 0 1 1 0 1 1 1 1 0 0 s s s s s P P i u u u u u i v v t t t t t if (!Pv.new) memw(Rs+Ru<<#u2)=Rt - ICLASS s5 Parse - -0 0 1 1 1 0 0 0 0 1 0 s s s s s P P I i i i i i i v v I I I I I if (Pv) memw(Rs+#u6:2)=#S6 -0 0 1 1 1 0 0 0 1 1 0 s s s s s P P I i i i i i i v v I I I I I if (!Pv) memw(Rs+#u6:2)=#S6 -0 0 1 1 1 0 0 1 0 1 0 s s s s s P P I i i i i i i v v I I I I I if (Pv.new) memw(Rs+#u6:2)=#S6 -0 0 1 1 1 0 0 1 1 1 0 s s s s s P P I i i i i i i v v I I I I I if (!Pv.new) memw(Rs+#u6:2)=#S6 - Pr - Se ed - ICLASS ns Ne Type s5 Parse t5 - e w - -0 1 0 0 0 0 0 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v if (Pv) memw(Rs+#u6:2)=Rt -0 1 0 0 0 0 1 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v if (Pv.new) memw(Rs+#u6:2)=Rt -0 1 0 0 0 1 0 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv) memw(Rs+#u6:2)=Rt -0 1 0 0 0 1 1 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v if (!Pv.new) memw(Rs+#u6:2)=Rt - - U - ICLASS Amode Type x5 Parse t5 - N - -1 0 1 0 1 0 1 1 1 0 0 x x x x x P P 1 t t t t t 0 i i i i 0 v v if (Pv) memw(Rx++#s4:2)=Rt -1 0 1 0 1 0 1 1 1 0 0 x x x x x P P 1 t t t t t 0 i i i i 1 v v if (!Pv) memw(Rx++#s4:2)=Rt -1 0 1 0 1 0 1 1 1 0 0 x x x x x P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memw(Rx++#s4:2)=Rt -1 0 1 0 1 0 1 1 1 0 0 x x x x x P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memw(Rx++#s4:2)=Rt - U - ICLASS Amode Type Parse t5 - N -1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v if (Pv) memw(#u6)=Rt -1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v if (!Pv) memw(#u6)=Rt -1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v if (Pv.new) memw(#u6)=Rt -1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v if (!Pv.new) memw(#u6)=Rt - - - - - Field name Description - ICLASS Instruction Class - Type Type - PredNew PredNew - Sense Sense - Parse Packet/Loop parse bits - - - -80-N2040-36 B 327 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - s5 Field to encode register s - t5 Field to encode register t - u5 Field to encode register u - v2 Field to encode register v - x5 Field to encode register x - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 328 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Allocate stack frame - Allocate a stack frame on the call stack. This instruction first pushes LR and FP to the top - of stack. It then subtracts an unsigned immediate from SP to allocate room for local - variables. FP is set to the address of the old frame pointer on the stack. - - The following figure shows the stack layout. - - - Stack in Memory - - Saved LR - Saved FP - - - - - Higher Address - Procedure Local - Data on Stack - - Stack frame - - - - Saved LR - Saved FP FP register - - - - Procedure Local - Data on Stack - - SP register - Lower Address - - - - - Unallocated Stack - - - - - Syntax Behavior - allocframe(#u11:3) EA=SP+-8; - *EA = frame_scramble((LR << 32) | FP); - FP=EA; - frame_check_limit(EA-#u); - SP=EA-#u; - - - - -80-N2040-36 B 329 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: ST (slots 0) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type Parse - N -1 0 1 0 0 0 0 0 1 0 0 1 1 1 0 1 P P 0 0 0 i i i i i i i i i i i allocframe(#u11:3) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 330 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.9 SYSTEM - The SYSTEM instruction class includes instructions for managing system resources. - - - 11.9.1 SYSTEM/GUEST - The SYSTEM/GUEST instruction subclass includes instructions for Guest Mode. - -Guest control register transfer - Move registers between the guest control and general register files. The figure shows the - guest control registers and their register field encodings. Registers can be moved as - singles or as aligned 64-bit pairs. - - - 0 G0 16 ISDBMBXIN - - 1 G1 17 ISDBMBXOUT - - 2 G2 - 3 G3 - - Reserved - - - - 24 GPCYCLELO - - 25 GPCYCLEHI - Reserved - 26 GPMUCNT0 - - 27 GPMUCNT1 - - 28 GPMUCNT2 - - 29 GPMUCNT3 - - 30 Reserved - - 15 31 Reserved - - - - - Syntax Behavior - Gd=Rs Gd=Rs; - Gdd=Rss Gdd=Rss; - Rd=Gs Rd=Gs; - Rdd=Gss Rdd=Gss; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a guest-level feature. If performed in user mode, a privilege error - exception will occur. - - - - -80-N2040-36 B 331 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse d5 -0 1 1 0 0 0 1 0 0 0 0 s s s s s P P - - - - - - - - - d d d d d Gd=Rs -0 1 1 0 0 0 1 1 0 0 0 s s s s s P P - - - - - - - - - d d d d d Gdd=Rss -0 1 1 0 1 0 0 0 0 0 1 s s s s s P P - - - - - - - - - d d d d d Rdd=Gss -0 1 1 0 1 0 1 0 0 0 1 s s s s s P P - - - - - - - - - d d d d d Rd=Gs - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 332 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.9.2 SYSTEM/MONITOR - The SYSTEM/MONITOR instruction subclass includes instructions for Monitor Mode. - -Clear interrupt auto disable - The register Rs specifies a 32-bit mask, where bit 0 corresponds to the highest-priority - interrupt 0, and register bit 31 refers to the lowest-priority interrupt 31. For bits set in Rs, - the corresponding bit in IAD is cleared. This re-enables the interrupt. For bits clear in Rs, - the corresponding bit in IAD is unaffected. - - Syntax Behavior - ciad(Rs) IAD &= ~Rs; - - - Class: SYSTEM (slot 3) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 0 0 0 s s s s s P P - - - - - - 0 1 1 - - - - - ciad(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 333 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Swap SGP control register - This instruction swaps the contents of a general register with one of the Supervisor - General Pointer registers, either SGP0 or SGP1. These registers can be used to hold, for - example, a supervisor and/or exception stack pointers, or other general pointers for fast - exception processing. A pair swap form exists to swap both SGP registers with an aligned - pair of general registers. - - Syntax Behavior - crswap(Rx,sgp) Assembler mapped to: "crswap(Rx,sgp0)" - crswap(Rx,sgp0) tmp = Rx; - Rx = SGP0; - SGP0 = tmp; - crswap(Rx,sgp1) tmp = Rx; - Rx = SGP1; - SGP1 = tmp; - crswap(Rxx,sgp1:0) tmp = Rxx; - Rxx=SGP; - SGP = tmp; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm x5 Parse -0 1 1 0 0 1 0 1 0 0 0 x x x x x P P - - - - - - - - - - - - - - crswap(Rx,sgp0) -0 1 1 0 0 1 0 1 0 0 1 x x x x x P P - - - - - - - - - - - - - - crswap(Rx,sgp1) -0 1 1 0 1 1 0 1 1 0 - x x x x x P P - - - - - - - - - 0 0 0 0 0 crswap(Rxx,sgp1:0) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - x5 Field to encode register x - - - - -80-N2040-36 B 334 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Cancel pending interrupts - The register Rs specifies a 32-bit mask, where bit 0 corresponds to the highest-priority - interrupt 0, and register bit 31 refers to the lowest-priority interrupt 31. This instruction - cancels any pending interrupts indicated in the mask by clearing the interrupt from the - IPEND register. - - Syntax Behavior - cswi(Rs) IPEND &= ~Rs; - - - Class: SYSTEM (slot 3) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 0 0 0 s s s s s P P - - - - - - 0 0 1 - - - - - cswi(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 335 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Data cache kill - The data cache kill (dckill) instruction invalidates the entire contents of the data cache. On - power-up, the caches are not guaranteed to contain valid data. This instruction should be - used to establish an initial clean cache state. All dirty data in the data cache which has not - yet been written back to memory is lost when dckill is executed. If data needs to be saved, - it should be cleaned out using dclean instructions prior to executing dckill. Because the - caches are shared between all threads, this instruction must be performed only while - ensuring that no other thread is using the caches. The best option is to use this instruction - when only one thread is powered on and others are powered off. - - Syntax Behavior - dckill dcache_inv_all(); - - - Class: SYSTEM (slots 0) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type Parse - N -1 0 1 0 0 0 1 0 0 0 0 - - - - - P P - - - - - - - - - - - - - - dckill - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 336 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Data cache maintenance monitor instructions - These instructions perform maintenance operations on the data cache. - - dccleaninvidx looks at index Rs in the data cache. If this line has dirty data, then the data - is written back out to memory. The line is invalidated. The set is provided in Rs[11:5] and - the way in Rs[2:0]. This instruction can only be grouped with X-type or A-type - instructions. - - dccleanidx looks at index Rs in the data cache. If this line has dirty data, then the data is - written back out to memory. The set is provided in Rs[11:5] and the way in Rs[2:0]. This - instruction can only be grouped with X-type or A-type instructions. - - dcinvidx invalidates the line at index Rs. The set is provided in Rs[11:5] and the way in - Rs[2:0]. This instruction can only be grouped with X-type or A-type instructions. - - dctagr reads the tag at indicated by Rs and returns the data into Rd. The set is provided - Rs[11:5], and the Way is provided in Rs[2:0]. The tag is returned in Rd[23:0], and the state - is returned in Rd[30:29]. This instruction can only be grouped with X-type or A-type - instructions. - - dctagw uses register Rs and Rt. Register Rs contains the set in [11:5] and way in [2:0] - while the Rt value contains the Tag in [23:0] and the state in [30:29]. The dctagw - instruction is Single-Thread only. All other threads must be in STOP or DEBUG mode - with no outstanding transactions. This instruction is solo and must not appear in a packet - with other instructions. - - The state bits are encoded as: - - 00 : Invalid - - 01 : Valid & Clean - - 10 : Reserved - - 11 : Valid & Clean - - Syntax Behavior - Rd=dctagr(Rs) dcache_tag_read(Rs); - dccleanidx(Rs) dcache_clean_idx(Rs); - dccleaninvidx(Rs) dcache_clean_idx(Rs); - dcache_inv_idx(Rs); - dcinvidx(Rs) dcache_inv_idx(Rs); - dctagw(Rs,Rt) dcache_tag_write(Rs,Rt); - - - - -80-N2040-36 B 337 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: SYSTEM (slots 0) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse - N -1 0 1 0 0 0 1 0 0 0 1 s s s s s P P - - - - - - - - - - - - - - dccleanidx(Rs) -1 0 1 0 0 0 1 0 0 1 0 s s s s s P P - - - - - - - - - - - - - - dcinvidx(Rs) -1 0 1 0 0 0 1 0 0 1 1 s s s s s P P - - - - - - - - - - - - - - dccleaninvidx(Rs) - U - ICLASS Amode Type s5 Parse t5 - N -1 0 1 0 0 1 0 0 0 0 0 s s s s s P P - t t t t t - - - - - - - - dctagw(Rs,Rt) - U - ICLASS Amode Type N s5 Parse d5 - -1 0 1 0 0 1 0 0 0 0 1 s s s s s P P - - - - - - - - - d d d d d Rd=dctagr(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 338 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Read the interrupt mask for a thread - Each thread contains an IMASK register that holds the interrupt enable/disable for - individual interrupts 0-31. This instruction reads the IMASK for the thread indicated by - the low bits of Rs. The result is returned in Rd. For Rs values outside of [0- - NUM_THREADS-1], the results are undefined. - - Syntax Behavior - Rd=getimask(Rs) Rd=IMASK[Rs&0x7]; - - - Class: SYSTEM (slot 3) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse d5 -0 1 1 0 0 1 1 0 0 0 0 s s s s s P P - - - - - - - - - d d d d d Rd=getimask(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 339 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Acquire hardware lock - These instructions acquire a hardware lock. - - If the lock bit is set, sleep until the lock bit is clear. The packet with the lock instruction - will only complete once the lock is set and acquired by this thread. In the case that - multiple threads are waiting for the lock, the hardware guarantees round-robin fairness - such that no thread will be starved. - - The tlblock is acquired automatically whenever a thread raises a TLB miss-RW or TLB- - miss-X exception. - - The TLB lock can also be released by the rteunlock instruction. - - Syntax Behavior - k0lock if (can_aquire_k0_lock) { - SYSCFG.K0LOCK = 1; - } else { - sleep_until_available; - }; - tlblock if (can_aquire_tlb_lock) { - SYSCFG.TLBLOCK = 1; - } else { - sleep_until_available; - }; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm Parse -0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 0 1 - - - - - tlblock -0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 1 1 - - - - - k0lock - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 340 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Release hardware lock - These instructions release a hardware lock. - - Syntax Behavior - k0unlock SYSCFG.K0LOCK = 0; - tlbunlock SYSCFG.TLBLOCK = 0; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm Parse -0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 1 0 - - - - - tlbunlock -0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 1 0 0 - - - - - k0unlock - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 341 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Interrupt to thread assignment read - Each thread contains an IMASK register that holds the interrupt enable/disable for - individual interrupts 0-31. For a given interrupt, the iassignr instruction reads the - corresponding bit in every thread's IMASK register. The upper halfword of source register - Rs contains the interrupt number from 0-31 (0 is the highest priority interrupt, 31 the - lowest). The low bits of the destination register Rd contain a bit mask where bit 0 contains - the corresponding IMASK value for thread 0, bit 1 the value for thread 1, etc. The number - of defined bits depends on the number of HW threads provided in the core. All bits beyond - the number of threads provided will be cleared. For example, if the interrupt number is set - to 0, then Rd[0] will be the value of IMASK[0] for thread 0, Rd[1] will be the value of - IMASK[0] for thread 1, etc. - - - 31 16 15 0 - - Int# Rs - - - - Interrupt number [0-31] - 0=highest priority - interrupt - 31=lowest priority - - - 31 0 - - Rd - - - Thread 0: - Value of IMASK[int#] - - - - - Thread 5 assignment - - - Syntax Behavior - Rd=iassignr(Rs) Rd=IASSIGNR(Rs); - - - Class: SYSTEM (slot 3) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - - -80-N2040-36 B 342 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse d5 -0 1 1 0 0 1 1 0 0 1 1 s s s s s P P - - - - - - - - - d d d d d Rd=iassignr(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 343 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Interrupt to thread assignment write - Each thread contains an IMASK register that holds the interrupt enable/disable for - individual interrupts 0-31. For a given interrupt, the iassignw instruction sets or clears the - corresponding bit in every thread's IMASK register. This allows for easy re-assignment of - interrupts to selected threads. The source register Rs contains two fields. The upper - halfword should contain the interrupt number from 0-31 (0 is the highest priority interrupt, - 31 the lowest). The low bits contain a bit mask where bit 0 contains the corresponding - IMASK value for thread 0, bit 1 the value for thread 1, etc. For example, if the interrupt - number is set to 0, and the bitmask is set to 0x03, then the IMASK[0] for threads 0 and 1 - will be set and the IMASK[0] for all other threads will be cleared. This means that threads - 0,1 will not accept this interrupt, whereas other threads will accept it. - - - 31 16 15 0 - - Int# Rs - - Thread 0 assignment: - 1=Set Thread0:IMASK[Int#] - Interrupt number [0-31] (interrupt disabled) - 0=highest priority - interrupt 0=Clear Thread0:IMASK[Int#] - 31=lowest priority (interrupt enabled for T0) - - Thread 5 assignment - - - Syntax Behavior - iassignw(Rs) IASSIGNW(Rs); - - - Class: SYSTEM (slot 3) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 0 0 0 s s s s s P P - - - - - - 0 1 0 - - - - - iassignw(Rs) - - - - -80-N2040-36 B 344 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 345 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Instruction cache maintenance supervisor operations - These instructions perform maintenance operations on the instruction cache. - - ictagr reads the tag entry at set Rs[13:5] and way Rs[0]. The tag information is returned in - Rd[31:4] (with the G bit in bit 31, the ASID value in bits 30:24, and the Tag value in bits - 23:4). The Valid bit is returned in Rd[1], and the Reserved bit in Rd[0]. - - icdatar reads the data word at set Rs[13:5], word Rs[4:2], and way Rs[0]. The data value is - returned in Rd[31:0]. - - icinvidx invalidates the instruction cache index indicated by Rs. - - Syntax Behavior - Rd=icdatar(Rs) icache_data_read(Rs); - Rd=ictagr(Rs) icache_tag_read(Rs); - icinvidx(Rs) icache_inv_idx(Rs); - - - Class: SYSTEM (slot 2) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse d5 -0 1 0 1 0 1 0 1 1 0 1 s s s s s P P - - - - - - - - - d d d d d Rd=icdatar(Rs) -0 1 0 1 0 1 0 1 1 1 1 s s s s s P P - - - - - - - - - d d d d d Rd=ictagr(Rs) - ICLASS s5 Parse -0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 1 - - - - - - - - - - - icinvidx(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 346 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Instruction cache maintenance operations (single-thread) - These instructions perform maintenance operations on the instruction cache. - - ickill invalidates the instruction cache. - - ictagw updates specified tag entry with contents of Rt. Rs[13:5] selects index and Rs[0] is - used to select cache way. Rt must have the Tag information in bits 27:0 (G bit is bit 27, - ASID is bits 26:20 and Tag is 19:0), the Valid bit in Rt[30] and the Reserved bit in Rt[31]. - - These instructions are Single-Thread only. All other threads must be in STOP or DEBUG - mode with no outstanding transactions. - - Syntax Behavior - ickill icache_inv_all(); - ictagw(Rs,Rt) icache_tag_write(Rs,Rt); - - - Class: SYSTEM (slot 2) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse t5 -0 1 0 1 0 1 0 1 1 1 0 s s s s s P P - t t t t t - - - - - - - - ictagw(Rs,Rt) - ICLASS Parse -0 1 0 1 0 1 1 0 1 1 0 - - - - - P P 0 1 0 - - - - - - - - - - - ickill - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 347 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -L2 cache operations by index - L2 cacheops by index work on a specified line in L2 cache. The clean operation pushed - dirty data out to the system. The invalidate operations marks the line as invalidate, and the - cleaninv operation first cleans the line and then invalidates it. The index is provided in - Rs[S:8] and the way in Rs[2:0], where S is determined by the number of sets in the L2 - cache. For segmented L2 caches, the granule bit provided in Rs[3]. This bit is ignored if - the cache is not segmented. - - Different versions of Hexagon may have different L2 cache sizes. Please see the section - on Core Versions for more information. - - Syntax Behavior - l2cleanidx(Rs) l2cache_clean_idx(Rs); - l2cleaninvidx(Rs) l2cache_clean_invalidate_idx(Rs); - l2invidx(Rs) l2cache_inv_idx(Rs); - - - Class: SYSTEM (slots 0) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse - N -1 0 1 0 0 1 1 0 0 0 1 s s s s s P P - - - - - - - - - - - - - - l2cleanidx(Rs) -1 0 1 0 0 1 1 0 0 1 0 s s s s s P P - - - - - - - - - - - - - - l2invidx(Rs) -1 0 1 0 1 0 0 0 0 1 1 s s s s s P P - - - - - - - - - - - - - - l2cleaninvidx(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 348 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -L2 cache global operations - These instructions perform maintenance operations over the entire L2 cache. The - instructions will commit and set the SYSCFG:L2GCA bit to indicate that the Global - Cache state machine is Active. Once the state machine is started it will process every L2 - cacheline in the background. After all cachelines have been processed, the - SYSCFG:L2GCA status bit is cleared. The instructions are: - - l2kill will invalidate every line. It is required to execute this instruction prior to using L2 - after a poweron reset, as the cache will start in an unknown state. - - l2gclean will force a clean (write back) operation for all L2 cachelines that are dirty. - - l2gcleaninv will force a clean (write back) for dirty L2 lines and then invalidate them. - - l2gunlock will clear the lock bit for all L2 cachelines. - - The l2gclean and l2gcleaninv instructions are available with PA range and mask option. In - this form, the Rtt register contains a mask in the lower word and match value in the upper - word. If the Physical Page Number of the cache line anded with the mask is equal to the - match value, then the cacheop is performed. Otherwise, the cacheline is left unchanged. - The semantics are: - - for every cacheline in L2: - - if (Rtt[23:0] & PA[35:12]) == Rtt[55:32]) do clean/cleaninv on the cacheline - - Syntax Behavior - l2gclean l2cache_global_clean(); - l2gclean(Rtt) l2cache_global_clean_range(Rtt); - l2gcleaninv l2cache_global_clean_inv(); - l2gcleaninv(Rtt) l2cache_global_clean_inv_range(Rtt); - l2gunlock l2cache_global_unlock(); - l2kill l2cache_inv_all(); - - - Class: SYSTEM (slots 0) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - - - -80-N2040-36 B 349 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type Parse t5 - N -1 0 1 0 0 1 1 0 1 0 1 - - - - - P P - t t t t t - - - - - - - - l2gclean(Rtt) -1 0 1 0 0 1 1 0 1 1 0 - - - - - P P - t t t t t - - - - - - - - l2gcleaninv(Rtt) - U - ICLASS Amode Type N Parse - -1 0 1 0 1 0 0 0 0 0 1 - - - - - P P - 0 0 0 - - - - - - - - - - l2kill -1 0 1 0 1 0 0 0 0 0 1 - - - - - P P - 0 1 0 - - - - - - - - - - l2gunlock -1 0 1 0 1 0 0 0 0 0 1 - - - - - P P - 1 0 0 - - - - - - - - - - l2gclean -1 0 1 0 1 0 0 0 0 0 1 - - - - - P P - 1 1 0 - - - - - - - - - - l2gcleaninv - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - t5 Field to encode register t - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 350 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -L2 cache operations by address - The L2 lock instruction will first allocate a line in L2 based on the address provided in Rs. - It will then set the lock bit so the line will not be replaced in the future, unless explicitly - unlocked. A fetch will be initiated for the data. Finally, the instruction will return a status - result to the destination predicate. The predicate is set to 0xff if the operation was - successful, or 0x00 if the operation did not succeed. The failure state can be returned - either because all the L2 cache ways are already locked, or because of some internal - transient conditions. The software should resolve transient conditions by re-trying the - l2locka instruction with a large number of attempts (1000 recommended). - - The l2unlocka instruction will clear the lock bit on an L2 cacheline which holds the - provided address. - - Syntax Behavior - Pd=l2locka(Rs) EA=Rs; - Pd=l2locka(EA); - l2unlocka(Rs) EA=Rs; - l2unlocka(EA); - - - Class: SYSTEM (slots 0) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type N s5 Parse d2 - -1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 1 - - - - - - - - - - - d d Pd=l2locka(Rs) - U - ICLASS Amode Type s5 Parse - N -1 0 1 0 0 1 1 0 0 1 1 s s s s s P P - - - - - - - - - - - - - - l2unlocka(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 351 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 352 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -L2 tag read/write - L2tagr reads the tag at indicated by Rs and returns the data into Rd. The L2tagr instruction - can be grouped with A-type and X-type instructions. The L2tagw instruction should not be - grouped in a packet. Register Rs is formatted as - - Rs[17:8] = Set - - Rs[2:0] = Way - - The return register Rd is formatted as - - Rd[31] = A1 - - Rd[30] = A0 - - Rd[28:8] = Tag address bits 35:15 - - Rd[4] = Lock bit - - Rd[3] = Reserve bit - - Rd[2:0] = State[2:0] - - The state bits are defined as follows: - - 0 = Invalid - - 1,3 = Reserved - - 4 = Valid & Clean - - 6 = Valid & Dirty - - Syntax Behavior - Rd=l2tagr(Rs) l2cache_tag_read(Rs); - l2tagw(Rs,Rt) l2cache_tag_write(Rs,Rt); - - - Class: SYSTEM (slots 0) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - - - -80-N2040-36 B 353 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse t5 - N -1 0 1 0 0 1 0 0 0 1 0 s s s s s P P 0 t t t t t - - - - - - - - l2tagw(Rs,Rt) - U - ICLASS Amode Type s5 Parse d5 - N -1 0 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - - - - d d d d d Rd=l2tagr(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 354 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Load from physical address - Perform a word load using the 36-bit physical address held in source registers Rt:Rs. Rs - holds PA[10:0] and Rt holds PA[35:11] in the least-significant bits. This instruction will - first look in the L1 and L2 caches for the data. If found, the data will be returned. If the - access misses in cache, it will be treated as a non-allocating (uncached) load. The - hardware will force the two least-significant bits to zero, so will never result in an - alignment violation. - - This instruction is used for the monitor software to walk guest mode page tables, and for - easier debugging. - - Syntax Behavior - Rd=memw_phys(Rs,Rt) Rd = *((Rs&0x7ff) | (Rt<<11)); - - - Class: SYSTEM (slots 0) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse t5 d5 - N -1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 1 t t t t t - - 0 d d d d d Rd=memw_phys(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 355 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Raise NMI on threads - The low bits of Rs specify a thread mask, where bit 0 corresponds to thread 0. The number - of defined bits depends on the how many HW threads are supported. The NMI instruction - raises a non-maskable NMI interrupt for all threads specified in the mask. This interrupt - will cause the thread jump to the NMI vector at the address specified in EVB. - - Syntax Behavior - nmi(Rs) Raise NMI on threads; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - 0 1 0 - - - - - nmi(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 356 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Resume from wait mode - The low bits of Rs specify a thread mask, where bit 0 corresponds to thread 0. The number - of defined bits depends on the how many HW threads are supported. The resume - instruction causes all threads specified in the mask which are in wait mode to exit wait - mode back to either supervisor or user mode (whichever was active when the thread - entered wait mode). If the thread to be resumed is off (stop mode), or already running - (user or supervisor mode), then the resume instruction has no affect. - - Syntax Behavior - resume(Rs) for (i = 0; i < THREADS_MAX; i++) { - if (Rs.i) { - modectl[(i+16)] = 0; - }; - }; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 0 1 0 s s s s s P P - - - - - - 0 0 1 - - - - - resume(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 357 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Return from exception - This instruction is used to return from an interrupt or exception handler. It clears the EX - bit in SSR and jumps to the location specified in the ELR register. rte clears the - SYSCFG.TLBLOCK bit, thus releasing the TLB lock and allowing other threads to - acquire the lock if needed. rte must not be grouped with another exception-causing - instruction. If it is grouped with any other instruction that causes an exception, the - behavior is undefined. - - Syntax Behavior - rte SSR.SSR_EX = 0; - PC=ELR; - - - Class: SYSTEM (slot 2) - - Notes - -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Parse -0 1 0 1 0 1 1 1 1 1 1 - - - - - P P 0 0 - - - - 0 0 0 - - - - - rte - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 358 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Return from exception and unlock TLB - This instruction is used to return from an interrupt or exception handler. It clears the EX - bit in SSR and jumps to the location specified in the ELR register. - - Syntax Behavior - rteunlock SSR.SSR_EX = 0; - SYSCFG.TLBLOCK = 0; - PC=ELR; - - - Class: SYSTEM (slot 2) - - Notes - -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Parse -0 1 0 1 0 1 1 1 1 1 1 - - - - - P P 0 1 - - - - 0 0 0 - - - - - rteunlock - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 359 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Set the interrupt mask for a thread - Each thread contains an IMASK register that holds the interrupt enable/disable for - individual interrupts 0-31. This instruction writes the IMASK for the thread indicated by - the low bits of predicate Pt. The register Rs contains the 32-bit mask value to be written. - For Pt values outside of [0-NUM_THREADS-1], the results are undefined. - - Syntax Behavior - setimask(Pt,Rs) IMASK[Pt&0x7]=Rs; - - - Class: SYSTEM (slot 3) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse t2 -0 1 1 0 0 1 0 0 1 0 0 s s s s s P P - - - - t t 0 0 0 - - - - - setimask(Pt,Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - t2 Field to encode register t - - - - -80-N2040-36 B 360 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Set interrupt auto disable - The register Rs specifies a 32-bit mask, where bit 0 corresponds to the highest-priority - interrupt 0, and register bit 31 refers to the lowest-priority interrupt 31. For bits set in Rs, - the corresponding bit in IAD is set. This disables the interrupt. For bits clear in Rs, the - corresponding bit in IAD is unaffected. - - Syntax Behavior - siad(Rs) IAD |= Rs; - - - Class: SYSTEM (slot 3) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 1 0 0 s s s s s P P - - - - - - 0 1 1 - - - - - siad(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 361 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Start threads - The low bits of Rs specify a thread mask, where bit 0 corresponds to thread 0. The number - of defined bits depends on the how many HW threads are supported. The start instruction - raises a non-maskable software reset interrupt for all threads specified in the mask. This - interrupt will cause the thread to clear all writable bits in the supervisor status register and - then jump to the start vector at the address specified in EVB. Typically, start should be - used to power up threads after they have been disabled by the stop instruction. - - Syntax Behavior - start(Rs) for (i = 0; i < THREADS_MAX; i++) { - if (Rs.i && (modectl[i] == 0)) { - modectl[i] = 1; - reset_thread(i); - }; - }; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - 0 0 1 - - - - - start(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 362 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Stop threads - The stop instruction causes the calling thread to enter stop mode. Stop mode is a power off - mode where all register contents for that thread should be assumed lost. The only way out - of stop mode is through a reset interrupt. The reset interrupt can be from another thread - executing the start instruction, or from an external hardware reset signal. - - Note that the source register Rs is not used in the instruction. It exists for backwards - compatibility. - - Syntax Behavior - stop(Rs) if (!in_debug_mode) modectl[TNUM] = 0; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - 0 0 0 - - - - - stop(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 363 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Software interrupt - Register Rs specifies a 32-bit mask, where bit 0 corresponds to the highest-priority - interrupt 0, and register bit 31 refers to the lowest-priority interrupt 31. This instruction - causes the interrupts indicated in the mask to be raised. Interrupt processing will be - initiated as described in the System Architecture Specification. - - This instruction is provided so that threads can very quickly interrupt one another. - - Syntax Behavior - swi(Rs) IPEND |= Rs; - - - Class: SYSTEM (slot 3) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 0 0 0 s s s s s P P - - - - - - 0 0 0 - - - - - swi(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 364 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -TLB read/write/probe operations - These instructions manage the software-programmable Translation Lookaside Buffer. - - The TLB Read (tlbr) instruction returns the 64-bit TLB entry at the location specified in - register Rs. The result is written into the 64-bit destination register pair. - - The TLB Write (tlbw) instruction writes the 64-bit TLB entry specified by register Rt with - the contents of register pair Rss. - - The TLB Probe (tlbp) instruction looks up the TLB based on the virtual page number - contained in register Rs[19:0] together with the 7-bit ASID provided in Rs[26:20]. If the - entry is found and marked valid, its index is placed in Rd, otherwise Rd is set to - 0x8000_0000. - - The TLB Invalidate ASID (tlbinvasid) instruction invalidates all TLB entries with the - Global bit NOT set and with the ASID matching the Rs[26:20] operand. - - The Conditional TLB Write (ctlbw) instruction first checks if the new entry would overlap - the virtual address range of any other entry in the TLB. The overlap check considers page - size and ASID. In the overlap check, the Global bit of the incoming Rss entry is forced to - zero and the Valid bit is forced to 1. If there is no overlap, the entry is written and the - destination register is set to 0x8000_0000. Otherwise, if an overlap occurs, no TLB entry - is written and the index on the overlapping entry is placed in Rd. If multiple entries - overlap, the value 0xffff_ffff is returned. - - The TLB Overlap Check (tlboc) instruction looks up the TLB based on the VPN, page - size, and ASID contained in register Rss (in the same format as TLBW). The overlap - check considers page size and ASID. In the overlap check, the Global bit of the incoming - Rss entry is forced to zero and the Valid bit is forced to 1. If the Rss entry overlaps virtual - address range of any another entry in the TLB, the index of the overlapping entry is placed - in Rd, otherwise Rd is set to 0x8000_0000. If multiple entries overlap, the value - 0xffff_ffff is returned. - - For both tlboc and ctlbw, if the PPN[5:0] are all zero, then the behavior is undefined. - - - - -80-N2040-36 B 365 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - Rd=ctlbw(Rss,Rt) if (CHECK_TLB_OVERLAP((1LL<<63) | Rss)) { - Rd=GET_OVERLAPPING_IDX((1LL<<63) | - Rss); - } else { - TLB[Rt] = Rss; - Rd=0x80000000; - }; - Rd=tlboc(Rss) if (CHECK_TLB_OVERLAP((1LL<<63) | Rss)) { - Rd=GET_OVERLAPPING_IDX((1LL<<63) | - Rss); - } else { - Rd=0x80000000; - }; - Rd=tlbp(Rs) Rd=search_TLB(Rs); - Rdd=tlbr(Rs) Rdd = TLB[Rs]; - tlbinvasid(Rs) for (i = 0; i < NUM_TLB_ENTRIES; i++) { - if ((TLB[i].PTE_G == 0) && - (TLB[i].PTE_ASID == Rs[26:20])) { - TLB[i] = TLB[i] & ~(1ULL << 63); - }; - }; - tlbw(Rss,Rt) TLB[Rt] = Rss; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse t5 -0 1 1 0 1 1 0 0 0 0 0 s s s s s P P 0 t t t t t - - - - - - - - tlbw(Rss,Rt) - ICLASS sm s5 Parse d5 -0 1 1 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - - - - d d d d d Rdd=tlbr(Rs) -0 1 1 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - - - - d d d d d Rd=tlbp(Rs) - ICLASS sm s5 Parse -0 1 1 0 1 1 0 0 1 0 1 s s s s s P P - - - - - - - - - - - - - - tlbinvasid(Rs) - ICLASS sm s5 Parse t5 d5 -0 1 1 0 1 1 0 0 1 1 0 s s s s s P P 0 t t t t t - - - d d d d d Rd=ctlbw(Rss,Rt) - ICLASS sm s5 Parse d5 -0 1 1 0 1 1 0 0 1 1 1 s s s s s P P - - - - - - - - - d d d d d Rd=tlboc(Rss) - - - - -80-N2040-36 B 366 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 367 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -System control register transfer - These instructions move data between supervisor control registers and general registers. - Registers can be moved as 32-bit singles or as 64-bit aligned pairs. The figure shows the - system control registers and their register field encodings. - - - 0 SGP0 16 EVB 32 ISDBST 48 PMUCNT0 - - 1 SGP1 17 MODECTL 33 ISDBCFG0 49 PMUCNT1 - - 2 STID 18 SYSCFG 34 ISDBCFG1 50 PMUCNT2 - - 3 ELR 19 - 35 - 51 PMUCNT3 - - 4 BADVA0 20 IPEND 36 BRKPTPC0 52 PMUEVTCFG - - - 5 BADVA1 21 VID 37 BRKPTCFG0 53 PMUCFG - - 6 SSR 22 IAD 38 BRKPTPC1 54 - - 7 CCR 23 - 39 BRKPTCFG1 - Reserved - 8 HTID 24 IEL 40 ISDBMBXIN - - 9 BADVA 25 - 41 ISDBMBXOUT - - 10 IMASK 26 IAHL ISDBEN - 42 - - 11 27 CFGBASE 43 ISDBGPR - - 28 DIAG - - - Reserved 29 REV Reserved - - 30 PCYCLELO - - 31 PCYCLEHI - 15 47 63 - - - - - Syntax Behavior - Rd=Ss Rd=Ss; - Rdd=Sss Rdd=Sss; - Sd=Rs Sd=Rs; - Sdd=Rss Sdd=Rss; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - - - -80-N2040-36 B 368 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse d6 -0 1 1 0 0 1 1 1 0 0 - s s s s s P P - - - - - - - - d d d d d d Sd=Rs -0 1 1 0 1 1 0 1 0 0 - s s s s s P P - - - - - - - - d d d d d d Sdd=Rss - ICLASS sm s6 Parse d5 -0 1 1 0 1 1 1 0 1 - s s s s s s P P - - - - - - - - - d d d d d Rd=Ss -0 1 1 0 1 1 1 1 0 - s s s s s s P P - - - - - - - - - d d d d d Rdd=Sss - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - d6 Field to encode register d - s5 Field to encode register s - s6 Field to encode register s - - - - -80-N2040-36 B 369 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Transition threads to wait mode - The wait instruction causes the calling thread to enter wait mode. Wait mode is a low- - power mode where the thread idles. The thread will not fetch or execute instructions in - wait mode. - - When a thread executes wait, the PC is set to the packet after the wait instruction. - - To exit wait mode, a waiting thread can either receive an interrupt, or another thread can - execute the resume instruction for the waiting thread. In the case that a thread is woken up - by an interrupt, at the time the interrupt service routine completes and executes an rte - instruction, the thread will remain running. - - Note that the source register Rs is not used in the instruction. It exists for backwards - compatibility. - - Syntax Behavior - wait(Rs) if (!in_debug_mode) modectl[(TNUM+16)] = 1; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. -  This is a monitor-level feature. If performed in user or guest mode, a privilege - error exception will occur. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 1 0 0 0 1 0 s s s s s P P - - - - - - 0 0 0 - - - - - wait(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 370 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.9.3 SYSTEM/USER - The SYSTEM/USER instruction subclass includes instructions which allow user access to - system resources. - -Load locked - Perform a word or double-word locked load. This returns the contents of the memory at - address Rs and also reserves a lock reservation at that address. See the section on Atomic - Operations for more information. - - Syntax Behavior - Rd=memw_locked(Rs) EA=Rs; - Rd = *EA; - Rdd=memd_locked(Rs) EA=Rs; - Rdd = *EA; - - - Class: SYSTEM (slots 0) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse d5 - N -1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 0 - - - - - - 0 d d d d d Rd=memw_locked(Rs) -1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 1 - - - - - - 0 d d d d d Rdd=memd_locked(Rs) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - - - - -80-N2040-36 B 371 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Store conditional - Perform a word or double-word conditional store operation. If the address reservation is - held by this thread and there have been no intervening accesses to the memory location, - then the store is performed and the predicate is set to true. Otherwise, the store is not - performed and the predicate returns false. See the section on Atomic Operations for more - information. - - Syntax Behavior - memd_locked(Rs,Pd)=Rtt EA=Rs; - if (lock_valid) { - *EA = Rtt; - Pd = 0xff; - lock_valid = 0; - } else { - Pd = 0; - }; - memw_locked(Rs,Pd)=Rt EA=Rs; - if (lock_valid) { - *EA = Rt; - Pd = 0xff; - lock_valid = 0; - } else { - Pd = 0; - }; - - - Class: SYSTEM (slots 0) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse t5 d2 - N -1 0 1 0 0 0 0 0 1 0 1 s s s s s P P - t t t t t - - - - - - d d memw_locked(Rs,Pd)=Rt -1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - - - - - d d memd_locked(Rs,Pd)=Rtt - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 372 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 373 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Zero a cache line - Clear a 32-byte line in memory. - - If the memory is marked write-back cacheable, the line is allocated in the data cache and - cleared. - - If it is write-through or write-back, then the zero line is sent to memory. - - This instruction is useful for efficiently handling write-only data by pre-allocating lines in - the cache. - - The address should be 32-byte aligned. If not, an unaligned error exception is raised. - - If these instruction appears in a packet, then slot 1 must be A-type or empty. - - Syntax Behavior - dczeroa(Rs) EA=Rs; - dcache_zero_addr(EA); - - - Class: SYSTEM (slots 0) - - Notes - -  A packet containing this instruction must have slot 1 either empty or executing an - ALU32 instruction. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse - N -1 0 1 0 0 0 0 0 1 1 0 s s s s s P P 0 - - - - - - - - - - - - - dczeroa(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 374 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Memory barrier - Establish a memory barrier to ensure proper ordering between accesses before the barrier - instruction and accesses after the barrier instruction. All accesses before the barrier will be - globally observable before any access after the barrier can be observed. - - The use of this instruction is system-dependent. - - Syntax Behavior - barrier memory_barrier; - - - Class: SYSTEM (slots 0) - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type Parse - N -1 0 1 0 1 0 0 0 0 0 0 - - - - - P P - - - - - - - - - - - - - - barrier - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 375 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Breakpoint - Cause the program to enter debug mode if enabled by ISDB. Execution control is handed - to ISDB and the program will not proceed until directed by the debugger. - - If ISDB is disabled, this instruction is treated as a NOP. - - Syntax Behavior - brkpt Enter debug mode; - - - Class: SYSTEM (slot 3) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm Parse -0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 0 0 - - - - - brkpt - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 376 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Data cache prefetch - Prefetch the data at address Rs + unsigned immediate. - - This instruction is a hint to the memory system, and is handled in an implementation- - dependent manner. - - Syntax Behavior - dcfetch(Rs) Assembler mapped to: "dcfetch(Rs+#0)" - dcfetch(Rs+#u11:3) EA=Rs+#u; - dcache_fetch(EA); - - - Class: SYSTEM (slots 0) - - Intrinsics - - - dcfetch(Rs) void Q6_dcfetch_A(Address a) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse - N -1 0 0 1 0 1 0 0 0 0 0 s s s s s P P 0 - - i i i i i i i i i i i dcfetch(Rs+#u11:3) - - - - - Field name Description - ICLASS Instruction Class - Amode Amode - Type Type - UN Unsigned - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 377 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Data cache maintenance user operations - Perform maintenance operations on the data cache. - - dccleaninva looks up the data cache at address Rs. If this address is in the cache and has - dirty data, then the data is written back out to memory and the line is then invalidated. - - dccleana looks up the data cache at address Rs. If this address is in the cache and has dirty - data, then the data is written back out to memory. - - dcinva looks up the data cache at address Rs. If this address is in the cache, then the line - containing the data is invalidated. - - If these instruction appears in a packet, then slot 1 must be A-type or empty. - - In implementations that support L2 cache, these instructions operate on both L1 data and - L2 caches. - - Syntax Behavior - dccleana(Rs) EA=Rs; - dcache_clean_addr(EA); - dccleaninva(Rs) EA=Rs; - dcache_cleaninv_addr(EA); - dcinva(Rs) EA=Rs; - dcache_cleaninv_addr(EA); - - - Class: SYSTEM (slots 0) - - Notes - -  A packet containing this instruction must have slot 1 either empty or executing an - ALU32 instruction. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse - N -1 0 1 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - - - - - - - - - dccleana(Rs) -1 0 1 0 0 0 0 0 0 0 1 s s s s s P P - - - - - - - - - - - - - - dcinva(Rs) -1 0 1 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - - - - - - - - - dccleaninva(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - Amode Amode - Type Type - UN Unsigned - - - -80-N2040-36 B 378 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Instruction cache maintenance user operations - Look up the address in Rs in the instruction cache. If the address is found, invalidate the - corresponding cache line. If the user does not have proper permissions to the page which - is to be invalidated, the instruction is converted to a NOP. - - Syntax Behavior - icinva(Rs) EA=Rs; - icache_inv_addr(EA); - - - Class: SYSTEM (slot 2) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS s5 Parse -0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 0 - - - - - - - - - - - icinva(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 379 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Instruction synchronization - Ensure that all prior instructions have committed before continuing to the next instruction. - - This instruction should be executed after the following events (when subsequent - instructions need to observe the results of the event): -  After modifying the TLB with a tlbw instruction -  After modifying the SSR register -  After modifying the SYSCFG register -  After any instruction cache maintenance operation -  After modifying the TID register - - Syntax Behavior - isync instruction_sync; - - - Class: SYSTEM (slot 2) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Parse -0 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 P P 0 - - - 0 0 0 0 0 0 0 0 1 0 isync - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 380 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -L2 cache prefetch - This instruction initiates background prefetching into the L2 cache. - - Rs specifies the 32-bit virtual start address. - - There are two forms of this instruction. In the first form, the dimensions of the area to - prefetch are encoded in source register Rt as follows: - - Rt[15:8] = Width of a fetch block in bytes. - - Rt[7:0] = Height: the number of Width-sized blocks to fetch. - - Rt[31:16] = Stride: an unsigned byte offset which is used to increment the pointer after - each Width-sized block is fetched. - - In the second form, the operands are encoded in register pair Rtt as follows: - - Rtt[31:16] = Width of a fetch block in bytes. - - Rtt[15:0] = Height: the number of Width-sized blocks to fetch. - - Rtt[47:32] = Stride: an unsigned byte offset which is used to increment the pointer after - each Width-sized block is fetched. - - Rtt[48] = Direction: if clear, the prefetches should be performed in row major form - meaning all cache lines in a row should be fetched before proceeding to the next row. If - the bit is set, prefetch should be done in column major form, meaning all cache lines in a - column are fetched before proceeding to the next column. - - The following figure shows two examples of using the l2fetch instruction. In the box - prefetch, a 2-D range of memory is defined within a larger frame. The second example - shows prefetch for a large linear area of memory, which has size Lines * 128. - L2FETCH for box prefetch L2FETCH for large linear prefetch - - 31 31 16 15 8 7 0 - 16 15 8 7 0 - - Rt Stride Width Height Rt 128 128 Lines - - - - Rs Start Address Rs Start Address - - - - Stride - - - - Width - - - Prefetch - Height 128* Lines - Area - - - - -80-N2040-36 B 381 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - l2fetch(Rs,Rt) l2fetch(Rs,INFO); - l2fetch(Rs,Rtt) l2fetch(Rs,INFO); - - l2fetch is non-blocking. After the instruction is initiated, the program will continue on to - the next instruction while the prefetching is performed in the background. l2fetch can be - used to bring in either code or data to the L2 cache. If the lines of interest are already in the - L2, no action is performed. If the lines are missing from the L2$, the hardware attempts to - fetch them from the system memory. - - The hardware prefetch engine continues to request all lines in the programmed memory - range. The prefetching hardware makes a best-effort to prefetch the requested data, and - attempts to perform prefetching at a lower priority than demand fetches. This prevents - prefetch from adding traffic while the system is under heavy load. - - If a program initiates a new l2fetch while an older l2fetch operation is still pending, the - new request is queued, up to 3 deep. If 3 l2fetch operations are already pending, the oldest - request is dropped. During the time an L2 prefetch is active for a thread, the USR:PFA - status bit is set to indicate that prefetches are in-progress. This bit can be used by the - programmer to decide whether or not to start a new l2fetch before the previous one - completes. Note that because L2FETCH is uses low priority, it is not guaranteed to - complete in all cases. - - Executing an l2fetch instruction with any subfield programmed as zero cancels all pending - prefetches by the calling thread. - - The implementation is free to drop prefetches when needed. - - - Class: SYSTEM (slots 0) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type s5 Parse t5 - N -1 0 1 0 0 1 1 0 0 0 0 s s s s s P P - t t t t t - - - - - - - - l2fetch(Rs,Rt) -1 0 1 0 0 1 1 0 1 0 0 s s s s s P P - t t t t t - - - - - - - - l2fetch(Rs,Rtt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - - - -80-N2040-36 B 382 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 383 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Pause - Pause execution for a specified period of time. - - During the pause duration, the program enters a low-power state and will not fetch and - execute instructions. The instruction provides a short immediate which indicates the pause - duration. The program will pause for at most the number of cycles specified in the - immediate plus 8. The minimum pause is 0 cycles, and the maximum pause is - implementation-defined. - - An interrupt to the program exits the paused state. - - System events, such as HW or DMA completion, can trigger exits from pause mode. - - An implementation is free to pause for durations shorter than (immediate+8), but not - longer. - - This instruction is useful for implementing user-level low-power synchronization - operations, such as spin locks or wait-for-event signaling. - - Syntax Behavior - pause(#u8) Pause for #u cycles; - - - Class: SYSTEM (slot 2) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Parse -0 1 0 1 0 1 0 0 0 1 - - - - - - P P - i i i i i - - - i i i - - pause(#u8) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 384 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Memory thread synchronization - Synchronizes memory. - - All outstanding memory operations, including cached and uncached loads and stores, are - completed before the processor continues to the next instruction. This ensures that certain - memory operations are performed in the desired order (for example, when accessing I/O - devices). - - After performing a syncht operation, the processor ceases fetching and executing - instructions from the program until all outstanding memory operations of that program are - completed. - - In multithreaded or multicore environments, syncht is not concerned with other execution - contexts. - - The use of this instruction is system-dependent. - - Syntax Behavior - syncht memory_synch; - - - Class: SYSTEM (slots 0) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - U - ICLASS Amode Type Parse - N -1 0 1 0 1 0 0 0 0 1 0 - - - - - P P - - - - - - - - - - - - - - syncht - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - Amode Amode - Type Type - UN Unsigned - - - - -80-N2040-36 B 385 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Send value to ETM trace - Take the value of register Rs and emit it to the ETM trace. - - The ETM block must be enabled, and the thread must have permissions to perform - tracing. The contents of Rs are user-defined. - - Syntax Behavior - trace(Rs) Send value to ETM trace; - - - Class: SYSTEM (slot 3) - - Notes - -  This instruction may only be grouped with ALU32 or non floating-point XTYPE - instructions. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS sm s5 Parse -0 1 1 0 0 0 1 0 0 1 0 s s s s s P P - - - - - - - - - - - - - - trace(Rs) - - - - - Field name Description - sm Supervisor mode only - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - - -80-N2040-36 B 386 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Trap - Cause a precise exception. - - Executing a trap instruction sets the EX bit in SSR to 1, which disables interrupts and - enables supervisor mode. The program then jumps to the vector location (either trap0 - location or trap1 location). The instruction specifies an 8-bit immediate field. This field is - copied into the system status register cause field. - - Upon returning from the service routine with an rte instruction, execution resumes at the - packet after the trap instruction. - - These instructions are generally intended for user code to request services from the - operating system. Two trap instructions are provided so the OS can optimize for fast - service routines and slower service routines. - - Syntax Behavior - trap0(#u8) SSR.CAUSE = #u; - TRAP "0"; - trap1(#u8) SSR.CAUSE = #u; - TRAP "1"; - - - Class: SYSTEM (slot 2) - - Notes - -  This is a solo instruction. It must not be grouped with other instructions in a - packet. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS Parse -0 1 0 1 0 1 0 0 0 0 - - - - - - P P - i i i i i - - - i i i - - trap0(#u8) -0 1 0 1 0 1 0 0 1 0 - - - - - - P P - i i i i i - - - i i i - - trap1(#u8) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 387 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.10 XTYPE - The XTYPE instruction class includes instructions which perform most of the data - processing done by the Hexagon processor. - - XTYPE instructions are executable on slot 2 or slot 3. - - - 11.10.1 XTYPE/ALU - The XTYPE/ALU instruction subclass includes instructions which perform arithmetic and - logical operations. - -Absolute value doubleword - Take the absolute value of the 64-bit source register and place it in the destination register. - - Syntax Behavior - Rdd=abs(Rss) Rdd = ABS(Rss); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=abs(Rss) Word64 Q6_P_abs_P(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 1 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rdd=abs(Rss) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 388 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Absolute value word - Take the absolute value of the source register and place it in the destination register. - - The 32-bit absolute value is available with optional saturation. The single case of - saturation is if the source register is equal to 0x8000_0000, the destination saturates to - 0x7fff_ffff. - - Syntax Behavior - Rd=abs(Rs)[:sat] Rd = [sat32](ABS(sxt32->64(Rs))); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=abs(Rs) Word32 Q6_R_abs_R(Word32 Rs) - Rd=abs(Rs):sat Word32 Q6_R_abs_R_sat(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rd=abs(Rs) -1 0 0 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - 1 0 1 d d d d d Rd=abs(Rs):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 389 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Add and accumulate - Add Rs and Rt or a signed immediate, then add or subtract the resulting value. The result - is saved in Rx. - - Syntax Behavior - Rd=add(Rs,add(Ru,#s6)) Rd = Rs + Ru + apply_extension(#s); - Rd=add(Rs,sub(#s6,Ru)) Rd = Rs - Ru + apply_extension(#s); - Rx+=add(Rs,#s8) apply_extension(#s); - Rx=Rx + Rs + #s; - Rx+=add(Rs,Rt) Rx=Rx + Rs + Rt; - Rx-=add(Rs,#s8) apply_extension(#s); - Rx=Rx - (Rs + #s); - Rx-=add(Rs,Rt) Rx=Rx - (Rs + Rt); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=add(Rs,add(Ru,#s6)) Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 - Ru, Word32 Is6) - Rd=add(Rs,sub(#s6,Ru)) Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 - Is6, Word32 Ru) - Rx+=add(Rs,#s8) Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, - Word32 Is8) - Rx+=add(Rs,Rt) Word32 Q6_R_addacc_RR(Word32 Rx, Word32 Rs, - Word32 Rt) - Rx-=add(Rs,#s8) Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, - Word32 Is8) - Rx-=add(Rs,Rt) Word32 Q6_R_addnac_RR(Word32 Rx, Word32 Rs, - Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse d5 u5 -1 1 0 1 1 0 1 1 0 i i s s s s s P P i d d d d d i i i u u u u u Rd=add(Rs,add(Ru,#s6)) -1 1 0 1 1 0 1 1 1 i i s s s s s P P i d d d d d i i i u u u u u Rd=add(Rs,sub(#s6,Ru)) - ICLASS RegType MajOp s5 Parse MinOp x5 -1 1 1 0 0 0 1 0 0 - - s s s s s P P 0 i i i i i i i i x x x x x Rx+=add(Rs,#s8) -1 1 1 0 0 0 1 0 1 - - s s s s s P P 0 i i i i i i i i x x x x x Rx-=add(Rs,#s8) - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x Rx+=add(Rs,Rt) -1 1 1 0 1 1 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x Rx-=add(Rs,Rt) - - - - -80-N2040-36 B 390 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - RegType Register Type - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u5 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 391 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Add doublewords - The first form of this instruction adds two 32-bit registers. If the result overflows 32 bits, - the result is saturated to 0x7FFF_FFFF for a positive result, or 0x8000_0000 for a - negative result. Note that 32-bit non-saturating register add is a ALU32-class instruction - and can be executed on any slot. - - The second instruction form sign-extends a 32-bit register Rt to 64-bits and performs a 64- - bit add with Rss. The result is stored in Rdd. - - The third instruction form adds 64-bit registers Rss and Rtt and places the result in Rdd. - - The final instruction form adds two 64-bit registers Rss and Rtt. If the result overflows 64 - bits, it is saturated to 0x7fff_ffff_ffff_ffff for a positive result, or - 0x8000_0000_0000_0000 for a negative result. - - Syntax Behavior - Rd=add(Rs,Rt):sat:deprecated Rd=sat32(Rs+Rt); - Rdd=add(Rs,Rtt) if ("Rs & 1") { - Assembler mapped to: - "Rdd=add(Rss,Rtt):raw:hi"; - } else { - Assembler mapped to: - "Rdd=add(Rss,Rtt):raw:lo"; - }; - Rdd=add(Rss,Rtt) Rdd=Rss+Rtt; - Rdd=add(Rss,Rtt):raw:hi Rdd=Rtt+sxt32->64(Rss.w[1]); - Rdd=add(Rss,Rtt):raw:lo Rdd=Rtt+sxt32->64(Rss.w[0]); - Rdd=add(Rss,Rtt):sat Rdd=sat64(Rss+Rtt); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=add(Rs,Rtt) Word64 Q6_P_add_RP(Word32 Rs, Word64 Rtt) - Rdd=add(Rss,Rtt) Word64 Q6_P_add_PP(Word64 Rss, Word64 Rtt) - Rdd=add(Rss,Rtt):sat Word64 Q6_P_add_PP_sat(Word64 Rss, Word64 - Rtt) - - - - -80-N2040-36 B 392 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 1 1 1 d d d d d Rdd=add(Rss,Rtt) -1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 1 0 1 d d d d d Rdd=add(Rss,Rtt):sat -1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 1 1 0 d d d d d Rdd=add(Rss,Rtt):raw:lo -1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 1 1 1 d d d d d Rdd=add(Rss,Rtt):raw:hi -1 1 0 1 0 1 0 1 1 0 0 s s s s s P P - t t t t t 0 - - d d d d d Rd=add(Rs,Rt):sat:deprecated - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 393 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Add halfword - Perform a 16-bit add with optional saturation, and place the result in either the upper or - lower half of a register. If the result goes in the upper half, the sources can be any high or - low halfword of Rs and Rt. The lower 16 bits of the result are zeroed. - - If the result is to be placed in the lower 16 bits of Rd, the Rs source can be either high or - low, but the other source must be the low halfword of Rt. In this case, the upper halfword - of Rd is the sign-extension of the low halfword. - - - Rd=add(Rs.[hl],Rt.[hl])[:sat] - - Rs.H Rs.L Rs Rt.H Rt.L Rt - - - Mux Mux - - - - 16-bit Add - 0x7FFF 0x8000 - - Saturate - - - - Sign-extend Result Rd - - - Syntax Behavior - Rd=add(Rt.L,Rs.[HL])[:sat] Rd=[sat16](Rt.h[0]+Rs.h[01]); - Rd=add(Rt.[HL],Rs.[HL])[:sat]:<<16 Rd=([sat16](Rt.h[01]+Rs.h[01]))<<16; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - - - -80-N2040-36 B 394 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rd=add(Rt.H,Rs.H):<<16 Word32 Q6_R_add_RhRh_s16(Word32 Rt, Word32 - Rs) - Rd=add(Rt.H,Rs.H):sat:<<16 Word32 Q6_R_add_RhRh_sat_s16(Word32 Rt, - Word32 Rs) - Rd=add(Rt.H,Rs.L):<<16 Word32 Q6_R_add_RhRl_s16(Word32 Rt, Word32 - Rs) - Rd=add(Rt.H,Rs.L):sat:<<16 Word32 Q6_R_add_RhRl_sat_s16(Word32 Rt, - Word32 Rs) - Rd=add(Rt.L,Rs.H) Word32 Q6_R_add_RlRh(Word32 Rt, Word32 Rs) - Rd=add(Rt.L,Rs.H):<<16 Word32 Q6_R_add_RlRh_s16(Word32 Rt, Word32 - Rs) - Rd=add(Rt.L,Rs.H):sat Word32 Q6_R_add_RlRh_sat(Word32 Rt, Word32 - Rs) - Rd=add(Rt.L,Rs.H):sat:<<16 Word32 Q6_R_add_RlRh_sat_s16(Word32 Rt, - Word32 Rs) - Rd=add(Rt.L,Rs.L) Word32 Q6_R_add_RlRl(Word32 Rt, Word32 Rs) - Rd=add(Rt.L,Rs.L):<<16 Word32 Q6_R_add_RlRl_s16(Word32 Rt, Word32 - Rs) - Rd=add(Rt.L,Rs.L):sat Word32 Q6_R_add_RlRl_sat(Word32 Rt, Word32 - Rs) - Rd=add(Rt.L,Rs.L):sat:<<16 Word32 Q6_R_add_RlRl_sat_s16(Word32 Rt, - Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 1 0 1 0 0 0 s s s s s P P - t t t t t 0 0 - d d d d d Rd=add(Rt.L,Rs.L) -1 1 0 1 0 1 0 1 0 0 0 s s s s s P P - t t t t t 0 1 - d d d d d Rd=add(Rt.L,Rs.H) -1 1 0 1 0 1 0 1 0 0 0 s s s s s P P - t t t t t 1 0 - d d d d d Rd=add(Rt.L,Rs.L):sat -1 1 0 1 0 1 0 1 0 0 0 s s s s s P P - t t t t t 1 1 - d d d d d Rd=add(Rt.L,Rs.H):sat -1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 0 0 0 d d d d d Rd=add(Rt.L,Rs.L):<<16 -1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 0 0 1 d d d d d Rd=add(Rt.L,Rs.H):<<16 -1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 0 1 0 d d d d d Rd=add(Rt.H,Rs.L):<<16 -1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 0 1 1 d d d d d Rd=add(Rt.H,Rs.H):<<16 -1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 1 0 0 d d d d d Rd=add(Rt.L,Rs.L):sat:<<16 -1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 1 0 1 d d d d d Rd=add(Rt.L,Rs.H):sat:<<16 -1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 1 1 0 d d d d d Rd=add(Rt.H,Rs.L):sat:<<16 -1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 1 1 1 d d d d d Rd=add(Rt.H,Rs.H):sat:<<16 - - - -80-N2040-36 B 395 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 396 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Add or subtract doublewords with carry - Add or subtract with carry. Predicate register Px is used as an extra input and output. - - For adds, the LSB of the predicate is added to the sum of the two input pairs. - - For subtracts, the predicate is considered a not-borrow. The LSB of the predicate is added - to the first source register and the logical complement of the second argument. - - The carry-out from the sum is saved in predicate Px. - - These instructions allow efficient addition or subtraction of numbers larger than 64 bits. - - Syntax Behavior - Rdd=add(Rss,Rtt,Px):carry Rdd = Rss + Rtt + Px[0]; - Px = carry_from_add(Rss,Rtt,Px[0]) ? 0xff : - 0x00; - Rdd=sub(Rss,Rtt,Px):carry Rdd = Rss + ~Rtt + Px[0]; - Px = carry_from_add(Rss,~Rtt,Px[0]) ? 0xff - : 0x00; - - - Class: XTYPE (slots 2,3) - - Notes - -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 x2 d5 -1 1 0 0 0 0 1 0 1 1 0 s s s s s P P - t t t t t - x x d d d d d Rdd=add(Rss,Rtt,Px):carry -1 1 0 0 0 0 1 0 1 1 1 s s s s s P P - t t t t t - x x d d d d d Rdd=sub(Rss,Rtt,Px):carry - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - x2 Field to encode register x - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 397 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Logical doublewords - Perform bitwise logical AND, OR, XOR, and NOT operations. - - The source and destination registers are 64-bit. - - For 32-bit logical operations, see the ALU32 logical instructions. - - Syntax Behavior - Rdd=and(Rss,Rtt) Rdd=Rss&Rtt; - Rdd=and(Rtt,~Rss) Rdd = (Rtt & ~Rss); - Rdd=not(Rss) Rdd=~Rss; - Rdd=or(Rss,Rtt) Rdd=Rss|Rtt; - Rdd=or(Rtt,~Rss) Rdd = (Rtt | ~Rss); - Rdd=xor(Rss,Rtt) Rdd=Rss^Rtt; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=and(Rss,Rtt) Word64 Q6_P_and_PP(Word64 Rss, Word64 Rtt) - Rdd=and(Rtt,~Rss) Word64 Q6_P_and_PnP(Word64 Rtt, Word64 Rss) - Rdd=not(Rss) Word64 Q6_P_not_P(Word64 Rss) - Rdd=or(Rss,Rtt) Word64 Q6_P_or_PP(Word64 Rss, Word64 Rtt) - Rdd=or(Rtt,~Rss) Word64 Q6_P_or_PnP(Word64 Rtt, Word64 Rss) - Rdd=xor(Rss,Rtt) Word64 Q6_P_xor_PP(Word64 Rss, Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 1 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rdd=not(Rss) - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=and(Rss,Rtt) -1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 0 1 d d d d d Rdd=and(Rtt,~Rss) -1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=or(Rss,Rtt) -1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 1 1 d d d d d Rdd=or(Rtt,~Rss) -1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 1 0 0 d d d d d Rdd=xor(Rss,Rtt) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - -80-N2040-36 B 398 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 399 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Logical-logical doublewords - Perform a logical operation of the two source operands, then perform a second logical - operation of the result with the destination register Rxx. - - The source and destination registers are 64-bit. - - Syntax Behavior - Rxx^=xor(Rss,Rtt) Rxx^=Rss^Rtt; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rxx^=xor(Rss,Rtt) Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 - Rss, Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min x5 -1 1 0 0 1 0 1 0 1 0 - s s s s s P P 0 t t t t t 0 0 0 x x x x x Rxx^=xor(Rss,Rtt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 400 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Logical-logical words - Perform a logical operation of the two source operands, then perform a second logical - operation of the result with the destination register Rx. - - The source and destination registers are 32-bit. - - Syntax Behavior - Rx=or(Ru,and(Rx,#s10)) Rx = Ru | (Rx & apply_extension(#s)); - Rx[&|^]=and(Rs,Rt) Rx [|&^]= (Rs [|&^] Rt); - Rx[&|^]=and(Rs,~Rt) Rx [|&^]= (Rs [|&^] ~Rt); - Rx[&|^]=or(Rs,Rt) Rx [|&^]= (Rs [|&^] Rt); - Rx[&|^]=xor(Rs,Rt) Rx[|&^]=Rs[|&^]Rt; - Rx|=and(Rs,#s10) Rx = Rx | (Rs & apply_extension(#s)); - Rx|=or(Rs,#s10) Rx = Rx | (Rs | apply_extension(#s)); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rx&=and(Rs,Rt) Word32 Q6_R_andand_RR(Word32 Rx, Word32 Rs, - Word32 Rt) - Rx&=and(Rs,~Rt) Word32 Q6_R_andand_RnR(Word32 Rx, Word32 - Rs, Word32 Rt) - Rx&=or(Rs,Rt) Word32 Q6_R_orand_RR(Word32 Rx, Word32 Rs, - Word32 Rt) - Rx&=xor(Rs,Rt) Word32 Q6_R_xorand_RR(Word32 Rx, Word32 Rs, - Word32 Rt) - Rx=or(Ru,and(Rx,#s10)) Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 - Rx, Word32 Is10) - Rx^=and(Rs,Rt) Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 - Rs, Word32 Rt) - Rx^=and(Rs,~Rt) Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 - Rs, Word32 Rt) - Rx^=or(Rs,Rt) Word32 Q6_R_orxacc_RR(Word32 Rx, Word32 Rs, - Word32 Rt) - Rx^=xor(Rs,Rt) Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 - Rs, Word32 Rt) - Rx|=and(Rs,#s10) Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, - Word32 Is10) - - - - -80-N2040-36 B 401 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Rx|=and(Rs,Rt) Word32 Q6_R_andor_RR(Word32 Rx, Word32 Rs, - Word32 Rt) - Rx|=and(Rs,~Rt) Word32 Q6_R_andor_RnR(Word32 Rx, Word32 Rs, - Word32 Rt) - Rx|=or(Rs,#s10) Word32 Q6_R_oror_RI(Word32 Rx, Word32 Rs, - Word32 Is10) - Rx|=or(Rs,Rt) Word32 Q6_R_oror_RR(Word32 Rx, Word32 Rs, - Word32 Rt) - Rx|=xor(Rs,Rt) Word32 Q6_R_xoror_RR(Word32 Rx, Word32 Rs, - Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse x5 -1 1 0 1 1 0 1 0 0 0 i s s s s s P P i i i i i i i i i x x x x x Rx|=and(Rs,#s10) - ICLASS RegType x5 Parse u5 -1 1 0 1 1 0 1 0 0 1 i x x x x x P P i i i i i i i i i u u u u u Rx=or(Ru,and(Rx,#s10)) - ICLASS RegType s5 Parse x5 -1 1 0 1 1 0 1 0 1 0 i s s s s s P P i i i i i i i i i x x x x x Rx|=or(Rs,#s10) - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 1 1 1 1 0 0 1 s s s s s P P 0 t t t t t 0 0 0 x x x x x Rx|=and(Rs,~Rt) -1 1 1 0 1 1 1 1 0 0 1 s s s s s P P 0 t t t t t 0 0 1 x x x x x Rx&=and(Rs,~Rt) -1 1 1 0 1 1 1 1 0 0 1 s s s s s P P 0 t t t t t 0 1 0 x x x x x Rx^=and(Rs,~Rt) -1 1 1 0 1 1 1 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x Rx&=and(Rs,Rt) -1 1 1 0 1 1 1 1 0 1 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x Rx&=or(Rs,Rt) -1 1 1 0 1 1 1 1 0 1 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x Rx&=xor(Rs,Rt) -1 1 1 0 1 1 1 1 0 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x Rx|=and(Rs,Rt) -1 1 1 0 1 1 1 1 1 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x Rx^=xor(Rs,Rt) -1 1 1 0 1 1 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x Rx|=or(Rs,Rt) -1 1 1 0 1 1 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x Rx|=xor(Rs,Rt) -1 1 1 0 1 1 1 1 1 1 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x Rx^=and(Rs,Rt) -1 1 1 0 1 1 1 1 1 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x Rx^=or(Rs,Rt) - - - - - Field name Description - RegType Register Type - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - u5 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 402 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Maximum words - Select either the signed or unsigned maximum of two source registers and place in a - destination register Rdd. - - Syntax Behavior - Rd=max(Rs,Rt) Rd = max(Rs,Rt); - Rd=maxu(Rs,Rt) Rd = max(Rs.uw[0],Rt.uw[0]); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=max(Rs,Rt) Word32 Q6_R_max_RR(Word32 Rs, Word32 Rt) - Rd=maxu(Rs,Rt) UWord32 Q6_R_maxu_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 1 0 1 1 1 0 s s s s s P P - t t t t t 0 - - d d d d d Rd=max(Rs,Rt) -1 1 0 1 0 1 0 1 1 1 0 s s s s s P P - t t t t t 1 - - d d d d d Rd=maxu(Rs,Rt) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 403 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Maximum doublewords - Select either the signed or unsigned maximum of two 64-bit source registers and place in a - destination register. - - Syntax Behavior - Rdd=max(Rss,Rtt) Rdd = max(Rss,Rtt); - Rdd=maxu(Rss,Rtt) Rdd = max(Rss.u64,Rtt.u64); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=max(Rss,Rtt) Word64 Q6_P_max_PP(Word64 Rss, Word64 Rtt) - Rdd=maxu(Rss,Rtt) UWord64 Q6_P_maxu_PP(Word64 Rss, Word64 - Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 1 0 0 d d d d d Rdd=max(Rss,Rtt) -1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 1 0 1 d d d d d Rdd=maxu(Rss,Rtt) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 404 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Minimum words - Select either the signed or unsigned minimum of two source registers and place in - destination register Rd. - - Syntax Behavior - Rd=min(Rt,Rs) Rd = min(Rt,Rs); - Rd=minu(Rt,Rs) Rd = min(Rt.uw[0],Rs.uw[0]); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=min(Rt,Rs) Word32 Q6_R_min_RR(Word32 Rt, Word32 Rs) - Rd=minu(Rt,Rs) UWord32 Q6_R_minu_RR(Word32 Rt, Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 1 0 1 1 0 1 s s s s s P P - t t t t t 0 - - d d d d d Rd=min(Rt,Rs) -1 1 0 1 0 1 0 1 1 0 1 s s s s s P P - t t t t t 1 - - d d d d d Rd=minu(Rt,Rs) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 405 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Minimum doublewords - Select either the signed or unsigned minimum of two 64-bit source registers and place in - the destination register Rdd. - - Syntax Behavior - Rdd=min(Rtt,Rss) Rdd = min(Rtt,Rss); - Rdd=minu(Rtt,Rss) Rdd = min(Rtt.u64,Rss.u64); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=min(Rtt,Rss) Word64 Q6_P_min_PP(Word64 Rtt, Word64 Rss) - Rdd=minu(Rtt,Rss) UWord64 Q6_P_minu_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 1 1 0 d d d d d Rdd=min(Rtt,Rss) -1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 1 1 1 d d d d d Rdd=minu(Rtt,Rss) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 406 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Modulo wrap - Wrap the Rs value into the modulo range from 0 to Rt. - - If Rs is greater than or equal to Rt, wrap it to the bottom of the range by subtracting Rt. - - If Rs is less than zero, wrap it to the top of the range by adding Rt. - - Otherwise, when Rs fits within the range, no adjustment is necessary. The result is - returned in register Rd. - - Syntax Behavior - Rd=modwrap(Rs,Rt) if (Rs < 0) { - Rd = Rs + Rt.uw[0]; - } else if (Rs.uw[0] >= Rt.uw[0]) { - Rd = Rs - Rt.uw[0]; - } else { - Rd = Rs; - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=modwrap(Rs,Rt) Word32 Q6_R_modwrap_RR(Word32 Rs, Word32 - Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 1 1 1 d d d d d Rd=modwrap(Rs,Rt) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 407 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Negate - The first form of this instruction performs a negate on a 32-bit register with saturation. If - the input is 0x80000000, the result is saturated to 0x7fffffff. Note that the non-saturating - 32-bit register negate is a ALU32-class instruction and can be executed on any slot. - - The second form of this instruction negates a 64-bit source register and place the result in - destination Rdd. - - Syntax Behavior - Rd=neg(Rs):sat Rd = sat32(-Rs.s64); - Rdd=neg(Rss) Rdd = -Rss; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=neg(Rs):sat Word32 Q6_R_neg_R_sat(Word32 Rs) - Rdd=neg(Rss) Word64 Q6_P_neg_P(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 1 0 0 s s s s s P P - - - - - - 1 0 1 d d d d d Rdd=neg(Rss) -1 0 0 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rd=neg(Rs):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 408 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Round - Perform either arithmetic (.5 is rounded up) or convergent (.5 is rounded towards even) - rounding to any bit location. - - Arithmetic rounding has optional saturation. In this version, the result is saturated to a 32- - bit number after adding the rounding constant. After the rounding and saturation have - been performed, the final result is right shifted using a sign-extending shift. - - Syntax Behavior - Rd=cround(Rs,#u5) Rd = (#u==0)?Rs:convround(Rs,2**(#u- - 1))>>#u; - Rd=cround(Rs,Rt) Rd = (zxt5- - >32(Rt)==0)?Rs:convround(Rs,2**(zxt5- - >32(Rt)-1))>>zxt5->32(Rt); - - Rd=round(Rs,#u5)[:sat] Rd = ([sat32]((#u==0)?(Rs):round(Rs,2**(#u- - 1))))>>#u; - Rd=round(Rs,Rt)[:sat] Rd = ([sat32]((zxt5- - >32(Rt)==0)?(Rs):round(Rs,2**(zxt5->32(Rt)- - 1))))>>zxt5->32(Rt); - Rd=round(Rss):sat tmp=sat64(Rss+0x080000000ULL); - Rd = tmp.w[1]; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=cround(Rs,#u5) Word32 Q6_R_cround_RI(Word32 Rs, Word32 - Iu5) - Rd=cround(Rs,Rt) Word32 Q6_R_cround_RR(Word32 Rs, Word32 Rt) - Rd=round(Rs,#u5) Word32 Q6_R_round_RI(Word32 Rs, Word32 Iu5) - Rd=round(Rs,#u5):sat Word32 Q6_R_round_RI_sat(Word32 Rs, Word32 - Iu5) - Rd=round(Rs,Rt) Word32 Q6_R_round_RR(Word32 Rs, Word32 Rt) - Rd=round(Rs,Rt):sat Word32 Q6_R_round_RR_sat(Word32 Rs, Word32 - Rt) - Rd=round(Rss):sat Word32 Q6_R_round_P_sat(Word64 Rss) - - - - -80-N2040-36 B 409 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 1 1 0 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=round(Rss):sat -1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 0 0 - d d d d d Rd=cround(Rs,#u5) -1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 0 - d d d d d Rd=round(Rs,#u5) -1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 1 - d d d d d Rd=round(Rs,#u5):sat - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 1 1 0 1 1 - s s s s s P P - t t t t t 0 0 - d d d d d Rd=cround(Rs,Rt) -1 1 0 0 0 1 1 0 1 1 - s s s s s P P - t t t t t 1 0 - d d d d d Rd=round(Rs,Rt) -1 1 0 0 0 1 1 0 1 1 - s s s s s P P - t t t t t 1 1 - d d d d d Rd=round(Rs,Rt):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - MajOp Major Opcode - MinOp Minor Opcode - Maj Major Opcode - Min Minor Opcode - RegType Register Type - RegType Register Type - - - - -80-N2040-36 B 410 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Subtract doublewords - Subtract the 64-bit register Rss from register Rtt. - - Syntax Behavior - Rd=sub(Rt,Rs):sat:deprecated Rd=sat32(Rt - Rs); - Rdd=sub(Rtt,Rss) Rdd=Rtt-Rss; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=sub(Rtt,Rss) Word64 Q6_P_sub_PP(Word64 Rtt, Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 1 1 1 d d d d d Rdd=sub(Rtt,Rss) - -1 1 0 1 0 1 0 1 1 0 0 s s s s s P P - t t t t t 1 - - d d d d d Rd=sub(Rt,Rs):sat:deprecated - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 411 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Subtract and accumulate words - Subtract Rs from Rt, then add the resulting value with Rx. The result is saved in Rx. - - Syntax Behavior - Rx+=sub(Rt,Rs) Rx=Rx + Rt - Rs; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rx+=sub(Rt,Rs) Word32 Q6_R_subacc_RR(Word32 Rx, Word32 Rt, - Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x Rx+=sub(Rt,Rs) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - - - - -80-N2040-36 B 412 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Subtract halfword - Perform a 16-bit subtract with optional saturation and place the result in either the upper or - lower half of a register. If the result goes in the upper half, then the sources can be any - high or low halfword of Rs and Rt. The lower 16 bits of the result are zeroed. - - If the result is to be placed in the lower 16 bits of Rd, then the Rs source can be either high - or low, but the other source must be the low halfword of Rt. In this case, the upper - halfword of Rd is the sign-extension of the low halfword. - - - Rd=sub(Rt.[hl],Rs.l)[:sat] Rd=sub(Rt.[hl],Rs.[hl])[:sat]:<<16 - - Rt.H Rt.L Rt Rt.H Rt.L Rt - - - Mux Rs Mux Rs - - Rs.H Rs.L Rs.H Rs.L - - - Mux - - - - 16-bit Sub 16-bit Sub - 0x7FFF 0x8000 0x7FFF 0x8000 - - Saturate Saturate - - - - Sign-extend Result Rd Result 0x0000 Rd - - - Syntax Behavior - Rd=sub(Rt.L,Rs.[HL])[:sat] Rd=[sat16](Rt.h[0]-Rs.h[01]); - Rd=sub(Rt.[HL],Rs.[HL])[:sat]:<<16 Rd=([sat16](Rt.h[01]-Rs.h[01]))<<16; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - - - -80-N2040-36 B 413 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rd=sub(Rt.H,Rs.H):<<16 Word32 Q6_R_sub_RhRh_s16(Word32 Rt, Word32 - Rs) - Rd=sub(Rt.H,Rs.H):sat:<<16 Word32 Q6_R_sub_RhRh_sat_s16(Word32 Rt, - Word32 Rs) - Rd=sub(Rt.H,Rs.L):<<16 Word32 Q6_R_sub_RhRl_s16(Word32 Rt, Word32 - Rs) - Rd=sub(Rt.H,Rs.L):sat:<<16 Word32 Q6_R_sub_RhRl_sat_s16(Word32 Rt, - Word32 Rs) - Rd=sub(Rt.L,Rs.H) Word32 Q6_R_sub_RlRh(Word32 Rt, Word32 Rs) - Rd=sub(Rt.L,Rs.H):<<16 Word32 Q6_R_sub_RlRh_s16(Word32 Rt, Word32 - Rs) - Rd=sub(Rt.L,Rs.H):sat Word32 Q6_R_sub_RlRh_sat(Word32 Rt, Word32 - Rs) - Rd=sub(Rt.L,Rs.H):sat:<<16 Word32 Q6_R_sub_RlRh_sat_s16(Word32 Rt, - Word32 Rs) - Rd=sub(Rt.L,Rs.L) Word32 Q6_R_sub_RlRl(Word32 Rt, Word32 Rs) - Rd=sub(Rt.L,Rs.L):<<16 Word32 Q6_R_sub_RlRl_s16(Word32 Rt, Word32 - Rs) - Rd=sub(Rt.L,Rs.L):sat Word32 Q6_R_sub_RlRl_sat(Word32 Rt, Word32 - Rs) - Rd=sub(Rt.L,Rs.L):sat:<<16 Word32 Q6_R_sub_RlRl_sat_s16(Word32 Rt, - Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 1 0 1 0 0 1 s s s s s P P - t t t t t 0 0 - d d d d d Rd=sub(Rt.L,Rs.L) -1 1 0 1 0 1 0 1 0 0 1 s s s s s P P - t t t t t 0 1 - d d d d d Rd=sub(Rt.L,Rs.H) -1 1 0 1 0 1 0 1 0 0 1 s s s s s P P - t t t t t 1 0 - d d d d d Rd=sub(Rt.L,Rs.L):sat -1 1 0 1 0 1 0 1 0 0 1 s s s s s P P - t t t t t 1 1 - d d d d d Rd=sub(Rt.L,Rs.H):sat -1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 0 0 0 d d d d d Rd=sub(Rt.L,Rs.L):<<16 -1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 0 0 1 d d d d d Rd=sub(Rt.L,Rs.H):<<16 -1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 0 1 0 d d d d d Rd=sub(Rt.H,Rs.L):<<16 -1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 0 1 1 d d d d d Rd=sub(Rt.H,Rs.H):<<16 -1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 1 0 0 d d d d d Rd=sub(Rt.L,Rs.L):sat:<<16 -1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 1 0 1 d d d d d Rd=sub(Rt.L,Rs.H):sat:<<16 -1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 1 1 0 d d d d d Rd=sub(Rt.H,Rs.L):sat:<<16 -1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 1 1 1 d d d d d Rd=sub(Rt.H,Rs.H):sat:<<16 - - - -80-N2040-36 B 414 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 415 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Sign extend word to doubleword - Sign-extend a 32-bit word to a 64-bit doubleword. - - Syntax Behavior - Rdd=sxtw(Rs) Rdd = sxt32->64(Rs); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=sxtw(Rs) Word64 Q6_P_sxtw_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 1 0 0 0 1 - s s s s s P P - - - - - - 0 0 - d d d d d Rdd=sxtw(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 416 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector absolute value halfwords - Take the absolute value of each of the four halfwords in the 64-bit source vector Rss. Place - the result in Rdd. - - Saturation is optionally available. - - Syntax Behavior - Rdd=vabsh(Rss) for (i=0;i<4;i++) { - Rdd.h[i]=ABS(Rss.h[i]); - }; - Rdd=vabsh(Rss):sat for (i=0;i<4;i++) { - Rdd.h[i]=sat16(ABS(Rss.h[i])); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vabsh(Rss) Word64 Q6_P_vabsh_P(Word64 Rss) - Rdd=vabsh(Rss):sat Word64 Q6_P_vabsh_P_sat(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rdd=vabsh(Rss) -1 0 0 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - 1 0 1 d d d d d Rdd=vabsh(Rss):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 417 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector absolute value words - Take the absolute value of each of the two words in the 64-bit source vector Rss. Place the - result in Rdd. - - Saturation is optionally available. - - Syntax Behavior - Rdd=vabsw(Rss) for (i=0;i<2;i++) { - Rdd.w[i]=ABS(Rss.w[i]); - }; - Rdd=vabsw(Rss):sat for (i=0;i<2;i++) { - Rdd.w[i]=sat32(ABS(Rss.w[i])); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vabsw(Rss) Word64 Q6_P_vabsw_P(Word64 Rss) - Rdd=vabsw(Rss):sat Word64 Q6_P_vabsw_P_sat(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rdd=vabsw(Rss) -1 0 0 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - 1 1 1 d d d d d Rdd=vabsw(Rss):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 418 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector absolute difference bytes - For each element in the source vector Rss, subtract the corresponding element in source - vector Rtt. Take the absolute value of the results, and store into Rdd. - - Syntax Behavior - Rdd=vabsdiffb(Rtt,Rss) for (i=0;i<8;i++) { - Rdd.b[i]=ABS(Rtt.b[i] - Rss.b[i]); - }; - Rdd=vabsdiffub(Rtt,Rss) for (i=0;i<8;i++) { - Rdd.b[i]=ABS(Rtt.ub[i] - Rss.ub[i]); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vabsdiffb(Rtt,Rss) Word64 Q6_P_vabsdiffb_PP(Word64 Rtt, Word64 - Rss) - Rdd=vabsdiffub(Rtt,Rss) Word64 Q6_P_vabsdiffub_PP(Word64 Rtt, - Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rdd=vabsdiffub(Rtt,Rss) -1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rdd=vabsdiffb(Rtt,Rss) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 419 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector absolute difference halfwords - For each element in the source vector Rss, subtract the corresponding element in source - vector Rtt. Take the absolute value of the results, and store into Rdd. - - Syntax Behavior - Rdd=vabsdiffh(Rtt,Rss) for (i=0;i<4;i++) { - Rdd.h[i]=ABS(Rtt.h[i] - Rss.h[i]); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vabsdiffh(Rtt,Rss) Word64 Q6_P_vabsdiffh_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 0 0 0 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rdd=vabsdiffh(Rtt,Rss) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 420 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector absolute difference words - For each element in the source vector Rss, subtract the corresponding element in source - vector Rtt. Take the absolute value of the results, and store into Rdd. - - Syntax Behavior - Rdd=vabsdiffw(Rtt,Rss) for (i=0;i<2;i++) { - Rdd.w[i]=ABS(Rtt.w[i] - Rss.w[i]); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vabsdiffw(Rtt,Rss) Word64 Q6_P_vabsdiffw_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 0 0 0 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rdd=vabsdiffw(Rtt,Rss) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 421 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector add compare and select maximum bytes - Add each byte element in Rxx and Rtt, and compare the resulting sums with the - corresponding differences between Rss and Rtt. Store the maximum value of each - compare in Rxx, and set the corresponding bits in a predicate destination to '1' if the - compare result is greater, '0' if not. Each sum and difference is saturated to 8 bits before - the compare, and the compare operation is a signed byte compare. - - - Rxx.H3 Rxx.H2 Rxx.H1 Rxx.H0 Rxx - - Rss.H3 Rss.H2 Rss.H1 Rss.H0 Rss - - Rtt.H3 Rtt.H2 Rtt.H1 Rtt.H0 Rtt - - - + - + - + - + - - Rxx,Pd=vacsh(Rss,Rtt) - sat16 sat16 sat16 sat16 sat16 sat16 sat16 sat16 - - - - - > - > - - > - 1 0 - > 1bit - - 16bits 1 0 - - - 1 0 - - - - 1 0 - - - - - Rxx.H3 Rxx.H2 Rxx.H1 Rxx.H0 Pd - - - - -80-N2040-36 B 422 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector add compare and select maximum halfwords - Add each halfword element in Rxx and Rtt, and compare the resulting sums with the - corresponding differences between Rss and Rtt. Store the maximum value of each - compare in Rxx, and set the corresponding bits in a predicate destination to '11' if the - compare result is greater, '00' if not. Each sum and difference is saturated to 16 bits before - the compare, and the compare operation is a signed halfword compare. - - - Rxx.H3 Rxx.H2 Rxx.H1 Rxx.H0 Rxx - - Rss.H3 Rss.H2 Rss.H1 Rss.H0 Rss - - Rtt.H3 Rtt.H2 Rtt.H1 Rtt.H0 Rtt - - - + - + - + - + - - Rxx,Pd=vacsh(Rss,Rtt) - sat16 sat16 sat16 sat16 sat16 sat16 sat16 sat16 - - - - - > - > - - > - 1 0 - > 1bit - - 16bits 1 0 - - - 1 0 - - - - 1 0 - - - - - Rxx.H3 Rxx.H2 Rxx.H1 Rxx.H0 Pd - - - Syntax Behavior - Rxx,Pe=vacsh(Rss,Rtt) for (i = 0; i < 4; i++) { - xv = (int) Rxx.h[i]; - sv = (int) Rss.h[i]; - tv = (int) Rtt.h[i]; - xv = xv + tv; - sv = sv - tv; - Pe.i*2 = (xv > sv); - Pe.i*2+1 = (xv > sv); - Rxx.h[i]=sat16(max(xv,sv)); - }; - - - - -80-N2040-36 B 423 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Notes - -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 e2 x5 -1 1 1 0 1 0 1 0 1 0 1 s s s s s P P 0 t t t t t 0 e e x x x x x Rxx,Pe=vacsh(Rss,Rtt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - e2 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - - - - -80-N2040-36 B 424 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector add halfwords - Add each of the four halfwords in 64-bit vector Rss to the corresponding halfword in - vector Rtt. - - Optionally saturate each 16-bit addition to either a signed or unsigned 16-bit value. - Applying saturation to the vaddh instruction clamps the result to the signed range 0x8000 - to 0x7fff, whereas applying saturation to the vadduh instruction ensures that the unsigned - result falls within the range 0 to 0xffff. When saturation is not needed, the vaddh form - should be used. - - For the 32-bit version of this vector operation, see the ALU32 instructions. - - Syntax Behavior - Rdd=vaddh(Rss,Rtt)[:sat] for (i=0;i<4;i++) { - Rdd.h[i]=[sat16](Rss.h[i]+Rtt.h[i]); - }; - Rdd=vadduh(Rss,Rtt):sat for (i=0;i<4;i++) { - Rdd.h[i]=usat16(Rss.uh[i]+Rtt.uh[i]); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vaddh(Rss,Rtt) Word64 Q6_P_vaddh_PP(Word64 Rss, Word64 - Rtt) - Rdd=vaddh(Rss,Rtt):sat Word64 Q6_P_vaddh_PP_sat(Word64 Rss, Word64 - Rtt) - Rdd=vadduh(Rss,Rtt):sat Word64 Q6_P_vadduh_PP_sat(Word64 Rss, - Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=vaddh(Rss,Rtt) -1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 0 1 1 d d d d d Rdd=vaddh(Rss,Rtt):sat -1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 1 0 0 d d d d d Rdd=vadduh(Rss,Rtt):sat - - - - -80-N2040-36 B 425 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 426 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector add halfwords with saturate and pack to unsigned -bytes - Add the four 16-bit halfwords of Rss to the four 16-bit halfwords of Rtt. The results are - saturated to unsigned 8-bits and packed in destination register Rd. - - Syntax Behavior - Rd=vaddhub(Rss,Rtt):sat for (i=0;i<4;i++) { - Rd.b[i]=usat8(Rss.h[i]+Rtt.h[i]); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=vaddhub(Rss,Rtt):sat Word32 Q6_R_vaddhub_PP_sat(Word64 Rss, - Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 0 0 1 d d d d d Rd=vaddhub(Rss,Rtt):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 427 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector reduce add unsigned bytes - For each byte in the source vector Rss, add the corresponding byte in the source vector Rtt. - Add the four upper intermediate results and optionally the upper word of the destination. - Add the four lower results and optionally the lower word of the destination. - - - Rss - - - Rtt - - - + + + + + + + + - - - - - 32bit Add 32bit Add - - Rdd - - - - - Syntax Behavior - Rdd=vraddub(Rss,Rtt) Rdd = 0; - for (i=0;i<4;i++) { - Rdd.w[0]=(Rdd.w[0] + - (Rss.ub[i]+Rtt.ub[i])); - }; - for (i=4;i<8;i++) { - Rdd.w[1]=(Rdd.w[1] + - (Rss.ub[i]+Rtt.ub[i])); - }; - Rxx+=vraddub(Rss,Rtt) for (i = 0; i < 4; i++) { - Rxx.w[0]=(Rxx.w[0] + - (Rss.ub[i]+Rtt.ub[i])); - }; - for (i = 4; i < 8; i++) { - Rxx.w[1]=(Rxx.w[1] + - (Rss.ub[i]+Rtt.ub[i])); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vraddub(Rss,Rtt) Word64 Q6_P_vraddub_PP(Word64 Rss, Word64 - Rtt) - Rxx+=vraddub(Rss,Rtt) Word64 Q6_P_vraddubacc_PP(Word64 Rxx, - Word64 Rss, Word64 Rtt) - - - - -80-N2040-36 B 428 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d Rdd=vraddub(Rss,Rtt) - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x Rxx+=vraddub(Rss,Rtt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - - - - -80-N2040-36 B 429 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector reduce add unsigned halfwords - For each halfword in the source vector Rss, add the corresponding halfword in the source - vector Rtt. Add these intermediate results together, and place the result in Rd. - - - Rss - - - Rtt - - - - - + + + + - - - + - - - Rd - - - Syntax Behavior - Rd=vraddh(Rss,Rtt) Rd = 0; - for (i=0;i<4;i++) { - Rd += (Rss.h[i]+Rtt.h[i]); - }; - Rd=vradduh(Rss,Rtt) Rd = 0; - for (i=0;i<4;i++) { - Rd += (Rss.uh[i]+Rtt.uh[i]); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=vraddh(Rss,Rtt) Word32 Q6_R_vraddh_PP(Word64 Rss, Word64 - Rtt) - Rd=vradduh(Rss,Rtt) Word32 Q6_R_vradduh_PP(Word64 Rss, Word64 - Rtt) - - - - -80-N2040-36 B 430 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 0 1 0 - - s s s s s P P 0 t t t t t - 0 1 d d d d d Rd=vradduh(Rss,Rtt) -1 1 1 0 1 0 0 1 0 - 1 s s s s s P P 0 t t t t t 1 1 1 d d d d d Rd=vraddh(Rss,Rtt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 431 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector add bytes - Add each of the eight bytes in 64-bit vector Rss to the corresponding byte in vector Rtt. - Optionally, saturate each 8-bit addition to an unsigned value between 0 and 255. The eight - results are stored in destination register Rdd. - - Syntax Behavior - Rdd=vaddb(Rss,Rtt) Assembler mapped to: "Rdd=vaddub(Rss,Rtt)" - Rdd=vaddub(Rss,Rtt)[:sat] for (i = 0; i < 8; i++) { - Rdd.b[i]=[usat8](Rss.ub[i]+Rtt.ub[i]); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vaddb(Rss,Rtt) Word64 Q6_P_vaddb_PP(Word64 Rss, Word64 - Rtt) - Rdd=vaddub(Rss,Rtt) Word64 Q6_P_vaddub_PP(Word64 Rss, Word64 - Rtt) - Rdd=vaddub(Rss,Rtt):sat Word64 Q6_P_vaddub_PP_sat(Word64 Rss, - Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=vaddub(Rss,Rtt) -1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 0 0 1 d d d d d Rdd=vaddub(Rss,Rtt):sat - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 432 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector add words - Add each of the two words in 64-bit vector Rss to the corresponding word in vector Rtt. - Optionally, saturate each 32-bit addition to a signed value between 0x80000000 and - 0x7fffffff. The two word results are stored in destination register Rdd. - - Syntax Behavior - Rdd=vaddw(Rss,Rtt)[:sat] for (i=0;i<2;i++) { - Rdd.w[i]=[sat32](Rss.w[i]+Rtt.w[i]); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vaddw(Rss,Rtt) Word64 Q6_P_vaddw_PP(Word64 Rss, Word64 - Rtt) - Rdd=vaddw(Rss,Rtt):sat Word64 Q6_P_vaddw_PP_sat(Word64 Rss, Word64 - Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 1 0 1 d d d d d Rdd=vaddw(Rss,Rtt) -1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 1 1 0 d d d d d Rdd=vaddw(Rss,Rtt):sat - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 433 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector average halfwords - Average each of the four halfwords in the 64-bit source vector Rss with the corresponding - halfword in Rtt. The average operation performed on each halfword adds the two - halfwords and shifts the result right by 1 bit. Unsigned average uses a logical right shift - (shift in 0), whereas signed average uses an arithmetic right shift (shift in the sign bit). If - the round option is used, a 0x0001 is also added to each result before shifting. This - operation does not overflow. In the case that a summation (before right shift by 1) causes - an overflow of 32 bits, the value shifted in is the most-significant carry out. - - The signed average and negative average halfwords is available with optional convergent - rounding. In convergent rounding, if the two LSBs after the addition/subtraction are 11, a - rounding constant of 1 is added, otherwise a 0 is added. This result is then shifted right by - one bit. Convergent rounding accumulates less error than arithmetic rounding. - - Syntax Behavior - Rdd=vavgh(Rss,Rtt) for (i=0;i<4;i++) { - Rdd.h[i]=(Rss.h[i]+Rtt.h[i])>>1; - }; - Rdd=vavgh(Rss,Rtt):crnd for (i=0;i<4;i++) { - Rdd.h[i]=convround(Rss.h[i]+Rtt.h[i])> - >1; - }; - Rdd=vavgh(Rss,Rtt):rnd for (i=0;i<4;i++) { - Rdd.h[i]=(Rss.h[i]+Rtt.h[i]+1)>>1; - }; - Rdd=vavguh(Rss,Rtt) for (i=0;i<4;i++) { - Rdd.h[i]=(Rss.uh[i]+Rtt.uh[i])>>1; - }; - Rdd=vavguh(Rss,Rtt):rnd for (i=0;i<4;i++) { - Rdd.h[i]=(Rss.uh[i]+Rtt.uh[i]+1)>>1; - }; - Rdd=vnavgh(Rtt,Rss) for (i=0;i<4;i++) { - Rdd.h[i]=(Rtt.h[i]-Rss.h[i])>>1; - }; - Rdd=vnavgh(Rtt,Rss):crnd:sat for (i=0;i<4;i++) { - Rdd.h[i]=sat16(convround(Rtt.h[i]- - Rss.h[i])>>1); - }; - Rdd=vnavgh(Rtt,Rss):rnd:sat for (i=0;i<4;i++) { - Rdd.h[i]=sat16((Rtt.h[i]- - Rss.h[i]+1)>>1); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - -80-N2040-36 B 434 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rdd=vavgh(Rss,Rtt) Word64 Q6_P_vavgh_PP(Word64 Rss, Word64 - Rtt) - Rdd=vavgh(Rss,Rtt):crnd Word64 Q6_P_vavgh_PP_crnd(Word64 Rss, - Word64 Rtt) - Rdd=vavgh(Rss,Rtt):rnd Word64 Q6_P_vavgh_PP_rnd(Word64 Rss, Word64 - Rtt) - Rdd=vavguh(Rss,Rtt) Word64 Q6_P_vavguh_PP(Word64 Rss, Word64 - Rtt) - Rdd=vavguh(Rss,Rtt):rnd Word64 Q6_P_vavguh_PP_rnd(Word64 Rss, - Word64 Rtt) - Rdd=vnavgh(Rtt,Rss) Word64 Q6_P_vnavgh_PP(Word64 Rtt, Word64 - Rss) - Rdd=vnavgh(Rtt,Rss):crnd:sat Word64 Q6_P_vnavgh_PP_crnd_sat(Word64 Rtt, - Word64 Rss) - Rdd=vnavgh(Rtt,Rss):rnd:sat Word64 Q6_P_vnavgh_PP_rnd_sat(Word64 Rtt, - Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=vavgh(Rss,Rtt) -1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 0 1 1 d d d d d Rdd=vavgh(Rss,Rtt):rnd -1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 1 0 0 d d d d d Rdd=vavgh(Rss,Rtt):crnd -1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 1 0 1 d d d d d Rdd=vavguh(Rss,Rtt) -1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 1 1 - d d d d d Rdd=vavguh(Rss,Rtt):rnd -1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=vnavgh(Rtt,Rss) -1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 0 0 1 d d d d d Rdd=vnavgh(Rtt,Rss):rnd:sat -1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=vnavgh(Rtt,Rss):crnd:sat - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 435 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector average unsigned bytes - Average each of the eight unsigned bytes in the 64-bit source vector Rss with the - corresponding byte in Rtt. The average operation performed on each byte is the sum of the - two bytes shifted right by 1 bit. If the round option is used, then a 0x01 is also added to - each result before shifting. This operation does not overflow. In the case that a summation - (before right shift by 1) causes an overflow of 8 bits, the value shifted in is the most- - significant carry out. - - Syntax Behavior - Rdd=vavgub(Rss,Rtt) for (i = 0; i < 8; i++) { - Rdd.b[i]=((Rss.ub[i] + Rtt.ub[i])>>1); - }; - Rdd=vavgub(Rss,Rtt):rnd for (i = 0; i < 8; i++) { - Rdd.b[i]=((Rss.ub[i]+Rtt.ub[i]+1)>>1); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rdd=vavgub(Rss,Rtt) Word64 Q6_P_vavgub_PP(Word64 Rss, Word64 - Rtt) - Rdd=vavgub(Rss,Rtt):rnd Word64 Q6_P_vavgub_PP_rnd(Word64 Rss, - Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=vavgub(Rss,Rtt) -1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 0 0 1 d d d d d Rdd=vavgub(Rss,Rtt):rnd - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 436 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector average words - Average each of the two words in the 64-bit source vector Rss with the corresponding - word in Rtt. The average operation performed on each halfword adds the two words and - shifts the result right by 1 bit. Unsigned average uses a logical right shift (shift in 0), - whereas signed average uses an arithmetic right shift (shift in the sign bit). If the round - option is used, a 0x1 is also added to each result before shifting. This operation does not - overflow. In the case that a summation (before right shift by 1) causes an overflow of 32 - bits, the value shifted in is the most-significant carry out. - - The signed average and negative average words is available with optional convergent - rounding. In convergent rounding, if the two LSBs after the addition/subtraction are 11, - then a rounding constant of 1 is added, otherwise a 0 is added. This result is then shifted - right by one bit. Convergent rounding accumulates less error than arithmetic rounding. - - Syntax Behavior - Rdd=vavguw(Rss,Rtt)[:rnd] for (i=0;i<2;i++) { - Rdd.w[i]=(zxt32->33(Rss.uw[i])+zxt32- - >33(Rtt.uw[i])+1)>>1; - }; - Rdd=vavgw(Rss,Rtt):crnd for (i=0;i<2;i++) { - Rdd.w[i]=(convround(sxt32- - >33(Rss.w[i])+sxt32->33(Rtt.w[i]))>>1); - }; - Rdd=vavgw(Rss,Rtt)[:rnd] for (i=0;i<2;i++) { - Rdd.w[i]=(sxt32->33(Rss.w[i])+sxt32- - >33(Rtt.w[i])+1)>>1; - }; - Rdd=vnavgw(Rtt,Rss) for (i=0;i<2;i++) { - Rdd.w[i]=(sxt32->33(Rtt.w[i])-sxt32- - >33(Rss.w[i]))>>1; - }; - Rdd=vnavgw(Rtt,Rss):crnd:sat for (i=0;i<2;i++) { - Rdd.w[i]=sat32(convround(sxt32- - >33 (Rtt.w[i])-sxt 32->33(Rss.w[i]))>>1); - }; - Rdd=vnavgw(Rtt,Rss):rnd:sat for (i=0;i<2;i++) { - Rdd.w[i]=sat32((sxt32->33(Rtt.w[i])- - sxt32->33(Rss.w[i])+1)>>1); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - - - -80-N2040-36 B 437 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rdd=vavguw(Rss,Rtt) Word64 Q6_P_vavguw_PP(Word64 Rss, Word64 - Rtt) - Rdd=vavguw(Rss,Rtt):rnd Word64 Q6_P_vavguw_PP_rnd(Word64 Rss, - Word64 Rtt) - Rdd=vavgw(Rss,Rtt) Word64 Q6_P_vavgw_PP(Word64 Rss, Word64 - Rtt) - Rdd=vavgw(Rss,Rtt):crnd Word64 Q6_P_vavgw_PP_crnd(Word64 Rss, - Word64 Rtt) - Rdd=vavgw(Rss,Rtt):rnd Word64 Q6_P_vavgw_PP_rnd(Word64 Rss, Word64 - Rtt) - Rdd=vnavgw(Rtt,Rss) Word64 Q6_P_vnavgw_PP(Word64 Rtt, Word64 - Rss) - Rdd=vnavgw(Rtt,Rss):crnd:sat Word64 Q6_P_vnavgw_PP_crnd_sat(Word64 Rtt, - Word64 Rss) - Rdd=vnavgw(Rtt,Rss):rnd:sat Word64 Q6_P_vnavgw_PP_rnd_sat(Word64 Rtt, - Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=vavgw(Rss,Rtt) -1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 0 0 1 d d d d d Rdd=vavgw(Rss,Rtt):rnd -1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=vavgw(Rss,Rtt):crnd -1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 0 1 1 d d d d d Rdd=vavguw(Rss,Rtt) -1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 1 0 0 d d d d d Rdd=vavguw(Rss,Rtt):rnd -1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 0 1 1 d d d d d Rdd=vnavgw(Rtt,Rss) -1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 1 0 - d d d d d Rdd=vnavgw(Rtt,Rss):rnd:sat -1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 1 1 - d d d d d Rdd=vnavgw(Rtt,Rss):crnd:sat - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 438 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector conditional negate - Based on bits in Rt, conditionally negate halves in Rss. - - Syntax Behavior - Rdd=vcnegh(Rss,Rt) for (i = 0; i < 4; i++) { - if (Rt.i) { - Rdd.h[i]=sat16(-Rss.h[i]); - } else { - Rdd.h[i]=Rss.h[i]; - }; - }; - Rxx+=vrcnegh(Rss,Rt) for (i = 0; i < 4; i++) { - if (Rt.i) { - Rxx += -Rss.h[i]; - } else { - Rxx += Rss.h[i]; - }; - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vcnegh(Rss,Rt) Word64 Q6_P_vcnegh_PR(Word64 Rss, Word32 - Rt) - Rxx+=vrcnegh(Rss,Rt) Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, - Word64 Rss, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 1 1 1 1 - s s s s s P P - t t t t t 0 1 - d d d d d Rdd=vcnegh(Rss,Rt) - ICLASS RegType Maj s5 Parse t5 Min x5 -1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 t t t t t 1 1 1 x x x x x Rxx+=vrcnegh(Rss,Rt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - -80-N2040-36 B 439 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - x5 Field to encode register x - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 440 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector maximum bytes - Compare each of the eight unsigned bytes in the 64-bit source vector Rss to the - corresponding byte in Rtt. For each comparison, select the maximum of the two bytes and - place that byte in the corresponding location in Rdd. - - Syntax Behavior - Rdd=vmaxb(Rtt,Rss) for (i = 0; i < 8; i++) { - Rdd.b[i]=max(Rtt.b[i],Rss.b[i]); - }; - Rdd=vmaxub(Rtt,Rss) for (i = 0; i < 8; i++) { - Rdd.b[i]=max(Rtt.ub[i],Rss.ub[i]); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rdd=vmaxb(Rtt,Rss) Word64 Q6_P_vmaxb_PP(Word64 Rtt, Word64 - Rss) - Rdd=vmaxub(Rtt,Rss) Word64 Q6_P_vmaxub_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=vmaxub(Rtt,Rss) -1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 1 1 0 d d d d d Rdd=vmaxb(Rtt,Rss) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 441 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector maximum halfwords - Compare each of the four halfwords in the 64-bit source vector Rss to the corresponding - halfword in Rtt. For each comparison, select the maximum of the two halfwords and place - that halfword in the corresponding location in Rdd. Comparisons are available in both - signed and unsigned form. - - Syntax Behavior - Rdd=vmaxh(Rtt,Rss) for (i = 0; i < 4; i++) { - Rdd.h[i]=max(Rtt.h[i],Rss.h[i]); - }; - Rdd=vmaxuh(Rtt,Rss) for (i = 0; i < 4; i++) { - Rdd.h[i]=max(Rtt.uh[i],Rss.uh[i]); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vmaxh(Rtt,Rss) Word64 Q6_P_vmaxh_PP(Word64 Rtt, Word64 - Rss) - Rdd=vmaxuh(Rtt,Rss) Word64 Q6_P_vmaxuh_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 0 0 1 d d d d d Rdd=vmaxh(Rtt,Rss) -1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=vmaxuh(Rtt,Rss) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 442 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector reduce maximum halfwords - Register Rxx contains a maximum value in the low word and the address of that maximum - value in the high word. Register Rss contains a vector of four halfword values, and register - Ru contains the address of this data. The instruction finds the maximum halfword between - the previous maximum in Rxx[0] and the four values in Rss. The address of the new - maximum is stored in Rxx[1]. - - Syntax Behavior - Rxx=vrmaxh(Rss,Ru) max = Rxx.h[0]; - addr = Rxx.w[1]; - for (i = 0; i < 4; i++) { - if (max < Rss.h[i]) { - max = Rss.h[i]; - addr = Ru | i<<1; - }; - }; - Rxx.w[0]=max; - Rxx.w[1]=addr; - Rxx=vrmaxuh(Rss,Ru) max = Rxx.uh[0]; - addr = Rxx.w[1]; - for (i = 0; i < 4; i++) { - if (max < Rss.uh[i]) { - max = Rss.uh[i]; - addr = Ru | i<<1; - }; - }; - Rxx.w[0]=max; - Rxx.w[1]=addr; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rxx=vrmaxh(Rss,Ru) Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 - Rss, Word32 Ru) - Rxx=vrmaxuh(Rss,Ru) Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 - Rss, Word32 Ru) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse x5 Min u5 -1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 0 0 1 u u u u u Rxx=vrmaxh(Rss,Ru) -1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 0 1 u u u u u Rxx=vrmaxuh(Rss,Ru) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - - - -80-N2040-36 B 443 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - u5 Field to encode register u - x5 Field to encode register x - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 444 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector reduce maximum words - Find the maximum word between the previous maximum in Rxx[0] and the two values in - Rss. The address of the new maximum is stored in Rxx[1]. - - Register Rxx contains a maximum value in the low word and the address of that maximum - value in the high word. Register Rss contains a vector of two word values, and register Ru - contains the address of this data. - - Syntax Behavior - Rxx=vrmaxuw(Rss,Ru) max = Rxx.uw[0]; - addr = Rxx.w[1]; - for (i = 0; i < 2; i++) { - if (max < Rss.uw[i]) { - max = Rss.uw[i]; - addr = Ru | i<<2; - }; - }; - Rxx.w[0]=max; - Rxx.w[1]=addr; - Rxx=vrmaxw(Rss,Ru) max = Rxx.w[0]; - addr = Rxx.w[1]; - for (i = 0; i < 2; i++) { - if (max < Rss.w[i]) { - max = Rss.w[i]; - addr = Ru | i<<2; - }; - }; - Rxx.w[0]=max; - Rxx.w[1]=addr; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rxx=vrmaxuw(Rss,Ru) Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 - Rss, Word32 Ru) - Rxx=vrmaxw(Rss,Ru) Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 - Rss, Word32 Ru) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse x5 Min u5 -1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 0 1 0 u u u u u Rxx=vrmaxw(Rss,Ru) -1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 1 0 u u u u u Rxx=vrmaxuw(Rss,Ru) - - - - -80-N2040-36 B 445 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - u5 Field to encode register u - x5 Field to encode register x - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 446 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector maximum words - Compare each of the two words in the 64-bit source vector Rss to the corresponding word - in Rtt. For each comparison, select the maximum of the two words and place that word in - the corresponding location in Rdd. - - Comparisons are available in both signed and unsigned form. - - Syntax Behavior - Rdd=vmaxuw(Rtt,Rss) for (i = 0; i < 2; i++) { - Rdd.w[i]=max(Rtt.uw[i],Rss.uw[i]); - }; - Rdd=vmaxw(Rtt,Rss) for (i = 0; i < 2; i++) { - Rdd.w[i]=max(Rtt.w[i],Rss.w[i]); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vmaxuw(Rtt,Rss) Word64 Q6_P_vmaxuw_PP(Word64 Rtt, Word64 - Rss) - Rdd=vmaxw(Rtt,Rss) Word64 Q6_P_vmaxw_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 1 0 1 d d d d d Rdd=vmaxuw(Rtt,Rss) -1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 0 1 1 d d d d d Rdd=vmaxw(Rtt,Rss) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 447 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector minimum bytes - Compare each of the eight unsigned bytes in the 64-bit source vector Rss to the - corresponding byte in Rtt. For each comparison, select the minimum of the two bytes and - place that byte in the corresponding location in Rdd. - - Syntax Behavior - Rdd,Pe=vminub(Rtt,Rss) for (i = 0; i < 8; i++) { - Pe.i = (Rtt.ub[i] > Rss.ub[i]); - Rdd.b[i]=min(Rtt.ub[i],Rss.ub[i]); - }; - Rdd=vminb(Rtt,Rss) for (i = 0; i < 8; i++) { - Rdd.b[i]=min(Rtt.b[i],Rss.b[i]); - }; - Rdd=vminub(Rtt,Rss) for (i = 0; i < 8; i++) { - Rdd.b[i]=min(Rtt.ub[i],Rss.ub[i]); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. - - Intrinsics - - Rdd=vminb(Rtt,Rss) Word64 Q6_P_vminb_PP(Word64 Rtt, Word64 - Rss) - Rdd=vminub(Rtt,Rss) Word64 Q6_P_vminub_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=vminub(Rtt,Rss) -1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 1 1 1 d d d d d Rdd=vminb(Rtt,Rss) - ICLASS RegType MajOp s5 Parse t5 e2 d5 -1 1 1 0 1 0 1 0 1 1 1 s s s s s P P 0 t t t t t 0 e e d d d d d Rdd,Pe=vminub(Rtt,Rss) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - - - - -80-N2040-36 B 448 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - e2 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 449 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector minimum halfwords - Compare each of the four halfwords in the 64-bit source vector Rss to the corresponding - halfword in Rtt. For each comparison, select the minimum of the two halfwords and place - that halfword in the corresponding location in Rdd. - - Comparisons are available in both signed and unsigned form. - - Syntax Behavior - Rdd=vminh(Rtt,Rss) for (i = 0; i < 4; i++) { - Rdd.h[i]=min(Rtt.h[i],Rss.h[i]); - }; - Rdd=vminuh(Rtt,Rss) for (i = 0; i < 4; i++) { - Rdd.h[i]=min(Rtt.uh[i],Rss.uh[i]); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vminh(Rtt,Rss) Word64 Q6_P_vminh_PP(Word64 Rtt, Word64 - Rss) - Rdd=vminuh(Rtt,Rss) Word64 Q6_P_vminuh_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 0 0 1 d d d d d Rdd=vminh(Rtt,Rss) -1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=vminuh(Rtt,Rss) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 450 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector reduce minimum halfwords - Find the minimum halfword between the previous minimum in Rxx[0] and the four values - in Rss. The address of the new minimum is stored in Rxx[1]. - - Register Rxx contains a minimum value in the low word and the address of that minimum - value in the high word. Register Rss contains a vector of four halfword values, and register - Ru contains the address of this data. - - Syntax Behavior - Rxx=vrminh(Rss,Ru) min = Rxx.h[0]; - addr = Rxx.w[1]; - for (i = 0; i < 4; i++) { - if (min > Rss.h[i]) { - min = Rss.h[i]; - addr = Ru | i<<1; - }; - }; - Rxx.w[0]=min; - Rxx.w[1]=addr; - Rxx=vrminuh(Rss,Ru) min = Rxx.uh[0]; - addr = Rxx.w[1]; - for (i = 0; i < 4; i++) { - if (min > Rss.uh[i]) { - min = Rss.uh[i]; - addr = Ru | i<<1; - }; - }; - Rxx.w[0]=min; - Rxx.w[1]=addr; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rxx=vrminh(Rss,Ru) Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 - Rss, Word32 Ru) - Rxx=vrminuh(Rss,Ru) Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 - Rss, Word32 Ru) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse x5 Min u5 -1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 0 1 u u u u u Rxx=vrminh(Rss,Ru) -1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 0 1 u u u u u Rxx=vrminuh(Rss,Ru) - - - - -80-N2040-36 B 451 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - u5 Field to encode register u - x5 Field to encode register x - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 452 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector reduce minimum words - Find the minimum word between the previous minimum in Rxx[0] and the two values in - Rss. The address of the new minimum is stored in Rxx[1]. - - Register Rxx contains a minimum value in the low word and the address of that minimum - value in the high word. Register Rss contains a vector of two word values, and register Ru - contains the address of this data. - - Syntax Behavior - Rxx=vrminuw(Rss,Ru) min = Rxx.uw[0]; - addr = Rxx.w[1]; - for (i = 0; i < 2; i++) { - if (min > Rss.uw[i]) { - min = Rss.uw[i]; - addr = Ru | i<<2; - }; - }; - Rxx.w[0]=min; - Rxx.w[1]=addr; - Rxx=vrminw(Rss,Ru) min = Rxx.w[0]; - addr = Rxx.w[1]; - for (i = 0; i < 2; i++) { - if (min > Rss.w[i]) { - min = Rss.w[i]; - addr = Ru | i<<2; - }; - }; - Rxx.w[0]=min; - Rxx.w[1]=addr; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rxx=vrminuw(Rss,Ru) Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 - Rss, Word32 Ru) - Rxx=vrminw(Rss,Ru) Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 - Rss, Word32 Ru) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse x5 Min u5 -1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 1 0 u u u u u Rxx=vrminw(Rss,Ru) -1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 1 0 u u u u u Rxx=vrminuw(Rss,Ru) - - - - -80-N2040-36 B 453 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - u5 Field to encode register u - x5 Field to encode register x - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 454 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector minimum words - Compare each of the two words in the 64-bit source vector Rss to the corresponding word - in Rtt. For each comparison, select the minimum of the two words and place that word in - the corresponding location in Rdd. - - Comparisons are available in both signed and unsigned form. - - Syntax Behavior - Rdd=vminuw(Rtt,Rss) for (i = 0; i < 2; i++) { - Rdd.w[i]=min(Rtt.uw[i],Rss.uw[i]); - }; - Rdd=vminw(Rtt,Rss) for (i = 0; i < 2; i++) { - Rdd.w[i]=min(Rtt.w[i],Rss.w[i]); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vminuw(Rtt,Rss) Word64 Q6_P_vminuw_PP(Word64 Rtt, Word64 - Rss) - Rdd=vminw(Rtt,Rss) Word64 Q6_P_vminw_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 0 1 1 d d d d d Rdd=vminw(Rtt,Rss) -1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 1 0 0 d d d d d Rdd=vminuw(Rtt,Rss) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 455 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector sum of absolute differences unsigned bytes - For each byte in the source vector Rss, subtract the corresponding byte in source vector - Rtt. Take the absolute value of the intermediate results, and the upper four together and - add the lower four together. Optionally, add the destination upper and lower words to these - results. - - This instruction is useful in determining distance between two vectors, in applications - such as motion estimation. - - - Rss - - - Rtt - - - sad sad sad sad sad sad sad sad - - - - - 32bit Add 32bit Add - - Rdd - - - - - Syntax Behavior - Rdd=vrsadub(Rss,Rtt) Rdd = 0; - for (i = 0; i < 4; i++) { - Rdd.w[0]=(Rdd.w[0] + ABS((Rss.ub[i] - - Rtt.ub[i]))); - }; - for (i = 4; i < 8; i++) { - Rdd.w[1]=(Rdd.w[1] + ABS((Rss.ub[i] - - Rtt.ub[i]))); - }; - Rxx+=vrsadub(Rss,Rtt) for (i = 0; i < 4; i++) { - Rxx.w[0]=(Rxx.w[0] + ABS((Rss.ub[i] - - Rtt.ub[i]))); - }; - for (i = 4; i < 8; i++) { - Rxx.w[1]=(Rxx.w[1] + ABS((Rss.ub[i] - - Rtt.ub[i]))); - }; - - - - -80-N2040-36 B 456 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rdd=vrsadub(Rss,Rtt) Word64 Q6_P_vrsadub_PP(Word64 Rss, Word64 - Rtt) - Rxx+=vrsadub(Rss,Rtt) Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, - Word64 Rss, Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d Rdd=vrsadub(Rss,Rtt) - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x Rxx+=vrsadub(Rss,Rtt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - - - - -80-N2040-36 B 457 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector subtract halfwords - Subtract each of the four halfwords in 64-bit vector Rss from the corresponding halfword - in vector Rtt. - - Optionally, saturate each 16-bit addition to either a signed or unsigned 16-bit value. - Applying saturation to the vsubh instruction clamps the result to the signed range 0x8000 - to 0x7fff, whereas applying saturation to the vsubuh instruction ensures that the unsigned - result falls within the range 0 to 0xffff. - - When saturation is not needed, vsubh should be used. - - Syntax Behavior - Rdd=vsubh(Rtt,Rss)[:sat] for (i=0;i<4;i++) { - Rdd.h[i]=[sat16](Rtt.h[i]-Rss.h[i]); - }; - Rdd=vsubuh(Rtt,Rss):sat for (i=0;i<4;i++) { - Rdd.h[i]=usat16(Rtt.uh[i]-Rss.uh[i]); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vsubh(Rtt,Rss) Word64 Q6_P_vsubh_PP(Word64 Rtt, Word64 - Rss) - Rdd=vsubh(Rtt,Rss):sat Word64 Q6_P_vsubh_PP_sat(Word64 Rtt, Word64 - Rss) - Rdd=vsubuh(Rtt,Rss):sat Word64 Q6_P_vsubuh_PP_sat(Word64 Rtt, - Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=vsubh(Rtt,Rss) -1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 0 1 1 d d d d d Rdd=vsubh(Rtt,Rss):sat -1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 1 0 0 d d d d d Rdd=vsubuh(Rtt,Rss):sat - - - - -80-N2040-36 B 458 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 459 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector subtract bytes - Subtract each of the eight bytes in 64-bit vector Rss from the corresponding byte in vector - Rtt. - - Optionally, saturate each 8-bit subtraction to an unsigned value between 0 and 255. The - eight results are stored in destination register Rdd. - - Syntax Behavior - Rdd=vsubb(Rss,Rtt) Assembler mapped to: "Rdd=vsubub(Rss,Rtt)" - Rdd=vsubub(Rtt,Rss)[:sat] for (i = 0; i < 8; i++) { - Rdd.b[i]=[usat8](Rtt.ub[i]-Rss.ub[i]); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vsubb(Rss,Rtt) Word64 Q6_P_vsubb_PP(Word64 Rss, Word64 - Rtt) - Rdd=vsubub(Rtt,Rss) Word64 Q6_P_vsubub_PP(Word64 Rtt, Word64 - Rss) - Rdd=vsubub(Rtt,Rss):sat Word64 Q6_P_vsubub_PP_sat(Word64 Rtt, - Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=vsubub(Rtt,Rss) -1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 0 0 1 d d d d d Rdd=vsubub(Rtt,Rss):sat - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 460 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector subtract words - Subtract each of the two words in 64-bit vector Rss from the corresponding word in vector - Rtt. - - Optionally, saturate each 32-bit subtraction to a signed value between 0x8000_0000 and - 0x7fff_ffff. The two word results are stored in destination register Rdd. - - Syntax Behavior - Rdd=vsubw(Rtt,Rss)[:sat] for (i=0;i<2;i++) { - Rdd.w[i]=[sat32](Rtt.w[i]-Rss.w[i]); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vsubw(Rtt,Rss) Word64 Q6_P_vsubw_PP(Word64 Rtt, Word64 - Rss) - Rdd=vsubw(Rtt,Rss):sat Word64 Q6_P_vsubw_PP_sat(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 1 0 1 d d d d d Rdd=vsubw(Rtt,Rss) -1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 1 1 0 d d d d d Rdd=vsubw(Rtt,Rss):sat - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 461 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.10.2 XTYPE/BIT - The XTYPE/BIT instruction subclass includes instructions for bit manipulation. - -Count leading - Count leading zeros (cl0) counts the number of consecutive zeros starting with the most - significant bit. - - Count leading ones (cl1) counts the number of consecutive ones starting with the most - significant bit. - - Count leading bits (clb) counts both leading ones and leading zeros and then selects the - maximum. - - The NORMAMT instruction returns the number of leading bits minus one. - - For a two's-complement number, the number of leading zeros is zero for negative - numbers. The number of leading ones is zero for positive numbers. - - The number of leading bits can be used to judge the magnitude of the value. - - Syntax Behavior - Rd=add(clb(Rs),#s6) Rd = - (max(count_leading_ones(Rs),count_leading_ - ones(~Rs)))+#s; - Rd=add(clb(Rss),#s6) Rd = - (max(count_leading_ones(Rss),count_leading - _ones(~Rss)))+#s; - Rd=cl0(Rs) Rd = count_leading_ones(~Rs); - Rd=cl0(Rss) Rd = count_leading_ones(~Rss); - Rd=cl1(Rs) Rd = count_leading_ones(Rs); - - - - -80-N2040-36 B 462 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rd=cl1(Rss) Rd = count_leading_ones(Rss); - Rd=clb(Rs) Rd = - max(count_leading_ones(Rs),count_leading_o - nes(~Rs)); - Rd=clb(Rss) Rd = - max(count_leading_ones(Rss),count_leading_ - ones(~Rss)); - Rd=normamt(Rs) if (Rs == 0) { - Rd = 0; - } else { - Rd = - (max(count_leading_ones(Rs),count_leading_ - ones(~Rs)))-1; - }; - Rd=normamt(Rss) if (Rss == 0) { - Rd = 0; - } else { - Rd = - (max(count_leading_ones(Rss),count_leading - _ones(~Rss)))-1; - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=add(clb(Rs),#s6) Word32 Q6_R_add_clb_RI(Word32 Rs, Word32 - Is6) - Rd=add(clb(Rss),#s6) Word32 Q6_R_add_clb_PI(Word64 Rss, Word32 - Is6) - Rd=cl0(Rs) Word32 Q6_R_cl0_R(Word32 Rs) - Rd=cl0(Rss) Word32 Q6_R_cl0_P(Word64 Rss) - Rd=cl1(Rs) Word32 Q6_R_cl1_R(Word32 Rs) - Rd=cl1(Rss) Word32 Q6_R_cl1_P(Word64 Rss) - Rd=clb(Rs) Word32 Q6_R_clb_R(Word32 Rs) - Rd=clb(Rss) Word32 Q6_R_clb_P(Word64 Rss) - Rd=normamt(Rs) Word32 Q6_R_normamt_R(Word32 Rs) - Rd=normamt(Rss) Word32 Q6_R_normamt_P(Word64 Rss) - - - - -80-N2040-36 B 463 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 0 1 0 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=clb(Rss) -1 0 0 0 1 0 0 0 0 1 0 s s s s s P P - - - - - - 0 1 0 d d d d d Rd=cl0(Rss) -1 0 0 0 1 0 0 0 0 1 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rd=cl1(Rss) -1 0 0 0 1 0 0 0 0 1 1 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=normamt(Rss) -1 0 0 0 1 0 0 0 0 1 1 s s s s s P P i i i i i i 0 1 0 d d d d d Rd=add(clb(Rss),#s6) -1 0 0 0 1 1 0 0 0 0 1 s s s s s P P i i i i i i 0 0 0 d d d d d Rd=add(clb(Rs),#s6) -1 0 0 0 1 1 0 0 0 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rd=clb(Rs) -1 0 0 0 1 1 0 0 0 0 0 s s s s s P P - - - - - - 1 0 1 d d d d d Rd=cl0(Rs) -1 0 0 0 1 1 0 0 0 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rd=cl1(Rs) -1 0 0 0 1 1 0 0 0 0 0 s s s s s P P - - - - - - 1 1 1 d d d d d Rd=normamt(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 464 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Count population - Population Count (popcount) counts the number of bits in Rss that are set. - - Syntax Behavior - Rd=popcount(Rss) Rd = count_ones(Rss); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=popcount(Rss) Word32 Q6_R_popcount_P(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 0 1 1 s s s s s P P - - - - - - 0 1 1 d d d d d Rd=popcount(Rss) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 465 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Count trailing - Count trailing zeros (ct0) counts the number of consecutive zeros starting with the least - significant bit. - - Count trailing ones (ct1) counts the number of consecutive ones starting with the least - significant bit. - - Syntax Behavior - Rd=ct0(Rs) Rd = count_leading_ones(~reverse_bits(Rs)); - Rd=ct0(Rss) Rd = - count_leading_ones(~reverse_bits(Rss)); - Rd=ct1(Rs) Rd = count_leading_ones(reverse_bits(Rs)); - Rd=ct1(Rss) Rd = count_leading_ones(reverse_bits(Rss)); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=ct0(Rs) Word32 Q6_R_ct0_R(Word32 Rs) - Rd=ct0(Rss) Word32 Q6_R_ct0_P(Word64 Rss) - Rd=ct1(Rs) Word32 Q6_R_ct1_R(Word32 Rs) - Rd=ct1(Rss) Word32 Q6_R_ct1_P(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 1 1 1 s s s s s P P - - - - - - 0 1 0 d d d d d Rd=ct0(Rss) -1 0 0 0 1 0 0 0 1 1 1 s s s s s P P - - - - - - 1 0 0 d d d d d Rd=ct1(Rss) -1 0 0 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rd=ct0(Rs) -1 0 0 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - 1 0 1 d d d d d Rd=ct1(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 466 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Extract bitfield - Extract a bitfield from the source register (or register pair) and deposit into the least - significant bits of the destination register (or register pair). The other, more significant bits - in the destination are either cleared or sign-extended, depending on the instruction. - - The width of the extracted field is obtained from the first immediate or from the most- - significant word of Rtt. The field offset is obtained from either the second immediate or - from the least-significant word of Rtt. - - For register-based extract, where Rtt supplies the offset and width, the offset value is - treated as a signed 7-bit number. If this value is negative, the source register Rss is shifted - left (the reverse direction). Width number of bits are then taken from the least-significant - portion of this result. - - If the shift amount and/or offset captures data beyond the most significant end of the input, - these bits will be taken as zero. - - Width Offset - - - Rs - - - - - Rd - - Zero Extension - - - - -80-N2040-36 B 467 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - Rd=extract(Rs,#u5,#U5) width=#u; - offset=#U; - Rd = sxtwidth->32((Rs >> offset)); - Rd=extract(Rs,Rtt) width=zxt6->32((Rtt.w[1])); - offset=sxt7->32((Rtt.w[0])); - Rd = sxtwidth->64((offset>0)?(zxt32->64(zxt32- - >64(Rs))>>>offset):(zxt32->64(zxt32- - >64(Rs))<32((Rs >> offset)); - Rd=extractu(Rs,Rtt) width=zxt6->32((Rtt.w[1])); - offset=sxt7->32((Rtt.w[0])); - Rd = zxtwidth->64((offset>0)?(zxt32->64(zxt32- - >64(Rs))>>>offset):(zxt32->64(zxt32- - >64(Rs))<64((Rss >> offset)); - Rdd=extract(Rss,Rtt) width=zxt6->32((Rtt.w[1])); - offset=sxt7->32((Rtt.w[0])); - Rdd = sxtwidth- - >64((offset>0)?(Rss>>>offset):(Rss<64((Rss >> offset)); - Rdd=extractu(Rss,Rtt) width=zxt6->32((Rtt.w[1])); - offset=sxt7->32((Rtt.w[0])); - Rdd = zxtwidth- - >64((offset>0)?(Rss>>>offset):(Rss<32((Rtt.w[1])); - offset=sxt7->32((Rtt.w[0])); - mask = ((1<32((Rtt.w[1])); - offset=sxt7->32((Rtt.w[0])); - mask = ((1<> 1) | ((1&count_ones(Rss & - Rtt)).u64<<63) ; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=lfs(Rss,Rtt) Word64 Q6_P_lfs_PP(Word64 Rss, Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 1 1 0 d d d d d Rdd=lfs(Rss,Rtt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 473 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Masked parity - Count the number of ones of the logical AND of the two source input values, and take the - least significant bit of that sum. - - Syntax Behavior - Rd=parity(Rs,Rt) Rd = 1&count_ones(Rs & Rt); - Rd=parity(Rss,Rtt) Rd = 1&count_ones(Rss & Rtt); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=parity(Rs,Rt) Word32 Q6_R_parity_RR(Word32 Rs, Word32 Rt) - Rd=parity(Rss,Rtt) Word32 Q6_R_parity_PP(Word64 Rss, Word64 - Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 d5 -1 1 0 1 0 0 0 0 - - - s s s s s P P - t t t t t - - - d d d d d Rd=parity(Rss,Rtt) -1 1 0 1 0 1 0 1 1 1 1 s s s s s P P - t t t t t - - - d d d d d Rd=parity(Rs,Rt) - - - - - Field name Description - RegType Register Type - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 474 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Bit reverse - Reverse the order of bits. The most significant gets swapped with the least significant, bit - 30 gets swapped with bit 1, and so on. - - Syntax Behavior - Rd=brev(Rs) Rd = reverse_bits(Rs); - Rdd=brev(Rss) Rdd = reverse_bits(Rss); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=brev(Rs) Word32 Q6_R_brev_R(Word32 Rs) - Rdd=brev(Rss) Word64 Q6_P_brev_P(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 1 1 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rdd=brev(Rss) -1 0 0 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rd=brev(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 475 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Set/clear/toggle bit - Set (to 1), clear (to 0), or toggle a single bit in the source, and place the resulting value in - the destination. The bit to be manipulated can be indicated using an immediate or register - value. - - If a register is used to indicate the bit position, and the value of the least-significant 7 bits - of Rt is out of range, then the destination register will be unchanged. - - Syntax Behavior - Rd=clrbit(Rs,#u5) Rd = (Rs & (~(1<<#u))); - Rd=clrbit(Rs,Rt) Rd = (Rs & (~((sxt7->32(Rt)>0)?(zxt32- - >64(1)<32(Rt)):(zxt32->64(1)>>>sxt7- - >32(Rt))))); - - Rd=setbit(Rs,#u5) Rd = (Rs | (1<<#u)); - Rd=setbit(Rs,Rt) Rd = (Rs | (sxt7->32(Rt)>0)?(zxt32- - >64(1)<32(Rt)):(zxt32->64(1)>>>sxt7- - >32(Rt))); - - Rd=togglebit(Rs,#u5) Rd = (Rs ^ (1<<#u)); - Rd=togglebit(Rs,Rt) Rd = (Rs ^ (sxt7->32(Rt)>0)?(zxt32- - >64(1)<32(Rt)):(zxt32->64(1)>>>sxt7- - >32(Rt))); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rd=clrbit(Rs,#u5) Word32 Q6_R_clrbit_RI(Word32 Rs, Word32 - Iu5) - Rd=clrbit(Rs,Rt) Word32 Q6_R_clrbit_RR(Word32 Rs, Word32 Rt) - Rd=setbit(Rs,#u5) Word32 Q6_R_setbit_RI(Word32 Rs, Word32 - Iu5) - Rd=setbit(Rs,Rt) Word32 Q6_R_setbit_RR(Word32 Rs, Word32 Rt) - Rd=togglebit(Rs,#u5) Word32 Q6_R_togglebit_RI(Word32 Rs, Word32 - Iu5) - Rd=togglebit(Rs,Rt) Word32 Q6_R_togglebit_RR(Word32 Rs, Word32 - Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 1 0 0 1 1 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d Rd=setbit(Rs,#u5) -1 0 0 0 1 1 0 0 1 1 0 s s s s s P P 0 i i i i i 0 0 1 d d d d d Rd=clrbit(Rs,#u5) - - - - -80-N2040-36 B 476 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 0 1 1 0 0 1 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d Rd=togglebit(Rs,#u5) - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 1 1 0 1 0 - s s s s s P P - t t t t t 0 0 - d d d d d Rd=setbit(Rs,Rt) -1 1 0 0 0 1 1 0 1 0 - s s s s s P P - t t t t t 0 1 - d d d d d Rd=clrbit(Rs,Rt) -1 1 0 0 0 1 1 0 1 0 - s s s s s P P - t t t t t 1 0 - d d d d d Rd=togglebit(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - MajOp Major Opcode - MinOp Minor Opcode - Maj Major Opcode - Min Minor Opcode - RegType Register Type - RegType Register Type - - - - -80-N2040-36 B 477 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Split bitfield - Split the bitfield in a register into upper and lower parts of variable size. The lower part is - placed in the lower word of a destination register pair, and the upper part is placed in the - upper word of the destination. An immediate value or register Rt is used to determine the - bit position of the split. - - - Bits - - Rs - - - - - Rdd[0] - - Zero - - - - Rdd[1] - - Zero - - - Syntax Behavior - Rdd=bitsplit(Rs,#u5) Rdd.w[1]=(Rs>>#u); - Rdd.w[0]=zxt#u->32(Rs); - Rdd=bitsplit(Rs,Rt) shamt = zxt5->32(Rt); - Rdd.w[1]=(Rs>>shamt); - Rdd.w[0]=zxtshamt->32(Rs); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=bitsplit(Rs,#u5) Word64 Q6_P_bitsplit_RI(Word32 Rs, Word32 - Iu5) - Rdd=bitsplit(Rs,Rt) Word64 Q6_P_bitsplit_RR(Word32 Rs, Word32 - Rt) - - - - -80-N2040-36 B 478 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 1 0 0 d d d d d Rdd=bitsplit(Rs,#u5) - ICLASS RegType s5 Parse t5 d5 -1 1 0 1 0 1 0 0 - - 1 s s s s s P P - t t t t t - - - d d d d d Rdd=bitsplit(Rs,Rt) - - - - - Field name Description - RegType Register Type - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 479 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Table index - The table index instruction supports fast lookup tables where the index into the table is - stored in a bit-field. The instruction forms the address of a table element by extracting the - bit-field and inserting it into the appropriate bits of a pointer to the table element. - - Tables are defined to contain entries of bytes, halfwords, words, or doublewords. The table - must be aligned to a power-of-2 size greater than or equal to the table size. For example, a - 4Kbyte table should be aligned to a 4Kbyte boundary. This instruction supports tables - with a maximum of 32K table entries. - - Register Rx contains a pointer to within the table. Register Rs contains a field to be - extracted and used as a table index. This instruction first extracts the field from register Rs - and then inserts it into register Rx. The insertion point is bit 0 for tables of bytes, bit 1 for - tables of halfwords, bit 2 for tables of words, and bit 3 for tables of doublewords. - - In the assembly syntax, the width and offset values represent the field in Rs to be - extracted. Unsigned constants should be used to specify the width and offsets in assembly. - In the encoded instruction, however, these values are adjusted by the assembler as follows. -  For tableidxb, no adjustment is necessary. -  For tableidxh, the assembler encodes offset-1 in the signed immediate field. -  For tableidxw, the assembler encodes offset-2 in the signed immediate field. -  For tableidxd, the assembler encodes offset-3 in the signed immediate field. - Rx=TABLEIDXD(Rs,#width,#offset) - - Width Offset - - - - Rs - - - - - Unchanged Rx - - - Unchanged - - - - -80-N2040-36 B 480 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - Rx=tableidxb(Rs,#u4,#S6):raw width=#u; - offset=#S; - field = Rs[(width+offset-1):offset]; - Rx[(width-1+0):0]=field; - Rx=tableidxb(Rs,#u4,#U5) Assembler mapped to: - "Rx=tableidxb(Rs,#u4,#U5):raw" - Rx=tableidxd(Rs,#u4,#S6):raw width=#u; - offset=#S+3; - field = Rs[(width+offset-1):offset]; - Rx[(width-1+3):3]=field; - Rx=tableidxd(Rs,#u4,#U5) Assembler mapped to: - "Rx=tableidxd(Rs,#u4,#U5-3):raw" - Rx=tableidxh(Rs,#u4,#S6):raw width=#u; - offset=#S+1; - field = Rs[(width+offset-1):offset]; - Rx[(width-1+1):1]=field; - Rx=tableidxh(Rs,#u4,#U5) Assembler mapped to: - "Rx=tableidxh(Rs,#u4,#U5-1):raw" - Rx=tableidxw(Rs,#u4,#S6):raw width=#u; - offset=#S+2; - field = Rs[(width+offset-1):offset]; - Rx[(width-1+2):2]=field; - Rx=tableidxw(Rs,#u4,#U5) Assembler mapped to: - "Rx=tableidxw(Rs,#u4,#U5-2):raw" - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rx=tableidxb(Rs,#u4,#U5) Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 - Rs, Word32 Iu4, Word32 IU5) - Rx=tableidxd(Rs,#u4,#U5) Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 - Rs, Word32 Iu4, Word32 IU5) - Rx=tableidxh(Rs,#u4,#U5) Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 - Rs, Word32 Iu4, Word32 IU5) - Rx=tableidxw(Rs,#u4,#U5) Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 - Rs, Word32 Iu4, Word32 IU5) - - - - -80-N2040-36 B 481 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp x5 -1 0 0 0 0 1 1 1 0 0 i s s s s s P P I I I I I I i i i x x x x x Rx=tableidxb(Rs,#u4,#S6):raw -1 0 0 0 0 1 1 1 0 1 i s s s s s P P I I I I I I i i i x x x x x Rx=tableidxh(Rs,#u4,#S6):raw -1 0 0 0 0 1 1 1 1 0 i s s s s s P P I I I I I I i i i x x x x x Rx=tableidxw(Rs,#u4,#S6):raw -1 0 0 0 0 1 1 1 1 1 i s s s s s P P I I I I I I i i i x x x x x Rx=tableidxd(Rs,#u4,#S6):raw - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - s5 Field to encode register s - x5 Field to encode register x - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 482 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.10.3 XTYPE/COMPLEX - The XTYPE/COMPLEX instruction subclass includes instructions which are for complex - math, using imaginary values. - -Complex add/sub halfwords - Cross vector add-sub or sub-add used to perform X+jY and X-jY complex operations. - Each 16-bit result is saturated to 16-bits. - - - Rdd=vxaddsubh(Rss,Rtt):sat - I R I R Rss - - I R I R Rtt - - - - - + + + + - - Sat_16 Sat_16 Sat_16 Sat_16 - - - I R I R Rdd - - - - Rdd=vxsubaddh(Rss,Rt):rnd:>>1:sat - I R I R Rss - I R I R Rtt - - - - - 1 + 1 + 1 + 1 + - - >>1 >>1 >>1 >>1 - - Rdd - Sat_16 Sat_16 Sat_16 Sat_16 - - - I R I R - - - - -80-N2040-36 B 483 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat Rdd.h[0]=sat16((Rss.h[0]+Rtt.h[1]+1)>>1); - Rdd.h[1]=sat16((Rss.h[1]-Rtt.h[0]+1)>>1); - Rdd.h[2]=sat16((Rss.h[2]+Rtt.h[3]+1)>>1); - Rdd.h[3]=sat16((Rss.h[3]-Rtt.h[2]+1)>>1); - Rdd=vxaddsubh(Rss,Rtt):sat Rdd.h[0]=sat16(Rss.h[0]+Rtt.h[1]); - Rdd.h[1]=sat16(Rss.h[1]-Rtt.h[0]); - Rdd.h[2]=sat16(Rss.h[2]+Rtt.h[3]); - Rdd.h[3]=sat16(Rss.h[3]-Rtt.h[2]); - Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat Rdd.h[0]=sat16((Rss.h[0]-Rtt.h[1]+1)>>1); - Rdd.h[1]=sat16((Rss.h[1]+Rtt.h[0]+1)>>1); - Rdd.h[2]=sat16((Rss.h[2]-Rtt.h[3]+1)>>1); - Rdd.h[3]=sat16((Rss.h[3]+Rtt.h[2]+1)>>1); - Rdd=vxsubaddh(Rss,Rtt):sat Rdd.h[0]=sat16(Rss.h[0]-Rtt.h[1]); - Rdd.h[1]=sat16(Rss.h[1]+Rtt.h[0]); - Rdd.h[2]=sat16(Rss.h[2]-Rtt.h[3]); - Rdd.h[3]=sat16(Rss.h[3]+Rtt.h[2]); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 - Rss, Word64 Rtt) - Rdd=vxaddsubh(Rss,Rtt):sat Word64 Q6_P_vxaddsubh_PP_sat(Word64 Rss, - Word64 Rtt) - Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 - Rss, Word64 Rtt) - Rdd=vxsubaddh(Rss,Rtt):sat Word64 Q6_P_vxsubaddh_PP_sat(Word64 Rss, - Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 1 0 0 d d d d d Rdd=vxaddsubh(Rss,Rtt):sat -1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 1 1 0 d d d d d Rdd=vxsubaddh(Rss,Rtt):sat -1 1 0 0 0 0 0 1 1 1 - s s s s s P P - t t t t t 0 0 - d d d d d Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat -1 1 0 0 0 0 0 1 1 1 - s s s s s P P - t t t t t 0 1 - d d d d d Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat - - - - -80-N2040-36 B 484 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 485 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Complex add/sub words - Cross vector add-sub or sub-add used to perform X+jY and X-jY complex operations. - Each 32-bit result is saturated to 32-bits. - - - Rdd=vxaddsubw(Rss,Rt):sat Rdd=vxsubaddw(Rss,Rt):sat - I R Rss I R Rss - - I R Rtt I R Rtt - - - - - - + + - - - Sat_32 Sat_32 Sat_32 Sat_32 - - - I R Rdd I R Rdd - - - Syntax Behavior - Rdd=vxaddsubw(Rss,Rtt):sat Rdd.w[0]=sat32(Rss.w[0]+Rtt.w[1]); - Rdd.w[1]=sat32(Rss.w[1]-Rtt.w[0]); - Rdd=vxsubaddw(Rss,Rtt):sat Rdd.w[0]=sat32(Rss.w[0]-Rtt.w[1]); - Rdd.w[1]=sat32(Rss.w[1]+Rtt.w[0]); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), then the OVF bit in the Status Register is - set. OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vxaddsubw(Rss,Rtt):sat Word64 Q6_P_vxaddsubw_PP_sat(Word64 Rss, - Word64 Rtt) - Rdd=vxsubaddw(Rss,Rtt):sat Word64 Q6_P_vxsubaddw_PP_sat(Word64 Rss, - Word64 Rtt) - - - - -80-N2040-36 B 486 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=vxaddsubw(Rss,Rtt):sat -1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=vxsubaddw(Rss,Rtt):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 487 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Complex multiply - Multiply complex values Rs and Rt. The inputs have a real 16-bit value in the low - halfword and an imaginary 16-bit value in the high halfword. Optionally, scale the result - by 0-1 bits. Optionally, add a complex accumulator. Saturate the real and imaginary - portions to 32-bits. The output has a real 32-bit value in the low word and an imaginary - 32-bit value in the high word. The Rt input can be optionally conjugated. Another option - is that the result can be subtracted from the destination rather than accumulated. - - Rxx+=cmpy(Rs,Rt):sat - - Rs I R I R Rs - - - Rt I R I R Rt - - - - - * * * * - 32 32 32 32 - - - <<0-1 <<0-1 <<0-1 <<0-1 - - - - Add Add - - - Sat_32 Sat_32 32 - - - - 32 - - - - Imaginary Accumulation Real Accumulation - - Rxx - - - - -80-N2040-36 B 488 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - Rdd=cmpy(Rs,Rt)[:<<1]:sat Rdd.w[1]=sat32((Rs.h[1] * Rt.h[0])[<<1] + - (Rs.h[0] * Rt.h[1])[<<1]); - Rdd.w[0]=sat32((Rs.h[0] * Rt.h[0])[<<1] - - (Rs.h[1] * Rt.h[1])[<<1]); - Rdd=cmpy(Rs,Rt*)[:<<1]:sat Rdd.w[1]=sat32((Rs.h[1] * Rt.h[0])[<<1] - - (Rs.h[0] * Rt.h[1])[<<1]); - Rdd.w[0]=sat32((Rs.h[0] * Rt.h[0])[<<1] + - (Rs.h[1] * Rt.h[1])[<<1]); - Rxx+=cmpy(Rs,Rt)[:<<1]:sat Rxx.w[1]=sat32(Rxx.w[1] + (Rs.h[1] * - Rt.h[0])[<<1] + (Rs.h[0] * Rt.h[1])[<<1]); - Rxx.w[0]=sat32(Rxx.w[0] + (Rs.h[0] * - Rt.h[0])[<<1] - (Rs.h[1] * Rt.h[1])[<<1]); - Rxx+=cmpy(Rs,Rt*)[:<<1]:sat Rxx.w[1]=sat32(Rxx.w[1] + (Rs.h[1] * - Rt.h[0])[<<1] - (Rs.h[0] * Rt.h[1])[<<1]); - Rxx.w[0]=sat32(Rxx.w[0] + (Rs.h[0] * - Rt.h[0])[<<1] + (Rs.h[1] * Rt.h[1])[<<1]); - Rxx-=cmpy(Rs,Rt)[:<<1]:sat Rxx.w[1]=sat32(Rxx.w[1] - ((Rs.h[1] * - Rt.h[0])[<<1] + (Rs.h[0] * Rt.h[1])[<<1])); - Rxx.w[0]=sat32(Rxx.w[0] - ((Rs.h[0] * - Rt.h[0])[<<1] - (Rs.h[1] * Rt.h[1])[<<1])); - Rxx-=cmpy(Rs,Rt*)[:<<1]:sat Rxx.w[1]=sat32(Rxx.w[1] - ((Rs.h[1] * - Rt.h[0])[<<1] - (Rs.h[0] * Rt.h[1])[<<1])); - Rxx.w[0]=sat32(Rxx.w[0] - ((Rs.h[0] * - Rt.h[0])[<<1] + (Rs.h[1] * Rt.h[1])[<<1])); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=cmpy(Rs,Rt):<<1:sat Word64 Q6_P_cmpy_RR_s1_sat(Word32 Rs, - Word32 Rt) - Rdd=cmpy(Rs,Rt):sat Word64 Q6_P_cmpy_RR_sat(Word32 Rs, Word32 - Rt) - Rdd=cmpy(Rs,Rt*):<<1:sat Word64 Q6_P_cmpy_RR_conj_s1_sat(Word32 Rs, - Word32 Rt) - Rdd=cmpy(Rs,Rt*):sat Word64 Q6_P_cmpy_RR_conj_sat(Word32 Rs, - Word32 Rt) - Rxx+=cmpy(Rs,Rt):<<1:sat Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, - Word32 Rs, Word32 Rt) - Rxx+=cmpy(Rs,Rt):sat Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, - Word32 Rs, Word32 Rt) - Rxx+=cmpy(Rs,Rt*):<<1:sat Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 - Rxx, Word32 Rs, Word32 Rt) - - - -80-N2040-36 B 489 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Rxx+=cmpy(Rs,Rt*):sat Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, - Word32 Rs, Word32 Rt) - Rxx-=cmpy(Rs,Rt):<<1:sat Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, - Word32 Rs, Word32 Rt) - Rxx-=cmpy(Rs,Rt):sat Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, - Word32 Rs, Word32 Rt) - Rxx-=cmpy(Rs,Rt*):<<1:sat Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 - Rxx, Word32 Rs, Word32 Rt) - Rxx-=cmpy(Rs,Rt*):sat Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, - Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 0 1 0 1 N 0 0 s s s s s P P 0 t t t t t 1 1 0 d d d d d Rdd=cmpy(Rs,Rt)[:<>15); - Rd=cmpyiwh(Rss,Rt*):<<1:rnd:sat Rd = sat32(( (Rss.w[1] * Rt.h[0]) - - (Rss.w[0] * Rt.h[1]) + 0x4000)>>15); - Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat Rd = sat32(( (Rss.w[0] * Rt.h[0]) - - (Rss.w[1] * Rt.h[1]) + 0x4000)>>15); - Rd=cmpyrwh(Rss,Rt*):<<1:rnd:sat Rd = sat32(( (Rss.w[0] * Rt.h[0]) + - (Rss.w[1] * Rt.h[1]) + 0x4000)>>15); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - - - -80-N2040-36 B 495 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rd=cmpyiwh(Rss,Rt):<<1:rnd:sat Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 - Rss, Word32 Rt) - Rd=cmpyiwh(Rss,Rt*):<<1:rnd:sat Word32 - Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, - Word32 Rt) - Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 - Rss, Word32 Rt) - Rd=cmpyrwh(Rss,Rt*):<<1:rnd:sat Word32 - Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, - Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 Min d5 -1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 1 0 0 d d d d d Rd=cmpyiwh(Rss,Rt):<<1:rnd:sat -1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 1 0 1 d d d d d Rd=cmpyiwh(Rss,Rt*):<<1:rnd:sat -1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 1 1 0 d d d d d Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat -1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 1 1 1 d d d d d Rd=cmpyrwh(Rss,Rt*):<<1:rnd:sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 496 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector complex multiply real or imaginary - The inputs Rss and Rtt are a vector of two complex values. Each complex value is - composed of a 16-bit imaginary portion in the upper halfword and a 16-bit real portion in - the lower halfword. Generate two complex results, either the real result or the imaginary - result. These results are optionally shifted left by 0-1 bits, and optionally accumulated - with the destination register. - - Rxx+=vcmpyi(Rss,Rtt):sat - - I R I R Rss - - - I R I R Rtt - - - - - * * * * - 32 32 32 32 - - - <<0-1 <<0-1 <<0-1 <<0-1 - - - - - Add Add - - - Sat_32 Sat_32 32 - - - - 32 - - - - Imag Accumulation Imag Accumulation - - Rxx - - - - -80-N2040-36 B 497 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat Rdd.w[0]=sat32((Rss.h[1] * Rtt.h[0]) + - (Rss.h[0] * Rtt.h[1])[<<1]); - Rdd.w[1]=sat32((Rss.h[3] * Rtt.h[2]) + - (Rss.h[2] * Rtt.h[3])[<<1]); - Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat Rdd.w[0]=sat32((Rss.h[0] * Rtt.h[0]) - - (Rss.h[1] * Rtt.h[1])[<<1]); - Rdd.w[1]=sat32((Rss.h[2] * Rtt.h[2]) - - (Rss.h[3] * Rtt.h[3])[<<1]); - Rxx+=vcmpyi(Rss,Rtt):sat Rxx.w[0]=sat32(Rxx.w[0] + (Rss.h[1] * - Rtt.h[0]) + (Rss.h[0] * Rtt.h[1])<<0); - Rxx.w[1]=sat32(Rxx.w[1] + (Rss.h[3] * - Rtt.h[2]) + (Rss.h[2] * Rtt.h[3])<<0); - Rxx+=vcmpyr(Rss,Rtt):sat Rxx.w[0]=sat32(Rxx.w[0] + (Rss.h[0] * - Rtt.h[0]) - (Rss.h[1] * Rtt.h[1])<<0); - Rxx.w[1]=sat32(Rxx.w[1] + (Rss.h[2] * - Rtt.h[2]) - (Rss.h[3] * Rtt.h[3])<<0); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vcmpyi(Rss,Rtt):<<1:sat Word64 Q6_P_vcmpyi_PP_s1_sat(Word64 Rss, - Word64 Rtt) - Rdd=vcmpyi(Rss,Rtt):sat Word64 Q6_P_vcmpyi_PP_sat(Word64 Rss, - Word64 Rtt) - Rdd=vcmpyr(Rss,Rtt):<<1:sat Word64 Q6_P_vcmpyr_PP_s1_sat(Word64 Rss, - Word64 Rtt) - Rdd=vcmpyr(Rss,Rtt):sat Word64 Q6_P_vcmpyr_PP_sat(Word64 Rss, - Word64 Rtt) - Rxx+=vcmpyi(Rss,Rtt):sat Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, - Word64 Rss, Word64 Rtt) - Rxx+=vcmpyr(Rss,Rtt):sat Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, - Word64 Rss, Word64 Rtt) - - - - -80-N2040-36 B 498 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 0 0 N 0 1 s s s s s P P 0 t t t t t 1 1 0 d d d d d Rdd=vcmpyr(Rss,Rtt)[:<> 2; - }; - Rdd.w[0]=sumr; - Rdd.w[1]=sumi; - Rxx+=vrcrotate(Rss,Rt,#u2) sumr = 0; - sumi = 0; - control = Rt.ub[#u]; - for (i = 0; i < 8; i += 2) { - tmpr = Rss.b[i]; - tmpi = Rss.b[i+1]; - switch (control & 3) { - case 0: sumr += tmpr; - sumi += tmpi; - break; - case 1: sumr += tmpi; - sumi -= tmpr; - break; - case 2: sumr -= tmpi; - sumi += tmpr; - break; - case 3: sumr -= tmpr; - sumi -= tmpi; - break; - }; - control = control >> 2; - }; - Rxx.w[0]=Rxx.w[0] + sumr; - Rxx.w[1]=Rxx.w[1] + sumi; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vrcrotate(Rss,Rt,#u2) Word64 Q6_P_vrcrotate_PRI(Word64 Rss, - Word32 Rt, Word32 Iu2) - Rxx+=vrcrotate(Rss,Rt,#u2) Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, - Word64 Rss, Word32 Rt, Word32 Iu2) - - - -80-N2040-36 B 513 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 1 1 1 1 - s s s s s P P i t t t t t 1 1 i d d d d d Rdd=vrcrotate(Rss,Rt,#u2) - ICLASS RegType Maj s5 Parse t5 x5 -1 1 0 0 1 0 1 1 1 0 1 s s s s s P P i t t t t t - - i x x x x x Rxx+=vrcrotate(Rss,Rt,#u2) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 514 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.10.4 XTYPE/FP - The XTYPE/FP instruction subclass includes instructions which are for floating point - math. - - - - -80-N2040-36 B 515 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point addition - Add two floating point values - - Syntax Behavior - Rd=sfadd(Rs,Rt) Rd=Rs+Rt; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=sfadd(Rs,Rt) Word32 Q6_R_sfadd_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rd=sfadd(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 516 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Classify floating-point value - Classify floating point values. Classes are Normal, Subnormal, Zero, NaN, or Infinity. If - the number is one of the specified classes, return true. - - Syntax Behavior - Pd=dfclass(Rss,#u5) Pd = 0; - class = fpclassify(Rss); - if (#u.0 && (class == FP_ZERO)) Pd = 0xff; - if (#u.1 && (class == FP_NORMAL)) Pd = - 0xff; - if (#u.2 && (class == FP_SUBNORMAL)) Pd = - 0xff; - if (#u.3 && (class == FP_INFINITE)) Pd = - 0xff; - if (#u.4 && (class == FP_NAN)) Pd = 0xff; - cancel_flags(); - Pd=sfclass(Rs,#u5) Pd = 0; - class = fpclassify(Rs); - if (#u.0 && (class == FP_ZERO)) Pd = 0xff; - if (#u.1 && (class == FP_NORMAL)) Pd = - 0xff; - if (#u.2 && (class == FP_SUBNORMAL)) Pd = - 0xff; - if (#u.3 && (class == FP_INFINITE)) Pd = - 0xff; - if (#u.4 && (class == FP_NAN)) Pd = 0xff; - cancel_flags(); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Pd=dfclass(Rss,#u5) Byte Q6_p_dfclass_PI(Word64 Rss, Word32 - Iu5) - Pd=sfclass(Rs,#u5) Byte Q6_p_sfclass_RI(Word32 Rs, Word32 Iu5) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse d2 -1 0 0 0 0 1 0 1 1 1 1 s s s s s P P 0 i i i i i - - - - - - d d Pd=sfclass(Rs,#u5) - ICLASS RegType s5 Parse d2 -1 1 0 1 1 1 0 0 1 0 0 s s s s s P P - 0 0 0 i i i i i 1 0 - d d Pd=dfclass(Rss,#u5) - - - - - Field name Description - RegType Register Type - MajOp Major Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - - - - -80-N2040-36 B 517 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - d2 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - RegType Register Type - - - - -80-N2040-36 B 518 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Compare floating-point value - Compare floating point values. p0 returns true if at least one value is a NaN, zero - otherwise. - - Syntax Behavior - Pd=dfcmp.eq(Rss,Rtt) Pd=Rss==Rtt ? 0xff : 0x00; - Pd=dfcmp.ge(Rss,Rtt) Pd=Rss>=Rtt ? 0xff : 0x00; - Pd=dfcmp.gt(Rss,Rtt) Pd=Rss>Rtt ? 0xff : 0x00; - Pd=dfcmp.uo(Rss,Rtt) Pd=isunordered(Rss,Rtt) ? 0xff : 0x00; - Pd=sfcmp.eq(Rs,Rt) Pd=Rs==Rt ? 0xff : 0x00; - Pd=sfcmp.ge(Rs,Rt) Pd=Rs>=Rt ? 0xff : 0x00; - Pd=sfcmp.gt(Rs,Rt) Pd=Rs>Rt ? 0xff : 0x00; - Pd=sfcmp.uo(Rs,Rt) Pd=isunordered(Rs,Rt) ? 0xff : 0x00; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Pd=dfcmp.eq(Rss,Rtt) Byte Q6_p_dfcmp_eq_PP(Word64 Rss, Word64 - Rtt) - Pd=dfcmp.ge(Rss,Rtt) Byte Q6_p_dfcmp_ge_PP(Word64 Rss, Word64 - Rtt) - Pd=dfcmp.gt(Rss,Rtt) Byte Q6_p_dfcmp_gt_PP(Word64 Rss, Word64 - Rtt) - Pd=dfcmp.uo(Rss,Rtt) Byte Q6_p_dfcmp_uo_PP(Word64 Rss, Word64 - Rtt) - Pd=sfcmp.eq(Rs,Rt) Byte Q6_p_sfcmp_eq_RR(Word32 Rs, Word32 Rt) - Pd=sfcmp.ge(Rs,Rt) Byte Q6_p_sfcmp_ge_RR(Word32 Rs, Word32 Rt) - Pd=sfcmp.gt(Rs,Rt) Byte Q6_p_sfcmp_gt_RR(Word32 Rs, Word32 Rt) - Pd=sfcmp.uo(Rs,Rt) Byte Q6_p_sfcmp_uo_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d2 -1 1 0 0 0 1 1 1 1 1 1 s s s s s P P - t t t t t 0 0 0 - - - d d Pd=sfcmp.ge(Rs,Rt) -1 1 0 0 0 1 1 1 1 1 1 s s s s s P P - t t t t t 0 0 1 - - - d d Pd=sfcmp.uo(Rs,Rt) -1 1 0 0 0 1 1 1 1 1 1 s s s s s P P - t t t t t 0 1 1 - - - d d Pd=sfcmp.eq(Rs,Rt) -1 1 0 0 0 1 1 1 1 1 1 s s s s s P P - t t t t t 1 0 0 - - - d d Pd=sfcmp.gt(Rs,Rt) - - - - -80-N2040-36 B 519 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d2 -1 1 0 1 0 0 1 0 1 1 1 s s s s s P P - t t t t t 0 0 0 - - - d d Pd=dfcmp.eq(Rss,Rtt) -1 1 0 1 0 0 1 0 1 1 1 s s s s s P P - t t t t t 0 0 1 - - - d d Pd=dfcmp.gt(Rss,Rtt) -1 1 0 1 0 0 1 0 1 1 1 s s s s s P P - t t t t t 0 1 0 - - - d d Pd=dfcmp.ge(Rss,Rtt) -1 1 0 1 0 0 1 0 1 1 1 s s s s s P P - t t t t t 0 1 1 - - - d d Pd=dfcmp.uo(Rss,Rtt) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 520 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Convert floating-point value to other format - Convert floating point values. If rounding is required, it happens according to the rounding - mode. - - Syntax Behavior - Rd=convert_df2sf(Rss) Rd = conv_df_to_sf(Rss); - Rdd=convert_sf2df(Rs) Rdd = conv_sf_to_df(Rs); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=convert_df2sf(Rss) Word32 Q6_R_convert_df2sf_P(Word64 Rss) - Rdd=convert_sf2df(Rs) Word64 Q6_P_convert_sf2df_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 0 0 0 d d d d d Rdd=convert_sf2df(Rs) -1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=convert_df2sf(Rss) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 521 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Convert integer to floating-point value - Convert floating point values. If rounding is required, it happens according to the rounding - mode unless the :chop option is specified. - - Syntax Behavior - Rd=convert_d2sf(Rss) Rd = conv_8s_to_sf(Rss.s64); - Rd=convert_ud2sf(Rss) Rd = conv_8u_to_sf(Rss.u64); - Rd=convert_uw2sf(Rs) Rd = conv_4u_to_sf(Rs.uw[0]); - Rd=convert_w2sf(Rs) Rd = conv_4s_to_sf(Rs.s32); - Rdd=convert_d2df(Rss) Rdd = conv_8s_to_df(Rss.s64); - Rdd=convert_ud2df(Rss) Rdd = conv_8u_to_df(Rss.u64); - Rdd=convert_uw2df(Rs) Rdd = conv_4u_to_df(Rs.uw[0]); - Rdd=convert_w2df(Rs) Rdd = conv_4s_to_df(Rs.s32); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=convert_d2sf(Rss) Word32 Q6_R_convert_d2sf_P(Word64 Rss) - Rd=convert_ud2sf(Rss) Word32 Q6_R_convert_ud2sf_P(Word64 Rss) - Rd=convert_uw2sf(Rs) Word32 Q6_R_convert_uw2sf_R(Word32 Rs) - Rd=convert_w2sf(Rs) Word32 Q6_R_convert_w2sf_R(Word32 Rs) - Rdd=convert_d2df(Rss) Word64 Q6_P_convert_d2df_P(Word64 Rss) - Rdd=convert_ud2df(Rss) Word64 Q6_P_convert_ud2df_P(Word64 Rss) - Rdd=convert_uw2df(Rs) Word64 Q6_P_convert_uw2df_R(Word32 Rs) - Rdd=convert_w2df(Rs) Word64 Q6_P_convert_w2df_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 0 1 0 d d d d d Rdd=convert_ud2df(Rss) -1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 0 1 1 d d d d d Rdd=convert_d2df(Rss) -1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 0 0 1 d d d d d Rdd=convert_uw2df(Rs) -1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 0 1 0 d d d d d Rdd=convert_w2df(Rs) -1 0 0 0 1 0 0 0 0 0 1 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=convert_ud2sf(Rss) -1 0 0 0 1 0 0 0 0 1 0 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=convert_d2sf(Rss) -1 0 0 0 1 0 1 1 0 0 1 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=convert_uw2sf(Rs) -1 0 0 0 1 0 1 1 0 1 0 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=convert_w2sf(Rs) - - - - -80-N2040-36 B 522 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 523 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Convert floating-point value to integer - Convert floating point values. If rounding is required, it happens according to the rounding - mode unless the :chop option is specified. If the value is out of range of the destination - integer type, the INVALID flag is raised and closest integer is chosen, including for - infinite inputs. For NaN inputs, the INVALID flag is also raised, and the output value is - IMPLEMENTATION DEFINED. - - Syntax Behavior - Rd=convert_df2uw(Rss) Rd = conv_df_to_4u(Rss).uw[0]; - Rd=convert_df2uw(Rss):chop round_to_zero(); - Rd = conv_df_to_4u(Rss).uw[0]; - Rd=convert_df2w(Rss) Rd = conv_df_to_4s(Rss).s32; - Rd=convert_df2w(Rss):chop round_to_zero(); - Rd = conv_df_to_4s(Rss).s32; - Rd=convert_sf2uw(Rs) Rd = conv_sf_to_4u(Rs).uw[0]; - Rd=convert_sf2uw(Rs):chop round_to_zero(); - Rd = conv_sf_to_4u(Rs).uw[0]; - Rd=convert_sf2w(Rs) Rd = conv_sf_to_4s(Rs).s32; - Rd=convert_sf2w(Rs):chop round_to_zero(); - Rd = conv_sf_to_4s(Rs).s32; - Rdd=convert_df2d(Rss) Rdd = conv_df_to_8s(Rss).s64; - Rdd=convert_df2d(Rss):chop round_to_zero(); - Rdd = conv_df_to_8s(Rss).s64; - Rdd=convert_df2ud(Rss) Rdd = conv_df_to_8u(Rss).u64; - Rdd=convert_df2ud(Rss):chop round_to_zero(); - Rdd = conv_df_to_8u(Rss).u64; - Rdd=convert_sf2d(Rs) Rdd = conv_sf_to_8s(Rs).s64; - Rdd=convert_sf2d(Rs):chop round_to_zero(); - Rdd = conv_sf_to_8s(Rs).s64; - Rdd=convert_sf2ud(Rs) Rdd = conv_sf_to_8u(Rs).u64; - Rdd=convert_sf2ud(Rs):chop round_to_zero(); - Rdd = conv_sf_to_8u(Rs).u64; - - - - -80-N2040-36 B 524 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rd=convert_df2uw(Rss) Word32 Q6_R_convert_df2uw_P(Word64 Rss) - Rd=convert_df2uw(Rss):chop Word32 Q6_R_convert_df2uw_P_chop(Word64 - Rss) - Rd=convert_df2w(Rss) Word32 Q6_R_convert_df2w_P(Word64 Rss) - Rd=convert_df2w(Rss):chop Word32 Q6_R_convert_df2w_P_chop(Word64 Rss) - Rd=convert_sf2uw(Rs) Word32 Q6_R_convert_sf2uw_R(Word32 Rs) - Rd=convert_sf2uw(Rs):chop Word32 Q6_R_convert_sf2uw_R_chop(Word32 Rs) - Rd=convert_sf2w(Rs) Word32 Q6_R_convert_sf2w_R(Word32 Rs) - Rd=convert_sf2w(Rs):chop Word32 Q6_R_convert_sf2w_R_chop(Word32 Rs) - Rdd=convert_df2d(Rss) Word64 Q6_P_convert_df2d_P(Word64 Rss) - Rdd=convert_df2d(Rss):chop Word64 Q6_P_convert_df2d_P_chop(Word64 Rss) - Rdd=convert_df2ud(Rss) Word64 Q6_P_convert_df2ud_P(Word64 Rss) - Rdd=convert_df2ud(Rss):chop Word64 Q6_P_convert_df2ud_P_chop(Word64 - Rss) - Rdd=convert_sf2d(Rs) Word64 Q6_P_convert_sf2d_R(Word32 Rs) - Rdd=convert_sf2d(Rs):chop Word64 Q6_P_convert_sf2d_R_chop(Word32 Rs) - Rdd=convert_sf2ud(Rs) Word64 Q6_P_convert_sf2ud_R(Word32 Rs) - Rdd=convert_sf2ud(Rs):chop Word64 Q6_P_convert_sf2ud_R_chop(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 0 0 0 d d d d d Rdd=convert_df2d(Rss) -1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 0 0 1 d d d d d Rdd=convert_df2ud(Rss) -1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 1 1 0 d d d d d Rdd=convert_df2d(Rss):chop -1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 1 1 1 d d d d d Rdd=convert_df2ud(Rss):chop -1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 0 1 1 d d d d d Rdd=convert_sf2ud(Rs) -1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 1 0 0 d d d d d Rdd=convert_sf2d(Rs) -1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 1 0 1 d d d d d Rdd=convert_sf2ud(Rs):ch -1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 1 1 0 d d d d d Rdd=convert_sf2d(Rs):chop -1 0 0 0 1 0 0 0 0 1 1 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=convert_df2uw(Rss) -1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=convert_df2w(Rss) -1 0 0 0 1 0 0 0 1 0 1 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=convert_df2uw(Rss):chop - - - - -80-N2040-36 B 525 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 0 1 0 0 0 1 1 1 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=convert_df2w(Rss):chop -1 0 0 0 1 0 1 1 0 1 1 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=convert_sf2uw(Rs) -1 0 0 0 1 0 1 1 0 1 1 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=convert_sf2uw(Rs):chop -1 0 0 0 1 0 1 1 1 0 0 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=convert_sf2w(Rs) -1 0 0 0 1 0 1 1 1 0 0 s s s s s P P - - - - - - 0 0 1 d d d d d Rd=convert_sf2w(Rs):chop - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 526 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point extreme value assistance - For divide and square root routines, certain values are problematic for the default routine. - These instructions appropriately fix up the numerator (fixupn), denominator (fixupd), or - radicand (fixupr) for proper calculations when combined with the divide or square root - approximation instructions. - - Syntax Behavior - Rd=sffixupd(Rs,Rt) (Rs,Rt,Rd,adjust)=recip_common(Rs,Rt); - Rd = Rt; - Rd=sffixupn(Rs,Rt) (Rs,Rt,Rd,adjust)=recip_common(Rs,Rt); - Rd = Rs; - Rd=sffixupr(Rs) (Rs,Rd,adjust)=invsqrt_common(Rs); - Rd = Rs; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=sffixupd(Rs,Rt) Word32 Q6_R_sffixupd_RR(Word32 Rs, Word32 - Rt) - Rd=sffixupn(Rs,Rt) Word32 Q6_R_sffixupn_RR(Word32 Rs, Word32 - Rt) - Rd=sffixupr(Rs) Word32 Q6_R_sffixupr_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 1 1 1 0 1 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=sffixupr(Rs) - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rd=sffixupn(Rs,Rt) -1 1 1 0 1 0 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d Rd=sffixupd(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - -80-N2040-36 B 527 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point fused multiply-add - Multiply two values, and add to (or subtract from) the accumulator. Full intermediate - precision is kept. - - Syntax Behavior - Rx+=sfmpy(Rs,Rt) Rx=fmaf(Rs,Rt,Rx); - Rx-=sfmpy(Rs,Rt) Rx=fmaf(-Rs,Rt,Rx); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rx+=sfmpy(Rs,Rt) Word32 Q6_R_sfmpyacc_RR(Word32 Rx, Word32 - Rs, Word32 Rt) - Rx-=sfmpy(Rs,Rt) Word32 Q6_R_sfmpynac_RR(Word32 Rx, Word32 - Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 0 0 x x x x x Rx+=sfmpy(Rs,Rt) -1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 0 1 x x x x x Rx-=sfmpy(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - - - - -80-N2040-36 B 528 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point fused multiply-add with scaling - Multiply two values, and add to (or subtract from) the accumulator. Full intermediate - precision is kept. Additionally, scale the output. This instruction has special handling of - corner cases. If a multiplicand source is zero, the accumulator is left unchanged; this is - important as -0.0 + 0.0*x yields -0.0. The scaling factor is the predicate taken as a two's - compliment number for single precision. The scaling factor is twice the predicate taken as - a two's compliment number for double precision. - - Syntax Behavior - Rx+=sfmpy(Rs,Rt,Pu):scale if (isnan(Rx) || isnan(Rs) || isnan(Rt)) Rx - = NaN; - ; - tmp=fmaf(Rs,Rt,Rx) * 2**(Pu); - if ((tmp != Rx) || ((Rs != 0.0) && (Rt != - 0.0))) Rx = tmp; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rx+=sfmpy(Rs,Rt,Pu):scale Word32 Q6_R_sfmpyacc_RRp_scale(Word32 Rx, - Word32 Rs, Word32 Rt, Byte Pu) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 u2 x5 - -1 1 1 0 1 1 1 1 0 1 1 s s s s s P P 0 t t t t t 1 u u x x x x x Rx+=sfmpy(Rs,Rt,Pu):scale - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - u2 Field to encode register u - x5 Field to encode register x - - - - -80-N2040-36 B 529 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point reciprocal square root approximation - Provides an approximation of the reciprocal square root of the radicand (Rs), if combined - with the appropriate fixup instruction. Certain values (such as infinities or zeros) in the - numerator or denominator may yield values that are not reciprocal approximations, but - yield the correct answer when combined with fixup instructions and the appropriate - routines. - - For compatibility, exact results of these instructions can not be relied on. The precision of - the approximation for this architecture and later is at least 6.6 bits. - - Syntax Behavior - Rd,Pe=sfinvsqrta(Rs) if ((Rs,Rd,adjust)=invsqrt_common(Rs)) { - Pe = adjust; - idx = (Rs >> 17) & 0x7f; - mant = (invsqrt_lut[idx] << 15); - exp = 127 - ((exponent(Rs) - 127) >> 1) - - 1; - Rd = -1**Rs.31 * 1.MANT * 2**(exp- - BIAS); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  This instruction provides a certain amount of accuracy. In future versions the - accuracy may increase. For future compatibility, dependence on exact values must - be avoided. -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse e2 d5 -1 0 0 0 1 0 1 1 1 1 1 s s s s s P P - - - - - - 0 e e d d d d d Rd,Pe=sfinvsqrta(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - e2 Field to encode register e - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 530 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point fused multiply-add for library routines - Multiply two values, and add to (or subtract from) the accumulator. Full intermediate - precision is kept. This instruction has special handling of corner cases. Addition of - infinities with opposite signs, or subtraction of infinities with like signs, is defined as - (positive) zero. Rounding is always Nearest-Even, except that overflows to infinity round - to maximal finite values. If a multiplicand source is zero, the accumulator is left - unchanged; this is important as -0.0 + 0.0*x yields -0.0. Flags and exceptions are not - generated. - - Syntax Behavior - Rx+=sfmpy(Rs,Rt):lib round_to_nearest(); - infminusinf = ((isinf(Rx)) && - (isinf(Rs*Rt)) && (Rs ^ Rx ^ Rt.31 != 0)); - infinp = (isinf(Rx)) || (isinf(Rt)) || - (isinf(Rs)); - if (isnan(Rx) || isnan(Rs) || isnan(Rt)) Rx - = NaN; - ; - if ((Rs != 0.0) && (Rt != 0.0)) { - Rx=fmaf(Rs,Rt,Rx); - } else { - if (isinf(Rs) || isinf(Rt)) Rx = NaN; - }; - cancel_flags(); - if (isinf(Rx) && !infinp) Rx = Rx - 1; - if (infminusinf) Rx = 0; - Rx-=sfmpy(Rs,Rt):lib round_to_nearest(); - infinp = (isinf(Rx)) || (isinf(Rt)) || - (isinf(Rs)); - infminusinf = ((isinf(Rx)) && - (isinf(Rs*Rt)) && (Rs ^ Rx ^ Rt.31 == 0)); - if (isnan(Rx) || isnan(Rs) || isnan(Rt)) Rx - = NaN; - ; - if ((Rs != 0.0) && (Rt != 0.0)) { - Rx=fmaf(-Rs,Rt,Rx); - } else { - if (isinf(Rs) || isinf(Rt)) Rx = NaN; - }; - cancel_flags(); - if (isinf(Rx) && !infinp) Rx = Rx - 1; - if (infminusinf) Rx = 0; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rx+=sfmpy(Rs,Rt):lib Word32 Q6_R_sfmpyacc_RR_lib(Word32 Rx, - Word32 Rs, Word32 Rt) - Rx-=sfmpy(Rs,Rt):lib Word32 Q6_R_sfmpynac_RR_lib(Word32 Rx, - Word32 Rs, Word32 Rt) - - - - -80-N2040-36 B 531 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x Rx+=sfmpy(Rs,Rt):lib -1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x Rx-=sfmpy(Rs,Rt):lib - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - - - - -80-N2040-36 B 532 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Create floating-point constant - Using ten bits of immediate, form a floating-point constant. - - Syntax Behavior - Rd=sfmake(#u10):neg Rd = (127 - 6) << 23; - Rd += (#u << 17); - Rd |= (1 << 31); - Rd=sfmake(#u10):pos Rd = (127 - 6) << 23; - Rd += #u << 17; - Rdd=dfmake(#u10):neg Rdd = (1023ULL - 6) << 52; - Rdd += (#u) << 46; - Rdd |= ((1ULL) << 63); - Rdd=dfmake(#u10):pos Rdd = (1023ULL - 6) << 52; - Rdd += (#u) << 46; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=sfmake(#u10):neg Word32 Q6_R_sfmake_I_neg(Word32 Iu10) - Rd=sfmake(#u10):pos Word32 Q6_R_sfmake_I_pos(Word32 Iu10) - Rdd=dfmake(#u10):neg Word64 Q6_P_dfmake_I_neg(Word32 Iu10) - Rdd=dfmake(#u10):pos Word64 Q6_P_dfmake_I_pos(Word32 Iu10) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Parse MinOp d5 -1 1 0 1 0 1 1 0 0 0 i - - - - - P P i i i i i i i i i d d d d d Rd=sfmake(#u10):pos -1 1 0 1 0 1 1 0 0 1 i - - - - - P P i i i i i i i i i d d d d d Rd=sfmake(#u10):neg - ICLASS RegType Parse d5 -1 1 0 1 1 0 0 1 0 0 i - - - - - P P i i i i i i i i i d d d d d Rdd=dfmake(#u10):pos -1 1 0 1 1 0 0 1 0 1 i - - - - - P P i i i i i i i i i d d d d d Rdd=dfmake(#u10):neg - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - - - - -80-N2040-36 B 533 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point maximum - Maximum of two floating point values. If one value is a NaN, the other is chosen. - - Syntax Behavior - Rd=sfmax(Rs,Rt) Rd = fmaxf(Rs,Rt); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=sfmax(Rs,Rt) Word32 Q6_R_sfmax_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rd=sfmax(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 534 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point minimum - Minimum of two floating point values. If one value is a NaN, the other is chosen. - - Syntax Behavior - Rd=sfmin(Rs,Rt) Rd = fmin(Rs,Rt); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=sfmin(Rs,Rt) Word32 Q6_R_sfmin_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d Rd=sfmin(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 535 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point multiply - Add two floating point values - - Syntax Behavior - Rd=sfmpy(Rs,Rt) Rd=Rs*Rt; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=sfmpy(Rs,Rt) Word32 Q6_R_sfmpy_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 1 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rd=sfmpy(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 536 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point reciprocal approximation - Provides an approximation of the reciprocal of the denominator (Rt), if combined with the - appropriate fixup instructions. Certain values (such as infinities or zeros) in the numerator - or denominator may yield values that are not reciprocal approximations, but yield the - correct answer when combined with fixup instructions and the appropriate routines. - - For compatibility, exact results of these instructions can not be relied on. The precision of - the approximation for this architecture and later is at least 6.6 bits. - - Syntax Behavior - Rd,Pe=sfrecipa(Rs,Rt) if ((Rs,Rt,Rd,adjust)=recip_common(Rs,Rt)) - { - Pe = adjust; - idx = (Rt >> 16) & 0x7f; - mant = (recip_lut[idx] << 15) | 1; - exp = 127 - (exponent(Rt) - 127) - 1; - Rd = -1**Rt.31 * 1.MANT * 2**(exp- - BIAS); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  This instruction provides a certain amount of accuracy. In future versions the - accuracy may increase. For future compatibility, dependence on exact values must - be avoided. -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 e2 d5 -1 1 1 0 1 0 1 1 1 1 1 s s s s s P P 0 t t t t t 1 e e d d d d d Rd,Pe=sfrecipa(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - e2 Field to encode register e - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 537 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Floating point subtraction - Subtract two floating point values. - - Syntax Behavior - Rd=sfsub(Rs,Rt) Rd=Rs-Rt; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=sfsub(Rs,Rt) Word32 Q6_R_sfsub_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d Rd=sfsub(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 538 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.10.5 XTYPE/MPY - The XTYPE/MPY instruction subclass includes instructions which perform - multiplication. - -Multiply and use lower result - Multiply the signed 32-bit integer in Rs by either the signed 32-bit integer in Rt or an - unsigned immediate value. The 64-bit result is optionally accumulated with the 32-bit - destination, or added to an immediate. The least-significant 32-bits of the result are written - to the single destination register. - - This multiply produces the correct results for the ANSI C multiplication of two signed or - unsigned integers with an integer result. - - - Rs - - - Rt /#u8 - - - - - * - 64 - - - Add - - - Low 32-bits 32 - - - - Rx - - - Syntax Behavior - Rd=+mpyi(Rs,#u8) apply_extension(#u); - Rd=Rs*#u; - Rd=-mpyi(Rs,#u8) Rd=Rs*-#u; - Rd=add(#u6,mpyi(Rs,#U6)) apply_extension(#u); - Rd = #u + Rs*#U; - Rd=add(#u6,mpyi(Rs,Rt)) apply_extension(#u); - Rd = #u + Rs*Rt; - Rd=add(Ru,mpyi(#u6:2,Rs)) Rd = Ru + Rs*#u; - Rd=add(Ru,mpyi(Rs,#u6)) apply_extension(#u); - Rd = Ru + Rs*#u; - - - - -80-N2040-36 B 539 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rd=mpyi(Rs,#m9) if ("((#m9<0) && (#m9>-256))") { - Assembler mapped to: "Rd=- - mpyi(Rs,#m9*(-1))"; - } else { - Assembler mapped to: - "Rd=+mpyi(Rs,#m9)"; - }; - Rd=mpyi(Rs,Rt) Rd=Rs*Rt; - Rd=mpyui(Rs,Rt) Assembler mapped to: "Rd=mpyi(Rs,Rt)" - Rx+=mpyi(Rs,#u8) apply_extension(#u); - Rx=Rx + (Rs*#u); - Rx+=mpyi(Rs,Rt) Rx=Rx + Rs*Rt; - Rx-=mpyi(Rs,#u8) apply_extension(#u); - Rx=Rx - (Rs*#u); - Ry=add(Ru,mpyi(Ry,Rs)) Ry = Ru + Rs*Ry; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rd=add(#u6,mpyi(Rs,#U6)) Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 - Rs, Word32 IU6) - Rd=add(#u6,mpyi(Rs,Rt)) Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 - Rs, Word32 Rt) - Rd=add(Ru,mpyi(#u6:2,Rs)) Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 - Iu6_2, Word32 Rs) - Rd=add(Ru,mpyi(Rs,#u6)) Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 - Rs, Word32 Iu6) - Rd=mpyi(Rs,#m9) Word32 Q6_R_mpyi_RI(Word32 Rs, Word32 Im9) - Rd=mpyi(Rs,Rt) Word32 Q6_R_mpyi_RR(Word32 Rs, Word32 Rt) - Rd=mpyui(Rs,Rt) Word32 Q6_R_mpyui_RR(Word32 Rs, Word32 Rt) - Rx+=mpyi(Rs,#u8) Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 - Rs, Word32 Iu8) - Rx+=mpyi(Rs,Rt) Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 - Rs, Word32 Rt) - Rx-=mpyi(Rs,#u8) Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 - Rs, Word32 Iu8) - Ry=add(Ru,mpyi(Ry,Rs)) Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 - Ry, Word32 Rs) - - - - -80-N2040-36 B 540 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d5 -1 1 0 1 0 1 1 1 0 i i s s s s s P P i t t t t t i i i d d d d d Rd=add(#u6,mpyi(Rs,Rt)) - ICLASS RegType s5 Parse d5 -1 1 0 1 1 0 0 0 I i i s s s s s P P i d d d d d i i i I I I I I Rd=add(#u6,mpyi(Rs,#U6)) - ICLASS RegType s5 Parse d5 u5 -1 1 0 1 1 1 1 1 0 i i s s s s s P P i d d d d d i i i u u u u u Rd=add(Ru,mpyi(#u6:2,Rs)) -1 1 0 1 1 1 1 1 1 i i s s s s s P P i d d d d d i i i u u u u u Rd=add(Ru,mpyi(Rs,#u6)) - ICLASS RegType MajOp s5 Parse y5 u5 -1 1 1 0 0 0 1 1 0 0 0 s s s s s P P - y y y y y - - - u u u u u Ry=add(Ru,mpyi(Ry,Rs)) - ICLASS RegType MajOp s5 Parse MinOp d5 -1 1 1 0 0 0 0 0 0 - - s s s s s P P 0 i i i i i i i i d d d d d Rd=+mpyi(Rs,#u8) -1 1 1 0 0 0 0 0 1 - - s s s s s P P 0 i i i i i i i i d d d d d Rd=-mpyi(Rs,#u8) - ICLASS RegType MajOp s5 Parse MinOp x5 -1 1 1 0 0 0 0 1 0 - - s s s s s P P 0 i i i i i i i i x x x x x Rx+=mpyi(Rs,#u8) -1 1 1 0 0 0 0 1 1 - - s s s s s P P 0 i i i i i i i i x x x x x Rx-=mpyi(Rs,#u8) - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 1 0 1 0 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rd=mpyi(Rs,Rt) - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x Rx+=mpyi(Rs,Rt) - - - - - Field name Description - RegType Register Type - MajOp Major Opcode - MinOp Minor Opcode - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u5 Field to encode register u - x5 Field to encode register x - y5 Field to encode register y - - - - -80-N2040-36 B 541 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector multiply word by signed half (32x16) - Perform mixed precision vector multiply operations. A 32-bit word from vector Rss is - multiplied by a 16-bit halfword (either even or odd) from vector Rtt. The multiplication is - performed as a signed 32x16, which produces a 48-bit result. This result is optionally - scaled left by one bit. This result is then shifted right by 16 bits, optionally accumulated - and then saturated to 32-bits. This operation is available in vector form - (vmpyweh/vmpywoh) and non-vector form (mpyweh/mpywoh). - - s16 s16 s16 s16 Rtt - - - - mux mux - - - s32 s32 Rss - - - - * * - 48 0x0 0x8000 48 0x0 0x8000 - - <<0-1 <<0-1 - mux mux - - - - - Add Add - - >>16 >>16 - - - Add Add - - - Sat_32 Sat_32 32 - - - - 32 - - - - - Rxx - - - - -80-N2040-36 B 542 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - Rdd=vmpyweh(Rss,Rtt)[:<<1]:rnd:sat Rdd.w[1]=sat32(((Rss.w[1] * - Rtt.h[2])[<<1]+0x8000)>>16); - Rdd.w[0]=sat32(((Rss.w[0] * - Rtt.h[0])[<<1]+0x8000)>>16); - Rdd=vmpyweh(Rss,Rtt)[:<<1]:sat Rdd.w[1]=sat32(((Rss.w[1] * - Rtt.h[2])[<<1])>>16); - Rdd.w[0]=sat32(((Rss.w[0] * - Rtt.h[0])[<<1])>>16); - Rdd=vmpywoh(Rss,Rtt)[:<<1]:rnd:sat Rdd.w[1]=sat32(((Rss.w[1] * - Rtt.h[3])[<<1]+0x8000)>>16); - Rdd.w[0]=sat32(((Rss.w[0] * - Rtt.h[1])[<<1]+0x8000)>>16); - Rdd=vmpywoh(Rss,Rtt)[:<<1]:sat Rdd.w[1]=sat32(((Rss.w[1] * - Rtt.h[3])[<<1])>>16); - Rdd.w[0]=sat32(((Rss.w[0] * - Rtt.h[1])[<<1])>>16); - Rxx+=vmpyweh(Rss,Rtt)[:<<1]:rnd:sat Rxx.w[1]=sat32(Rxx.w[1] + (((Rss.w[1] * - Rtt.h[2])[<<1]+0x8000)>>16)); - Rxx.w[0]=sat32(Rxx.w[0] + (((Rss.w[0] * - Rtt.h[0])[<<1]+0x8000)>>16)); - Rxx+=vmpyweh(Rss,Rtt)[:<<1]:sat Rxx.w[1]=sat32(Rxx.w[1] + (((Rss.w[1] * - Rtt.h[2])[<<1])>>16)); - Rxx.w[0]=sat32(Rxx.w[0] + (((Rss.w[0] * - Rtt.h[0])[<<1])>>16)); - Rxx+=vmpywoh(Rss,Rtt)[:<<1]:rnd:sat Rxx.w[1]=sat32(Rxx.w[1] + (((Rss.w[1] * - Rtt.h[3])[<<1]+0x8000)>>16)); - Rxx.w[0]=sat32(Rxx.w[0] + (((Rss.w[0] * - Rtt.h[1])[<<1]+0x8000)>>16 )); - Rxx+=vmpywoh(Rss,Rtt)[:<<1]:sat Rxx.w[1]=sat32(Rxx.w[1] + (((Rss.w[1] * - Rtt.h[3])[<<1])>>16)); - Rxx.w[0]=sat32(Rxx.w[0] + (((Rss.w[0] * - Rtt.h[1])[<<1])>>16 )); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - - - -80-N2040-36 B 543 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rdd=vmpyweh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 - Rss, Word64 Rtt) - Rdd=vmpyweh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpyweh_PP_s1_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpyweh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpyweh_PP_rnd_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpyweh(Rss,Rtt):sat Word64 Q6_P_vmpyweh_PP_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpywoh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 - Rss, Word64 Rtt) - Rdd=vmpywoh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywoh_PP_s1_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpywoh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywoh_PP_rnd_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpywoh(Rss,Rtt):sat Word64 Q6_P_vmpywoh_PP_sat(Word64 Rss, - Word64 Rtt) - Rxx+=vmpyweh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpyweh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpyweh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpyweh(Rss,Rtt):sat Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, - Word64 Rss, Word64 Rtt) - Rxx+=vmpywoh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpywoh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpywoh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpywoh(Rss,Rtt):sat Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, - Word64 Rss, Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 - -1 1 1 0 1 0 0 0 N 0 0 s s s s s P P 0 t t t t t 1 0 1 d d d d d Rdd=vmpyweh(Rss,Rtt)[:<>16 >>16 - - - Add Add - - - Sat_32 Sat_32 32 - - - - 32 - - - - - Rxx - - - - -80-N2040-36 B 546 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - Rdd=vmpyweuh(Rss,Rtt)[:<<1]:rnd:sat Rdd.w[1]=sat32(((Rss.w[1] * - Rtt.uh[2])[<<1]+0x8000)>>16); - Rdd.w[0]=sat32(((Rss.w[0] * - Rtt.uh[0])[<<1]+0x8000)>>16); - Rdd=vmpyweuh(Rss,Rtt)[:<<1]:sat Rdd.w[1]=sat32(((Rss.w[1] * - Rtt.uh[2])[<<1])>>16); - Rdd.w[0]=sat32(((Rss.w[0] * - Rtt.uh[0])[<<1])>>16); - Rdd=vmpywouh(Rss,Rtt)[:<<1]:rnd:sat Rdd.w[1]=sat32(((Rss.w[1] * - Rtt.uh[3])[<<1]+0x8000)>>16); - Rdd.w[0]=sat32(((Rss.w[0] * - Rtt.uh[1])[<<1]+0x8000)>>16); - Rdd=vmpywouh(Rss,Rtt)[:<<1]:sat Rdd.w[1]=sat32(((Rss.w[1] * - Rtt.uh[3])[<<1])>>16); - Rdd.w[0]=sat32(((Rss.w[0] * - Rtt.uh[1])[<<1])>>16); - Rxx+=vmpyweuh(Rss,Rtt)[:<<1]:rnd:sat Rxx.w[1]=sat32(Rxx.w[1] + (((Rss.w[1] * - Rtt.uh[2])[<<1]+0x8000)>>16)); - Rxx.w[0]=sat32(Rxx.w[0] + (((Rss.w[0] * - Rtt.uh[0])[<<1]+0x8000)>>16)); - Rxx+=vmpyweuh(Rss,Rtt)[:<<1]:sat Rxx.w[1]=sat32(Rxx.w[1] + (((Rss.w[1] * - Rtt.uh[2])[<<1])>>16)); - Rxx.w[0]=sat32(Rxx.w[0] + (((Rss.w[0] * - Rtt.uh[0])[<<1])>>16)); - Rxx+=vmpywouh(Rss,Rtt)[:<<1]:rnd:sat Rxx.w[1]=sat32(Rxx.w[1] + (((Rss.w[1] * - Rtt.uh[3])[<<1]+0x8000)>>16)); - Rxx.w[0]=sat32(Rxx.w[0] + (((Rss.w[0] * - Rtt.uh[1])[<<1]+0x8000)>>16 )); - Rxx+=vmpywouh(Rss,Rtt)[:<<1]:sat Rxx.w[1]=sat32(Rxx.w[1] + (((Rss.w[1] * - Rtt.uh[3])[<<1])>>16)); - Rxx.w[0]=sat32(Rxx.w[0] + (((Rss.w[0] * - Rtt.uh[1])[<<1])>>16 )); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - - - -80-N2040-36 B 547 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rdd=vmpyweuh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 - Rss, Word64 Rtt) - Rdd=vmpyweuh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpyweuh_PP_s1_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpyweuh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpyweuh(Rss,Rtt):sat Word64 Q6_P_vmpyweuh_PP_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpywouh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 - Rss, Word64 Rtt) - Rdd=vmpywouh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywouh_PP_s1_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpywouh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, - Word64 Rtt) - Rdd=vmpywouh(Rss,Rtt):sat Word64 Q6_P_vmpywouh_PP_sat(Word64 Rss, - Word64 Rtt) - Rxx+=vmpyweuh(Rss,Rtt):<<1:rnd:sat Word64 - Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, - Word64 Rss, Word64 Rtt) - Rxx+=vmpyweuh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpyweuh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpyweuh(Rss,Rtt):sat Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, - Word64 Rss, Word64 Rtt) - Rxx+=vmpywouh(Rss,Rtt):<<1:rnd:sat Word64 - Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, - Word64 Rss, Word64 Rtt) - Rxx+=vmpywouh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpywouh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 - Rxx, Word64 Rss, Word64 Rtt) - Rxx+=vmpywouh(Rss,Rtt):sat Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, - Word64 Rss, Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 0 0 N 1 0 s s s s s P P 0 t t t t t 1 0 1 d d d d d Rdd=vmpyweuh(Rss,Rtt)[:<> i) & 1) prod ^= (x << i); - }; - Rdd = prod; - Rxx^=pmpyw(Rs,Rt) x = Rs.uw[0]; - y = Rt.uw[0]; - prod = 0; - for(i=0; i < 32; i++) { - if((y >> i) & 1) prod ^= (x << i); - }; - Rxx ^= prod; - - - - -80-N2040-36 B 563 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rdd=pmpyw(Rs,Rt) Word64 Q6_P_pmpyw_RR(Word32 Rs, Word32 Rt) - Rxx^=pmpyw(Rs,Rt) Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 - Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 0 1 0 1 0 1 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d Rdd=pmpyw(Rs,Rt) - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 0 1 1 1 0 0 1 s s s s s P P 0 t t t t t 1 1 1 x x x x x Rxx^=pmpyw(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - - - - -80-N2040-36 B 564 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector reduce multiply word by signed half (32x16) - Perform mixed precision vector multiply operations and accumulate the results. A 32-bit - word from vector Rss is multiplied by a 16-bit halfword (either even or odd) from vector - Rtt. The multiplication is performed as a signed 32x16, which produces a 48-bit result. - This result is optionally scaled left by one bit. A similar operation is performed for both - words in Rss, and the two results are accumulated. The final result is optionally - accumulated with Rxx. - - - s16 s16 s16 s16 Rtt - - - - mux mux - - - s32 s32 Rss - - - - * * - 48 48 - - - <<0-1 <<0-1 - - - - - Add - - - - - Rxx - - - Syntax Behavior - Rdd=vrmpyweh(Rss,Rtt)[:<<1] Rdd = (Rss.w[1] * Rtt.h[2])[<<1] + - (Rss.w[0] * Rtt.h[0])[<<1]; - Rdd=vrmpywoh(Rss,Rtt)[:<<1] Rdd = (Rss.w[1] * Rtt.h[3])[<<1] + - (Rss.w[0] * Rtt.h[1])[<<1]; - Rxx+=vrmpyweh(Rss,Rtt)[:<<1] Rxx += (Rss.w[1] * Rtt.h[2])[<<1] + - (Rss.w[0] * Rtt.h[0])[<<1]; - Rxx+=vrmpywoh(Rss,Rtt)[:<<1] Rxx += (Rss.w[1] * Rtt.h[3])[<<1] + - (Rss.w[0] * Rtt.h[1])[<<1]; - - - - -80-N2040-36 B 565 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rdd=vrmpyweh(Rss,Rtt) Word64 Q6_P_vrmpyweh_PP(Word64 Rss, Word64 - Rtt) - Rdd=vrmpyweh(Rss,Rtt):<<1 Word64 Q6_P_vrmpyweh_PP_s1(Word64 Rss, - Word64 Rtt) - Rdd=vrmpywoh(Rss,Rtt) Word64 Q6_P_vrmpywoh_PP(Word64 Rss, Word64 - Rtt) - Rdd=vrmpywoh(Rss,Rtt):<<1 Word64 Q6_P_vrmpywoh_PP_s1(Word64 Rss, - Word64 Rtt) - Rxx+=vrmpyweh(Rss,Rtt) Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, - Word64 Rss, Word64 Rtt) - Rxx+=vrmpyweh(Rss,Rtt):<<1 Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, - Word64 Rss, Word64 Rtt) - Rxx+=vrmpywoh(Rss,Rtt) Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, - Word64 Rss, Word64 Rtt) - Rxx+=vrmpywoh(Rss,Rtt):<<1 Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, - Word64 Rss, Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 0 0 0 N 0 1 s s s s s P P 0 t t t t t 0 1 0 d d d d d Rdd=vrmpywoh(Rss,Rtt)[:<>16); - Rd=mpy(Rs,Rt.H):<<1:sat Rd = sat32(((Rs * Rt.h[1])<<1)>>16); - Rd=mpy(Rs,Rt.L):<<1:rnd:sat Rd = sat32(((Rs * Rt.h[0])<<1+0x8000)>>16); - Rd=mpy(Rs,Rt.L):<<1:sat Rd = sat32(((Rs * Rt.h[0])<<1)>>16); - Rd=mpy(Rs,Rt) Rd=(Rs * Rt)>>32; - Rd=mpy(Rs,Rt):<<1 Rd=(Rs * Rt)>>31; - Rd=mpy(Rs,Rt):<<1:sat Rd=sat32((Rs * Rt)>>31); - Rd=mpy(Rs,Rt):rnd Rd=((Rs * Rt)+0x80000000)>>32; - Rd=mpysu(Rs,Rt) Rd=(Rs * Rt.uw[0])>>32; - Rd=mpyu(Rs,Rt) Rd=(Rs.uw[0] * Rt.uw[0])>>32; - Rx+=mpy(Rs,Rt):<<1:sat Rx=sat32((Rx) + ((Rs * Rt)>>31)); - Rx-=mpy(Rs,Rt):<<1:sat Rx=sat32((Rx) - ((Rs * Rt)>>31)); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), then the OVF bit in the Status Register is - set. OVF will remain set until explicitly cleared by a transfer to SR. - - - - -80-N2040-36 B 567 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rd=mpy(Rs,Rt.H):<<1:rnd:sat Word32 Q6_R_mpy_RRh_s1_rnd_sat(Word32 Rs, - Word32 Rt) - Rd=mpy(Rs,Rt.H):<<1:sat Word32 Q6_R_mpy_RRh_s1_sat(Word32 Rs, - Word32 Rt) - Rd=mpy(Rs,Rt.L):<<1:rnd:sat Word32 Q6_R_mpy_RRl_s1_rnd_sat(Word32 Rs, - Word32 Rt) - Rd=mpy(Rs,Rt.L):<<1:sat Word32 Q6_R_mpy_RRl_s1_sat(Word32 Rs, - Word32 Rt) - Rd=mpy(Rs,Rt) Word32 Q6_R_mpy_RR(Word32 Rs, Word32 Rt) - Rd=mpy(Rs,Rt):<<1 Word32 Q6_R_mpy_RR_s1(Word32 Rs, Word32 Rt) - Rd=mpy(Rs,Rt):<<1:sat Word32 Q6_R_mpy_RR_s1_sat(Word32 Rs, Word32 - Rt) - Rd=mpy(Rs,Rt):rnd Word32 Q6_R_mpy_RR_rnd(Word32 Rs, Word32 - Rt) - Rd=mpysu(Rs,Rt) Word32 Q6_R_mpysu_RR(Word32 Rs, Word32 Rt) - Rd=mpyu(Rs,Rt) UWord32 Q6_R_mpyu_RR(Word32 Rs, Word32 Rt) - Rx+=mpy(Rs,Rt):<<1:sat Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, - Word32 Rs, Word32 Rt) - Rx-=mpy(Rs,Rt):<<1:sat Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, - Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 1 1 0 1 0 0 1 s s s s s P P 0 t t t t t 0 0 1 d d d d d Rd=mpy(Rs,Rt):rnd -1 1 1 0 1 1 0 1 0 1 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d Rd=mpyu(Rs,Rt) -1 1 1 0 1 1 0 1 0 1 1 s s s s s P P 0 t t t t t 0 0 1 d d d d d Rd=mpysu(Rs,Rt) -1 1 1 0 1 1 0 1 1 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rd=mpy(Rs,Rt.H):<<1:sat -1 1 1 0 1 1 0 1 1 0 1 s s s s s P P 0 t t t t t 0 0 1 d d d d d Rd=mpy(Rs,Rt.L):<<1:sat -1 1 1 0 1 1 0 1 1 0 1 s s s s s P P 0 t t t t t 1 0 0 d d d d d Rd=mpy(Rs,Rt.H):<<1:rnd:sat -1 1 1 0 1 1 0 1 1 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d Rd=mpy(Rs,Rt):<<1:sat -1 1 1 0 1 1 0 1 1 1 1 s s s s s P P 0 t t t t t 1 0 0 d d d d d Rd=mpy(Rs,Rt.L):<<1:rnd:sat -1 1 1 0 1 1 0 1 N 0 N s s s s s P P 0 t t t t t 0 N N d d d d d Rd=mpy(Rs,Rt)[:<> i) & 1) prod0 ^= (x0 << i); - if((y1 >> i) & 1) prod1 ^= (x1 << i); - }; - Rdd.h[0]=prod0.uh[0]; - Rdd.h[1]=prod1.uh[0]; - Rdd.h[2]=prod0.uh[1]; - Rdd.h[3]=prod1.uh[1]; - Rxx^=vpmpyh(Rs,Rt) x0 = Rs.uh[0]; - x1 = Rs.uh[1]; - y0 = Rt.uh[0]; - y1 = Rt.uh[1]; - prod0 = prod1 = 0; - for(i=0; i < 16; i++) { - if((y0 >> i) & 1) prod0 ^= (x0 << i); - if((y1 >> i) & 1) prod1 ^= (x1 << i); - }; - Rxx.h[0]=Rxx.uh[0] ^ prod0.uh[0]; - Rxx.h[1]=Rxx.uh[1] ^ prod1.uh[0]; - Rxx.h[2]=Rxx.uh[2] ^ prod0.uh[1]; - Rxx.h[3]=Rxx.uh[3] ^ prod1.uh[1]; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vpmpyh(Rs,Rt) Word64 Q6_P_vpmpyh_RR(Word32 Rs, Word32 Rt) - Rxx^=vpmpyh(Rs,Rt) Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, - Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse t5 MinOp d5 -1 1 1 0 0 1 0 1 1 1 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d Rdd=vpmpyh(Rs,Rt) - ICLASS RegType MajOp s5 Parse t5 MinOp x5 -1 1 1 0 0 1 1 1 1 0 1 s s s s s P P 0 t t t t t 1 1 1 x x x x x Rxx^=vpmpyh(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - Parse Packet/Loop parse bits - d5 Field to encode register d - - - - -80-N2040-36 B 595 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - s5 Field to encode register s - t5 Field to encode register t - x5 Field to encode register x - - - - -80-N2040-36 B 596 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.10.6 XTYPE/PERM - The XTYPE/PERM instruction subclass includes instructions which perform - permutations. - -CABAC decode bin - This is a special-purpose instruction to support H.264 Context Adaptive Binary - Arithmetic Coding (CABAC). See Section 4.8.1 for a complete description. - - Syntax Behavior - Rdd=decbin(Rss,Rtt) state = Rtt.w[1][5:0]; - valMPS = Rtt.w[1][8:8]; - bitpos = Rtt.w[0][4:0]; - range = Rss.w[0]; - offset = Rss.w[1]; - range <<= bitpos; - offset <<= bitpos; - rLPS = rLPS_table_64x4[state][ (range - >>29)&3]; - rLPS = rLPS << 23; - rMPS= (range&0xff800000) - rLPS; - if (offset < rMPS) { - Rdd = AC_next_state_MPS_64[state]; - Rdd[8:8]=valMPS; - Rdd[31:23]=(rMPS>>23); - Rdd.w[1]=offset; - P0=valMPS; - } else { - Rdd = AC_next_state_LPS_64[state]; - Rdd[8:8]=((!state)?(1- - valMPS):(valMPS)); - Rdd[31:23]=(rLPS>>23); - Rdd.w[1]=(offset-rMPS); - P0=(valMPS^1); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 0 1 1 1 - s s s s s P P - t t t t t 1 1 - d d d d d Rdd=decbin(Rss,Rtt) - - - - -80-N2040-36 B 597 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 598 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Saturate - Saturate a single scalar value. - - sath saturates a signed 32-bit number to a signed 16-bit number, which is sign-extended - back to 32 bits and placed in the destination register. The minimum negative value of the - result is 0xffff8000 and the maximum positive value is 0x00007fff. - - satuh saturates a signed 32-bit number to an unsigned 16-bit number, which is zero- - extended back to 32 bits and placed in the destination register. The minimum value of the - result is 0 and the maximum value is 0x0000ffff. - - satb saturates a signed 32-bit number to an signed 8-bit number, which is sign-extended - back to 32 bits and placed in the destination register. The minimum value of the result is - 0xffffff80 and the maximum value is 0x0000007f. - - satub saturates a signed 32-bit number to an unsigned 8-bit number, which is zero- - extended back to 32 bits and placed in the destination register. The minimum value of the - result is 0 and the maximum value is 0x000000ff. - - Syntax Behavior - Rd=sat(Rss) Rd = sat32(Rss); - Rd=satb(Rs) Rd = sat8(Rs); - Rd=sath(Rs) Rd = sat16(Rs); - Rd=satub(Rs) Rd = usat8(Rs); - Rd=satuh(Rs) Rd = usat16(Rs); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=sat(Rss) Word32 Q6_R_sat_P(Word64 Rss) - Rd=satb(Rs) Word32 Q6_R_satb_R(Word32 Rs) - Rd=sath(Rs) Word32 Q6_R_sath_R(Word32 Rs) - Rd=satub(Rs) Word32 Q6_R_satub_R(Word32 Rs) - Rd=satuh(Rs) Word32 Q6_R_satuh_R(Word32 Rs) - - - - -80-N2040-36 B 599 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 1 1 0 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=sat(Rss) -1 0 0 0 1 1 0 0 1 1 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rd=sath(Rs) -1 0 0 0 1 1 0 0 1 1 0 s s s s s P P - - - - - - 1 0 1 d d d d d Rd=satuh(Rs) -1 0 0 0 1 1 0 0 1 1 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rd=satub(Rs) -1 0 0 0 1 1 0 0 1 1 0 s s s s s P P - - - - - - 1 1 1 d d d d d Rd=satb(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 600 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Swizzle bytes - Swizzle the bytes of a word. This instruction is useful in converting between little and big - endian formats. - - - Rd=swiz(Rs) - Rs - - - - Rd - - - Syntax Behavior - Rd=swiz(Rs) Rd.b[0]=Rs.b[3]; - Rd.b[1]=Rs.b[2]; - Rd.b[2]=Rs.b[1]; - Rd.b[3]=Rs.b[0]; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=swiz(Rs) Word32 Q6_R_swiz_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - 1 1 1 d d d d d Rd=swiz(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 601 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector align - Align a vector. Use the immediate amount, or the least significant 3 bits of a Predicate - register, as the number of bytes to align. Shift the Rss register pair right by this number of - bytes. Fill the vacated positions with the least significant elements from Rtt. - - - #u3/P - - - Rtt Rss - - - - Rdd - - - Syntax Behavior - Rdd=valignb(Rtt,Rss,#u3) Rdd = (Rss >>> #u*8)|(Rtt << ((8-#u)*8)); - Rdd=valignb(Rtt,Rss,Pu) Rdd = Rss >>> (Pu&0x7)*8|(Rtt << (8- - (Pu&0x7))*8); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=valignb(Rtt,Rss,#u3) Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 - Rss, Word32 Iu3) - Rdd=valignb(Rtt,Rss,Pu) Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 - Rss, Byte Pu) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 0 0 0 - - s s s s s P P - t t t t t i i i d d d d d Rdd=valignb(Rtt,Rss,#u3) - ICLASS RegType Maj s5 Parse t5 u2 d5 -1 1 0 0 0 0 1 0 0 - - s s s s s P P - t t t t t - u u d d d d d Rdd=valignb(Rtt,Rss,Pu) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u2 Field to encode register u - - - - -80-N2040-36 B 602 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 603 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector round and pack - Add the constant 0x00008000 to each word in the 64-bit source vector Rss. Optionally - saturate this addition to 32bits. Pack the high halfwords of the result into the - corresponding halfword of the 32-bit destination register. - - - Rss.w[1] Rss.w[0] Rss - - - - 0x8000 0x8000 - - 32-bit Add 32-bit Add - - - - - Rd.h[1] Rd.h[0] Rd - - - Syntax Behavior - Rd=vrndwh(Rss) for (i=0;i<2;i++) { - Rd.h[i]=(Rss.w[i]+0x08000).h[1]; - }; - Rd=vrndwh(Rss):sat for (i=0;i<2;i++) { - Rd.h[i]=sat32(Rss.w[i]+0x08000).h[1]; - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=vrndwh(Rss) Word32 Q6_R_vrndwh_P(Word64 Rss) - Rd=vrndwh(Rss):sat Word32 Q6_R_vrndwh_P_sat(Word64 Rss) - - - - -80-N2040-36 B 604 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rd=vrndwh(Rss) -1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rd=vrndwh(Rss):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 605 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector saturate and pack - For each element in the vector, saturate the value to the next smaller size. VSATHUB - saturates signed halfwords to unsigned bytes, while VSATHB saturates signed halfwords - to signed bytes. - - - Rd=vsathub(Rss) Rd=vsathub(Rs) - - s16 s16 s16 s16 s16 s16 Rs - Rss - - Sat_u8 Sat_u8 - Sat_u8 Sat_u8 Sat_u8 Sat_u8 - - - - u8 u8 u8 u8 Rd 0 0 u8 u8 Rd - - - Rd=vsathb(Rss) Rd=vsathb(Rs) - s16 s16 s16 s16 Rss s16 s16 Rs - - - Sat_s8 Sat_s8 Sat_s8 Sat_s8 Sat_s8 Sat_s8 - - - - s8 s8 s8 s8 Rd 0 0 s8 s8 Rd - - - VSATWH saturates signed words to signed halfwords, while VSATWUH saturates signed - words to unsigned halfwords. The resulting values are packed together into destination - register Rd. - - - Rd=vsathwh(Rss) Rd=vsathwuh(Rss) - s32 s32 Rss s32 s32 Rss - - Sat_s16 Sat_s16 Sat_u16 - Sat_u16 - - s16 s16 Rd u16 u16 Rd - - - - -80-N2040-36 B 606 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Syntax Behavior - Rd=vsathb(Rs) Rd.b[0]=sat8(Rs.h[0]); - Rd.b[1]=sat8(Rs.h[1]); - Rd.b[2]=0; - Rd.b[3]=0; - Rd=vsathb(Rss) for (i=0;i<4;i++) { - Rd.b[i]=sat8(Rss.h[i]); - }; - Rd=vsathub(Rs) Rd.b[0]=usat8(Rs.h[0]); - Rd.b[1]=usat8(Rs.h[1]); - Rd.b[2]=0; - Rd.b[3]=0; - Rd=vsathub(Rss) for (i=0;i<4;i++) { - Rd.b[i]=usat8(Rss.h[i]); - }; - Rd=vsatwh(Rss) for (i=0;i<2;i++) { - Rd.h[i]=sat16(Rss.w[i]); - }; - Rd=vsatwuh(Rss) for (i=0;i<2;i++) { - Rd.h[i]=usat16(Rss.w[i]); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=vsathb(Rs) Word32 Q6_R_vsathb_R(Word32 Rs) - Rd=vsathb(Rss) Word32 Q6_R_vsathb_P(Word64 Rss) - Rd=vsathub(Rs) Word32 Q6_R_vsathub_R(Word32 Rs) - Rd=vsathub(Rss) Word32 Q6_R_vsathub_P(Word64 Rss) - Rd=vsatwh(Rss) Word32 Q6_R_vsatwh_P(Word64 Rss) - Rd=vsatwuh(Rss) Word32 Q6_R_vsatwuh_P(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=vsathub(Rss) - - - - -80-N2040-36 B 607 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 0 1 0 d d d d d Rd=vsatwh(Rss) -1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rd=vsatwuh(Rss) -1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rd=vsathb(Rss) -1 0 0 0 1 1 0 0 1 0 - s s s s s P P - - - - - - 0 0 - d d d d d Rd=vsathb(Rs) -1 0 0 0 1 1 0 0 1 0 - s s s s s P P - - - - - - 0 1 - d d d d d Rd=vsathub(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 608 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector saturate without pack - Saturate each element of source vector Rss to the next smaller size. VSATHUB saturates - signed halfwords to unsigned bytes. VSATWH saturates signed words to signed - halfwords, and VSATWUH saturates signed words to unsigned halfwords. The resulting - values are placed in destination register Rdd in unpacked form. - - - Rdd=vsathub(Rss) - - s16 s16 s16 s16 Rss - - - - Sat_u8 Sat_u8 Sat_u8 Sat_u8 - - - - - 0 u8 0 u8 0 u8 0 u8 Rdd - - - - - Rdd=vsathb(Rss) - - s16 s16 s16 s16 Rss - - - - Sat_s8 Sat_s8 Sat_s8 Sat_s8 - - - - - se se se se - s8 s8 s8 s8 Rdd - - - Syntax Behavior - Rdd=vsathb(Rss) for (i=0;i<4;i++) { - Rdd.h[i]=sat8(Rss.h[i]); - }; - Rdd=vsathub(Rss) for (i=0;i<4;i++) { - Rdd.h[i]=usat8(Rss.h[i]); - }; - Rdd=vsatwh(Rss) for (i=0;i<2;i++) { - Rdd.w[i]=sat16(Rss.w[i]); - }; - Rdd=vsatwuh(Rss) for (i=0;i<2;i++) { - Rdd.w[i]=usat16(Rss.w[i]); - }; - - - - -80-N2040-36 B 609 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rdd=vsathb(Rss) Word64 Q6_P_vsathb_P(Word64 Rss) - Rdd=vsathub(Rss) Word64 Q6_P_vsathub_P(Word64 Rss) - Rdd=vsatwh(Rss) Word64 Q6_P_vsatwh_P(Word64 Rss) - Rdd=vsatwuh(Rss) Word64 Q6_P_vsatwuh_P(Word64 Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d Rdd=vsathub(Rss) -1 0 0 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - 1 0 1 d d d d d Rdd=vsatwuh(Rss) -1 0 0 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d Rdd=vsatwh(Rss) -1 0 0 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - 1 1 1 d d d d d Rdd=vsathb(Rss) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 610 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector shuffle - Shuffle odd halfwords (shuffoh) takes the odd halfwords from Rtt and the odd halfwords - from Rss and merges them together into vector Rdd. Shuffle even halfwords (shuffeh) - performs the same operation on every even halfword in Rss and Rtt. The same operation is - available for odd and even bytes. - - shuffoh shuffeh - Rtt Rss - - - Rss Rtt - - - - - Rdd Rdd - - - - shuffob shuffeb - Rtt Rss - - - Rss Rtt - - - - - Rdd Rdd - - - Syntax Behavior - Rdd=shuffeb(Rss,Rtt) for (i=0;i<4;i++) { - Rdd.b[i*2]=Rtt.b[i*2]; - Rdd.b[i*2+1]=Rss.b[i*2]; - }; - Rdd=shuffeh(Rss,Rtt) for (i=0;i<2;i++) { - Rdd.h[i*2]=Rtt.h[i*2]; - Rdd.h[i*2+1]=Rss.h[i*2]; - }; - Rdd=shuffob(Rtt,Rss) for (i=0;i<4;i++) { - Rdd.b[i*2]=Rss.b[i*2+1]; - Rdd.b[i*2+1]=Rtt.b[i*2+1]; - }; - Rdd=shuffoh(Rtt,Rss) for (i=0;i<2;i++) { - Rdd.h[i*2]=Rss.h[i*2+1]; - Rdd.h[i*2+1]=Rtt.h[i*2+1]; - }; - - - - -80-N2040-36 B 611 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rdd=shuffeb(Rss,Rtt) Word64 Q6_P_shuffeb_PP(Word64 Rss, Word64 - Rtt) - Rdd=shuffeh(Rss,Rtt) Word64 Q6_P_shuffeh_PP(Word64 Rss, Word64 - Rtt) - Rdd=shuffob(Rtt,Rss) Word64 Q6_P_shuffob_PP(Word64 Rtt, Word64 - Rss) - Rdd=shuffoh(Rtt,Rss) Word64 Q6_P_shuffoh_PP(Word64 Rtt, Word64 - Rss) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 0 1 0 0 - s s s s s P P - t t t t t 0 1 - d d d d d Rdd=shuffeb(Rss,Rtt) -1 1 0 0 0 0 0 1 0 0 - s s s s s P P - t t t t t 1 0 - d d d d d Rdd=shuffob(Rtt,Rss) -1 1 0 0 0 0 0 1 0 0 - s s s s s P P - t t t t t 1 1 - d d d d d Rdd=shuffeh(Rss,Rtt) -1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 0 0 0 d d d d d Rdd=shuffoh(Rtt,Rss) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 612 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector splat bytes - Replicate the low 8-bits from register Rs into each of the four bytes of destination register - Rd. - - - Rd=vsplatb(Rs) - - Rs - - - - Rd - - Syntax Behavior - Rd=vsplatb(Rs) for (i=0;i<4;i++) { - Rd.b[i]=Rs.b[0]; - }; - Rdd=vsplatb(Rs) for (i=0;i<8;i++) { - Rdd.b[i]=Rs.b[0]; - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=vsplatb(Rs) Word32 Q6_R_vsplatb_R(Word32 Rs) - Rdd=vsplatb(Rs) Word64 Q6_P_vsplatb_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 1 0 0 0 1 - s s s s s P P - - - - - - 1 0 - d d d d d Rdd=vsplatb(Rs) -1 0 0 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - 1 1 1 d d d d d Rd=vsplatb(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 613 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector splat halfwords - Replicate the low 16-bits from register Rs into each of the four halfwords of destination - Rdd. - - - Rdd=vsplath(Rs) - - Rs - - - - Rdd - - Syntax Behavior - Rdd=vsplath(Rs) for (i=0;i<4;i++) { - Rdd.h[i]=Rs.h[0]; - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vsplath(Rs) Word64 Q6_P_vsplath_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 1 0 0 0 1 - s s s s s P P - - - - - - 0 1 - d d d d d Rdd=vsplath(Rs) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 614 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector splice - Concatenate the low (8-N) bytes of vector Rtt with the low N bytes of vector Rss. This - instruction is helpful to vectorize unaligned stores. - - - #u3/P - - Rtt Rss - - - - - Rdd - - - Syntax Behavior - Rdd=vspliceb(Rss,Rtt,#u3) Rdd = Rtt << #u*8 | zxt#u*8->64(Rss); - Rdd=vspliceb(Rss,Rtt,Pu) Rdd = Rtt << (Pu&7)*8 | zxt(Pu&7)*8->64(Rss); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vspliceb(Rss,Rtt,#u3) Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 - Rtt, Word32 Iu3) - Rdd=vspliceb(Rss,Rtt,Pu) Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 - Rtt, Byte Pu) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 0 0 1 - - s s s s s P P - t t t t t i i i d d d d d Rdd=vspliceb(Rss,Rtt,#u3) - ICLASS RegType Maj s5 Parse t5 u2 d5 -1 1 0 0 0 0 1 0 1 0 0 s s s s s P P - t t t t t - u u d d d d d Rdd=vspliceb(Rss,Rtt,Pu) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u2 Field to encode register u - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 615 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector sign extend - vsxtbh sign-extends each byte of a single register source to halfwords, and places the - result in the destination register pair. - - vsxthw sign-extends each halfword of a single register source to words, and places the - result in the destination register pair. - - - Rdd=vsxtbh(Rs) Rs - - - sign sign sign sign Rdd - - - - - Rs - Rdd=vsxthw(Rs) - - - sign sign Rdd - - - Syntax Behavior - Rdd=vsxtbh(Rs) for (i=0;i<4;i++) { - Rdd.h[i]=Rs.b[i]; - }; - Rdd=vsxthw(Rs) for (i=0;i<2;i++) { - Rdd.w[i]=Rs.h[i]; - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vsxtbh(Rs) Word64 Q6_P_vsxtbh_R(Word32 Rs) - Rdd=vsxthw(Rs) Word64 Q6_P_vsxthw_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 1 0 0 0 0 - s s s s s P P - - - - - - 0 0 - d d d d d Rdd=vsxtbh(Rs) -1 0 0 0 0 1 0 0 0 0 - s s s s s P P - - - - - - 1 0 - d d d d d Rdd=vsxthw(Rs) - - - - -80-N2040-36 B 616 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 617 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector truncate - In vtrunehb, for each halfword in a vector, take the even (lower) byte and ignore the other - byte. The resulting values are packed into destination register Rd. - - vtrunohb takes each odd byte of the source vector. - - vtrunewh uses two source register pairs, Rss and Rtt. The even (lower) halfwords of Rss - are packed in the upper word of Rdd, while the lower halfwords of Rtt are packed in the - lower word of Rdd. - - vtrunowh performs the same operation as vtrunewh, but uses the odd (upper) halfwords of - the source vectors instead. - - - Rd=vtrunehb(Rss) Rdd=vtrunewh(Rss,Rtt) - Rss - Rss - Rtt - Rd - Rdd - - - Rd=vtrunohb(Rss) - Rdd=vtrunowh(Rss,Rtt) - Rss Rss - Rtt - Rd - - Rdd - - - Syntax Behavior - Rd=vtrunehb(Rss) for (i=0;i<4;i++) { - Rd.b[i]=Rss.b[i*2]; - }; - - - - -80-N2040-36 B 618 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rd=vtrunohb(Rss) for (i=0;i<4;i++) { - Rd.b[i]=Rss.b[i*2+1]; - }; - Rdd=vtrunehb(Rss,Rtt) for (i=0;i<4;i++) { - Rdd.b[i]=Rtt.b[i*2]; - Rdd.b[i+4]=Rss.b[i*2]; - }; - Rdd=vtrunewh(Rss,Rtt) Rdd.h[0]=Rtt.h[0]; - Rdd.h[1]=Rtt.h[2]; - Rdd.h[2]=Rss.h[0]; - Rdd.h[3]=Rss.h[2]; - Rdd=vtrunohb(Rss,Rtt) for (i=0;i<4;i++) { - Rdd.b[i]=Rtt.b[i*2+1]; - Rdd.b[i+4]=Rss.b[i*2+1]; - }; - Rdd=vtrunowh(Rss,Rtt) Rdd.h[0]=Rtt.h[1]; - Rdd.h[1]=Rtt.h[3]; - Rdd.h[2]=Rss.h[1]; - Rdd.h[3]=Rss.h[3]; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=vtrunehb(Rss) Word32 Q6_R_vtrunehb_P(Word64 Rss) - Rd=vtrunohb(Rss) Word32 Q6_R_vtrunohb_P(Word64 Rss) - Rdd=vtrunehb(Rss,Rtt) Word64 Q6_P_vtrunehb_PP(Word64 Rss, Word64 - Rtt) - Rdd=vtrunewh(Rss,Rtt) Word64 Q6_P_vtrunewh_PP(Word64 Rss, Word64 - Rtt) - Rdd=vtrunohb(Rss,Rtt) Word64 Q6_P_vtrunohb_PP(Word64 Rss, Word64 - Rtt) - Rdd=vtrunowh(Rss,Rtt) Word64 Q6_P_vtrunowh_PP(Word64 Rss, Word64 - Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 0 0 0 d d d d d Rd=vtrunohb(Rss) -1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 0 1 0 d d d d d Rd=vtrunehb(Rss) - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 0 1 0 d d d d d Rdd=vtrunewh(Rss,Rtt) -1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 0 1 1 d d d d d Rdd=vtrunehb(Rss,Rtt) -1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 1 0 0 d d d d d Rdd=vtrunowh(Rss,Rtt) -1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 1 0 1 d d d d d Rdd=vtrunohb(Rss,Rtt) - - - - -80-N2040-36 B 619 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - MajOp Major Opcode - MinOp Minor Opcode - Maj Major Opcode - Min Minor Opcode - RegType Register Type - RegType Register Type - - - - -80-N2040-36 B 620 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector zero extend - vzxtbh zero-extends each byte of a single register source to halfwords, and places the - result in the destination register pair. - - vzxthw zero-extends each halfword of a single register source to words, and places the - result in the destination register pair. - - - Rdd=vzxtbh(Rs) Rs - - - zero zero zero zero Rdd - - - - - Rdd=vzxthw(Rs) Rs - - - zero zero Rdd - - - Syntax Behavior - Rdd=vzxtbh(Rs) for (i=0;i<4;i++) { - Rdd.h[i]=Rs.ub[i]; - }; - Rdd=vzxthw(Rs) for (i=0;i<2;i++) { - Rdd.w[i]=Rs.uh[i]; - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vzxtbh(Rs) Word64 Q6_P_vzxtbh_R(Word32 Rs) - Rdd=vzxthw(Rs) Word64 Q6_P_vzxthw_R(Word32 Rs) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 1 0 0 0 0 - s s s s s P P - - - - - - 0 1 - d d d d d Rdd=vzxtbh(Rs) -1 0 0 0 0 1 0 0 0 0 - s s s s s P P - - - - - - 1 1 - d d d d d Rdd=vzxthw(Rs) - - - - -80-N2040-36 B 621 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 622 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.10.7 XTYPE/PRED - The XTYPE/PRED instruction subclass includes instructions which perform - miscellaneous operations on predicates, including mask generation, predicate transfers, - and the Viterbi pack operation. - -Bounds check - Determine if Rs falls in the range defined by Rtt. - - Rtt.w0 is set by the user to the lower bound, and Rtt.w1 is set by the user to the upper - bound. - - All bits of the destination predicate are set if the value falls within the range, or all cleared - otherwise. - - Syntax Behavior - Pd=boundscheck(Rs,Rtt) if ("Rs & 1") { - Assembler mapped to: - "Pd=boundscheck(Rss,Rtt):raw:hi"; - } else { - Assembler mapped to: - "Pd=boundscheck(Rss,Rtt):raw:lo"; - }; - Pd=boundscheck(Rss,Rtt):raw:hi src = Rss.uw[1]; - Pd = (src.uw[0] >= Rtt.uw[0]) && (src.uw[0] - < Rtt.uw[1]) ? 0xff : 0x00; - Pd=boundscheck(Rss,Rtt):raw:lo src = Rss.uw[0]; - Pd = (src.uw[0] >= Rtt.uw[0]) && (src.uw[0] - < Rtt.uw[1]) ? 0xff : 0x00; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Pd=boundscheck(Rs,Rtt) Byte Q6_p_boundscheck_RP(Word32 Rs, Word64 - Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d2 -1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 1 0 0 - - - d d Pd=boundscheck(Rss,Rtt):raw:lo -1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 1 0 1 - - - d d Pd=boundscheck(Rss,Rtt):raw:hi - - - - -80-N2040-36 B 623 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 624 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Compare byte - These instructions sign- or zero-extend the low 8-bits of the source registers and perform - 32-bit comparisons on the result. In the case of an extended 32-bit immediate operand, the - full 32 immediate bits are used for the comparison. - - Syntax Behavior - Pd=cmpb.eq(Rs,#u8) Pd=Rs.ub[0] == #u ? 0xff : 0x00; - Pd=cmpb.eq(Rs,Rt) Pd=Rs.b[0] == Rt.b[0] ? 0xff : 0x00; - Pd=cmpb.gt(Rs,#s8) Pd=Rs.b[0] > #s ? 0xff : 0x00; - Pd=cmpb.gt(Rs,Rt) Pd=Rs.b[0] > Rt.b[0] ? 0xff : 0x00; - Pd=cmpb.gtu(Rs,#u7) apply_extension(#u); - Pd=Rs.ub[0] > #u.uw[0] ? 0xff : 0x00; - Pd=cmpb.gtu(Rs,Rt) Pd=Rs.ub[0] > Rt.ub[0] ? 0xff : 0x00; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Pd=cmpb.eq(Rs,#u8) Byte Q6_p_cmpb_eq_RI(Word32 Rs, Word32 Iu8) - Pd=cmpb.eq(Rs,Rt) Byte Q6_p_cmpb_eq_RR(Word32 Rs, Word32 Rt) - Pd=cmpb.gt(Rs,#s8) Byte Q6_p_cmpb_gt_RI(Word32 Rs, Word32 Is8) - Pd=cmpb.gt(Rs,Rt) Byte Q6_p_cmpb_gt_RR(Word32 Rs, Word32 Rt) - Pd=cmpb.gtu(Rs,#u7) Byte Q6_p_cmpb_gtu_RI(Word32 Rs, Word32 - Iu7) - Pd=cmpb.gtu(Rs,Rt) Byte Q6_p_cmpb_gtu_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d2 -1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 0 1 0 - - - d d Pd=cmpb.gt(Rs,Rt) -1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 1 1 0 - - - d d Pd=cmpb.eq(Rs,Rt) -1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 1 1 1 - - - d d Pd=cmpb.gtu(Rs,Rt) - ICLASS RegType s5 Parse d2 -1 1 0 1 1 1 0 1 - 0 0 s s s s s P P - i i i i i i i i 0 0 - d d Pd=cmpb.eq(Rs,#u8) -1 1 0 1 1 1 0 1 - 0 1 s s s s s P P - i i i i i i i i 0 0 - d d Pd=cmpb.gt(Rs,#s8) -1 1 0 1 1 1 0 1 - 1 0 s s s s s P P - 0 i i i i i i i 0 0 - d d Pd=cmpb.gtu(Rs,#u7) - - - - - Field name Description - RegType Register Type - MajOp Major Opcode - ICLASS Instruction Class - - - - -80-N2040-36 B 625 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 626 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Compare half - These instructions sign- or zero-extend the low 16-bits of the source registers and perform - 32-bit comparisons on the result. In the case of an extended 32-bit immediate operand, the - full 32 immediate bits are used for the comparison. - - Syntax Behavior - Pd=cmph.eq(Rs,#s8) apply_extension(#s); - Pd=Rs.h[0] == #s ? 0xff : 0x00; - Pd=cmph.eq(Rs,Rt) Pd=Rs.h[0] == Rt.h[0] ? 0xff : 0x00; - Pd=cmph.gt(Rs,#s8) apply_extension(#s); - Pd=Rs.h[0] > #s ? 0xff : 0x00; - Pd=cmph.gt(Rs,Rt) Pd=Rs.h[0] > Rt.h[0] ? 0xff : 0x00; - Pd=cmph.gtu(Rs,#u7) apply_extension(#u); - Pd=Rs.uh[0] > #u.uw[0] ? 0xff : 0x00; - Pd=cmph.gtu(Rs,Rt) Pd=Rs.uh[0] > Rt.uh[0] ? 0xff : 0x00; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Pd=cmph.eq(Rs,#s8) Byte Q6_p_cmph_eq_RI(Word32 Rs, Word32 Is8) - Pd=cmph.eq(Rs,Rt) Byte Q6_p_cmph_eq_RR(Word32 Rs, Word32 Rt) - Pd=cmph.gt(Rs,#s8) Byte Q6_p_cmph_gt_RI(Word32 Rs, Word32 Is8) - Pd=cmph.gt(Rs,Rt) Byte Q6_p_cmph_gt_RR(Word32 Rs, Word32 Rt) - Pd=cmph.gtu(Rs,#u7) Byte Q6_p_cmph_gtu_RI(Word32 Rs, Word32 - Iu7) - Pd=cmph.gtu(Rs,Rt) Byte Q6_p_cmph_gtu_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d2 -1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 0 1 1 - - - d d Pd=cmph.eq(Rs,Rt) -1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 1 0 0 - - - d d Pd=cmph.gt(Rs,Rt) -1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 1 0 1 - - - d d Pd=cmph.gtu(Rs,Rt) - ICLASS RegType s5 Parse d2 -1 1 0 1 1 1 0 1 - 0 0 s s s s s P P - i i i i i i i i 0 1 - d d Pd=cmph.eq(Rs,#s8) -1 1 0 1 1 1 0 1 - 0 1 s s s s s P P - i i i i i i i i 0 1 - d d Pd=cmph.gt(Rs,#s8) -1 1 0 1 1 1 0 1 - 1 0 s s s s s P P - 0 i i i i i i i 0 1 - d d Pd=cmph.gtu(Rs,#u7) - - - - -80-N2040-36 B 627 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - RegType Register Type - MajOp Major Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 628 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Compare doublewords - Compare two 64-bit register pairs for unsigned greater than, greater than, or equal. The 8- - bit predicate register Pd is set to all 1's or all 0's depending on the result. - - Syntax Behavior - Pd=cmp.eq(Rss,Rtt) Pd=Rss==Rtt ? 0xff : 0x00; - Pd=cmp.gt(Rss,Rtt) Pd=Rss>Rtt ? 0xff : 0x00; - Pd=cmp.gtu(Rss,Rtt) Pd=Rss.u64>Rtt.u64 ? 0xff : 0x00; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Pd=cmp.eq(Rss,Rtt) Byte Q6_p_cmp_eq_PP(Word64 Rss, Word64 Rtt) - Pd=cmp.gt(Rss,Rtt) Byte Q6_p_cmp_gt_PP(Word64 Rss, Word64 Rtt) - Pd=cmp.gtu(Rss,Rtt) Byte Q6_p_cmp_gtu_PP(Word64 Rss, Word64 - Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d2 -1 1 0 1 0 0 1 0 1 0 0 s s s s s P P - t t t t t 0 0 0 - - - d d Pd=cmp.eq(Rss,Rtt) -1 1 0 1 0 0 1 0 1 0 0 s s s s s P P - t t t t t 0 1 0 - - - d d Pd=cmp.gt(Rss,Rtt) -1 1 0 1 0 0 1 0 1 0 0 s s s s s P P - t t t t t 1 0 0 - - - d d Pd=cmp.gtu(Rss,Rtt) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 629 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Compare bit mask - If all the bits in the mask in Rt or a short immediate are set (BITSSET) or clear - (BITSCLEAR) in Rs, set the Pd to true. Otherwise, set the bits in Pd to false. - - Syntax Behavior - Pd=[!]bitsclr(Rs,#u6) Pd=(Rs&#u)[!]=0 ? 0xff : 0x00; - Pd=[!]bitsclr(Rs,Rt) Pd=(Rs&Rt)[!]=0 ? 0xff : 0x00; - Pd=[!]bitsset(Rs,Rt) Pd=(Rs&Rt)[!]=Rt ? 0xff : 0x00; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Pd=!bitsclr(Rs,#u6) Byte Q6_p_not_bitsclr_RI(Word32 Rs, Word32 - Iu6) - Pd=!bitsclr(Rs,Rt) Byte Q6_p_not_bitsclr_RR(Word32 Rs, Word32 - Rt) - Pd=!bitsset(Rs,Rt) Byte Q6_p_not_bitsset_RR(Word32 Rs, Word32 - Rt) - Pd=bitsclr(Rs,#u6) Byte Q6_p_bitsclr_RI(Word32 Rs, Word32 Iu6) - Pd=bitsclr(Rs,Rt) Byte Q6_p_bitsclr_RR(Word32 Rs, Word32 Rt) - Pd=bitsset(Rs,Rt) Byte Q6_p_bitsset_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse d2 -1 0 0 0 0 1 0 1 1 0 0 s s s s s P P i i i i i i - - - - - - d d Pd=bitsclr(Rs,#u6) -1 0 0 0 0 1 0 1 1 0 1 s s s s s P P i i i i i i - - - - - - d d Pd=!bitsclr(Rs,#u6) - ICLASS RegType Maj s5 Parse t5 d2 -1 1 0 0 0 1 1 1 0 1 0 s s s s s P P - t t t t t - - - - - - d d Pd=bitsset(Rs,Rt) -1 1 0 0 0 1 1 1 0 1 1 s s s s s P P - t t t t t - - - - - - d d Pd=!bitsset(Rs,Rt) -1 1 0 0 0 1 1 1 1 0 0 s s s s s P P - t t t t t - - - - - - d d Pd=bitsclr(Rs,Rt) -1 1 0 0 0 1 1 1 1 0 1 s s s s s P P - t t t t t - - - - - - d d Pd=!bitsclr(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - MajOp Major Opcode - - - - -80-N2040-36 B 630 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Maj Major Opcode - RegType Register Type - RegType Register Type - - - - -80-N2040-36 B 631 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Mask generate from predicate - For each of the low 8 bits in predicate register Pt, if the bit is set then set the corresponding - byte in 64-bit register pair Rdd to 0xff, otherwise, set the corresponding byte to 0x00. - - - 7 0 - - 1 0 1 0 1 0 1 0 Pt - - - - - 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 Rdd - - - Syntax Behavior - Rdd=mask(Pt) for (i = 0; i < 8; i++) { - Rdd.b[i]=(Pt.i?(0xff):(0x00)); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=mask(Pt) Word64 Q6_P_mask_p(Byte Pt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Parse t2 d5 -1 0 0 0 0 1 1 0 - - - - - - - - P P - - - - t t - - - d d d d d Rdd=mask(Pt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - t2 Field to encode register t - RegType Register Type - - - - -80-N2040-36 B 632 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Check for TLB match - Determine if the TLB entry in Rss matches the ASID:PPN in Rt. - - Syntax Behavior - Pd=tlbmatch(Rss,Rt) MASK = 0x07ffffff; - TLBLO = Rss.uw[0]; - TLBHI = Rss.uw[1]; - SIZE = - min(6,count_leading_ones(~reverse_bits(TLB - LO))); - MASK &= (0xffffffff << 2*SIZE); - Pd = TLBHI.31 && ((TLBHI & MASK) == (Rt & - MASK)) ? 0xff : 0x00; - - - Class: XTYPE (slots 2,3) - - Notes - -  The predicate generated by this instruction can not be used as a .new predicate, - nor can it be automatically ANDed with another predicate. - - Intrinsics - - - Pd=tlbmatch(Rss,Rt) Byte Q6_p_tlbmatch_PR(Word64 Rss, Word32 - Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d2 -1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 1 1 - - - d d Pd=tlbmatch(Rss,Rt) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 633 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Predicate transfer - Pd=Rs transfers a predicate to the 8 least-significant bits of a general register and zeros the - other bits. - - Rd=Ps transfers the 8 least-significant bits of a general register to a predicate. - - Syntax Behavior - Pd=Rs Pd = Rs.ub[0]; - Rd=Ps Rd = zxt8->32(Ps); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Pd=Rs Byte Q6_p_equals_R(Word32 Rs) - Rd=Ps Word32 Q6_R_equals_p(Byte Ps) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse d2 -1 0 0 0 0 1 0 1 0 1 0 s s s s s P P - - - - - - - - - - - - d d Pd=Rs - ICLASS RegType MajOp s2 Parse d5 -1 0 0 0 1 0 0 1 - 1 - - - - s s P P - - - - - - - - - d d d d d Rd=Ps - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - d5 Field to encode register d - s2 Field to encode register s - s5 Field to encode register s - MajOp Major Opcode - RegType Register Type - - - - -80-N2040-36 B 634 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Test bit - Extract a bit from a register. If the bit is true (1), set all the bits of the predicate register - destination to 1. If the bit is false (0), set all the bits of the predicate register destination to - 0. The bit to be tested can be indicated using an immediate or register value. - - If a register is used to indicate the bit to test, and the value specified is out of range, the - predicate result is zero. - - Syntax Behavior - Pd=[!]tstbit(Rs,#u5) Pd = (Rs & (1<<#u)) == 0 ? 0xff : 0x00; - Pd=[!]tstbit(Rs,Rt) Pd = (zxt32->64(Rs) & (sxt7->32(Rt)>0)?(zxt32- - >64(1)<32(Rt)):(zxt32->64(1)>>>sxt7- - >32(Rt))) == 0 ? 0xff : 0x00; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Pd=!tstbit(Rs,#u5) Byte Q6_p_not_tstbit_RI(Word32 Rs, Word32 - Iu5) - Pd=!tstbit(Rs,Rt) Byte Q6_p_not_tstbit_RR(Word32 Rs, Word32 - Rt) - Pd=tstbit(Rs,#u5) Byte Q6_p_tstbit_RI(Word32 Rs, Word32 Iu5) - Pd=tstbit(Rs,Rt) Byte Q6_p_tstbit_RR(Word32 Rs, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse d2 -1 0 0 0 0 1 0 1 0 0 0 s s s s s P P 0 i i i i i - - - - - - d d Pd=tstbit(Rs,#u5) -1 0 0 0 0 1 0 1 0 0 1 s s s s s P P 0 i i i i i - - - - - - d d Pd=!tstbit(Rs,#u5) - ICLASS RegType Maj s5 Parse t5 d2 -1 1 0 0 0 1 1 1 0 0 0 s s s s s P P - t t t t t - - - - - - d d Pd=tstbit(Rs,Rt) -1 1 0 0 0 1 1 1 0 0 1 s s s s s P P - t t t t t - - - - - - d d Pd=!tstbit(Rs,Rt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - MajOp Major Opcode - Maj Major Opcode - RegType Register Type - RegType Register Type - - - -80-N2040-36 B 635 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector compare halfwords - Compare each of four 16-bit halfwords in two 64-bit vectors and set the corresponding bits - in a predicate destination to '11' if true, '00' if false. - - Halfword comparisons can be for equal, signed greater than, or unsigned greater than. - - - Rss - - - Rtt - - - - - cmp cmp cmp cmp - - - - - 1 1 0 0 1 1 0 0 Pd - 7 0 - - - Syntax Behavior - Pd=vcmph.eq(Rss,#s8) for (i = 0; i < 4; i++) { - Pd.i*2 = (Rss.h[i] == #s); - Pd.i*2+1 = (Rss.h[i] == #s); - }; - Pd=vcmph.eq(Rss,Rtt) for (i = 0; i < 4; i++) { - Pd.i*2 = (Rss.h[i] == Rtt.h[i]); - Pd.i*2+1 = (Rss.h[i] == Rtt.h[i]); - }; - Pd=vcmph.gt(Rss,#s8) for (i = 0; i < 4; i++) { - Pd.i*2 = (Rss.h[i] > #s); - Pd.i*2+1 = (Rss.h[i] > #s); - }; - Pd=vcmph.gt(Rss,Rtt) for (i = 0; i < 4; i++) { - Pd.i*2 = (Rss.h[i] > Rtt.h[i]); - Pd.i*2+1 = (Rss.h[i] > Rtt.h[i]); - }; - Pd=vcmph.gtu(Rss,#u7) for (i = 0; i < 4; i++) { - Pd.i*2 = (Rss.uh[i] > #u); - Pd.i*2+1 = (Rss.uh[i] > #u); - }; - Pd=vcmph.gtu(Rss,Rtt) for (i = 0; i < 4; i++) { - Pd.i*2 = (Rss.uh[i] > Rtt.uh[i]); - Pd.i*2+1 = (Rss.uh[i] > Rtt.uh[i]); - }; - - - - -80-N2040-36 B 636 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Pd=vcmph.eq(Rss,#s8) Byte Q6_p_vcmph_eq_PI(Word64 Rss, Word32 - Is8) - Pd=vcmph.eq(Rss,Rtt) Byte Q6_p_vcmph_eq_PP(Word64 Rss, Word64 - Rtt) - Pd=vcmph.gt(Rss,#s8) Byte Q6_p_vcmph_gt_PI(Word64 Rss, Word32 - Is8) - Pd=vcmph.gt(Rss,Rtt) Byte Q6_p_vcmph_gt_PP(Word64 Rss, Word64 - Rtt) - Pd=vcmph.gtu(Rss,#u7) Byte Q6_p_vcmph_gtu_PI(Word64 Rss, Word32 - Iu7) - Pd=vcmph.gtu(Rss,Rtt) Byte Q6_p_vcmph_gtu_PP(Word64 Rss, Word64 - Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d2 -1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 0 1 1 - - - d d Pd=vcmph.eq(Rss,Rtt) -1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 1 0 0 - - - d d Pd=vcmph.gt(Rss,Rtt) -1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 1 0 1 - - - d d Pd=vcmph.gtu(Rss,Rtt) - ICLASS RegType s5 Parse d2 -1 1 0 1 1 1 0 0 0 0 0 s s s s s P P - i i i i i i i i 0 1 - d d Pd=vcmph.eq(Rss,#s8) -1 1 0 1 1 1 0 0 0 0 1 s s s s s P P - i i i i i i i i 0 1 - d d Pd=vcmph.gt(Rss,#s8) -1 1 0 1 1 1 0 0 0 1 0 s s s s s P P - 0 i i i i i i i 0 1 - d d Pd=vcmph.gtu(Rss,#u7) - - - - - Field name Description - RegType Register Type - MajOp Major Opcode - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 637 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector compare bytes for any match - Compare each byte in two 64-bit source vectors and set a predicate if any of the 8 bytes are - equal. - - This instruction can be used to quickly find the null terminator in a string. - - Syntax Behavior - Pd=any8(vcmpb.eq(Rss,Rtt)) Pd = 0; - for (i = 0; i < 8; i++) { - if (Rss.b[i] == Rtt.b[i]) Pd = 0xff; - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Pd=any8(vcmpb.eq(Rss,Rtt)) Byte Q6_p_any8_vcmpb_eq_PP(Word64 Rss, - Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d2 -1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 0 0 - - - d d Pd=any8(vcmpb.eq(Rss,Rtt)) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 638 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector compare bytes - Compare each of eight bytes in two 64-bit vectors and set the corresponding bit in a - predicate destination to 1 if true, 0 if false. - - Byte comparisons can be for equal or for unsigned greater than. - - In the following example, every other comparison is true. - - - Rss - - - Rtt - - - cmp cmp cmp cmp cmp cmp cmp cmp - - - - - 1 0 1 0 1 0 1 0 Pd - 7 0 - - - Syntax Behavior - Pd=vcmpb.eq(Rss,#u8) for (i = 0; i < 8; i++) { - Pd.i = (Rss.ub[i] == #u); - }; - Pd=vcmpb.eq(Rss,Rtt) for (i = 0; i < 8; i++) { - Pd.i = (Rss.b[i] == Rtt.b[i]); - }; - Pd=vcmpb.gt(Rss,#s8) for (i = 0; i < 8; i++) { - Pd.i = (Rss.b[i] > #s); - }; - Pd=vcmpb.gt(Rss,Rtt) for (i = 0; i < 8; i++) { - Pd.i = (Rss.b[i] > Rtt.b[i]); - }; - Pd=vcmpb.gtu(Rss,#u7) for (i = 0; i < 8; i++) { - Pd.i = (Rss.ub[i] > #u); - }; - Pd=vcmpb.gtu(Rss,Rtt) for (i = 0; i < 8; i++) { - Pd.i = (Rss.ub[i] > Rtt.ub[i]); - }; - - - - -80-N2040-36 B 639 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Pd=vcmpb.eq(Rss,#u8) Byte Q6_p_vcmpb_eq_PI(Word64 Rss, Word32 - Iu8) - Pd=vcmpb.eq(Rss,Rtt) Byte Q6_p_vcmpb_eq_PP(Word64 Rss, Word64 - Rtt) - Pd=vcmpb.gt(Rss,#s8) Byte Q6_p_vcmpb_gt_PI(Word64 Rss, Word32 - Is8) - Pd=vcmpb.gt(Rss,Rtt) Byte Q6_p_vcmpb_gt_PP(Word64 Rss, Word64 - Rtt) - Pd=vcmpb.gtu(Rss,#u7) Byte Q6_p_vcmpb_gtu_PI(Word64 Rss, Word32 - Iu7) - Pd=vcmpb.gtu(Rss,Rtt) Byte Q6_p_vcmpb_gtu_PP(Word64 Rss, Word64 - Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d2 -1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 1 1 0 - - - d d Pd=vcmpb.eq(Rss,Rtt) -1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 1 1 1 - - - d d Pd=vcmpb.gtu(Rss,Rtt) -1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 1 0 - - - d d Pd=vcmpb.gt(Rss,Rtt) - ICLASS RegType s5 Parse d2 -1 1 0 1 1 1 0 0 0 0 0 s s s s s P P - i i i i i i i i 0 0 - d d Pd=vcmpb.eq(Rss,#u8) -1 1 0 1 1 1 0 0 0 0 1 s s s s s P P - i i i i i i i i 0 0 - d d Pd=vcmpb.gt(Rss,#s8) -1 1 0 1 1 1 0 0 0 1 0 s s s s s P P - 0 i i i i i i i 0 0 - d d Pd=vcmpb.gtu(Rss,#u7) - - - - - Field name Description - RegType Register Type - MajOp Major Opcode - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 640 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector compare words - Compare each of two 32-bit words in two 64-bit vectors and set the corresponding bits in a - predicate destination to '1111' if true, '0000' if false. - - Word comparisons can be for equal, signed greater than, or unsigned greater than. - - - Rss - - - Rtt - - - - - cmp cmp - - - - - 1 1 1 1 0 0 0 0 Pd - 7 0 - - - Syntax Behavior - Pd=vcmpw.eq(Rss,#s8) Pd[3:0] = (Rss.w[0]==#s); - Pd[7:4] = (Rss.w[1]==#s); - Pd=vcmpw.eq(Rss,Rtt) Pd[3:0] = (Rss.w[0]==Rtt.w[0]); - Pd[7:4] = (Rss.w[1]==Rtt.w[1]); - Pd=vcmpw.gt(Rss,#s8) Pd[3:0] = (Rss.w[0]>#s); - Pd[7:4] = (Rss.w[1]>#s); - Pd=vcmpw.gt(Rss,Rtt) Pd[3:0] = (Rss.w[0]>Rtt.w[0]); - Pd[7:4] = (Rss.w[1]>Rtt.w[1]); - Pd=vcmpw.gtu(Rss,#u7) Pd[3:0] = (Rss.uw[0]>#u); - Pd[7:4] = (Rss.uw[1]>#u); - Pd=vcmpw.gtu(Rss,Rtt) Pd[3:0] = (Rss.uw[0]>Rtt.uw[0]); - Pd[7:4] = (Rss.uw[1]>Rtt.uw[1]); - - - - -80-N2040-36 B 641 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Pd=vcmpw.eq(Rss,#s8) Byte Q6_p_vcmpw_eq_PI(Word64 Rss, Word32 - Is8) - Pd=vcmpw.eq(Rss,Rtt) Byte Q6_p_vcmpw_eq_PP(Word64 Rss, Word64 - Rtt) - Pd=vcmpw.gt(Rss,#s8) Byte Q6_p_vcmpw_gt_PI(Word64 Rss, Word32 - Is8) - Pd=vcmpw.gt(Rss,Rtt) Byte Q6_p_vcmpw_gt_PP(Word64 Rss, Word64 - Rtt) - Pd=vcmpw.gtu(Rss,#u7) Byte Q6_p_vcmpw_gtu_PI(Word64 Rss, Word32 - Iu7) - Pd=vcmpw.gtu(Rss,Rtt) Byte Q6_p_vcmpw_gtu_PP(Word64 Rss, Word64 - Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 MinOp d2 -1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 0 0 0 - - - d d Pd=vcmpw.eq(Rss,Rtt) -1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 0 0 1 - - - d d Pd=vcmpw.gt(Rss,Rtt) -1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 0 1 0 - - - d d Pd=vcmpw.gtu(Rss,Rtt) - ICLASS RegType s5 Parse d2 -1 1 0 1 1 1 0 0 0 0 0 s s s s s P P - i i i i i i i i 1 0 - d d Pd=vcmpw.eq(Rss,#s8) -1 1 0 1 1 1 0 0 0 0 1 s s s s s P P - i i i i i i i i 1 0 - d d Pd=vcmpw.gt(Rss,#s8) -1 1 0 1 1 1 0 0 0 1 0 s s s s s P P - 0 i i i i i i i 1 0 - d d Pd=vcmpw.gtu(Rss,#u7) - - - - - Field name Description - RegType Register Type - MajOp Major Opcode - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d2 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - - -80-N2040-36 B 642 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Viterbi pack even and odd predicate bits - Pack the even and odd bits of two predicate registers into a single destination register. A - variant of this instruction is the R3:2 |= vitpack(P1,P0). This places the packed predicate - bits into the lower 8bits of the register pair which has been preshifted by 8bits. - - This instruction is useful in Viterbi decoding. Repeated use of the push version enables a - history to be stored for traceback, purposes. - - - 7 0 - Ps - - - Pt - - - - - 0 Rd - 31 8 7 0 - - - Syntax Behavior - Rd=vitpack(Ps,Pt) Rd = (Ps&0x55) | (Pt&0xAA); - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=vitpack(Ps,Pt) Word32 Q6_R_vitpack_pp(Byte Ps, Byte Pt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s2 Parse t2 d5 -1 0 0 0 1 0 0 1 - 0 0 - - - s s P P - - - - t t - - - d d d d d Rd=vitpack(Ps,Pt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s2 Field to encode register s - t2 Field to encode register t - MajOp Major Opcode - RegType Register Type - - - - -80-N2040-36 B 643 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector mux - Perform an element-wise byte selection between two vectors. - - For each of the low 8 bits of predicate register Pu, if the bit is set, then the corresponding - byte in Rdd is set to the corresponding byte from Rss. Otherwise, set the byte in Rdd to the - byte from Rtt. - - - Rss - - - Rtt - - - mux mux mux mux mux mux mux mux - P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] - - - Rdd - - - Syntax Behavior - Rdd=vmux(Pu,Rss,Rtt) for (i = 0; i < 8; i++) { - Rdd.b[i]=(Pu.i?(Rss.b[i]):(Rtt.b[i])); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vmux(Pu,Rss,Rtt) Word64 Q6_P_vmux_pPP(Byte Pu, Word64 Rss, - Word64 Rtt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType s5 Parse t5 u2 d5 -1 1 0 1 0 0 0 1 - - - s s s s s P P - t t t t t - u u d d d d d Rdd=vmux(Pu,Rss,Rtt) - - - - - Field name Description - RegType Register Type - MinOp Minor Opcode - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - u2 Field to encode register u - - - - -80-N2040-36 B 644 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - 11.10.8 XTYPE/SHIFT - The XTYPE/SHIFT instruction subclass includes instructions which perform shifts. - -Shift by immediate - Shift the source register value right or left based on the type of instruction. In these - instructions, the shift amount is contained in an unsigned immediate (5 bits for 32-bit - shifts, 6 bits for 64-bit shifts) and the shift instruction gives the shift direction. - - Arithmetic right shifts place the sign bit of the source value in the vacated positions, while - logical right shifts place zeros in the vacated positions. Left shifts always zero-fill the - vacated bits. - - - ASR LSR - - Lost Rs Lost Rs - - - - Sign-ext Rd Zero-fill Rd - - ASL - - Lost Rs - - - Zero-fill Rd - - - Syntax Behavior - Rd=asl(Rs,#u5) Rd = Rs << #u; - Rd=asr(Rs,#u5) Rd = Rs >> #u; - Rd=lsr(Rs,#u5) Rd = Rs >>> #u; - Rd=rol(Rs,#u5) Rd = Rs <> #u; - Rdd=lsr(Rss,#u6) Rdd = Rss >>> #u; - Rdd=rol(Rss,#u6) Rdd = Rss <>#U); - Rx=sub(#u8,asl(Rx,#U5)) Rx=apply_extension(#u)-(Rx<<#U); - Rx=sub(#u8,lsr(Rx,#U5)) Rx=apply_extension(#u)-(((unsigned - int)Rx)>>#U); - Rx[+-]=asl(Rs,#u5) Rx = Rx [+-] Rs << #u; - Rx[+-]=asr(Rs,#u5) Rx = Rx [+-] Rs >> #u; - Rx[+-]=lsr(Rs,#u5) Rx = Rx [+-] Rs >>> #u; - Rx[+-]=rol(Rs,#u5) Rx = Rx [+-] Rs <> #u; - Rxx[+-]=lsr(Rss,#u6) Rxx = Rxx [+-] Rss >>> #u; - Rxx[+-]=rol(Rss,#u6) Rxx = Rxx [+-] Rss <>#U); - Rx=or(#u8,asl(Rx,#U5)) Rx=apply_extension(#u)|(Rx<<#U); - Rx=or(#u8,lsr(Rx,#U5)) Rx=apply_extension(#u)|(((unsigned - int)Rx)>>#U); - Rx[&|]=asl(Rs,#u5) Rx = Rx [|&] Rs << #u; - Rx[&|]=asr(Rs,#u5) Rx = Rx [|&] Rs >> #u; - Rx[&|]=lsr(Rs,#u5) Rx = Rx [|&] Rs >>> #u; - Rx[&|]=rol(Rs,#u5) Rx = Rx [|&] Rs <>> #u; - Rx^=rol(Rs,#u5) Rx = Rx ^ Rs <> #u; - Rxx[&|]=lsr(Rss,#u6) Rxx = Rxx [|&] Rss >>> #u; - Rxx[&|]=rol(Rss,#u6) Rxx = Rxx [|&] Rss <>> #u; - Rxx^=rol(Rss,#u6) Rxx = Rxx ^ Rss <> #u)+1) >> 1; - Rd=asrrnd(Rs,#u5) if ("#u5==0") { - Assembler mapped to: "Rd=Rs"; - } else { - Assembler mapped to: "Rd=asr(Rs,#u5- - 1):rnd"; - }; - Rdd=asr(Rss,#u6):rnd tmp = Rss >> #u; - rnd = tmp & 1; - Rdd = tmp >> 1 + rnd; - Rdd=asrrnd(Rss,#u6) if ("#u6==0") { - Assembler mapped to: "Rdd=Rss"; - } else { - Assembler mapped to: "Rdd=asr(Rss,#u6- - 1):rnd"; - }; - - - - -80-N2040-36 B 655 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rd=asr(Rs,#u5):rnd Word32 Q6_R_asr_RI_rnd(Word32 Rs, Word32 - Iu5) - Rd=asrrnd(Rs,#u5) Word32 Q6_R_asrrnd_RI(Word32 Rs, Word32 - Iu5) - Rdd=asr(Rss,#u6):rnd Word64 Q6_P_asr_PI_rnd(Word64 Rss, Word32 - Iu6) - Rdd=asrrnd(Rss,#u6) Word64 Q6_P_asrrnd_PI(Word64 Rss, Word32 - Iu6) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 1 1 0 s s s s s P P i i i i i i 1 1 1 d d d d d Rdd=asr(Rss,#u6):rnd -1 0 0 0 1 1 0 0 0 1 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d Rd=asr(Rs,#u5):rnd - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 656 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Shift left by immediate with saturation - Perform a left shift of the 32-bit source register value by an immediate amount and - saturate. - - Saturation works by first sign-extending the 32-bit Rs register to 64 bits. It is then left - shifted by the immediate amount. If this 64-bit value cannot fit in a signed 32-bit number - (the upper word is not the sign-extension of bit 31), then saturation is performed based on - the sign of the original value. Saturation clamps the 32-bit result to the range - 0x8000_0000 to 0x7fff_ffff. - - Syntax Behavior - Rd=asl(Rs,#u5):sat Rd = sat32(sxt32->64(Rs) << #u); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), the OVF bit in the Status Register is set. - OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=asl(Rs,#u5):sat Word32 Q6_R_asl_RI_sat(Word32 Rs, Word32 - Iu5) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 1 0 0 0 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d Rd=asl(Rs,#u5):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 657 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Shift by register - The shift amount is the least significant 7 bits of Rt, treated as a two's complement value. - If the shift amount is negative (bit 6 of Rt is set), the direction of the shift indicted in the - opcode is reversed (see Figure). - - The source data to be shifted is always performed as a 64-bit shift. When the Rs source - register is a 32-bit register, this register is first sign or zero-extended to 64-bits. Arithmetic - shifts sign-extend the 32-bit source to 64-bits, while logical shifts zero extend. - - The 64-bit source value is then right or left shifted based on the shift amount and the type - of instruction. Arithmetic right shifts place the sign bit of the source value in the vacated - positions. Logical right shifts place zeros in the vacated positions. - - - ASR w/ Positive Rt LSR w/ Positive Rt - ASL w/ Negative Rt LSL w/ Negative Rt - - Lost Rs Lost Rs - - - - Sign-ext Rd Zero-fill Rd - - - ASL w/ Positive Rt - LSL w/ Positive Rt - ASR w/ Negative Rt - LSR w/ Negative Rt - - Lost Rs - - - Zero-fill Rd - - - Syntax Behavior - Rd=asl(Rs,Rt) shamt=sxt7->32(Rt); - Rd = (shamt>0)?(sxt32- - >64(Rs)<64(Rs)>>shamt); - - Rd=asr(Rs,Rt) shamt=sxt7->32(Rt); - Rd = (shamt>0)?(sxt32- - >64(Rs)>>shamt):(sxt32->64(Rs)<32(Rt); - Rd = (shamt>0)?(zxt32- - >64(#s)<64(#s)>>>shamt); - - Rd=lsl(Rs,Rt) shamt=sxt7->32(Rt); - Rd = (shamt>0)?(zxt32- - >64(Rs)<64(Rs)>>>shamt); - - - - -80-N2040-36 B 658 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rd=lsr(Rs,Rt) shamt=sxt7->32(Rt); - Rd = (shamt>0)?(zxt32- - >64(Rs)>>>shamt):(zxt32->64(Rs)<32(Rt); - Rdd = (shamt>0)?(Rss<>shamt); - Rdd=asr(Rss,Rt) shamt=sxt7->32(Rt); - Rdd = (shamt>0)?(Rss>>shamt):(Rss<32(Rt); - Rdd = (shamt>0)?(Rss<>>shamt); - Rdd=lsr(Rss,Rt) shamt=sxt7->32(Rt); - Rdd = (shamt>0)?(Rss>>>shamt):(Rss<32(Rt); - Rx = Rx [+-] (shamt>0)?(sxt32- - >64(Rs)<64(Rs)>>shamt); - - Rx[+-]=asr(Rs,Rt) shamt=sxt7->32(Rt); - Rx = Rx [+-] (shamt>0)?(sxt32- - >64(Rs)>>shamt):(sxt32->64(Rs)<32(Rt); - Rx = Rx [+-] (shamt>0)?(zxt32- - >64(Rs)<64(Rs)>>>shamt); - - - - -80-N2040-36 B 661 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Syntax Behavior - Rx[+-]=lsr(Rs,Rt) shamt=sxt7->32(Rt); - Rx = Rx [+-] (shamt>0)?(zxt32- - >64(Rs)>>>shamt):(zxt32->64(Rs)<32(Rt); - Rxx = Rxx [+-] - (shamt>0)?(Rss<>shamt); - Rxx[+-]=asr(Rss,Rt) shamt=sxt7->32(Rt); - Rxx = Rxx [+-] - (shamt>0)?(Rss>>shamt):(Rss<32(Rt); - Rxx = Rxx [+-] - (shamt>0)?(Rss<>>shamt); - Rxx[+-]=lsr(Rss,Rt) shamt=sxt7->32(Rt); - Rxx = Rxx [+-] - (shamt>0)?(Rss>>>shamt):(Rss<32(Rt); - Rx = Rx [|&] (shamt>0)?(sxt32- - >64(Rs)<64(Rs)>>shamt); - - Rx[&|]=asr(Rs,Rt) shamt=sxt7->32(Rt); - Rx = Rx [|&] (shamt>0)?(sxt32- - >64(Rs)>>shamt):(sxt32->64(Rs)<32(Rt); - Rx = Rx [|&] (shamt>0)?(zxt32- - >64(Rs)<64(Rs)>>>shamt); - - Rx[&|]=lsr(Rs,Rt) shamt=sxt7->32(Rt); - Rx = Rx [|&] (shamt>0)?(zxt32- - >64(Rs)>>>shamt):(zxt32->64(Rs)<32(Rt); - Rxx = Rxx [|&] - (shamt>0)?(Rss<>shamt); - Rxx[&|]=asr(Rss,Rt) shamt=sxt7->32(Rt); - Rxx = Rxx [|&] - (shamt>0)?(Rss>>shamt):(Rss<32(Rt); - Rxx = Rxx [|&] - (shamt>0)?(Rss<>>shamt); - Rxx[&|]=lsr(Rss,Rt) shamt=sxt7->32(Rt); - Rxx = Rxx [|&] - (shamt>0)?(Rss>>>shamt):(Rss<32(Rt); - Rxx = Rxx ^ - (shamt>0)?(Rss<>shamt); - Rxx^=asr(Rss,Rt) shamt=sxt7->32(Rt); - Rxx = Rxx ^ - (shamt>0)?(Rss>>shamt):(Rss<32(Rt); - Rxx = Rxx ^ - (shamt>0)?(Rss<>>shamt); - Rxx^=lsr(Rss,Rt) shamt=sxt7->32(Rt); - Rxx = Rxx ^ - (shamt>0)?(Rss>>>shamt):(Rss<32(Rt); - Rd = bidir_shiftl(Rs,shamt); - Rd=asr(Rs,Rt):sat shamt=sxt7->32(Rt); - Rd = bidir_shiftr(Rs,shamt); - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), then the OVF bit in the Status Register is - set. OVF will remain set until explicitly cleared by a transfer to SR. - - Intrinsics - - Rd=asl(Rs,Rt):sat Word32 Q6_R_asl_RR_sat(Word32 Rs, Word32 - Rt) - Rd=asr(Rs,Rt):sat Word32 Q6_R_asr_RR_sat(Word32 Rs, Word32 - Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 1 1 0 0 0 - s s s s s P P - t t t t t 0 0 - d d d d d Rd=asr(Rs,Rt):sat -1 1 0 0 0 1 1 0 0 0 - s s s s s P P - t t t t t 1 0 - d d d d d Rd=asl(Rs,Rt):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - - - -80-N2040-36 B 668 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Field name Description - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 669 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector shift halfwords by immediate - Shift individual halfwords of the source vector. Arithmetic right shifts place the sign bit of - the source values in the vacated positions. Logical right shifts place zeros in the vacated - positions. - - - Rdd = vaslh(Rss,#) Shift Amount Rt/#u4 - - lost lost lost lost Rss - - - - 0 0 0 0 - Rdd - - - Syntax Behavior - Rdd=vaslh(Rss,#u4) for (i=0;i<4;i++) { - Rdd.h[i]=(Rss.h[i]<<#u); - }; - Rdd=vasrh(Rss,#u4) for (i=0;i<4;i++) { - Rdd.h[i]=(Rss.h[i]>>#u); - }; - Rdd=vlsrh(Rss,#u4) for (i=0;i<4;i++) { - Rdd.h[i]=(Rss.uh[i]>>#u); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vaslh(Rss,#u4) Word64 Q6_P_vaslh_PI(Word64 Rss, Word32 - Iu4) - Rdd=vasrh(Rss,#u4) Word64 Q6_P_vasrh_PI(Word64 Rss, Word32 - Iu4) - Rdd=vlsrh(Rss,#u4) Word64 Q6_P_vlsrh_PI(Word64 Rss, Word32 - Iu4) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 1 0 0 s s s s s P P 0 0 i i i i 0 0 0 d d d d d Rdd=vasrh(Rss,#u4) -1 0 0 0 0 0 0 0 1 0 0 s s s s s P P 0 0 i i i i 0 0 1 d d d d d Rdd=vlsrh(Rss,#u4) -1 0 0 0 0 0 0 0 1 0 0 s s s s s P P 0 0 i i i i 0 1 0 d d d d d Rdd=vaslh(Rss,#u4) - - - - -80-N2040-36 B 670 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 671 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector arithmetic shift halfwords with round - For each halfword in the vector, round then arithmetic shift right by an immediate amount. - The results are stored in the destination register. - - - Rdd = vasrh(Rss,#u):rnd - - - - - 1<<(#u-1) 1<<(#u-1) 1<<(#u-1) 1<<(#u-1) - - - + + + + - lost lost lost lost - - - - - Sign- Sign- Sign- Sign- - ext ext ext ext - - - Syntax Behavior - Rdd=vasrh(Rss,#u4):raw for (i=0;i<4;i++) { - Rdd.h[i]=( ((Rss.h[i] >> #u)+1)>>1 ); - }; - Rdd=vasrh(Rss,#u4):rnd if ("#u4==0") { - Assembler mapped to: "Rdd=Rss"; - } else { - Assembler mapped to: - "Rdd=vasrh(Rss,#u4-1):raw"; - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - - Rdd=vasrh(Rss,#u4):rnd Word64 Q6_P_vasrh_PI_rnd(Word64 Rss, Word32 - Iu4) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 0 0 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d Rdd=vasrh(Rss,#u4):raw - - - - -80-N2040-36 B 672 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 673 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector arithmetic shift halfwords with saturate and pack - For each halfword in the vector, optionally round, then arithmetic shift right by an - immediate amount. The results are saturated to unsigned [0-255] and then packed in the - destination register. - - - Rd = vasrhub(Rss,#u):rnd:sat - - - - - 1<<(#u-1) 1<<(#u-1) 1<<(#u-1) 1<<(#u-1) - - - + + + + - lost lost lost lost - - - - - Sat_u8 Sat_u8 Sat_u8 Sat_u8 - - - - - Syntax Behavior - Rd=vasrhub(Rss,#u4):raw for (i=0;i<4;i++) { - Rd.b[i]=usat8(((Rss.h[i] >> #u - )+1)>>1); - }; - Rd=vasrhub(Rss,#u4):rnd:sat if ("#u4==0") { - Assembler mapped to: "Rd=vsathub(Rss)"; - } else { - Assembler mapped to: - "Rd=vasrhub(Rss,#u4-1):raw"; - }; - Rd=vasrhub(Rss,#u4):sat for (i=0;i<4;i++) { - Rd.b[i]=usat8(Rss.h[i] >> #u); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If saturation occurs during execution of this instruction (a result is clamped to - either maximum or minimum values), then the OVF bit in the Status Register is - set. OVF will remain set until explicitly cleared by a transfer to SR. - - - - -80-N2040-36 B 674 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rd=vasrhub(Rss,#u4):rnd:sat Word32 Q6_R_vasrhub_PI_rnd_sat(Word64 Rss, - Word32 Iu4) - Rd=vasrhub(Rss,#u4):sat Word32 Q6_R_vasrhub_PI_sat(Word64 Rss, - Word32 Iu4) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 1 0 0 d d d d d Rd=vasrhub(Rss,#u4):raw -1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 1 0 1 d d d d d Rd=vasrhub(Rss,#u4):sat - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 675 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector shift halfwords by register - The shift amount is the least significant 7 bits of Rt, treated as a two's complement value. - If the shift amount is negative, the direction of the shift is reversed. Shift the source values - right or left based on the shift amount and the type of instruction. Arithmetic right shifts - place the sign bit of the source value in the vacated positions. Logical right shifts place - zeros in the vacated positions. - - - Rdd = vaslh(Rss,#) Shift Amount Rt/#u4 - - lost lost lost lost Rss - - - - 0 0 0 0 - Rdd - - - Syntax Behavior - Rdd=vaslh(Rss,Rt) for (i=0;i<4;i++) { - Rdd.h[i]=(sxt7->32(Rt)>0)?(sxt16- - >64 (Rss.h[i])<32(Rt)):(sxt16- - >64(Rss.h[i])>>sxt7->32(Rt)); - }; - Rdd=vasrh(Rss,Rt) for (i=0;i<4;i++) { - Rdd.h[i]=(sxt7->32(Rt)>0)?(sxt16- - >64(Rss.h[i])>>sxt7->32(Rt)):(sxt16- - >64(Rss.h[i])<32(Rt)); - }; - Rdd=vlslh(Rss,Rt) for (i=0;i<4;i++) { - Rdd.h[i]=(sxt7->32(Rt)>0)?(zxt16- - >64(Rss.uh[i])<32(Rt)):(zxt16- - >64(Rss.uh[i])>>>sxt7->32(Rt)); - }; - Rdd=vlsrh(Rss,Rt) for (i=0;i<4;i++) { - Rdd.h[i]=(sxt7->32(Rt)>0)?(zxt16- - >64(Rss.uh[i])>>>sxt7->32(Rt)):(zxt16- - >64(Rss.uh[i])<32(Rt)); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If the number of bits to be shifted is greater than the width of the vector element, - the result is either all sign-bits (for arithmetic right shifts) or all zeros for logical - and left shifts. - - - - -80-N2040-36 B 676 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rdd=vaslh(Rss,Rt) Word64 Q6_P_vaslh_PR(Word64 Rss, Word32 Rt) - Rdd=vasrh(Rss,Rt) Word64 Q6_P_vasrh_PR(Word64 Rss, Word32 Rt) - Rdd=vlslh(Rss,Rt) Word64 Q6_P_vlslh_PR(Word64 Rss, Word32 Rt) - Rdd=vlsrh(Rss,Rt) Word64 Q6_P_vlsrh_PR(Word64 Rss, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 1 1 0 1 - s s s s s P P - t t t t t 0 0 - d d d d d Rdd=vasrh(Rss,Rt) -1 1 0 0 0 0 1 1 0 1 - s s s s s P P - t t t t t 0 1 - d d d d d Rdd=vlsrh(Rss,Rt) -1 1 0 0 0 0 1 1 0 1 - s s s s s P P - t t t t t 1 0 - d d d d d Rdd=vaslh(Rss,Rt) -1 1 0 0 0 0 1 1 0 1 - s s s s s P P - t t t t t 1 1 - d d d d d Rdd=vlslh(Rss,Rt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 677 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector shift words by immediate - Shift individual words of the source vector. Arithmetic right shifts place the sign bit of the - source values in the vacated positions. Logical right shifts place zeros in the vacated - positions. - - - Rdd = vaslw(Rss,{Rt/#}) Shift Amount Rt/#u5 - - - lost lost Rss - - - - 0 0 0 Rdd - - - Syntax Behavior - Rdd=vaslw(Rss,#u5) for (i=0;i<2;i++) { - Rdd.w[i]=(Rss.w[i]<<#u); - }; - Rdd=vasrw(Rss,#u5) for (i=0;i<2;i++) { - Rdd.w[i]=(Rss.w[i]>>#u); - }; - Rdd=vlsrw(Rss,#u5) for (i=0;i<2;i++) { - Rdd.w[i]=(Rss.uw[i]>>#u); - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rdd=vaslw(Rss,#u5) Word64 Q6_P_vaslw_PI(Word64 Rss, Word32 - Iu5) - Rdd=vasrw(Rss,#u5) Word64 Q6_P_vasrw_PI(Word64 Rss, Word32 - Iu5) - Rdd=vlsrw(Rss,#u5) Word64 Q6_P_vlsrw_PI(Word64 Rss, Word32 - Iu5) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 0 0 0 0 0 1 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d Rdd=vasrw(Rss,#u5) -1 0 0 0 0 0 0 0 0 1 0 s s s s s P P 0 i i i i i 0 0 1 d d d d d Rdd=vlsrw(Rss,#u5) -1 0 0 0 0 0 0 0 0 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d Rdd=vaslw(Rss,#u5) - - - - -80-N2040-36 B 678 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - MajOp Major Opcode - MinOp Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 679 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector shift words by register - The shift amount is the least significant 7 bits of Rt, treated as a two's complement value. - If the shift amount is negative, the direction of the shift is reversed. Shift the source values - right or left based on the shift amount and the type of instruction. Arithmetic right shifts - place the sign bit of the source value in the vacated positions. Logical right shifts place - zeros in the vacated positions. - - - Rdd = vaslw(Rss,{Rt/#}) Shift Amount Rt/#u5 - - - lost lost Rss - - - - 0 0 0 Rdd - - - Syntax Behavior - Rdd=vaslw(Rss,Rt) for (i=0;i<2;i++) { - Rdd.w[i]=(sxt7->32(Rt)>0)?(sxt32- - >64(Rss.w[i])<32(Rt)):(sxt32- - >64(Rss.w[i])>>sxt7->32(Rt)); - }; - Rdd=vasrw(Rss,Rt) for (i=0;i<2;i++) { - Rdd.w[i]=(sxt7->32(Rt)>0)?(sxt32- - >64(Rss.w[i])>>sxt7->32(Rt)):(sxt32- - >64(Rss.w[i])<32(Rt)); - }; - Rdd=vlslw(Rss,Rt) for (i=0;i<2;i++) { - Rdd.w[i]=(sxt7->32(Rt)>0)?(zxt32- - >64(Rss.uw[i])<32(Rt)):(zxt32- - >64(Rss.uw[i])>>>sxt7->32(Rt)); - }; - Rdd=vlsrw(Rss,Rt) for (i=0;i<2;i++) { - Rdd.w[i]=(sxt7->32(Rt)>0)?(zxt32- - >64(Rss.uw[i])>>>sxt7->32(Rt)):(zxt32- - >64(Rss.uw[i])<32(Rt)); - }; - - - Class: XTYPE (slots 2,3) - - Notes - -  If the number of bits to be shifted is greater than the width of the vector element, - the result is either all sign-bits (for arithmetic right shifts) or all zeros for logical - and left shifts. - - - - -80-N2040-36 B 680 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - Intrinsics - - Rdd=vaslw(Rss,Rt) Word64 Q6_P_vaslw_PR(Word64 Rss, Word32 Rt) - Rdd=vasrw(Rss,Rt) Word64 Q6_P_vasrw_PR(Word64 Rss, Word32 Rt) - Rdd=vlslw(Rss,Rt) Word64 Q6_P_vlslw_PR(Word64 Rss, Word32 Rt) - Rdd=vlsrw(Rss,Rt) Word64 Q6_P_vlsrw_PR(Word64 Rss, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType Maj s5 Parse t5 Min d5 -1 1 0 0 0 0 1 1 0 0 - s s s s s P P - t t t t t 0 0 - d d d d d Rdd=vasrw(Rss,Rt) -1 1 0 0 0 0 1 1 0 0 - s s s s s P P - t t t t t 0 1 - d d d d d Rdd=vlsrw(Rss,Rt) -1 1 0 0 0 0 1 1 0 0 - s s s s s P P - t t t t t 1 0 - d d d d d Rdd=vaslw(Rss,Rt) -1 1 0 0 0 0 1 1 0 0 - s s s s s P P - t t t t t 1 1 - d d d d d Rdd=vlslw(Rss,Rt) - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - Maj Major Opcode - Min Minor Opcode - RegType Register Type - - - - -80-N2040-36 B 681 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - -Vector shift words with truncate and pack - Shift individual words of the source vector Rss right by a register or immediate amount. - The low 16-bits of each word are packed into destination register Rd. - - - Rd = vasrw(Rss,{Rt/#}) Shift Amount Rt/#u5 - - - lost lost Rss - - - - - sxt sxt - - - - - Low 16bits Low 16bits - - - Rd - - - Syntax Behavior - Rd=vasrw(Rss,#u5) for (i=0;i<2;i++) { - Rd.h[i]=(Rss.w[i]>>#u).h[0]; - }; - Rd=vasrw(Rss,Rt) for (i=0;i<2;i++) { - Rd.h[i]=(sxt7->32(Rt)>0)?(sxt32- - >64 (Rss.w[i])>>sxt 7->32(Rt)):(sxt32- - >64(Rss.w[i])<32(Rt)).h[0]; - }; - - - Class: XTYPE (slots 2,3) - - Intrinsics - - Rd=vasrw(Rss,#u5) Word32 Q6_R_vasrw_PI(Word64 Rss, Word32 - Iu5) - Rd=vasrw(Rss,Rt) Word32 Q6_R_vasrw_PR(Word64 Rss, Word32 Rt) - - - Encoding - -31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ICLASS RegType MajOp s5 Parse MinOp d5 -1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d Rd=vasrw(Rss,#u5) - ICLASS RegType s5 Parse t5 Min d5 -1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 0 1 0 d d d d d Rd=vasrw(Rss,Rt) - - - - -80-N2040-36 B 682 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Hexagon V62 Programmer's Reference Manual Instruction Set - - - - - Field name Description - ICLASS Instruction Class - Parse Packet/Loop parse bits - d5 Field to encode register d - s5 Field to encode register s - t5 Field to encode register t - MajOp Major Opcode - MinOp Minor Opcode - Min Minor Opcode - RegType Register Type - RegType Register Type - - - - -80-N2040-36 B 683 - - MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION - Instruction Index - - -A asl - Rd=asl(Rs,#u5) 645 - Rd=asl(Rs,#u5):sat 657 -abs - Rd=asl(Rs,Rt) 658 - Rd=abs(Rs)[:sat] 389 Rd=asl(Rs,Rt):sat 668 - Rdd=abs(Rss) 388 - Rdd=asl(Rss,#u6) 645 - Rdd=asl(Rss,Rt) 659 -add Rx^=asl(Rs,#u5) 651 - if ([!]Pu[.new]) Rd=add(Rs,#s8) 196 Rx[&|]=asl(Rs,#u5) 651 - if ([!]Pu[.new]) Rd=add(Rs,Rt) 196 Rx[&|]=asl(Rs,Rt) 665 - Rd=add(#u6,mpyi(Rs,#U6)) 539 Rx[+-]=asl(Rs,#u5) 647 - Rd=add(#u6,mpyi(Rs,Rt)) 539 Rx[+-]=asl(Rs,Rt) 661 - Rd=add(Rs,#s16) 171 Rx=add(#u8,asl(Rx,#U5)) 647 - Rd=add(Rs,add(Ru,#s6)) 390 Rx=and(#u8,asl(Rx,#U5)) 651 - Rd=add(Rs,Rt) 171 Rx=or(#u8,asl(Rx,#U5)) 651 - Rd=add(Rs,Rt):sat 171 Rx=sub(#u8,asl(Rx,#U5)) 647 - Rd=add(Rs,Rt):sat:deprecated 392 Rxx^=asl(Rss,#u6) 652 - Rd=add(Rt.[HL],Rs.[HL])[:sat]:<<16 394 Rxx^=asl(Rss,Rt) 665 - Rd=add(Rt.L,Rs.[HL])[:sat] 394 Rxx[&|]=asl(Rss,#u6) 652 - Rd=add(Ru,mpyi(#u6:2,Rs)) 539 Rxx[&|]=asl(Rss,Rt) 665 - Rd=add(Ru,mpyi(Rs,#u6)) 539 Rxx[+-]=asl(Rss,#u6) 647 - Rdd=add(Rs,Rtt) 392 Rxx[+-]=asl(Rss,Rt) 662 - Rdd=add(Rss,Rtt,Px):carry 397 - Rdd=add(Rss,Rtt) 392 aslh - Rdd=add(Rss,Rtt):raw:hi 392 - if ([!]Pu[.new]) Rd=aslh(Rs) 198 - Rdd=add(Rss,Rtt):raw:lo 392 - Rd=aslh(Rs) 193 - Rdd=add(Rss,Rtt):sat 392 - Rx+=add(Rs,#s8) 390 - Rx+=add(Rs,Rt) 390 asr - Rx-=add(Rs,#s8) 390 Rd=asr(Rs,#u5) 645 - Rx-=add(Rs,Rt) 390 Rd=asr(Rs,#u5):rnd 655 - Ry=add(Ru,mpyi(Ry,Rs)) 540 Rd=asr(Rs,Rt) 658 - Rd=asr(Rs,Rt):sat 668 - Rdd=asr(Rss,#u6) 645 -addasl - Rdd=asr(Rss,#u6):rnd 655 - Rd=addasl(Rt,Rs,#u3) 650 Rdd=asr(Rss,Rt) 659 - Rx[&|]=asr(Rs,#u5) 651 -all8 Rx[&|]=asr(Rs,Rt) 665 - Pd=all8(Ps) 215 Rx[+-]=asr(Rs,#u5) 647 - Rx[+-]=asr(Rs,Rt) 661 -allocframe Rxx^=asr(Rss,Rt) 665 - allocframe(#u11:3) 329 Rxx[&|]=asr(Rss,#u6) 652 - Rxx[&|]=asr(Rss,Rt) 665 - Rxx[+-]=asr(Rss,#u6) 647 -and - Rxx[+-]=asr(Rss,Rt) 662 - if ([!]Pu[.new]) Rd=and(Rs,Rt) 201 - Pd=and(Ps,and(Pt,[!]Pu)) 221 - Pd=and(Pt,[!]Ps) 221 asrh - Rd=and(Rs,#s10) 173 if ([!]Pu[.new]) Rd=asrh(Rs) 198 - Rd=and(Rs,Rt) 173 Rd=asrh(Rs) 193 - Rd=and(Rt,~Rs) 173 - Rdd=and(Rss,Rtt) 398 asrrnd - Rdd=and(Rtt,~Rss) 398 Rd=asrrnd(Rs,#u5) 655 - Rx[&|^]=and(Rs,~Rt) 401 Rdd=asrrnd(Rss,#u6) 655 - Rx[&|^]=and(Rs,Rt) 401 - Rx|=and(Rs,#s10) 401 B -any8 barrier - Pd=any8(Ps) 215 barrier 375 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 684 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -bitsclr cmp.eq - Pd=[!]bitsclr(Rs,#u6) 630 if ([!]cmp.eq(Ns.new,#-1)) jump: #r9:2 289 - Pd=[!]bitsclr(Rs,Rt) 630 if ([!]cmp.eq(Ns.new,#U5)) jump: #r9:2 289 - if ([!]cmp.eq(Ns.new,Rt)) jump: #r9:2 289 -bitsplit p[01]=cmp.eq(Rs,#-1) 231 - Rdd=bitsplit(Rs,#u5) 478 p[01]=cmp.eq(Rs,#U5) 231 - Rdd=bitsplit(Rs,Rt) 478 p[01]=cmp.eq(Rs,Rt) 231 - Pd=[!]cmp.eq(Rs,#s10) 209 - Pd=[!]cmp.eq(Rs,Rt) 209 -bitsset Pd=cmp.eq(Rss,Rtt) 629 - Pd=[!]bitsset(Rs,Rt) 630 Rd=[!]cmp.eq(Rs,#s8) 211 - Rd=[!]cmp.eq(Rs,Rt) 211 -boundscheck - Pd=boundscheck(Rs,Rtt) 623 cmp.ge - Pd=boundscheck(Rss,Rtt):raw:hi 623 Pd=cmp.ge(Rs,#s8) 209 - Pd=boundscheck(Rss,Rtt):raw:lo 623 - cmp.geu -brev Pd=cmp.geu(Rs,#u8) 209 - Rd=brev(Rs) 475 - Rdd=brev(Rss) 475 - cmp.gt - if ([!]cmp.gt(Ns.new,#-1)) jump: #r9:2 289 -brkpt if ([!]cmp.gt(Ns.new,#U5)) jump: #r9:2 289 - brkpt 376 if ([!]cmp.gt(Ns.new,Rt)) jump: #r9:2 290 - if ([!]cmp.gt(Rt,Ns.new)) jump: #r9:2 290 -C p[01]=cmp.gt(Rs,#-1) 231 - p[01]=cmp.gt(Rs,#U5) 232 -call p[01]=cmp.gt(Rs,Rt) 232 - call #r22:2 229 Pd=[!]cmp.gt(Rs,#s10) 209 - if ([!]Pu) call #r15:2 229 Pd=[!]cmp.gt(Rs,Rt) 209 - Pd=cmp.gt(Rss,Rtt) 629 -callr - callr Rs 225 cmp.gtu - if ([!]Pu) callr Rs 225 if ([!]cmp.gtu(Ns.new,#U5)) jump: #r9:2 290 - if ([!]cmp.gtu(Ns.new,Rt)) jump: #r9:2 290 -ciad if ([!]cmp.gtu(Rt,Ns.new)) jump: #r9:2 290 - p[01]=cmp.gtu(Rs,#U5) 232 - ciad(Rs) 333 - p[01]=cmp.gtu(Rs,Rt) 232 - Pd=[!]cmp.gtu(Rs,#u9) 209 -cl0 Pd=[!]cmp.gtu(Rs,Rt) 209 - Rd=cl0(Rs) 462 Pd=cmp.gtu(Rss,Rtt) 629 - Rd=cl0(Rss) 462 - cmp.lt -cl1 Pd=cmp.lt(Rs,Rt) 209 - Rd=cl1(Rs) 462 - Rd=cl1(Rss) 463 - cmp.ltu - Pd=cmp.ltu(Rs,Rt) 209 -clb - Rd=add(clb(Rs),#s6) 462 - cmpb.eq - Rd=add(clb(Rss),#s6) 462 - Pd=cmpb.eq(Rs,#u8) 625 - Rd=clb(Rs) 463 - Pd=cmpb.eq(Rs,Rt) 625 - Rd=clb(Rss) 463 - -clrbit cmpb.gt - Pd=cmpb.gt(Rs,#s8) 625 - memb(Rs+#u6:0)=clrbit(#U5) 286 - Pd=cmpb.gt(Rs,Rt) 625 - memh(Rs+#u6:1)=clrbit(#U5) 287 - memw(Rs+#u6:2)=clrbit(#U5) 288 - Rd=clrbit(Rs,#u5) 476 cmpb.gtu - Rd=clrbit(Rs,Rt) 476 Pd=cmpb.gtu(Rs,#u7) 625 - Pd=cmpb.gtu(Rs,Rt) 625 - - cmph.eq - Pd=cmph.eq(Rs,#s8) 627 - Pd=cmph.eq(Rs,Rt) 627 - - cmph.gt - Pd=cmph.gt(Rs,#s8) 627 - Pd=cmph.gt(Rs,Rt) 627 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 685 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -cmph.gtu convert_sf2df - Pd=cmph.gtu(Rs,#u7) 627 Rdd=convert_sf2df(Rs) 521 - Pd=cmph.gtu(Rs,Rt) 627 - convert_sf2ud -cmpy Rdd=convert_sf2ud(Rs) 524 - Rd=cmpy(Rs,Rt)[:<<1]:rnd:sat 493 Rdd=convert_sf2ud(Rs):chop 524 - Rd=cmpy(Rs,Rt*)[:<<1]:rnd:sat 493 - Rdd=cmpy(Rs,Rt)[:<<1]:sat 489 convert_sf2uw - Rdd=cmpy(Rs,Rt*)[:<<1]:sat 489 Rd=convert_sf2uw(Rs) 524 - Rxx+=cmpy(Rs,Rt)[:<<1]:sat 489 Rd=convert_sf2uw(Rs):chop 524 - Rxx+=cmpy(Rs,Rt*)[:<<1]:sat 489 - Rxx-=cmpy(Rs,Rt)[:<<1]:sat 489 - Rxx-=cmpy(Rs,Rt*)[:<<1]:sat 489 - convert_sf2w - Rd=convert_sf2w(Rs) 524 - Rd=convert_sf2w(Rs):chop 524 -cmpyi - Rdd=cmpyi(Rs,Rt) 491 - Rxx+=cmpyi(Rs,Rt) 491 - convert_ud2df - Rdd=convert_ud2df(Rss) 522 -cmpyiwh - Rd=cmpyiwh(Rss,Rt):<<1:rnd:sat 495 - convert_ud2sf - Rd=cmpyiwh(Rss,Rt*):<<1:rnd:sat 495 Rd=convert_ud2sf(Rss) 522 - -cmpyr convert_uw2df - Rdd=cmpyr(Rs,Rt) 491 Rdd=convert_uw2df(Rs) 522 - Rxx+=cmpyr(Rs,Rt) 491 - convert_uw2sf -cmpyrwh Rd=convert_uw2sf(Rs) 522 - Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat 495 - Rd=cmpyrwh(Rss,Rt*):<<1:rnd:sat 495 convert_w2df - Rdd=convert_w2df(Rs) 522 -combine - if ([!]Pu[.new]) Rdd=combine(Rs,Rt) 200 convert_w2sf - Rd=combine(Rt.[HL],Rs.[HL]) 188 Rd=convert_w2sf(Rs) 522 - Rdd=combine(#s8,#S8) 189 - Rdd=combine(#s8,#U6) 189 cround - Rdd=combine(#s8,Rs) 189 Rd=cround(Rs,#u5) 409 - Rdd=combine(Rs,#s8) 189 Rd=cround(Rs,Rt) 409 - Rdd=combine(Rs,Rt) 189 - - cswi -convert_d2df cswi(Rs) 335 - Rdd=convert_d2df(Rss) 522 - ct0 -convert_d2sf Rd=ct0(Rs) 466 - Rd=convert_d2sf(Rss) 522 Rd=ct0(Rss) 466 - -convert_df2d ct1 - Rdd=convert_df2d(Rss) 524 Rd=ct1(Rs) 466 - Rdd=convert_df2d(Rss):chop 524 Rd=ct1(Rss) 466 - -convert_df2sf ctlbw - Rd=convert_df2sf(Rss) 521 Rd=ctlbw(Rss,Rt) 366 -convert_df2ud D - Rdd=convert_df2ud(Rss) 524 - Rdd=convert_df2ud(Rss):chop 524 dccleana - dccleana(Rs) 378 -convert_df2uw - Rd=convert_df2uw(Rss) 524 dccleanidx - Rd=convert_df2uw(Rss):chop 524 dccleanidx(Rs) 337 -convert_df2w dccleaninva - Rd=convert_df2w(Rss) 524 - dccleaninva(Rs) 378 - Rd=convert_df2w(Rss):chop 524 - dccleaninvidx -convert_sf2d - dccleaninvidx(Rs) 337 - Rdd=convert_sf2d(Rs) 524 - Rdd=convert_sf2d(Rs):chop 524 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 686 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -dcfetch endloop1 - dcfetch(Rs) 377 endloop1 212 - dcfetch(Rs+#u11:3) 377 - extract -dcinva Rd=extract(Rs,#u5,#U5) 468 - dcinva(Rs) 378 Rd=extract(Rs,Rtt) 468 - Rdd=extract(Rss,#u6,#U6) 468 -dcinvidx Rdd=extract(Rss,Rtt) 468 - dcinvidx(Rs) 337 - extractu -dckill Rd=extractu(Rs,#u5,#U5) 468 - dckill 336 Rd=extractu(Rs,Rtt) 468 - Rdd=extractu(Rss,#u6,#U6) 468 - Rdd=extractu(Rss,Rtt) 468 -dctagr - Rd=dctagr(Rs) 337 F -dctagw fastcorner9 - dctagw(Rs,Rt) 337 Pd=[!]fastcorner9(Ps,Pt) 214 -dczeroa G - dczeroa(Rs) 374 - getimask -dealloc_return Rd=getimask(Rs) 339 - dealloc_return 274 - if ([!]Ps) dealloc_return 274 H - nt - if ([!]Ps.new) dealloc_return:nt 274 - t hintjr - if ([!]Ps.new) dealloc_return:t 274 hintjr(Rs) 227 - -deallocframe I - deallocframe 272 - iassignr -decbin Rd=iassignr(Rs) 342 - Rdd=decbin(Rss,Rtt) 597 - iassignw -deinterleave iassignw(Rs) 344 - Rdd=deinterleave(Rss) 472 - icdatar -dfclass Rd=icdatar(Rs) 346 - Pd=dfclass(Rss,#u5) 517 - icinva -dfcmp.eq icinva(Rs) 379 - Pd=dfcmp.eq(Rss,Rtt) 519 - icinvidx -dfcmp.ge icinvidx(Rs) 346 - Pd=dfcmp.ge(Rss,Rtt) 519 - ickill -dfcmp.gt ickill 347 - Pd=dfcmp.gt(Rss,Rtt) 519 - ictagr -dfcmp.uo Rd=ictagr(Rs) 346 - Pd=dfcmp.uo(Rss,Rtt) 519 - ictagw -dfmake ictagw(Rs,Rt) 347 - Rdd=dfmake(#u10):neg 533 - Rdd=dfmake(#u10):pos 533 if ([!]p[01].new) jump: #r9:2 231, 231, - 231, 231, 232, 232, 232, 232, 232 -E - insert -endloop0 Rx=insert(Rs,#u5,#U5) 470 - endloop0 212 Rx=insert(Rs,Rtt) 470 - Rxx=insert(Rss,#u6,#U6) 470 -endloop01 Rxx=insert(Rss,Rtt) 470 - endloop01 212 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 687 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -interleave l2kill - Rdd=interleave(Rss) 472 l2kill 349 - -isync l2locka - isync 380 Pd=l2locka(Rs) 351 -J l2tagr - Rd=l2tagr(Rs) 353 -jump - if ([!]Pu.new) jump: #r15:2 238 l2tagw - if ([!]Pu) jump #r15:2 236 l2tagw(Rs,Rt) 353 - if ([!]Pu) jump: #r15:2 236 - jump #r22:2 236 - l2unlocka - nt - if (Rs!=#0) jump:nt #r13:2 239 - l2unlocka(Rs) 351 - if (Rs<=#0) jump:nt #r13:2 239 - if (Rs==#0) jump:nt #r13:2 239 lfs - if (Rs>=#0) jump:nt #r13:2 239 Rdd=lfs(Rss,Rtt) 473 - Rd=#U6 241 - Rd=Rs 241 - t - loop0 - if (Rs!=#0) jump:t #r13:2 239 loop0(#r7:2,#U10) 216 - if (Rs<=#0) jump:t #r13:2 239 loop0(#r7:2,Rs) 216 - if (Rs==#0) jump:t #r13:2 239 - if (Rs>=#0) jump:t #r13:2 239 loop1 - loop1(#r7:2,#U10) 216 -jump #r9:2 241, 241 loop1(#r7:2,Rs) 216 - -jumpr lsl - if ([!]Pu) jumpr Rs 228 Rd=lsl(#s6,Rt) 658 - if ([!]Pu[.new]) jumpr: Rs 228 Rd=lsl(Rs,Rt) 658 - jumpr Rs 228 Rdd=lsl(Rss,Rt) 659 - Rx[&|]=lsl(Rs,Rt) 665 -K Rx[+-]=lsl(Rs,Rt) 661 - Rxx^=lsl(Rss,Rt) 665 -k0lock Rxx[&|]=lsl(Rss,Rt) 665 - k0lock 340 Rxx[+-]=lsl(Rss,Rt) 662 - - -k0unlock lsr - k0unlock 341 Rd=lsr(Rs,#u5) 645 - Rd=lsr(Rs,Rt) 659 -L Rdd=lsr(Rss,#u6) 645 - Rdd=lsr(Rss,Rt) 659 - Rx^=lsr(Rs,#u5) 651 -l2cleanidx Rx[&|]=lsr(Rs,#u5) 651 - l2cleanidx(Rs) 348 Rx[&|]=lsr(Rs,Rt) 665 - Rx[+-]=lsr(Rs,#u5) 647 -l2cleaninvidx Rx[+-]=lsr(Rs,Rt) 662 - l2cleaninvidx(Rs) 348 Rx=add(#u8,lsr(Rx,#U5)) 647 - Rx=and(#u8,lsr(Rx,#U5)) 651 -l2fetch Rx=or(#u8,lsr(Rx,#U5)) 651 - Rx=sub(#u8,lsr(Rx,#U5)) 647 - l2fetch(Rs,Rt) 382 - Rxx^=lsr(Rss,#u6) 652 - l2fetch(Rs,Rtt) 382 - Rxx^=lsr(Rss,Rt) 665 - Rxx[&|]=lsr(Rss,#u6) 652 -l2gclean Rxx[&|]=lsr(Rss,Rt) 665 - l2gclean 349 Rxx[+-]=lsr(Rss,#u6) 647 - l2gclean(Rtt) 349 Rxx[+-]=lsr(Rss,Rt) 662 - -l2gcleaninv M - l2gcleaninv 349 - l2gcleaninv(Rtt) 349 mask - Rdd=mask(Pt) 632 -l2gunlock - l2gunlock 349 max - Rd=max(Rs,Rt) 403 -l2invidx Rdd=max(Rss,Rtt) 404 - l2invidx(Rs) 348 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 688 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -maxu membh - Rd=maxu(Rs,Rt) 403 Rd=membh(Re=#U6) 277 - Rdd=maxu(Rss,Rtt) 404 Rd=membh(Rs) 277 - Rd=membh(Rs+#s11:1) 277 -memb Rd=membh(Rt<<#u2+#U6) 277 - if ([!]Pt[.new]) Rd=memb(#u6) 248 Rd=membh(Rx++#s4:1:circ(Mu)) 277 - if ([!]Pt[.new]) Rd=memb(Rs+#u6:0) 248 Rd=membh(Rx++#s4:1) 277 - if ([!]Pt[.new]) Rd=memb(Rx++#s4:0) 248 Rd=membh(Rx++I:circ(Mu)) 277 - if ([!]Pv[.new]) memb(#u6)=Nt.new 295 Rd=membh(Rx++Mu:brev) 278 - if ([!]Pv[.new]) memb(#u6)=Rt 314 Rd=membh(Rx++Mu) 278 - if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6 314 Rdd=membh(Re=#U6) 279 - if ([!]Pv[.new]) memb(Rs+#u6:0)=Nt.new 295 Rdd=membh(Rs) 279 - if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt 314 Rdd=membh(Rs+#s11:2) 279 - if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Nt.new 295 Rdd=membh(Rt<<#u2+#U6) 280 - if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Rt 314 Rdd=membh(Rx++#s4:2:circ(Mu)) 280 - if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new 295 Rdd=membh(Rx++#s4:2) 280 - if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt 314 Rdd=membh(Rx++I:circ(Mu)) 280 - if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2) 248 Rdd=membh(Rx++Mu:brev) 280 - memb(gp+#u16:0)=Nt.new 293 Rdd=membh(Rx++Mu) 280 - memb(gp+#u16:0)=Rt 312 - memb(Re=#U6)=Nt.new 293 memd - memb(Re=#U6)=Rt 312 if ([!]Pt[.new]) Rdd=memd(#u6) 244 - memb(Rs+#s11:0)=Nt.new 293 if ([!]Pt[.new]) Rdd=memd(Rs+#u6:3) 244 - memb(Rs+#s11:0)=Rt 312 if ([!]Pt[.new]) Rdd=memd(Rx++#s4:3) 244 - memb(Rs+#u6:0)[+-]=#U5 286 if ([!]Pv[.new]) memd(#u6)=Rtt 310 - memb(Rs+#u6:0)[+-|&]=Rt 286 if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt 310 - memb(Rs+#u6:0)=#S8 312 if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt 310 - memb(Rs+Ru<<#u2)=Nt.new 293 if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt 310 - memb(Rs+Ru<<#u2)=Rt 312 if ([!]Pv[.new]) Rdd=memd(Rs+Rt<<#u2) 244 - memb(Ru<<#u2+#U6)=Nt.new 293 memd(gp+#u16:3)=Rtt 308 - memb(Ru<<#u2+#U6)=Rt 312 memd(Re=#U6)=Rtt 308 - memb(Rx++#s4:0:circ(Mu))=Nt.new 293 memd(Rs+#s11:3)=Rtt 308 - memb(Rx++#s4:0:circ(Mu))=Rt 312 memd(Rs+Ru<<#u2)=Rtt 308 - memb(Rx++#s4:0)=Nt.new 293 memd(Ru<<#u2+#U6)=Rtt 308 - memb(Rx++#s4:0)=Rt 312 memd(Rx++#s4:3:circ(Mu))=Rtt 308 - memb(Rx++I:circ(Mu))=Nt.new 293 memd(Rx++#s4:3)=Rtt 308 - memb(Rx++I:circ(Mu))=Rt 312 memd(Rx++I:circ(Mu))=Rtt 308 - memb(Rx++Mu:brev)=Nt.new 293 memd(Rx++Mu:brev)=Rtt 308 - memb(Rx++Mu:brev)=Rt 312 memd(Rx++Mu)=Rtt 308 - memb(Rx++Mu)=Nt.new 293 Rdd=memd(gp+#u16:3) 242 - memb(Rx++Mu)=Rt 312 Rdd=memd(Re=#U6) 242 - Rd=memb(gp+#u16:0) 246 Rdd=memd(Rs+#s11:3) 242 - Rd=memb(Re=#U6) 246 Rdd=memd(Rs+Rt<<#u2) 242 - Rd=memb(Rs+#s11:0) 246 Rdd=memd(Rt<<#u2+#U6) 242 - Rd=memb(Rs+Rt<<#u2) 246 Rdd=memd(Rx++#s4:3:circ(Mu)) 242 - Rd=memb(Rt<<#u2+#U6) 246 Rdd=memd(Rx++#s4:3) 242 - Rd=memb(Rx++#s4:0:circ(Mu)) 246 Rdd=memd(Rx++I:circ(Mu)) 242 - Rd=memb(Rx++#s4:0) 246 Rdd=memd(Rx++Mu:brev) 242 - Rd=memb(Rx++I:circ(Mu)) 246 Rdd=memd(Rx++Mu) 242 - Rd=memb(Rx++Mu:brev) 246 - Rd=memb(Rx++Mu) 246 memd_locked - memd_locked(Rs,Pd)=Rtt 372 -memb_fifo Rdd=memd_locked(Rs) 371 - Ryy=memb_fifo(Re=#U6) 250 - Ryy=memb_fifo(Rs) 250 - Ryy=memb_fifo(Rs+#s11:0) 250 - Ryy=memb_fifo(Rt<<#u2+#U6) 250 - Ryy=memb_fifo(Rx++#s4:0:circ(Mu)) 251 - Ryy=memb_fifo(Rx++#s4:0) 251 - Ryy=memb_fifo(Rx++I:circ(Mu)) 251 - Ryy=memb_fifo(Rx++Mu:brev) 251 - Ryy=memb_fifo(Rx++Mu) 251 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 689 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -memh memh_fifo - if ([!]Pt[.new]) Rd=memh(#u6) 258 Ryy=memh_fifo(Re=#U6) 253 - if ([!]Pt[.new]) Rd=memh(Rs+#u6:1) 258 Ryy=memh_fifo(Rs) 253 - if ([!]Pt[.new]) Rd=memh(Rx++#s4:1) 258 Ryy=memh_fifo(Rs+#s11:1) 253 - if ([!]Pv[.new]) memh(#u6)=Nt.new 300 Ryy=memh_fifo(Rt<<#u2+#U6) 253 - if ([!]Pv[.new]) memh(#u6)=Rt 320 Ryy=memh_fifo(Rx++#s4:1:circ(Mu)) 254 - if ([!]Pv[.new]) memh(#u6)=Rt.H 320 Ryy=memh_fifo(Rx++#s4:1) 254 - if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6 320 Ryy=memh_fifo(Rx++I:circ(Mu)) 254 - if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new 300 Ryy=memh_fifo(Rx++Mu:brev) 254 - if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt 321 Ryy=memh_fifo(Rx++Mu) 254 - if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H 320 - if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Nt.new 300 memub - if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt 321 if ([!]Pt[.new]) Rd=memub(#u6) 262 - if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt.H 321 if ([!]Pt[.new]) Rd=memub(Rs+#u6:0) 262 - if ([!]Pv[.new]) memh(Rx++#s4:1)=Nt.new 300 if ([!]Pt[.new]) Rd=memub(Rx++#s4:0) 262 - if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt 321 if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2) 262 - if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H 321 Rd=memub(gp+#u16:0) 260 - if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2) 258 Rd=memub(Re=#U6) 260 - memh(gp+#u16:1)=Nt.new 298 Rd=memub(Rs+#s11:0) 260 - memh(gp+#u16:1)=Rt 318 Rd=memub(Rs+Rt<<#u2) 260 - memh(gp+#u16:1)=Rt.H 318 Rd=memub(Rt<<#u2+#U6) 260 - memh(Re=#U6)=Nt.new 298 Rd=memub(Rx++#s4:0:circ(Mu)) 260 - memh(Re=#U6)=Rt 317 Rd=memub(Rx++#s4:0) 260 - memh(Re=#U6)=Rt.H 317 Rd=memub(Rx++I:circ(Mu)) 260 - memh(Rs+#s11:1)=Nt.new 298 Rd=memub(Rx++Mu:brev) 260 - memh(Rs+#s11:1)=Rt 317 Rd=memub(Rx++Mu) 260 - memh(Rs+#s11:1)=Rt.H 317 - memh(Rs+#u6:1)[+-]=#U5 287 - memh(Rs+#u6:1)[+-|&]=Rt 287 - memubh - memh(Rs+#u6:1)=#S8 317 Rd=memubh(Re=#U6) 278 - memh(Rs+Ru<<#u2)=Nt.new 298 Rd=memubh(Rs+#s11:1) 278 - memh(Rs+Ru<<#u2)=Rt 317 Rd=memubh(Rt<<#u2+#U6) 278 - memh(Rs+Ru<<#u2)=Rt.H 317 Rd=memubh(Rx++#s4:1:circ(Mu)) 279 - memh(Ru<<#u2+#U6)=Nt.new 298 Rd=memubh(Rx++#s4:1) 278 - memh(Ru<<#u2+#U6)=Rt 317 Rd=memubh(Rx++I:circ(Mu)) 279 - memh(Ru<<#u2+#U6)=Rt.H 317 Rd=memubh(Rx++Mu:brev) 279 - memh(Rx++#s4:1:circ(Mu))=Nt.new 298 Rd=memubh(Rx++Mu) 279 - memh(Rx++#s4:1:circ(Mu))=Rt 317 Rdd=memubh(Re=#U6) 281 - memh(Rx++#s4:1:circ(Mu))=Rt.H 317 Rdd=memubh(Rs+#s11:2) 281 - memh(Rx++#s4:1)=Nt.new 298 Rdd=memubh(Rt<<#u2+#U6) 281 - memh(Rx++#s4:1)=Rt 317 Rdd=memubh(Rx++#s4:2:circ(Mu)) 282 - memh(Rx++#s4:1)=Rt.H 317 Rdd=memubh(Rx++#s4:2) 282 - memh(Rx++I:circ(Mu))=Nt.new 298 Rdd=memubh(Rx++I:circ(Mu)) 282 - memh(Rx++I:circ(Mu))=Rt 317 Rdd=memubh(Rx++Mu:brev) 282 - memh(Rx++I:circ(Mu))=Rt.H 317 Rdd=memubh(Rx++Mu) 282 - memh(Rx++Mu:brev)=Nt.new 298 - memh(Rx++Mu:brev)=Rt 318 memuh - memh(Rx++Mu:brev)=Rt.H 318 if ([!]Pt[.new]) Rd=memuh(#u6) 266 - memh(Rx++Mu)=Nt.new 298 if ([!]Pt[.new]) Rd=memuh(Rs+#u6:1) 266 - memh(Rx++Mu)=Rt 318 if ([!]Pt[.new]) Rd=memuh(Rx++#s4:1) 266 - memh(Rx++Mu)=Rt.H 318 if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2) 266 - Rd=memh(gp+#u16:1) 256 Rd=memuh(gp+#u16:1) 264 - Rd=memh(Re=#U6) 256 Rd=memuh(Re=#U6) 264 - Rd=memh(Rs+#s11:1) 256 Rd=memuh(Rs+#s11:1) 264 - Rd=memh(Rs+Rt<<#u2) 256 Rd=memuh(Rs+Rt<<#u2) 264 - Rd=memh(Rt<<#u2+#U6) 256 Rd=memuh(Rt<<#u2+#U6) 264 - Rd=memh(Rx++#s4:1:circ(Mu)) 256 Rd=memuh(Rx++#s4:1:circ(Mu)) 264 - Rd=memh(Rx++#s4:1) 256 Rd=memuh(Rx++#s4:1) 264 - Rd=memh(Rx++I:circ(Mu)) 256 Rd=memuh(Rx++I:circ(Mu)) 264 - Rd=memh(Rx++Mu:brev) 256 Rd=memuh(Rx++Mu:brev) 264 - Rd=memh(Rx++Mu) 256 Rd=memuh(Rx++Mu) 264 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 690 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -memw mpy - if ([!]Pt[.new]) Rd=memw(#u6) 270 Rd=mpy(Rs,Rt.H):<<1:rnd:sat 567 - if ([!]Pt[.new]) Rd=memw(Rs+#u6:2) 270 Rd=mpy(Rs,Rt.H):<<1:sat 567 - if ([!]Pt[.new]) Rd=memw(Rx++#s4:2) 270 Rd=mpy(Rs,Rt.L):<<1:rnd:sat 567 - if ([!]Pv[.new]) memw(#u6)=Nt.new 305 Rd=mpy(Rs,Rt.L):<<1:sat 567 - if ([!]Pv[.new]) memw(#u6)=Rt 326 Rd=mpy(Rs,Rt) 567 - if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6 326 Rd=mpy(Rs,Rt):<<1 567 - if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new 305 Rd=mpy(Rs,Rt):<<1:sat 567 - if ([!]Pv[.new]) memw(Rs+#u6:2)=Rt 326 Rd=mpy(Rs,Rt):rnd 567 - if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Nt.new 305 Rd=mpy(Rs.[HL],Rt.[HL])[:<<1][:rnd][:sat] 550 - if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Rt 326 Rdd=mpy(Rs,Rt) 570 - if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new 305 Rdd=mpy(Rs.[HL],Rt.[HL])[:<<1][:rnd] 550 - if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt 326 Rx+=mpy(Rs,Rt):<<1:sat 567 - if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2) 270 Rx+=mpy(Rs.[HL],Rt.[HL])[:<<1][:sat] 550 - memw(gp+#u16:2)=Nt.new 303 Rx-=mpy(Rs,Rt):<<1:sat 567 - memw(gp+#u16:2)=Rt 324 Rx-=mpy(Rs.[HL],Rt.[HL])[:<<1][:sat] 550 - memw(Re=#U6)=Nt.new 303 Rxx[+-]=mpy(Rs,Rt) 570 - memw(Re=#U6)=Rt 324 Rxx+=mpy(Rs.[HL],Rt.[HL])[:<<1] 550 - memw(Rs+#s11:2)=Nt.new 303 Rxx-=mpy(Rs.[HL],Rt.[HL])[:<<1] 550 - memw(Rs+#s11:2)=Rt 324 - memw(Rs+#u6:2)[+-]=#U5 288 mpyi - memw(Rs+#u6:2)[+-|&]=Rt 288 Rd=+mpyi(Rs,#u8) 539 - memw(Rs+#u6:2)=#S8 324 Rd=mpyi(Rs,#m9) 540 - memw(Rs+Ru<<#u2)=Nt.new 303 Rd=-mpyi(Rs,#u8) 539 - memw(Rs+Ru<<#u2)=Rt 324 Rd=mpyi(Rs,Rt) 540 - memw(Ru<<#u2+#U6)=Nt.new 303 Rx+=mpyi(Rs,#u8) 540 - memw(Ru<<#u2+#U6)=Rt 324 Rx+=mpyi(Rs,Rt) 540 - memw(Rx++#s4:2:circ(Mu))=Nt.new 303 Rx-=mpyi(Rs,#u8) 540 - memw(Rx++#s4:2:circ(Mu))=Rt 324 - memw(Rx++#s4:2)=Nt.new 303 - memw(Rx++#s4:2)=Rt 324 - mpysu - memw(Rx++I:circ(Mu))=Nt.new 303 Rd=mpysu(Rs,Rt) 567 - memw(Rx++I:circ(Mu))=Rt 324 - memw(Rx++Mu:brev)=Nt.new 303 mpyu - memw(Rx++Mu:brev)=Rt 324 Rd=mpyu(Rs,Rt) 567 - memw(Rx++Mu)=Nt.new 303 Rd=mpyu(Rs.[HL],Rt.[HL])[:<<1] 558 - memw(Rx++Mu)=Rt 324 Rdd=mpyu(Rs,Rt) 570 - Rd=memw(gp+#u16:2) 268 Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1] 558 - Rd=memw(Re=#U6) 268 Rx+=mpyu(Rs.[HL],Rt.[HL])[:<<1] 558 - Rd=memw(Rs+#s11:2) 268 Rx-=mpyu(Rs.[HL],Rt.[HL])[:<<1] 558 - Rd=memw(Rs+Rt<<#u2) 268 Rxx[+-]=mpyu(Rs,Rt) 570 - Rd=memw(Rt<<#u2+#U6) 268 Rxx+=mpyu(Rs.[HL],Rt.[HL])[:<<1] 558 - Rd=memw(Rx++#s4:2:circ(Mu)) 268 Rxx-=mpyu(Rs.[HL],Rt.[HL])[:<<1] 558 - Rd=memw(Rx++#s4:2) 268 - Rd=memw(Rx++I:circ(Mu)) 268 mpyui - Rd=memw(Rx++Mu:brev) 268 Rd=mpyui(Rs,Rt) 540 - Rd=memw(Rx++Mu) 268 - - mux -memw_locked Rd=mux(Pu,#s8,#S8) 191 - memw_locked(Rs,Pd)=Rt 372 Rd=mux(Pu,#s8,Rs) 191 - Rd=memw_locked(Rs) 371 Rd=mux(Pu,Rs,#s8) 191 - Rd=mux(Pu,Rs,Rt) 191 -memw_phys - Rd=memw_phys(Rs,Rt) 355 N -min neg - Rd=min(Rt,Rs) 405 Rd=neg(Rs) 175 - Rdd=min(Rtt,Rss) 406 Rd=neg(Rs):sat 408 - Rdd=neg(Rss) 408 -minu - Rd=minu(Rt,Rs) 405 nmi - Rdd=minu(Rtt,Rss) 406 nmi(Rs) 356 - -modwrap - Rd=modwrap(Rs,Rt) 407 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 691 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -no mnemonic pmpyw - Cd=Rs 223 Rdd=pmpyw(Rs,Rt) 563 - Cdd=Rss 223 Rxx^=pmpyw(Rs,Rt) 563 - Gd=Rs 331 - Gdd=Rss 331 popcount - if ([!]Pu[.new]) Rd=#s12 206 Rd=popcount(Rss) 465 - if ([!]Pu[.new]) Rd=Rs 206 - if ([!]Pu[.new]) Rdd=Rss 206 R - Pd=Ps 221 - Pd=Rs 634 - Rd=#s16 180 resume - Rd=Cs 223 resume(Rs) 357 - Rd=Gs 331 - Rd=Ps 634 rol - Rd=Rs 182 Rd=rol(Rs,#u5) 645 - Rd=Ss 368 Rdd=rol(Rss,#u6) 645 - Rdd=#s8 180 Rx^=rol(Rs,#u5) 651 - Rdd=Css 223 Rx[&|]=rol(Rs,#u5) 651 - Rdd=Gss 331 Rx[+-]=rol(Rs,#u5) 647 - Rdd=Rss 182 Rxx^=rol(Rss,#u6) 652 - Rdd=Sss 368 Rxx[&|]=rol(Rss,#u6) 652 - Rx.[HL]=#u16 180 Rxx[+-]=rol(Rss,#u6) 647 - Sd=Rs 368 - Sdd=Rss 368 round - Rd=round(Rs,#u5)[:sat] 409 -nop Rd=round(Rs,Rt)[:sat] 409 - nop 176 Rd=round(Rss):sat 409 - -normamt rte - Rd=normamt(Rs) 463 rte 358 - Rd=normamt(Rss) 463 - rteunlock -not rteunlock 359 - Pd=not(Ps) 221 - Rd=not(Rs) 173 S - Rdd=not(Rss) 398 - -O sat - Rd=sat(Rss) 599 -or satb - if ([!]Pu[.new]) Rd=or(Rs,Rt) 201 Rd=satb(Rs) 599 - Pd=and(Ps,or(Pt,[!]Pu)) 221 - Pd=or(Ps,and(Pt,[!]Pu)) 221 - Pd=or(Ps,or(Pt,[!]Pu)) 221 sath - Pd=or(Pt,[!]Ps) 221 Rd=sath(Rs) 599 - Rd=or(Rs,#s10) 173 - Rd=or(Rs,Rt) 173 satub - Rd=or(Rt,~Rs) 173 Rd=satub(Rs) 599 - Rdd=or(Rss,Rtt) 398 - Rdd=or(Rtt,~Rss) 398 satuh - Rx[&|^]=or(Rs,Rt) 401 - Rd=satuh(Rs) 599 - Rx=or(Ru,and(Rx,#s10)) 401 - Rx|=or(Rs,#s10) 401 - setbit -P memb(Rs+#u6:0)=setbit(#U5) 286 - memh(Rs+#u6:1)=setbit(#U5) 287 - memw(Rs+#u6:2)=setbit(#U5) 288 -packhl Rd=setbit(Rs,#u5) 476 - Rdd=packhl(Rs,Rt) 195 Rd=setbit(Rs,Rt) 476 - -parity setimask - Rd=parity(Rs,Rt) 474 setimask(Pt,Rs) 360 - Rd=parity(Rss,Rtt) 474 - - sfadd -pause Rd=sfadd(Rs,Rt) 516 - pause(#u8) 384 - sfclass -pc Pd=sfclass(Rs,#u5) 517 - Rd=add(pc,#u6) 218 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 692 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -sfcmp.eq shuffob - Pd=sfcmp.eq(Rs,Rt) 519 Rdd=shuffob(Rtt,Rss) 611 - -sfcmp.ge shuffoh - Pd=sfcmp.ge(Rs,Rt) 519 Rdd=shuffoh(Rtt,Rss) 611 - -sfcmp.gt siad - Pd=sfcmp.gt(Rs,Rt) 519 siad(Rs) 361 - -sfcmp.uo sp1loop0 - Pd=sfcmp.uo(Rs,Rt) 519 p3=sp1loop0(#r7:2,#U10) 219 - p3=sp1loop0(#r7:2,Rs) 219 -sffixupd - Rd=sffixupd(Rs,Rt) 527 sp2loop0 - p3=sp2loop0(#r7:2,#U10) 219 -sffixupn p3=sp2loop0(#r7:2,Rs) 219 - Rd=sffixupn(Rs,Rt) 527 - sp3loop0 -sffixupr p3=sp3loop0(#r7:2,#U10) 219 - Rd=sffixupr(Rs) 527 p3=sp3loop0(#r7:2,Rs) 219 - - -sfinvsqrta start - Rd,Pe=sfinvsqrta(Rs) 530 start(Rs) 362 - -sfmake stop - Rd=sfmake(#u10):neg 533 stop(Rs) 363 - Rd=sfmake(#u10):pos 533 - sub -sfmax if ([!]Pu[.new]) Rd=sub(Rt,Rs) 203 - Rd=sfmax(Rs,Rt) 534 Rd=add(Rs,sub(#s6,Ru)) 390 - Rd=sub(#s10,Rs) 177 - Rd=sub(Rt,Rs) 177 -sfmin Rd=sub(Rt,Rs):sat 177 - Rd=sfmin(Rs,Rt) 535 Rd=sub(Rt,Rs):sat:deprecated 411 - Rd=sub(Rt.[HL],Rs.[HL])[:sat]:<<16 413 -sfmpy Rd=sub(Rt.L,Rs.[HL])[:sat] 413 - Rd=sfmpy(Rs,Rt) 536 Rdd=sub(Rss,Rtt,Px):carry 397 - Rx+=sfmpy(Rs,Rt,Pu):scale 529 Rdd=sub(Rtt,Rss) 411 - Rx+=sfmpy(Rs,Rt) 528 Rx+=sub(Rt,Rs) 412 - Rx+=sfmpy(Rs,Rt):lib 531 - Rx-=sfmpy(Rs,Rt) 528 swi - Rx-=sfmpy(Rs,Rt):lib 531 swi(Rs) 364 -sfrecipa swiz - Rd,Pe=sfrecipa(Rs,Rt) 537 Rd=swiz(Rs) 601 -sfsub sxtb - Rd=sfsub(Rs,Rt) 538 if ([!]Pu[.new]) Rd=sxtb(Rs) 204 - Rd=sxtb(Rs) 179 -sgp - crswap(Rx,sgp) 334 sxth - if ([!]Pu[.new]) Rd=sxth(Rs) 204 -sgp0 Rd=sxth(Rs) 179 - crswap(Rx,sgp0) 334 - sxtw -sgp1 Rdd=sxtw(Rs) 416 - 0 - crswap(Rxx,sgp1:0) 334 syncht - crswap(Rx,sgp1) 334 - syncht 385 -shuffeb T - Rdd=shuffeb(Rss,Rtt) 611 - tableidxb -shuffeh Rx=tableidxb(Rs,#u4,#S6):raw 481 - Rdd=shuffeh(Rss,Rtt) 611 Rx=tableidxb(Rs,#u4,#U5) 481 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 693 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -tableidxd vabsdiffw - Rx=tableidxd(Rs,#u4,#S6):raw 481 Rdd=vabsdiffw(Rtt,Rss) 421 - Rx=tableidxd(Rs,#u4,#U5) 481 - vabsh -tableidxh Rdd=vabsh(Rss) 417 - Rx=tableidxh(Rs,#u4,#S6):raw 481 Rdd=vabsh(Rss):sat 417 - Rx=tableidxh(Rs,#u4,#U5) 481 - vabsw -tableidxw Rdd=vabsw(Rss) 418 - Rx=tableidxw(Rs,#u4,#S6):raw 481 Rdd=vabsw(Rss):sat 418 - Rx=tableidxw(Rs,#u4,#U5) 481 - vacsh -tlbinvasid Rxx,Pe=vacsh(Rss,Rtt) 423 - tlbinvasid(Rs) 366 - vaddb -tlblock Rdd=vaddb(Rss,Rtt) 432 - tlblock 340 - vaddh -tlbmatch Rd=vaddh(Rs,Rt)[:sat] 183 - Pd=tlbmatch(Rss,Rt) 633 Rdd=vaddh(Rss,Rtt)[:sat] 425 - -tlboc vaddhub - Rd=tlboc(Rss) 366 Rd=vaddhub(Rss,Rtt):sat 427 - -tlbp vaddub - Rd=tlbp(Rs) 366 Rdd=vaddub(Rss,Rtt)[:sat] 432 - -tlbr vadduh - Rdd=tlbr(Rs) 366 Rd=vadduh(Rs,Rt):sat 183 - Rdd=vadduh(Rss,Rtt):sat 425 -tlbunlock - tlbunlock 341 vaddw - Rdd=vaddw(Rss,Rtt)[:sat] 433 -tlbw - tlbw(Rss,Rt) 366 valignb - Rdd=valignb(Rtt,Rss,#u3) 602 -togglebit Rdd=valignb(Rtt,Rss,Pu) 602 - Rd=togglebit(Rs,#u5) 476 - Rd=togglebit(Rs,Rt) 476 vaslh - Rdd=vaslh(Rss,#u4) 670 -trace Rdd=vaslh(Rss,Rt) 676 - trace(Rs) 386 - vaslw -trap0 Rdd=vaslw(Rss,#u5) 678 - trap0(#u8) 387 Rdd=vaslw(Rss,Rt) 680 - - -trap1 vasrh - trap1(#u8) 387 Rdd=vasrh(Rss,#u4) 670 - Rdd=vasrh(Rss,#u4):raw 672 - Rdd=vasrh(Rss,#u4):rnd 672 -tstbit Rdd=vasrh(Rss,Rt) 676 - if ([!]tstbit(Ns.new,#0)) jump: #r9:2 290 - p[01]=tstbit(Rs,#0) 232 - Pd=[!]tstbit(Rs,#u5) 635 - vasrhub - Pd=[!]tstbit(Rs,Rt) 635 Rd=vasrhub(Rss,#u4):raw 674 - Rd=vasrhub(Rss,#u4):rnd:sat 674 -V Rd=vasrhub(Rss,#u4):sat 674 - - -vabsdiffb vasrw - Rd=vasrw(Rss,#u5) 682 - Rdd=vabsdiffb(Rtt,Rss) 419 - Rd=vasrw(Rss,Rt) 682 - Rdd=vasrw(Rss,#u5) 678 -vabsdiffh Rdd=vasrw(Rss,Rt) 680 - Rdd=vabsdiffh(Rtt,Rss) 420 - -vabsdiffub - Rdd=vabsdiffub(Rtt,Rss) 419 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 694 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -vavgh vcnegh - Rd=vavgh(Rs,Rt) 184 Rdd=vcnegh(Rss,Rt) 439 - Rd=vavgh(Rs,Rt):rnd 184 - Rdd=vavgh(Rss,Rtt) 434 vconj - Rdd=vavgh(Rss,Rtt):crnd 434 Rdd=vconj(Rss):sat 500 - Rdd=vavgh(Rss,Rtt):rnd 434 - - vcrotate -vavgub Rdd=vcrotate(Rss,Rt) 501 - Rdd=vavgub(Rss,Rtt) 436 - Rdd=vavgub(Rss,Rtt):rnd 436 - vdmpy - Rd=vdmpy(Rss,Rtt)[:<<1]:rnd:sat 575 -vavguh Rdd=vdmpy(Rss,Rtt):<<1:sat 573 - Rdd=vavguh(Rss,Rtt) 434 Rdd=vdmpy(Rss,Rtt):sat 573 - Rdd=vavguh(Rss,Rtt):rnd 434 Rxx+=vdmpy(Rss,Rtt):<<1:sat 573 - Rxx+=vdmpy(Rss,Rtt):sat 573 -vavguw - Rdd=vavguw(Rss,Rtt)[:rnd] 437 vdmpybsu - Rdd=vdmpybsu(Rss,Rtt):sat 580 -vavgw Rxx+=vdmpybsu(Rss,Rtt):sat 580 - Rdd=vavgw(Rss,Rtt):crnd 437 - Rdd=vavgw(Rss,Rtt)[:rnd] 437 vitpack - Rd=vitpack(Ps,Pt) 643 -vcmpb.eq - Pd=any8(vcmpb.eq(Rss,Rtt)) 638 vlslh - Pd=vcmpb.eq(Rss,#u8) 639 Rdd=vlslh(Rss,Rt) 676 - Pd=vcmpb.eq(Rss,Rtt) 639 - - vlslw -vcmpb.gt Rdd=vlslw(Rss,Rt) 680 - Pd=vcmpb.gt(Rss,#s8) 639 - Pd=vcmpb.gt(Rss,Rtt) 639 - vlsrh - Rdd=vlsrh(Rss,#u4) 670 -vcmpb.gtu Rdd=vlsrh(Rss,Rt) 676 - Pd=vcmpb.gtu(Rss,#u7) 639 - Pd=vcmpb.gtu(Rss,Rtt) 639 - vlsrw - Rdd=vlsrw(Rss,#u5) 678 -vcmph.eq Rdd=vlsrw(Rss,Rt) 680 - Pd=vcmph.eq(Rss,#s8) 636 - Pd=vcmph.eq(Rss,Rtt) 636 - vmaxb - Rdd=vmaxb(Rtt,Rss) 441 -vcmph.gt - Pd=vcmph.gt(Rss,#s8) 636 - Pd=vcmph.gt(Rss,Rtt) 636 vmaxh - Rdd=vmaxh(Rtt,Rss) 442 -vcmph.gtu - Pd=vcmph.gtu(Rss,#u7) 636 vmaxub - Pd=vcmph.gtu(Rss,Rtt) 636 Rdd=vmaxub(Rtt,Rss) 441 - -vcmpw.eq vmaxuh - Pd=vcmpw.eq(Rss,#s8) 641 Rdd=vmaxuh(Rtt,Rss) 442 - Pd=vcmpw.eq(Rss,Rtt) 641 - vmaxuw -vcmpw.gt Rdd=vmaxuw(Rtt,Rss) 447 - Pd=vcmpw.gt(Rss,#s8) 641 - Pd=vcmpw.gt(Rss,Rtt) 641 vmaxw - Rdd=vmaxw(Rtt,Rss) 447 -vcmpw.gtu - Pd=vcmpw.gtu(Rss,#u7) 641 vminb - Pd=vcmpw.gtu(Rss,Rtt) 641 Rdd=vminb(Rtt,Rss) 448 - -vcmpyi vminh - Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat 498 Rdd=vminh(Rtt,Rss) 450 - Rxx+=vcmpyi(Rss,Rtt):sat 498 - vminub -vcmpyr Rdd,Pe=vminub(Rtt,Rss) 448 - Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat 498 Rdd=vminub(Rtt,Rss) 448 - Rxx+=vcmpyr(Rss,Rtt):sat 498 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 695 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -vminuh vnavgw - Rdd=vminuh(Rtt,Rss) 450 Rdd=vnavgw(Rtt,Rss) 437 - Rdd=vnavgw(Rtt,Rss):crnd:sat 437 -vminuw Rdd=vnavgw(Rtt,Rss):rnd:sat 437 - Rdd=vminuw(Rtt,Rss) 455 - vpmpyh -vminw Rdd=vpmpyh(Rs,Rt) 595 - Rdd=vminw(Rtt,Rss) 455 Rxx^=vpmpyh(Rs,Rt) 595 - - -vmpybsu vraddh - Rdd=vmpybsu(Rs,Rt) 592 Rd=vraddh(Rss,Rtt) 430 - Rxx+=vmpybsu(Rs,Rt) 592 - vraddub -vmpybu Rdd=vraddub(Rss,Rtt) 428 - Rdd=vmpybu(Rs,Rt) 592 Rxx+=vraddub(Rss,Rtt) 428 - Rxx+=vmpybu(Rs,Rt) 592 - vradduh -vmpyeh Rd=vradduh(Rss,Rtt) 430 - Rdd=vmpyeh(Rss,Rtt):<<1:sat 582 - Rdd=vmpyeh(Rss,Rtt):sat 582 vrcmpyi - Rxx+=vmpyeh(Rss,Rtt) 582 Rdd=vrcmpyi(Rss,Rtt) 503 - Rxx+=vmpyeh(Rss,Rtt):<<1:sat 582 Rdd=vrcmpyi(Rss,Rtt*) 503 - Rxx+=vmpyeh(Rss,Rtt):sat 582 Rxx+=vrcmpyi(Rss,Rtt) 504 - Rxx+=vrcmpyi(Rss,Rtt*) 504 -vmpyh - Rd=vmpyh(Rs,Rt)[:<<1]:rnd:sat 586 vrcmpyr - Rdd=vmpyh(Rs,Rt)[:<<1]:sat 584 Rdd=vrcmpyr(Rss,Rtt) 503 - Rxx+=vmpyh(Rs,Rt) 584 Rdd=vrcmpyr(Rss,Rtt*) 504 - Rxx+=vmpyh(Rs,Rt)[:<<1]:sat 584 Rxx+=vrcmpyr(Rss,Rtt) 504 - Rxx+=vrcmpyr(Rss,Rtt*) 504 -vmpyhsu - Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat 588 vrcmpys - Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat 588 Rd=vrcmpys(Rss,Rt):<<1:rnd:sat 510 - Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:hi 510 -vmpyweh Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:lo 510 - Rdd=vmpyweh(Rss,Rtt)[:<<1]:rnd:sat 543 Rdd=vrcmpys(Rss,Rt):<<1:sat 507 - Rdd=vmpyweh(Rss,Rtt)[:<<1]:sat 543 Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:hi 507 - Rxx+=vmpyweh(Rss,Rtt)[:<<1]:rnd:sat 543 Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:lo 507 - Rxx+=vmpyweh(Rss,Rtt)[:<<1]:sat 543 Rxx+=vrcmpys(Rss,Rt):<<1:sat 507 - Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:hi 507 - Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:lo 507 -vmpyweuh - Rdd=vmpyweuh(Rss,Rtt)[:<<1]:rnd:sat 547 - Rdd=vmpyweuh(Rss,Rtt)[:<<1]:sat 547 - vrcnegh - Rxx+=vmpyweuh(Rss,Rtt)[:<<1]:rnd:sat 547 Rxx+=vrcnegh(Rss,Rt) 439 - Rxx+=vmpyweuh(Rss,Rtt)[:<<1]:sat 547 - vrcrotate -vmpywoh Rdd=vrcrotate(Rss,Rt,#u2) 513 - Rdd=vmpywoh(Rss,Rtt)[:<<1]:rnd:sat 543 Rxx+=vrcrotate(Rss,Rt,#u2) 513 - Rdd=vmpywoh(Rss,Rtt)[:<<1]:sat 543 - Rxx+=vmpywoh(Rss,Rtt)[:<<1]:rnd:sat 543 vrmaxh - Rxx+=vmpywoh(Rss,Rtt)[:<<1]:sat 543 Rxx=vrmaxh(Rss,Ru) 443 - -vmpywouh vrmaxuh - Rdd=vmpywouh(Rss,Rtt)[:<<1]:rnd:sat 547 Rxx=vrmaxuh(Rss,Ru) 443 - Rdd=vmpywouh(Rss,Rtt)[:<<1]:sat 547 - Rxx+=vmpywouh(Rss,Rtt)[:<<1]:rnd:sat 547 vrmaxuw - Rxx+=vmpywouh(Rss,Rtt)[:<<1]:sat 547 Rxx=vrmaxuw(Rss,Ru) 445 -vmux vrmaxw - Rdd=vmux(Pu,Rss,Rtt) 644 Rxx=vrmaxw(Rss,Ru) 445 -vnavgh vrminh - Rd=vnavgh(Rt,Rs) 184 Rxx=vrminh(Rss,Ru) 451 - Rdd=vnavgh(Rtt,Rss) 434 - Rdd=vnavgh(Rtt,Rss):crnd:sat 434 - Rdd=vnavgh(Rtt,Rss):rnd:sat 434 - vrminuh - Rxx=vrminuh(Rss,Ru) 451 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 696 - Hexagon V62 Programmer's Reference Manual Instruction Index - - -vrminuw vsubh - Rxx=vrminuw(Rss,Ru) 453 Rd=vsubh(Rt,Rs)[:sat] 185 - Rdd=vsubh(Rtt,Rss)[:sat] 458 -vrminw - Rxx=vrminw(Rss,Ru) 453 vsubub - Rdd=vsubub(Rtt,Rss)[:sat] 460 -vrmpybsu - Rdd=vrmpybsu(Rss,Rtt) 578 vsubuh - Rxx+=vrmpybsu(Rss,Rtt) 578 Rd=vsubuh(Rt,Rs):sat 185 - Rdd=vsubuh(Rtt,Rss):sat 458 -vrmpybu - Rdd=vrmpybu(Rss,Rtt) 578 vsubw - Rxx+=vrmpybu(Rss,Rtt) 578 Rdd=vsubw(Rtt,Rss)[:sat] 461 - -vrmpyh vsxtbh - Rdd=vrmpyh(Rss,Rtt) 590 Rdd=vsxtbh(Rs) 616 - Rxx+=vrmpyh(Rss,Rtt) 590 - vsxthw -vrmpyweh Rdd=vsxthw(Rs) 616 - Rdd=vrmpyweh(Rss,Rtt)[:<<1] 565 - Rxx+=vrmpyweh(Rss,Rtt)[:<<1] 565 vtrunehb - Rd=vtrunehb(Rss) 618 -vrmpywoh Rdd=vtrunehb(Rss,Rtt) 619 - Rdd=vrmpywoh(Rss,Rtt)[:<<1] 565 - Rxx+=vrmpywoh(Rss,Rtt)[:<<1] 565 vtrunewh - Rdd=vtrunewh(Rss,Rtt) 619 -vrndwh - Rd=vrndwh(Rss) 604 vtrunohb - Rd=vrndwh(Rss):sat 604 Rd=vtrunohb(Rss) 619 - Rdd=vtrunohb(Rss,Rtt) 619 -vrsadub - Rdd=vrsadub(Rss,Rtt) 456 vtrunowh - Rxx+=vrsadub(Rss,Rtt) 456 Rdd=vtrunowh(Rss,Rtt) 619 -vsathb vxaddsubh - Rd=vsathb(Rs) 607 Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat 484 - Rd=vsathb(Rss) 607 Rdd=vxaddsubh(Rss,Rtt):sat 484 - Rdd=vsathb(Rss) 609 - - vxaddsubw -vsathub Rdd=vxaddsubw(Rss,Rtt):sat 486 - Rd=vsathub(Rs) 607 - Rd=vsathub(Rss) 607 - Rdd=vsathub(Rss) 609 - vxsubaddh - Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat 484 - Rdd=vxsubaddh(Rss,Rtt):sat 484 -vsatwh - Rd=vsatwh(Rss) 607 - Rdd=vsatwh(Rss) 609 - vxsubaddw - Rdd=vxsubaddw(Rss,Rtt):sat 486 -vsatwuh - Rd=vsatwuh(Rss) 607 - vzxtbh - Rdd=vsatwuh(Rss) 609 Rdd=vzxtbh(Rs) 621 - -vsplatb vzxthw - Rd=vsplatb(Rs) 613 Rdd=vzxthw(Rs) 621 - Rdd=vsplatb(Rs) 613 - W -vsplath - Rdd=vsplath(Rs) 614 wait - wait(Rs) 370 -vspliceb - Rdd=vspliceb(Rss,Rtt,#u3) 615 - Rdd=vspliceb(Rss,Rtt,Pu) 615 - -vsubb - Rdd=vsubb(Rss,Rtt) 460 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 697 - Hexagon V62 Programmer's Reference Manual Instruction Index - - - -X -xor - if ([!]Pu[.new]) Rd=xor(Rs,Rt) 201 - Pd=xor(Ps,Pt) 221 - Rd=xor(Rs,Rt) 173 - Rdd=xor(Rss,Rtt) 398 - Rx[&|^]=xor(Rs,Rt) 401 - Rxx^=xor(Rss,Rtt) 400 - -Z -zxtb - if ([!]Pu[.new]) Rd=zxtb(Rs) 207 - Rd=zxtb(Rs) 187 - -zxth - if ([!]Pu[.new]) Rd=zxth(Rs) 207 - Rd=zxth(Rs) 187 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 698 - Intrinsics Index - - -A -abs -Rd=abs(Rs) Word32 Q6_R_abs_R(Word32 Rs) 389 -Rd=abs(Rs):sat Word32 Q6_R_abs_R_sat(Word32 Rs) 389 -Rdd=abs(Rss) Word64 Q6_P_abs_P(Word64 Rss) 388 - -add -Rd=add(#u6,mpyi(Rs,#U6)) Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32 IU6) 540 -Rd=add(#u6,mpyi(Rs,Rt)) Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32 Rt) 540 -Rd=add(Rs,#s16) Word32 Q6_R_add_RI(Word32 Rs, Word32 Is16) 171 -Rd=add(Rs,add(Ru,#s6)) Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32 Is6) 390 -Rd=add(Rs,Rt) Word32 Q6_R_add_RR(Word32 Rs, Word32 Rt) 171 -Rd=add(Rs,Rt):sat Word32 Q6_R_add_RR_sat(Word32 Rs, Word32 Rt) 171 -Rd=add(Rt.H,Rs.H):<<16 Word32 Q6_R_add_RhRh_s16(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.H,Rs.H):sat:<<16 Word32 Q6_R_add_RhRh_sat_s16(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.H,Rs.L):<<16 Word32 Q6_R_add_RhRl_s16(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.H,Rs.L):sat:<<16 Word32 Q6_R_add_RhRl_sat_s16(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.L,Rs.H) Word32 Q6_R_add_RlRh(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.L,Rs.H):<<16 Word32 Q6_R_add_RlRh_s16(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.L,Rs.H):sat Word32 Q6_R_add_RlRh_sat(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.L,Rs.H):sat:<<16 Word32 Q6_R_add_RlRh_sat_s16(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.L,Rs.L) Word32 Q6_R_add_RlRl(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.L,Rs.L):<<16 Word32 Q6_R_add_RlRl_s16(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.L,Rs.L):sat Word32 Q6_R_add_RlRl_sat(Word32 Rt, Word32 Rs) 395 -Rd=add(Rt.L,Rs.L):sat:<<16 Word32 Q6_R_add_RlRl_sat_s16(Word32 Rt, Word32 Rs) 395 -Rd=add(Ru,mpyi(#u6:2,Rs)) Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2, Word32 Rs) 540 -Rd=add(Ru,mpyi(Rs,#u6)) Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32 Iu6) 540 -Rdd=add(Rs,Rtt) Word64 Q6_P_add_RP(Word32 Rs, Word64 Rtt) 392 -Rdd=add(Rss,Rtt) Word64 Q6_P_add_PP(Word64 Rss, Word64 Rtt) 392 -Rdd=add(Rss,Rtt):sat Word64 Q6_P_add_PP_sat(Word64 Rss, Word64 Rtt) 392 -Rx+=add(Rs,#s8) Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32 Is8) 390 -Rx+=add(Rs,Rt) Word32 Q6_R_addacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 390 -Rx-=add(Rs,#s8) Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32 Is8) 390 -Rx-=add(Rs,Rt) Word32 Q6_R_addnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) 390 -Ry=add(Ru,mpyi(Ry,Rs)) Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32 Rs) 540 - -addasl -Rd=addasl(Rt,Rs,#u3) Word32 Q6_R_addasl_RRI(Word32 Rt, Word32 Rs, Word32 Iu3) 650 - -all8 -Pd=all8(Ps) Byte Q6_p_all8_p(Byte Ps) 215 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 699 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -and -Pd=and(Ps,and(Pt,!Pu)) Byte Q6_p_and_and_ppnp(Byte Ps, Byte Pt, Byte Pu) 221 -Pd=and(Ps,and(Pt,Pu)) Byte Q6_p_and_and_ppp(Byte Ps, Byte Pt, Byte Pu) 221 -Pd=and(Pt,!Ps) Byte Q6_p_and_pnp(Byte Pt, Byte Ps) 221 -Pd=and(Pt,Ps) Byte Q6_p_and_pp(Byte Pt, Byte Ps) 221 -Rd=and(Rs,#s10) Word32 Q6_R_and_RI(Word32 Rs, Word32 Is10) 173 -Rd=and(Rs,Rt) Word32 Q6_R_and_RR(Word32 Rs, Word32 Rt) 173 -Rd=and(Rt,~Rs) Word32 Q6_R_and_RnR(Word32 Rt, Word32 Rs) 173 -Rdd=and(Rss,Rtt) Word64 Q6_P_and_PP(Word64 Rss, Word64 Rtt) 398 -Rdd=and(Rtt,~Rss) Word64 Q6_P_and_PnP(Word64 Rtt, Word64 Rss) 398 -Rx^=and(Rs,~Rt) Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32 Rt) 401 -Rx^=and(Rs,Rt) Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 401 -Rx&=and(Rs,~Rt) Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32 Rt) 401 -Rx&=and(Rs,Rt) Word32 Q6_R_andand_RR(Word32 Rx, Word32 Rs, Word32 Rt) 401 -Rx|=and(Rs,#s10) Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32 Is10) 401 -Rx|=and(Rs,~Rt) Word32 Q6_R_andor_RnR(Word32 Rx, Word32 Rs, Word32 Rt) 402 -Rx|=and(Rs,Rt) Word32 Q6_R_andor_RR(Word32 Rx, Word32 Rs, Word32 Rt) 402 - -any8 -Pd=any8(Ps) Byte Q6_p_any8_p(Byte Ps) 215 - -asl -Rd=asl(Rs,#u5) Word32 Q6_R_asl_RI(Word32 Rs, Word32 Iu5) 646 -Rd=asl(Rs,#u5):sat Word32 Q6_R_asl_RI_sat(Word32 Rs, Word32 Iu5) 657 -Rd=asl(Rs,Rt) Word32 Q6_R_asl_RR(Word32 Rs, Word32 Rt) 659 -Rd=asl(Rs,Rt):sat Word32 Q6_R_asl_RR_sat(Word32 Rs, Word32 Rt) 668 -Rdd=asl(Rss,#u6) Word64 Q6_P_asl_PI(Word64 Rss, Word32 Iu6) 646 -Rdd=asl(Rss,Rt) Word64 Q6_P_asl_PR(Word64 Rss, Word32 Rt) 659 -Rx^=asl(Rs,#u5) Word32 Q6_R_aslxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx&=asl(Rs,#u5) Word32 Q6_R_asland_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx&=asl(Rs,Rt) Word32 Q6_R_asland_RR(Word32 Rx, Word32 Rs, Word32 Rt) 666 -Rx+=asl(Rs,#u5) Word32 Q6_R_aslacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 648 -Rx+=asl(Rs,Rt) Word32 Q6_R_aslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 662 -Rx=add(#u8,asl(Rx,#U5)) Word32 Q6_R_add_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) 648 -Rx=and(#u8,asl(Rx,#U5)) Word32 Q6_R_and_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) 652 -Rx-=asl(Rs,#u5) Word32 Q6_R_aslnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 648 -Rx-=asl(Rs,Rt) Word32 Q6_R_aslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) 662 -Rx=or(#u8,asl(Rx,#U5)) Word32 Q6_R_or_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) 652 -Rx=sub(#u8,asl(Rx,#U5)) Word32 Q6_R_sub_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) 648 -Rx|=asl(Rs,#u5) Word32 Q6_R_aslor_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx|=asl(Rs,Rt) Word32 Q6_R_aslor_RR(Word32 Rx, Word32 Rs, Word32 Rt) 666 -Rxx^=asl(Rss,#u6) Word64 Q6_P_aslxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 -Rxx^=asl(Rss,Rt) Word64 Q6_P_aslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 -Rxx&=asl(Rss,#u6) Word64 Q6_P_asland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 652 -Rxx&=asl(Rss,Rt) Word64 Q6_P_asland_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 -Rxx+=asl(Rss,#u6) Word64 Q6_P_aslacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 648 -Rxx+=asl(Rss,Rt) Word64 Q6_P_aslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 662 -Rxx-=asl(Rss,#u6) Word64 Q6_P_aslnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 648 -Rxx-=asl(Rss,Rt) Word64 Q6_P_aslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 663 -Rxx|=asl(Rss,#u6) Word64 Q6_P_aslor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 -Rxx|=asl(Rss,Rt) Word64 Q6_P_aslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 - -aslh -Rd=aslh(Rs) Word32 Q6_R_aslh_R(Word32 Rs) 193 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 700 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -asr -Rd=asr(Rs,#u5) Word32 Q6_R_asr_RI(Word32 Rs, Word32 Iu5) 646 -Rd=asr(Rs,#u5):rnd Word32 Q6_R_asr_RI_rnd(Word32 Rs, Word32 Iu5) 656 -Rd=asr(Rs,Rt) Word32 Q6_R_asr_RR(Word32 Rs, Word32 Rt) 659 -Rd=asr(Rs,Rt):sat Word32 Q6_R_asr_RR_sat(Word32 Rs, Word32 Rt) 668 -Rdd=asr(Rss,#u6) Word64 Q6_P_asr_PI(Word64 Rss, Word32 Iu6) 646 -Rdd=asr(Rss,#u6):rnd Word64 Q6_P_asr_PI_rnd(Word64 Rss, Word32 Iu6) 656 -Rdd=asr(Rss,Rt) Word64 Q6_P_asr_PR(Word64 Rss, Word32 Rt) 659 -Rx&=asr(Rs,#u5) Word32 Q6_R_asrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx&=asr(Rs,Rt) Word32 Q6_R_asrand_RR(Word32 Rx, Word32 Rs, Word32 Rt) 666 -Rx+=asr(Rs,#u5) Word32 Q6_R_asracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 648 -Rx+=asr(Rs,Rt) Word32 Q6_R_asracc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 662 -Rx-=asr(Rs,#u5) Word32 Q6_R_asrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 648 -Rx-=asr(Rs,Rt) Word32 Q6_R_asrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) 662 -Rx|=asr(Rs,#u5) Word32 Q6_R_asror_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx|=asr(Rs,Rt) Word32 Q6_R_asror_RR(Word32 Rx, Word32 Rs, Word32 Rt) 666 -Rxx^=asr(Rss,Rt) Word64 Q6_P_asrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 -Rxx&=asr(Rss,#u6) Word64 Q6_P_asrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 -Rxx&=asr(Rss,Rt) Word64 Q6_P_asrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 -Rxx+=asr(Rss,#u6) Word64 Q6_P_asracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 648 -Rxx+=asr(Rss,Rt) Word64 Q6_P_asracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 662 -Rxx-=asr(Rss,#u6) Word64 Q6_P_asrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 648 -Rxx-=asr(Rss,Rt) Word64 Q6_P_asrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 663 -Rxx|=asr(Rss,#u6) Word64 Q6_P_asror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 -Rxx|=asr(Rss,Rt) Word64 Q6_P_asror_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 - -asrh -Rd=asrh(Rs) Word32 Q6_R_asrh_R(Word32 Rs) 193 - -asrrnd -Rd=asrrnd(Rs,#u5) Word32 Q6_R_asrrnd_RI(Word32 Rs, Word32 Iu5) 656 -Rdd=asrrnd(Rss,#u6) Word64 Q6_P_asrrnd_PI(Word64 Rss, Word32 Iu6) 656 - -B -bitsclr -Pd=!bitsclr(Rs,#u6) Byte Q6_p_not_bitsclr_RI(Word32 Rs, Word32 Iu6) 630 -Pd=!bitsclr(Rs,Rt) Byte Q6_p_not_bitsclr_RR(Word32 Rs, Word32 Rt) 630 -Pd=bitsclr(Rs,#u6) Byte Q6_p_bitsclr_RI(Word32 Rs, Word32 Iu6) 630 -Pd=bitsclr(Rs,Rt) Byte Q6_p_bitsclr_RR(Word32 Rs, Word32 Rt) 630 - -bitsplit -Rdd=bitsplit(Rs,#u5) Word64 Q6_P_bitsplit_RI(Word32 Rs, Word32 Iu5) 478 -Rdd=bitsplit(Rs,Rt) Word64 Q6_P_bitsplit_RR(Word32 Rs, Word32 Rt) 478 - -bitsset -Pd=!bitsset(Rs,Rt) Byte Q6_p_not_bitsset_RR(Word32 Rs, Word32 Rt) 630 -Pd=bitsset(Rs,Rt) Byte Q6_p_bitsset_RR(Word32 Rs, Word32 Rt) 630 - -boundscheck -Pd=boundscheck(Rs,Rtt) Byte Q6_p_boundscheck_RP(Word32 Rs, Word64 Rtt) 623 - -brev -Rd=brev(Rs) Word32 Q6_R_brev_R(Word32 Rs) 475 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 701 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rdd=brev(Rss) Word64 Q6_P_brev_P(Word64 Rss) 475 - -C -cl0 -Rd=cl0(Rs) Word32 Q6_R_cl0_R(Word32 Rs) 463 -Rd=cl0(Rss) Word32 Q6_R_cl0_P(Word64 Rss) 463 - -cl1 -Rd=cl1(Rs) Word32 Q6_R_cl1_R(Word32 Rs) 463 -Rd=cl1(Rss) Word32 Q6_R_cl1_P(Word64 Rss) 463 - -clb -Rd=add(clb(Rs),#s6) Word32 Q6_R_add_clb_RI(Word32 Rs, Word32 Is6) 463 -Rd=add(clb(Rss),#s6) Word32 Q6_R_add_clb_PI(Word64 Rss, Word32 Is6) 463 -Rd=clb(Rs) Word32 Q6_R_clb_R(Word32 Rs) 463 -Rd=clb(Rss) Word32 Q6_R_clb_P(Word64 Rss) 463 - -clrbit -Rd=clrbit(Rs,#u5) Word32 Q6_R_clrbit_RI(Word32 Rs, Word32 Iu5) 476 -Rd=clrbit(Rs,Rt) Word32 Q6_R_clrbit_RR(Word32 Rs, Word32 Rt) 476 - -cmp.eq -Pd=!cmp.eq(Rs,#s10) Byte Q6_p_not_cmp_eq_RI(Word32 Rs, Word32 Is10) 209 -Pd=!cmp.eq(Rs,Rt) Byte Q6_p_not_cmp_eq_RR(Word32 Rs, Word32 Rt) 209 -Pd=cmp.eq(Rs,#s10) Byte Q6_p_cmp_eq_RI(Word32 Rs, Word32 Is10) 210 -Pd=cmp.eq(Rs,Rt) Byte Q6_p_cmp_eq_RR(Word32 Rs, Word32 Rt) 210 -Pd=cmp.eq(Rss,Rtt) Byte Q6_p_cmp_eq_PP(Word64 Rss, Word64 Rtt) 629 -Rd=!cmp.eq(Rs,#s8) Word32 Q6_R_not_cmp_eq_RI(Word32 Rs, Word32 Is8) 211 -Rd=!cmp.eq(Rs,Rt) Word32 Q6_R_not_cmp_eq_RR(Word32 Rs, Word32 Rt) 211 -Rd=cmp.eq(Rs,#s8) Word32 Q6_R_cmp_eq_RI(Word32 Rs, Word32 Is8) 211 -Rd=cmp.eq(Rs,Rt) Word32 Q6_R_cmp_eq_RR(Word32 Rs, Word32 Rt) 211 - -cmp.ge -Pd=cmp.ge(Rs,#s8) Byte Q6_p_cmp_ge_RI(Word32 Rs, Word32 Is8) 210 - -cmp.geu -Pd=cmp.geu(Rs,#u8) Byte Q6_p_cmp_geu_RI(Word32 Rs, Word32 Iu8) 210 - -cmp.gt -Pd=!cmp.gt(Rs,#s10) Byte Q6_p_not_cmp_gt_RI(Word32 Rs, Word32 Is10) 209 -Pd=!cmp.gt(Rs,Rt) Byte Q6_p_not_cmp_gt_RR(Word32 Rs, Word32 Rt) 209 -Pd=cmp.gt(Rs,#s10) Byte Q6_p_cmp_gt_RI(Word32 Rs, Word32 Is10) 210 -Pd=cmp.gt(Rs,Rt) Byte Q6_p_cmp_gt_RR(Word32 Rs, Word32 Rt) 210 -Pd=cmp.gt(Rss,Rtt) Byte Q6_p_cmp_gt_PP(Word64 Rss, Word64 Rtt) 629 - -cmp.gtu -Pd=!cmp.gtu(Rs,#u9) Byte Q6_p_not_cmp_gtu_RI(Word32 Rs, Word32 Iu9) 209 -Pd=!cmp.gtu(Rs,Rt) Byte Q6_p_not_cmp_gtu_RR(Word32 Rs, Word32 Rt) 209 -Pd=cmp.gtu(Rs,#u9) Byte Q6_p_cmp_gtu_RI(Word32 Rs, Word32 Iu9) 210 -Pd=cmp.gtu(Rs,Rt) Byte Q6_p_cmp_gtu_RR(Word32 Rs, Word32 Rt) 210 -Pd=cmp.gtu(Rss,Rtt) Byte Q6_p_cmp_gtu_PP(Word64 Rss, Word64 Rtt) 629 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 702 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -cmp.lt -Pd=cmp.lt(Rs,Rt) Byte Q6_p_cmp_lt_RR(Word32 Rs, Word32 Rt) 210 - -cmp.ltu -Pd=cmp.ltu(Rs,Rt) Byte Q6_p_cmp_ltu_RR(Word32 Rs, Word32 Rt) 210 - -cmpb.eq -Pd=cmpb.eq(Rs,#u8) Byte Q6_p_cmpb_eq_RI(Word32 Rs, Word32 Iu8) 625 -Pd=cmpb.eq(Rs,Rt) Byte Q6_p_cmpb_eq_RR(Word32 Rs, Word32 Rt) 625 - -cmpb.gt -Pd=cmpb.gt(Rs,#s8) Byte Q6_p_cmpb_gt_RI(Word32 Rs, Word32 Is8) 625 -Pd=cmpb.gt(Rs,Rt) Byte Q6_p_cmpb_gt_RR(Word32 Rs, Word32 Rt) 625 - -cmpb.gtu -Pd=cmpb.gtu(Rs,#u7) Byte Q6_p_cmpb_gtu_RI(Word32 Rs, Word32 Iu7) 625 -Pd=cmpb.gtu(Rs,Rt) Byte Q6_p_cmpb_gtu_RR(Word32 Rs, Word32 Rt) 625 - -cmph.eq -Pd=cmph.eq(Rs,#s8) Byte Q6_p_cmph_eq_RI(Word32 Rs, Word32 Is8) 627 -Pd=cmph.eq(Rs,Rt) Byte Q6_p_cmph_eq_RR(Word32 Rs, Word32 Rt) 627 - -cmph.gt -Pd=cmph.gt(Rs,#s8) Byte Q6_p_cmph_gt_RI(Word32 Rs, Word32 Is8) 627 -Pd=cmph.gt(Rs,Rt) Byte Q6_p_cmph_gt_RR(Word32 Rs, Word32 Rt) 627 - -cmph.gtu -Pd=cmph.gtu(Rs,#u7) Byte Q6_p_cmph_gtu_RI(Word32 Rs, Word32 Iu7) 627 -Pd=cmph.gtu(Rs,Rt) Byte Q6_p_cmph_gtu_RR(Word32 Rs, Word32 Rt) 627 - -cmpy -Rd=cmpy(Rs,Rt):<<1:rnd:sat Word32 Q6_R_cmpy_RR_s1_rnd_sat(Word32 Rs, Word32 Rt) 494 -Rd=cmpy(Rs,Rt):rnd:sat Word32 Q6_R_cmpy_RR_rnd_sat(Word32 Rs, Word32 Rt) 494 -Rd=cmpy(Rs,Rt*):<<1:rnd:sat Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32 Rt) 494 -Rd=cmpy(Rs,Rt*):rnd:sat Word32 Q6_R_cmpy_RR_conj_rnd_sat(Word32 Rs, Word32 Rt) 494 -Rdd=cmpy(Rs,Rt):<<1:sat Word64 Q6_P_cmpy_RR_s1_sat(Word32 Rs, Word32 Rt) 489 -Rdd=cmpy(Rs,Rt):sat Word64 Q6_P_cmpy_RR_sat(Word32 Rs, Word32 Rt) 489 -Rdd=cmpy(Rs,Rt*):<<1:sat Word64 Q6_P_cmpy_RR_conj_s1_sat(Word32 Rs, Word32 Rt) 489 -Rdd=cmpy(Rs,Rt*):sat Word64 Q6_P_cmpy_RR_conj_sat(Word32 Rs, Word32 Rt) 489 -Rxx+=cmpy(Rs,Rt):<<1:sat Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 489 -Rxx+=cmpy(Rs,Rt):sat Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 489 -Rxx+=cmpy(Rs,Rt*):<<1:sat Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 489 -Rxx+=cmpy(Rs,Rt*):sat Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 490 -Rxx-=cmpy(Rs,Rt):<<1:sat Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 490 -Rxx-=cmpy(Rs,Rt):sat Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 490 -Rxx-=cmpy(Rs,Rt*):<<1:sat Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 490 -Rxx-=cmpy(Rs,Rt*):sat Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 490 - -cmpyi -Rdd=cmpyi(Rs,Rt) Word64 Q6_P_cmpyi_RR(Word32 Rs, Word32 Rt) 492 -Rxx+=cmpyi(Rs,Rt) Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 492 - -cmpyiwh -Rd=cmpyiwh(Rss,Rt):<<1:rnd:sat Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) 496 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 703 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rd=cmpyiwh(Rss,Rt*):<<1:rnd:sat Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt) 496 - -cmpyr -Rdd=cmpyr(Rs,Rt) Word64 Q6_P_cmpyr_RR(Word32 Rs, Word32 Rt) 492 -Rxx+=cmpyr(Rs,Rt) Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 492 - -cmpyrwh -Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) 496 -Rd=cmpyrwh(Rss,Rt*):<<1:rnd:sat Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt) 496 - -combine -Rd=combine(Rt.H,Rs.H) Word32 Q6_R_combine_RhRh(Word32 Rt, Word32 Rs) 189 -Rd=combine(Rt.H,Rs.L) Word32 Q6_R_combine_RhRl(Word32 Rt, Word32 Rs) 189 -Rd=combine(Rt.L,Rs.H) Word32 Q6_R_combine_RlRh(Word32 Rt, Word32 Rs) 189 -Rd=combine(Rt.L,Rs.L) Word32 Q6_R_combine_RlRl(Word32 Rt, Word32 Rs) 189 -Rdd=combine(#s8,#S8) Word64 Q6_P_combine_II(Word32 Is8, Word32 IS8) 189 -Rdd=combine(#s8,Rs) Word64 Q6_P_combine_IR(Word32 Is8, Word32 Rs) 189 -Rdd=combine(Rs,#s8) Word64 Q6_P_combine_RI(Word32 Rs, Word32 Is8) 189 -Rdd=combine(Rs,Rt) Word64 Q6_P_combine_RR(Word32 Rs, Word32 Rt) 189 - -convert_d2df -Rdd=convert_d2df(Rss) Word64 Q6_P_convert_d2df_P(Word64 Rss) 522 - -convert_d2sf -Rd=convert_d2sf(Rss) Word32 Q6_R_convert_d2sf_P(Word64 Rss) 522 - -convert_df2d -Rdd=convert_df2d(Rss) Word64 Q6_P_convert_df2d_P(Word64 Rss) 525 -Rdd=convert_df2d(Rss):chop Word64 Q6_P_convert_df2d_P_chop(Word64 Rss) 525 - -convert_df2sf -Rd=convert_df2sf(Rss) Word32 Q6_R_convert_df2sf_P(Word64 Rss) 521 - -convert_df2ud -Rdd=convert_df2ud(Rss) Word64 Q6_P_convert_df2ud_P(Word64 Rss) 525 -Rdd=convert_df2ud(Rss):chop Word64 Q6_P_convert_df2ud_P_chop(Word64 Rss) 525 - -convert_df2uw -Rd=convert_df2uw(Rss) Word32 Q6_R_convert_df2uw_P(Word64 Rss) 525 -Rd=convert_df2uw(Rss):chop Word32 Q6_R_convert_df2uw_P_chop(Word64 Rss) 525 - -convert_df2w -Rd=convert_df2w(Rss) Word32 Q6_R_convert_df2w_P(Word64 Rss) 525 -Rd=convert_df2w(Rss):chop Word32 Q6_R_convert_df2w_P_chop(Word64 Rss) 525 - -convert_sf2d -Rdd=convert_sf2d(Rs) Word64 Q6_P_convert_sf2d_R(Word32 Rs) 525 -Rdd=convert_sf2d(Rs):chop Word64 Q6_P_convert_sf2d_R_chop(Word32 Rs) 525 - -convert_sf2df -Rdd=convert_sf2df(Rs) Word64 Q6_P_convert_sf2df_R(Word32 Rs) 521 - -convert_sf2ud -Rdd=convert_sf2ud(Rs) Word64 Q6_P_convert_sf2ud_R(Word32 Rs) 525 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 704 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rdd=convert_sf2ud(Rs):chop Word64 Q6_P_convert_sf2ud_R_chop(Word32 Rs) 525 - -convert_sf2uw -Rd=convert_sf2uw(Rs) Word32 Q6_R_convert_sf2uw_R(Word32 Rs) 525 -Rd=convert_sf2uw(Rs):chop Word32 Q6_R_convert_sf2uw_R_chop(Word32 Rs) 525 - -convert_sf2w -Rd=convert_sf2w(Rs) Word32 Q6_R_convert_sf2w_R(Word32 Rs) 525 -Rd=convert_sf2w(Rs):chop Word32 Q6_R_convert_sf2w_R_chop(Word32 Rs) 525 - -convert_ud2df -Rdd=convert_ud2df(Rss) Word64 Q6_P_convert_ud2df_P(Word64 Rss) 522 - -convert_ud2sf -Rd=convert_ud2sf(Rss) Word32 Q6_R_convert_ud2sf_P(Word64 Rss) 522 - -convert_uw2df -Rdd=convert_uw2df(Rs) Word64 Q6_P_convert_uw2df_R(Word32 Rs) 522 - -convert_uw2sf -Rd=convert_uw2sf(Rs) Word32 Q6_R_convert_uw2sf_R(Word32 Rs) 522 - -convert_w2df -Rdd=convert_w2df(Rs) Word64 Q6_P_convert_w2df_R(Word32 Rs) 522 - -convert_w2sf -Rd=convert_w2sf(Rs) Word32 Q6_R_convert_w2sf_R(Word32 Rs) 522 - -cround -Rd=cround(Rs,#u5) Word32 Q6_R_cround_RI(Word32 Rs, Word32 Iu5) 409 -Rd=cround(Rs,Rt) Word32 Q6_R_cround_RR(Word32 Rs, Word32 Rt) 409 - -ct0 -Rd=ct0(Rs) Word32 Q6_R_ct0_R(Word32 Rs) 466 -Rd=ct0(Rss) Word32 Q6_R_ct0_P(Word64 Rss) 466 - -ct1 -Rd=ct1(Rs) Word32 Q6_R_ct1_R(Word32 Rs) 466 -Rd=ct1(Rss) Word32 Q6_R_ct1_P(Word64 Rss) 466 - -D -dcfetch -dcfetch(Rs) void Q6_dcfetch_A(Address a) 377 - -deinterleave -Rdd=deinterleave(Rss) Word64 Q6_P_deinterleave_P(Word64 Rss) 472 - -dfclass -Pd=dfclass(Rss,#u5) Byte Q6_p_dfclass_PI(Word64 Rss, Word32 Iu5) 517 - -dfcmp.eq -Pd=dfcmp.eq(Rss,Rtt) Byte Q6_p_dfcmp_eq_PP(Word64 Rss, Word64 Rtt) 519 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 705 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -dfcmp.ge -Pd=dfcmp.ge(Rss,Rtt) Byte Q6_p_dfcmp_ge_PP(Word64 Rss, Word64 Rtt) 519 - -dfcmp.gt -Pd=dfcmp.gt(Rss,Rtt) Byte Q6_p_dfcmp_gt_PP(Word64 Rss, Word64 Rtt) 519 - -dfcmp.uo -Pd=dfcmp.uo(Rss,Rtt) Byte Q6_p_dfcmp_uo_PP(Word64 Rss, Word64 Rtt) 519 - -dfmake -Rdd=dfmake(#u10):neg Word64 Q6_P_dfmake_I_neg(Word32 Iu10) 533 -Rdd=dfmake(#u10):pos Word64 Q6_P_dfmake_I_pos(Word32 Iu10) 533 - -E -extract -Rd=extract(Rs,#u5,#U5) Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32 IU5) 468 -Rd=extract(Rs,Rtt) Word32 Q6_R_extract_RP(Word32 Rs, Word64 Rtt) 468 -Rdd=extract(Rss,#u6,#U6) Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32 IU6) 469 -Rdd=extract(Rss,Rtt) Word64 Q6_P_extract_PP(Word64 Rss, Word64 Rtt) 469 - -extractu -Rd=extractu(Rs,#u5,#U5) Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32 IU5) 468 -Rd=extractu(Rs,Rtt) Word32 Q6_R_extractu_RP(Word32 Rs, Word64 Rtt) 469 -Rdd=extractu(Rss,#u6,#U6) Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6, Word32 IU6) 469 -Rdd=extractu(Rss,Rtt) Word64 Q6_P_extractu_PP(Word64 Rss, Word64 Rtt) 469 - -F -fastcorner9 -Pd=!fastcorner9(Ps,Pt) Byte Q6_p_not_fastcorner9_pp(Byte Ps, Byte Pt) 214 -Pd=fastcorner9(Ps,Pt) Byte Q6_p_fastcorner9_pp(Byte Ps, Byte Pt) 214 - -I -insert -Rx=insert(Rs,#u5,#U5) Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32 Iu5, Word32 IU5) 471 -Rx=insert(Rs,Rtt) Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64 Rtt) 471 -Rxx=insert(Rss,#u6,#U6) Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32 Iu6, Word32 IU6) 471 -Rxx=insert(Rss,Rtt) Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 471 - -interleave -Rdd=interleave(Rss) Word64 Q6_P_interleave_P(Word64 Rss) 472 - -L -lfs -Rdd=lfs(Rss,Rtt) Word64 Q6_P_lfs_PP(Word64 Rss, Word64 Rtt) 473 - -lsl -Rd=lsl(#s6,Rt) Word32 Q6_R_lsl_IR(Word32 Is6, Word32 Rt) 659 -Rd=lsl(Rs,Rt) Word32 Q6_R_lsl_RR(Word32 Rs, Word32 Rt) 659 -Rdd=lsl(Rss,Rt) Word64 Q6_P_lsl_PR(Word64 Rss, Word32 Rt) 659 -Rx&=lsl(Rs,Rt) Word32 Q6_R_lsland_RR(Word32 Rx, Word32 Rs, Word32 Rt) 666 -Rx+=lsl(Rs,Rt) Word32 Q6_R_lslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 662 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 706 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rx-=lsl(Rs,Rt) Word32 Q6_R_lslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) 662 -Rx|=lsl(Rs,Rt) Word32 Q6_R_lslor_RR(Word32 Rx, Word32 Rs, Word32 Rt) 666 -Rxx^=lsl(Rss,Rt) Word64 Q6_P_lslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 -Rxx&=lsl(Rss,Rt) Word64 Q6_P_lsland_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 -Rxx+=lsl(Rss,Rt) Word64 Q6_P_lslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 662 -Rxx-=lsl(Rss,Rt) Word64 Q6_P_lslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 663 -Rxx|=lsl(Rss,Rt) Word64 Q6_P_lslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 - -lsr -Rd=lsr(Rs,#u5) Word32 Q6_R_lsr_RI(Word32 Rs, Word32 Iu5) 646 -Rd=lsr(Rs,Rt) Word32 Q6_R_lsr_RR(Word32 Rs, Word32 Rt) 659 -Rdd=lsr(Rss,#u6) Word64 Q6_P_lsr_PI(Word64 Rss, Word32 Iu6) 646 -Rdd=lsr(Rss,Rt) Word64 Q6_P_lsr_PR(Word64 Rss, Word32 Rt) 659 -Rx^=lsr(Rs,#u5) Word32 Q6_R_lsrxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx&=lsr(Rs,#u5) Word32 Q6_R_lsrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx&=lsr(Rs,Rt) Word32 Q6_R_lsrand_RR(Word32 Rx, Word32 Rs, Word32 Rt) 666 -Rx+=lsr(Rs,#u5) Word32 Q6_R_lsracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 648 -Rx+=lsr(Rs,Rt) Word32 Q6_R_lsracc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 662 -Rx=add(#u8,lsr(Rx,#U5)) Word32 Q6_R_add_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) 648 -Rx=and(#u8,lsr(Rx,#U5)) Word32 Q6_R_and_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) 652 -Rx-=lsr(Rs,#u5) Word32 Q6_R_lsrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 648 -Rx-=lsr(Rs,Rt) Word32 Q6_R_lsrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) 662 -Rx=or(#u8,lsr(Rx,#U5)) Word32 Q6_R_or_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) 652 -Rx=sub(#u8,lsr(Rx,#U5)) Word32 Q6_R_sub_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) 648 -Rx|=lsr(Rs,#u5) Word32 Q6_R_lsror_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx|=lsr(Rs,Rt) Word32 Q6_R_lsror_RR(Word32 Rx, Word32 Rs, Word32 Rt) 666 -Rxx^=lsr(Rss,#u6) Word64 Q6_P_lsrxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 -Rxx^=lsr(Rss,Rt) Word64 Q6_P_lsrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 -Rxx&=lsr(Rss,#u6) Word64 Q6_P_lsrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 -Rxx&=lsr(Rss,Rt) Word64 Q6_P_lsrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 -Rxx+=lsr(Rss,#u6) Word64 Q6_P_lsracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 648 -Rxx+=lsr(Rss,Rt) Word64 Q6_P_lsracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 663 -Rxx-=lsr(Rss,#u6) Word64 Q6_P_lsrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 648 -Rxx-=lsr(Rss,Rt) Word64 Q6_P_lsrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 663 -Rxx|=lsr(Rss,#u6) Word64 Q6_P_lsror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 -Rxx|=lsr(Rss,Rt) Word64 Q6_P_lsror_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 666 - -M -mask -Rdd=mask(Pt) Word64 Q6_P_mask_p(Byte Pt) 632 - -max -Rd=max(Rs,Rt) Word32 Q6_R_max_RR(Word32 Rs, Word32 Rt) 403 -Rdd=max(Rss,Rtt) Word64 Q6_P_max_PP(Word64 Rss, Word64 Rtt) 404 - -maxu -Rd=maxu(Rs,Rt) UWord32 Q6_R_maxu_RR(Word32 Rs, Word32 Rt) 403 -Rdd=maxu(Rss,Rtt) UWord64 Q6_P_maxu_PP(Word64 Rss, Word64 Rtt) 404 - -min -Rd=min(Rt,Rs) Word32 Q6_R_min_RR(Word32 Rt, Word32 Rs) 405 -Rdd=min(Rtt,Rss) Word64 Q6_P_min_PP(Word64 Rtt, Word64 Rss) 406 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 707 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -minu -Rd=minu(Rt,Rs) UWord32 Q6_R_minu_RR(Word32 Rt, Word32 Rs) 405 -Rdd=minu(Rtt,Rss) UWord64 Q6_P_minu_PP(Word64 Rtt, Word64 Rss) 406 - -modwrap -Rd=modwrap(Rs,Rt) Word32 Q6_R_modwrap_RR(Word32 Rs, Word32 Rt) 407 - -mpy -Rd=mpy(Rs,Rt.H):<<1:rnd:sat Word32 Q6_R_mpy_RRh_s1_rnd_sat(Word32 Rs, Word32 Rt) 568 -Rd=mpy(Rs,Rt.H):<<1:sat Word32 Q6_R_mpy_RRh_s1_sat(Word32 Rs, Word32 Rt) 568 -Rd=mpy(Rs,Rt.L):<<1:rnd:sat Word32 Q6_R_mpy_RRl_s1_rnd_sat(Word32 Rs, Word32 Rt) 568 -Rd=mpy(Rs,Rt.L):<<1:sat Word32 Q6_R_mpy_RRl_s1_sat(Word32 Rs, Word32 Rt) 568 -Rd=mpy(Rs,Rt) Word32 Q6_R_mpy_RR(Word32 Rs, Word32 Rt) 568 -Rd=mpy(Rs,Rt):<<1 Word32 Q6_R_mpy_RR_s1(Word32 Rs, Word32 Rt) 568 -Rd=mpy(Rs,Rt):<<1:sat Word32 Q6_R_mpy_RR_s1_sat(Word32 Rs, Word32 Rt) 568 -Rd=mpy(Rs,Rt):rnd Word32 Q6_R_mpy_RR_rnd(Word32 Rs, Word32 Rt) 568 -Rd=mpy(Rs.H,Rt.H) Word32 Q6_R_mpy_RhRh(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.H):<<1 Word32 Q6_R_mpy_RhRh_s1(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.H):<<1:rnd Word32 Q6_R_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.H):<<1:rnd:sat Word32 Q6_R_mpy_RhRh_s1_rnd_sat(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.H):<<1:sat Word32 Q6_R_mpy_RhRh_s1_sat(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.H):rnd Word32 Q6_R_mpy_RhRh_rnd(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.H):rnd:sat Word32 Q6_R_mpy_RhRh_rnd_sat(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.H):sat Word32 Q6_R_mpy_RhRh_sat(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.L) Word32 Q6_R_mpy_RhRl(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.L):<<1 Word32 Q6_R_mpy_RhRl_s1(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.L):<<1:rnd Word32 Q6_R_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.L):<<1:rnd:sat Word32 Q6_R_mpy_RhRl_s1_rnd_sat(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.L):<<1:sat Word32 Q6_R_mpy_RhRl_s1_sat(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.L):rnd Word32 Q6_R_mpy_RhRl_rnd(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.L):rnd:sat Word32 Q6_R_mpy_RhRl_rnd_sat(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.H,Rt.L):sat Word32 Q6_R_mpy_RhRl_sat(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.L,Rt.H) Word32 Q6_R_mpy_RlRh(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.L,Rt.H):<<1 Word32 Q6_R_mpy_RlRh_s1(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.L,Rt.H):<<1:rnd Word32 Q6_R_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.L,Rt.H):<<1:rnd:sat Word32 Q6_R_mpy_RlRh_s1_rnd_sat(Word32 Rs, Word32 Rt) 551 -Rd=mpy(Rs.L,Rt.H):<<1:sat Word32 Q6_R_mpy_RlRh_s1_sat(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.H):rnd Word32 Q6_R_mpy_RlRh_rnd(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.H):rnd:sat Word32 Q6_R_mpy_RlRh_rnd_sat(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.H):sat Word32 Q6_R_mpy_RlRh_sat(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.L) Word32 Q6_R_mpy_RlRl(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.L):<<1 Word32 Q6_R_mpy_RlRl_s1(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.L):<<1:rnd Word32 Q6_R_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.L):<<1:rnd:sat Word32 Q6_R_mpy_RlRl_s1_rnd_sat(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.L):<<1:sat Word32 Q6_R_mpy_RlRl_s1_sat(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.L):rnd Word32 Q6_R_mpy_RlRl_rnd(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.L):rnd:sat Word32 Q6_R_mpy_RlRl_rnd_sat(Word32 Rs, Word32 Rt) 552 -Rd=mpy(Rs.L,Rt.L):sat Word32 Q6_R_mpy_RlRl_sat(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs,Rt) Word64 Q6_P_mpy_RR(Word32 Rs, Word32 Rt) 570 -Rdd=mpy(Rs.H,Rt.H) Word64 Q6_P_mpy_RhRh(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.H,Rt.H):<<1 Word64 Q6_P_mpy_RhRh_s1(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.H,Rt.H):<<1:rnd Word64 Q6_P_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.H,Rt.H):rnd Word64 Q6_P_mpy_RhRh_rnd(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.H,Rt.L) Word64 Q6_P_mpy_RhRl(Word32 Rs, Word32 Rt) 552 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 708 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rdd=mpy(Rs.H,Rt.L):<<1 Word64 Q6_P_mpy_RhRl_s1(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.H,Rt.L):<<1:rnd Word64 Q6_P_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.H,Rt.L):rnd Word64 Q6_P_mpy_RhRl_rnd(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.L,Rt.H) Word64 Q6_P_mpy_RlRh(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.L,Rt.H):<<1 Word64 Q6_P_mpy_RlRh_s1(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.L,Rt.H):<<1:rnd Word64 Q6_P_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.L,Rt.H):rnd Word64 Q6_P_mpy_RlRh_rnd(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.L,Rt.L) Word64 Q6_P_mpy_RlRl(Word32 Rs, Word32 Rt) 552 -Rdd=mpy(Rs.L,Rt.L):<<1 Word64 Q6_P_mpy_RlRl_s1(Word32 Rs, Word32 Rt) 553 -Rdd=mpy(Rs.L,Rt.L):<<1:rnd Word64 Q6_P_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt) 553 -Rdd=mpy(Rs.L,Rt.L):rnd Word64 Q6_P_mpy_RlRl_rnd(Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs,Rt):<<1:sat Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 568 -Rx+=mpy(Rs.H,Rt.H) Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.H,Rt.H):<<1 Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.H,Rt.H):<<1:sat Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.H,Rt.H):sat Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.H,Rt.L) Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.H,Rt.L):<<1 Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.H,Rt.L):<<1:sat Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.H,Rt.L):sat Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.L,Rt.H) Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.L,Rt.H):<<1 Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.L,Rt.H):<<1:sat Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.L,Rt.H):sat Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.L,Rt.L) Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.L,Rt.L):<<1 Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.L,Rt.L):<<1:sat Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx+=mpy(Rs.L,Rt.L):sat Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx-=mpy(Rs,Rt):<<1:sat Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 568 -Rx-=mpy(Rs.H,Rt.H) Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx-=mpy(Rs.H,Rt.H):<<1 Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx-=mpy(Rs.H,Rt.H):<<1:sat Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx-=mpy(Rs.H,Rt.H):sat Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx-=mpy(Rs.H,Rt.L) Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) 553 -Rx-=mpy(Rs.H,Rt.L):<<1 Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.H,Rt.L):<<1:sat Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.H,Rt.L):sat Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.L,Rt.H) Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.L,Rt.H):<<1 Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.L,Rt.H):<<1:sat Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.L,Rt.H):sat Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.L,Rt.L) Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.L,Rt.L):<<1 Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.L,Rt.L):<<1:sat Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rx-=mpy(Rs.L,Rt.L):sat Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) 554 -Rxx+=mpy(Rs,Rt) Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 570 -Rxx+=mpy(Rs.H,Rt.H) Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx+=mpy(Rs.H,Rt.H):<<1 Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx+=mpy(Rs.H,Rt.L) Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx+=mpy(Rs.H,Rt.L):<<1 Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx+=mpy(Rs.L,Rt.H) Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx+=mpy(Rs.L,Rt.H):<<1 Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx+=mpy(Rs.L,Rt.L) Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx+=mpy(Rs.L,Rt.L):<<1 Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 554 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 709 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rxx-=mpy(Rs,Rt) Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 570 -Rxx-=mpy(Rs.H,Rt.H) Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx-=mpy(Rs.H,Rt.H):<<1 Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx-=mpy(Rs.H,Rt.L) Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) 554 -Rxx-=mpy(Rs.H,Rt.L):<<1 Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 555 -Rxx-=mpy(Rs.L,Rt.H) Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) 555 -Rxx-=mpy(Rs.L,Rt.H):<<1 Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 555 -Rxx-=mpy(Rs.L,Rt.L) Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) 555 -Rxx-=mpy(Rs.L,Rt.L):<<1 Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 555 - -mpyi -Rd=mpyi(Rs,#m9) Word32 Q6_R_mpyi_RI(Word32 Rs, Word32 Im9) 540 -Rd=mpyi(Rs,Rt) Word32 Q6_R_mpyi_RR(Word32 Rs, Word32 Rt) 540 -Rx+=mpyi(Rs,#u8) Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32 Iu8) 540 -Rx+=mpyi(Rs,Rt) Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 540 -Rx-=mpyi(Rs,#u8) Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32 Iu8) 540 - -mpysu -Rd=mpysu(Rs,Rt) Word32 Q6_R_mpysu_RR(Word32 Rs, Word32 Rt) 568 - -mpyu -Rd=mpyu(Rs,Rt) UWord32 Q6_R_mpyu_RR(Word32 Rs, Word32 Rt) 568 -Rd=mpyu(Rs.H,Rt.H) UWord32 Q6_R_mpyu_RhRh(Word32 Rs, Word32 Rt) 559 -Rd=mpyu(Rs.H,Rt.H):<<1 UWord32 Q6_R_mpyu_RhRh_s1(Word32 Rs, Word32 Rt) 559 -Rd=mpyu(Rs.H,Rt.L) UWord32 Q6_R_mpyu_RhRl(Word32 Rs, Word32 Rt) 559 -Rd=mpyu(Rs.H,Rt.L):<<1 UWord32 Q6_R_mpyu_RhRl_s1(Word32 Rs, Word32 Rt) 559 -Rd=mpyu(Rs.L,Rt.H) UWord32 Q6_R_mpyu_RlRh(Word32 Rs, Word32 Rt) 559 -Rd=mpyu(Rs.L,Rt.H):<<1 UWord32 Q6_R_mpyu_RlRh_s1(Word32 Rs, Word32 Rt) 559 -Rd=mpyu(Rs.L,Rt.L) UWord32 Q6_R_mpyu_RlRl(Word32 Rs, Word32 Rt) 559 -Rd=mpyu(Rs.L,Rt.L):<<1 UWord32 Q6_R_mpyu_RlRl_s1(Word32 Rs, Word32 Rt) 559 -Rdd=mpyu(Rs,Rt) UWord64 Q6_P_mpyu_RR(Word32 Rs, Word32 Rt) 570 -Rdd=mpyu(Rs.H,Rt.H) UWord64 Q6_P_mpyu_RhRh(Word32 Rs, Word32 Rt) 559 -Rdd=mpyu(Rs.H,Rt.H):<<1 UWord64 Q6_P_mpyu_RhRh_s1(Word32 Rs, Word32 Rt) 559 -Rdd=mpyu(Rs.H,Rt.L) UWord64 Q6_P_mpyu_RhRl(Word32 Rs, Word32 Rt) 559 -Rdd=mpyu(Rs.H,Rt.L):<<1 UWord64 Q6_P_mpyu_RhRl_s1(Word32 Rs, Word32 Rt) 559 -Rdd=mpyu(Rs.L,Rt.H) UWord64 Q6_P_mpyu_RlRh(Word32 Rs, Word32 Rt) 559 -Rdd=mpyu(Rs.L,Rt.H):<<1 UWord64 Q6_P_mpyu_RlRh_s1(Word32 Rs, Word32 Rt) 559 -Rdd=mpyu(Rs.L,Rt.L) UWord64 Q6_P_mpyu_RlRl(Word32 Rs, Word32 Rt) 559 -Rdd=mpyu(Rs.L,Rt.L):<<1 UWord64 Q6_P_mpyu_RlRl_s1(Word32 Rs, Word32 Rt) 559 -Rx+=mpyu(Rs.H,Rt.H) Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) 559 -Rx+=mpyu(Rs.H,Rt.H):<<1 Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) 559 -Rx+=mpyu(Rs.H,Rt.L) Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) 559 -Rx+=mpyu(Rs.H,Rt.L):<<1 Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) 559 -Rx+=mpyu(Rs.L,Rt.H) Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) 559 -Rx+=mpyu(Rs.L,Rt.H):<<1 Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rx+=mpyu(Rs.L,Rt.L) Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rx+=mpyu(Rs.L,Rt.L):<<1 Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rx-=mpyu(Rs.H,Rt.H) Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rx-=mpyu(Rs.H,Rt.H):<<1 Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rx-=mpyu(Rs.H,Rt.L) Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rx-=mpyu(Rs.H,Rt.L):<<1 Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rx-=mpyu(Rs.L,Rt.H) Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rx-=mpyu(Rs.L,Rt.H):<<1 Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rx-=mpyu(Rs.L,Rt.L) Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) 560 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 710 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rx-=mpyu(Rs.L,Rt.L):<<1 Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) 560 -Rxx+=mpyu(Rs,Rt) Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 570 -Rxx+=mpyu(Rs.H,Rt.H) Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx+=mpyu(Rs.H,Rt.H):<<1 Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx+=mpyu(Rs.H,Rt.L) Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx+=mpyu(Rs.H,Rt.L):<<1 Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx+=mpyu(Rs.L,Rt.H) Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx+=mpyu(Rs.L,Rt.H):<<1 Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx+=mpyu(Rs.L,Rt.L) Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx+=mpyu(Rs.L,Rt.L):<<1 Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx-=mpyu(Rs,Rt) Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 570 -Rxx-=mpyu(Rs.H,Rt.H) Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx-=mpyu(Rs.H,Rt.H):<<1 Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx-=mpyu(Rs.H,Rt.L) Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) 560 -Rxx-=mpyu(Rs.H,Rt.L):<<1 Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 561 -Rxx-=mpyu(Rs.L,Rt.H) Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) 561 -Rxx-=mpyu(Rs.L,Rt.H):<<1 Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 561 -Rxx-=mpyu(Rs.L,Rt.L) Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) 561 -Rxx-=mpyu(Rs.L,Rt.L):<<1 Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) 561 - -mpyui -Rd=mpyui(Rs,Rt) Word32 Q6_R_mpyui_RR(Word32 Rs, Word32 Rt) 540 - -mux -Rd=mux(Pu,#s8,#S8) Word32 Q6_R_mux_pII(Byte Pu, Word32 Is8, Word32 IS8) 191 -Rd=mux(Pu,#s8,Rs) Word32 Q6_R_mux_pIR(Byte Pu, Word32 Is8, Word32 Rs) 191 -Rd=mux(Pu,Rs,#s8) Word32 Q6_R_mux_pRI(Byte Pu, Word32 Rs, Word32 Is8) 191 -Rd=mux(Pu,Rs,Rt) Word32 Q6_R_mux_pRR(Byte Pu, Word32 Rs, Word32 Rt) 191 - -N -neg -Rd=neg(Rs) Word32 Q6_R_neg_R(Word32 Rs) 175 -Rd=neg(Rs):sat Word32 Q6_R_neg_R_sat(Word32 Rs) 408 -Rdd=neg(Rss) Word64 Q6_P_neg_P(Word64 Rss) 408 - -no mnemonic -Pd=Ps Byte Q6_p_equals_p(Byte Ps) 221 -Pd=Rs Byte Q6_p_equals_R(Word32 Rs) 634 -Rd=#s16 Word32 Q6_R_equals_I(Word32 Is16) 180 -Rd=Ps Word32 Q6_R_equals_p(Byte Ps) 634 -Rd=Rs Word32 Q6_R_equals_R(Word32 Rs) 182 -Rdd=#s8 Word64 Q6_P_equals_I(Word32 Is8) 180 -Rdd=Rss Word64 Q6_P_equals_P(Word64 Rss) 182 -Rx.H=#u16 Word32 Q6_Rh_equals_I(Word32 Rx, Word32 Iu16) 180 -Rx.L=#u16 Word32 Q6_Rl_equals_I(Word32 Rx, Word32 Iu16) 180 - -normamt -Rd=normamt(Rs) Word32 Q6_R_normamt_R(Word32 Rs) 463 -Rd=normamt(Rss) Word32 Q6_R_normamt_P(Word64 Rss) 463 - -not -Pd=not(Ps) Byte Q6_p_not_p(Byte Ps) 221 -Rd=not(Rs) Word32 Q6_R_not_R(Word32 Rs) 173 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 711 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rdd=not(Rss) Word64 Q6_P_not_P(Word64 Rss) 398 - -O -or -Pd=and(Ps,or(Pt,!Pu)) Byte Q6_p_and_or_ppnp(Byte Ps, Byte Pt, Byte Pu) 221 -Pd=and(Ps,or(Pt,Pu)) Byte Q6_p_and_or_ppp(Byte Ps, Byte Pt, Byte Pu) 221 -Pd=or(Ps,and(Pt,!Pu)) Byte Q6_p_or_and_ppnp(Byte Ps, Byte Pt, Byte Pu) 221 -Pd=or(Ps,and(Pt,Pu)) Byte Q6_p_or_and_ppp(Byte Ps, Byte Pt, Byte Pu) 221 -Pd=or(Ps,or(Pt,!Pu)) Byte Q6_p_or_or_ppnp(Byte Ps, Byte Pt, Byte Pu) 222 -Pd=or(Ps,or(Pt,Pu)) Byte Q6_p_or_or_ppp(Byte Ps, Byte Pt, Byte Pu) 222 -Pd=or(Pt,!Ps) Byte Q6_p_or_pnp(Byte Pt, Byte Ps) 222 -Pd=or(Pt,Ps) Byte Q6_p_or_pp(Byte Pt, Byte Ps) 222 -Rd=or(Rs,#s10) Word32 Q6_R_or_RI(Word32 Rs, Word32 Is10) 173 -Rd=or(Rs,Rt) Word32 Q6_R_or_RR(Word32 Rs, Word32 Rt) 173 -Rd=or(Rt,~Rs) Word32 Q6_R_or_RnR(Word32 Rt, Word32 Rs) 173 -Rdd=or(Rss,Rtt) Word64 Q6_P_or_PP(Word64 Rss, Word64 Rtt) 398 -Rdd=or(Rtt,~Rss) Word64 Q6_P_or_PnP(Word64 Rtt, Word64 Rss) 398 -Rx^=or(Rs,Rt) Word32 Q6_R_orxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 401 -Rx&=or(Rs,Rt) Word32 Q6_R_orand_RR(Word32 Rx, Word32 Rs, Word32 Rt) 401 -Rx=or(Ru,and(Rx,#s10)) Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32 Is10) 401 -Rx|=or(Rs,#s10) Word32 Q6_R_oror_RI(Word32 Rx, Word32 Rs, Word32 Is10) 402 -Rx|=or(Rs,Rt) Word32 Q6_R_oror_RR(Word32 Rx, Word32 Rs, Word32 Rt) 402 - -P -packhl -Rdd=packhl(Rs,Rt) Word64 Q6_P_packhl_RR(Word32 Rs, Word32 Rt) 195 - -parity -Rd=parity(Rs,Rt) Word32 Q6_R_parity_RR(Word32 Rs, Word32 Rt) 474 -Rd=parity(Rss,Rtt) Word32 Q6_R_parity_PP(Word64 Rss, Word64 Rtt) 474 - -pmpyw -Rdd=pmpyw(Rs,Rt) Word64 Q6_P_pmpyw_RR(Word32 Rs, Word32 Rt) 564 -Rxx^=pmpyw(Rs,Rt) Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 564 - -popcount -Rd=popcount(Rss) Word32 Q6_R_popcount_P(Word64 Rss) 465 - -R -rol -Rd=rol(Rs,#u5) Word32 Q6_R_rol_RI(Word32 Rs, Word32 Iu5) 646 -Rdd=rol(Rss,#u6) Word64 Q6_P_rol_PI(Word64 Rss, Word32 Iu6) 646 -Rx^=rol(Rs,#u5) Word32 Q6_R_rolxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx&=rol(Rs,#u5) Word32 Q6_R_roland_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rx+=rol(Rs,#u5) Word32 Q6_R_rolacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 648 -Rx-=rol(Rs,#u5) Word32 Q6_R_rolnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 648 -Rx|=rol(Rs,#u5) Word32 Q6_R_rolor_RI(Word32 Rx, Word32 Rs, Word32 Iu5) 652 -Rxx^=rol(Rss,#u6) Word64 Q6_P_rolxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 -Rxx&=rol(Rss,#u6) Word64 Q6_P_roland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 -Rxx+=rol(Rss,#u6) Word64 Q6_P_rolacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 648 -Rxx-=rol(Rss,#u6) Word64 Q6_P_rolnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 648 -Rxx|=rol(Rss,#u6) Word64 Q6_P_rolor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) 653 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 712 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -round -Rd=round(Rs,#u5) Word32 Q6_R_round_RI(Word32 Rs, Word32 Iu5) 409 -Rd=round(Rs,#u5):sat Word32 Q6_R_round_RI_sat(Word32 Rs, Word32 Iu5) 409 -Rd=round(Rs,Rt) Word32 Q6_R_round_RR(Word32 Rs, Word32 Rt) 409 -Rd=round(Rs,Rt):sat Word32 Q6_R_round_RR_sat(Word32 Rs, Word32 Rt) 409 -Rd=round(Rss):sat Word32 Q6_R_round_P_sat(Word64 Rss) 409 - -S -sat -Rd=sat(Rss) Word32 Q6_R_sat_P(Word64 Rss) 599 - -satb -Rd=satb(Rs) Word32 Q6_R_satb_R(Word32 Rs) 599 - -sath -Rd=sath(Rs) Word32 Q6_R_sath_R(Word32 Rs) 599 - -satub -Rd=satub(Rs) Word32 Q6_R_satub_R(Word32 Rs) 599 - -satuh -Rd=satuh(Rs) Word32 Q6_R_satuh_R(Word32 Rs) 599 - -setbit -Rd=setbit(Rs,#u5) Word32 Q6_R_setbit_RI(Word32 Rs, Word32 Iu5) 476 -Rd=setbit(Rs,Rt) Word32 Q6_R_setbit_RR(Word32 Rs, Word32 Rt) 476 - -sfadd -Rd=sfadd(Rs,Rt) Word32 Q6_R_sfadd_RR(Word32 Rs, Word32 Rt) 516 - -sfclass -Pd=sfclass(Rs,#u5) Byte Q6_p_sfclass_RI(Word32 Rs, Word32 Iu5) 517 - -sfcmp.eq -Pd=sfcmp.eq(Rs,Rt) Byte Q6_p_sfcmp_eq_RR(Word32 Rs, Word32 Rt) 519 - -sfcmp.ge -Pd=sfcmp.ge(Rs,Rt) Byte Q6_p_sfcmp_ge_RR(Word32 Rs, Word32 Rt) 519 - -sfcmp.gt -Pd=sfcmp.gt(Rs,Rt) Byte Q6_p_sfcmp_gt_RR(Word32 Rs, Word32 Rt) 519 - -sfcmp.uo -Pd=sfcmp.uo(Rs,Rt) Byte Q6_p_sfcmp_uo_RR(Word32 Rs, Word32 Rt) 519 - -sffixupd -Rd=sffixupd(Rs,Rt) Word32 Q6_R_sffixupd_RR(Word32 Rs, Word32 Rt) 527 - -sffixupn -Rd=sffixupn(Rs,Rt) Word32 Q6_R_sffixupn_RR(Word32 Rs, Word32 Rt) 527 - -sffixupr -Rd=sffixupr(Rs) Word32 Q6_R_sffixupr_R(Word32 Rs) 527 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 713 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -sfmake -Rd=sfmake(#u10):neg Word32 Q6_R_sfmake_I_neg(Word32 Iu10) 533 -Rd=sfmake(#u10):pos Word32 Q6_R_sfmake_I_pos(Word32 Iu10) 533 - -sfmax -Rd=sfmax(Rs,Rt) Word32 Q6_R_sfmax_RR(Word32 Rs, Word32 Rt) 534 - -sfmin -Rd=sfmin(Rs,Rt) Word32 Q6_R_sfmin_RR(Word32 Rs, Word32 Rt) 535 - -sfmpy -Rd=sfmpy(Rs,Rt) Word32 Q6_R_sfmpy_RR(Word32 Rs, Word32 Rt) 536 -Rx+=sfmpy(Rs,Rt,Pu):scale Word32 Q6_R_sfmpyacc_RRp_scale(Word32 Rx, Word32 Rs, Word32 Rt, Byte Pu) 529 -Rx+=sfmpy(Rs,Rt) Word32 Q6_R_sfmpyacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 528 -Rx+=sfmpy(Rs,Rt):lib Word32 Q6_R_sfmpyacc_RR_lib(Word32 Rx, Word32 Rs, Word32 Rt) 531 -Rx-=sfmpy(Rs,Rt) Word32 Q6_R_sfmpynac_RR(Word32 Rx, Word32 Rs, Word32 Rt) 528 -Rx-=sfmpy(Rs,Rt):lib Word32 Q6_R_sfmpynac_RR_lib(Word32 Rx, Word32 Rs, Word32 Rt) 531 - -sfsub -Rd=sfsub(Rs,Rt) Word32 Q6_R_sfsub_RR(Word32 Rs, Word32 Rt) 538 - -shuffeb -Rdd=shuffeb(Rss,Rtt) Word64 Q6_P_shuffeb_PP(Word64 Rss, Word64 Rtt) 612 - -shuffeh -Rdd=shuffeh(Rss,Rtt) Word64 Q6_P_shuffeh_PP(Word64 Rss, Word64 Rtt) 612 - -shuffob -Rdd=shuffob(Rtt,Rss) Word64 Q6_P_shuffob_PP(Word64 Rtt, Word64 Rss) 612 - -shuffoh -Rdd=shuffoh(Rtt,Rss) Word64 Q6_P_shuffoh_PP(Word64 Rtt, Word64 Rss) 612 - -sub -Rd=add(Rs,sub(#s6,Ru)) Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32 Ru) 390 -Rd=sub(#s10,Rs) Word32 Q6_R_sub_IR(Word32 Is10, Word32 Rs) 177 -Rd=sub(Rt,Rs) Word32 Q6_R_sub_RR(Word32 Rt, Word32 Rs) 177 -Rd=sub(Rt,Rs):sat Word32 Q6_R_sub_RR_sat(Word32 Rt, Word32 Rs) 177 -Rd=sub(Rt.H,Rs.H):<<16 Word32 Q6_R_sub_RhRh_s16(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.H,Rs.H):sat:<<16 Word32 Q6_R_sub_RhRh_sat_s16(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.H,Rs.L):<<16 Word32 Q6_R_sub_RhRl_s16(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.H,Rs.L):sat:<<16 Word32 Q6_R_sub_RhRl_sat_s16(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.L,Rs.H) Word32 Q6_R_sub_RlRh(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.L,Rs.H):<<16 Word32 Q6_R_sub_RlRh_s16(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.L,Rs.H):sat Word32 Q6_R_sub_RlRh_sat(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.L,Rs.H):sat:<<16 Word32 Q6_R_sub_RlRh_sat_s16(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.L,Rs.L) Word32 Q6_R_sub_RlRl(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.L,Rs.L):<<16 Word32 Q6_R_sub_RlRl_s16(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.L,Rs.L):sat Word32 Q6_R_sub_RlRl_sat(Word32 Rt, Word32 Rs) 414 -Rd=sub(Rt.L,Rs.L):sat:<<16 Word32 Q6_R_sub_RlRl_sat_s16(Word32 Rt, Word32 Rs) 414 -Rdd=sub(Rtt,Rss) Word64 Q6_P_sub_PP(Word64 Rtt, Word64 Rss) 411 -Rx+=sub(Rt,Rs) Word32 Q6_R_subacc_RR(Word32 Rx, Word32 Rt, Word32 Rs) 412 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 714 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -swiz -Rd=swiz(Rs) Word32 Q6_R_swiz_R(Word32 Rs) 601 - -sxtb -Rd=sxtb(Rs) Word32 Q6_R_sxtb_R(Word32 Rs) 179 - -sxth -Rd=sxth(Rs) Word32 Q6_R_sxth_R(Word32 Rs) 179 - -sxtw -Rdd=sxtw(Rs) Word64 Q6_P_sxtw_R(Word32 Rs) 416 - -T -tableidxb -Rx=tableidxb(Rs,#u4,#U5) Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) 481 - -tableidxd -Rx=tableidxd(Rs,#u4,#U5) Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) 481 - -tableidxh -Rx=tableidxh(Rs,#u4,#U5) Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) 481 - -tableidxw -Rx=tableidxw(Rs,#u4,#U5) Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) 481 - -tlbmatch -Pd=tlbmatch(Rss,Rt) Byte Q6_p_tlbmatch_PR(Word64 Rss, Word32 Rt) 633 - -togglebit -Rd=togglebit(Rs,#u5) Word32 Q6_R_togglebit_RI(Word32 Rs, Word32 Iu5) 476 -Rd=togglebit(Rs,Rt) Word32 Q6_R_togglebit_RR(Word32 Rs, Word32 Rt) 476 - -tstbit -Pd=!tstbit(Rs,#u5) Byte Q6_p_not_tstbit_RI(Word32 Rs, Word32 Iu5) 635 -Pd=!tstbit(Rs,Rt) Byte Q6_p_not_tstbit_RR(Word32 Rs, Word32 Rt) 635 -Pd=tstbit(Rs,#u5) Byte Q6_p_tstbit_RI(Word32 Rs, Word32 Iu5) 635 -Pd=tstbit(Rs,Rt) Byte Q6_p_tstbit_RR(Word32 Rs, Word32 Rt) 635 - -V -vabsdiffb -Rdd=vabsdiffb(Rtt,Rss) Word64 Q6_P_vabsdiffb_PP(Word64 Rtt, Word64 Rss) 419 - -vabsdiffh -Rdd=vabsdiffh(Rtt,Rss) Word64 Q6_P_vabsdiffh_PP(Word64 Rtt, Word64 Rss) 420 - -vabsdiffub -Rdd=vabsdiffub(Rtt,Rss) Word64 Q6_P_vabsdiffub_PP(Word64 Rtt, Word64 Rss) 419 - -vabsdiffw -Rdd=vabsdiffw(Rtt,Rss) Word64 Q6_P_vabsdiffw_PP(Word64 Rtt, Word64 Rss) 421 - -vabsh -Rdd=vabsh(Rss) Word64 Q6_P_vabsh_P(Word64 Rss) 417 - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 715 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rdd=vabsh(Rss):sat Word64 Q6_P_vabsh_P_sat(Word64 Rss) 417 - -vabsw -Rdd=vabsw(Rss) Word64 Q6_P_vabsw_P(Word64 Rss) 418 -Rdd=vabsw(Rss):sat Word64 Q6_P_vabsw_P_sat(Word64 Rss) 418 - -vaddb -Rdd=vaddb(Rss,Rtt) Word64 Q6_P_vaddb_PP(Word64 Rss, Word64 Rtt) 432 - -vaddh -Rd=vaddh(Rs,Rt) Word32 Q6_R_vaddh_RR(Word32 Rs, Word32 Rt) 183 -Rd=vaddh(Rs,Rt):sat Word32 Q6_R_vaddh_RR_sat(Word32 Rs, Word32 Rt) 183 -Rdd=vaddh(Rss,Rtt) Word64 Q6_P_vaddh_PP(Word64 Rss, Word64 Rtt) 425 -Rdd=vaddh(Rss,Rtt):sat Word64 Q6_P_vaddh_PP_sat(Word64 Rss, Word64 Rtt) 425 - -vaddhub -Rd=vaddhub(Rss,Rtt):sat Word32 Q6_R_vaddhub_PP_sat(Word64 Rss, Word64 Rtt) 427 - -vaddub -Rdd=vaddub(Rss,Rtt) Word64 Q6_P_vaddub_PP(Word64 Rss, Word64 Rtt) 432 -Rdd=vaddub(Rss,Rtt):sat Word64 Q6_P_vaddub_PP_sat(Word64 Rss, Word64 Rtt) 432 - -vadduh -Rd=vadduh(Rs,Rt):sat Word32 Q6_R_vadduh_RR_sat(Word32 Rs, Word32 Rt) 183 -Rdd=vadduh(Rss,Rtt):sat Word64 Q6_P_vadduh_PP_sat(Word64 Rss, Word64 Rtt) 425 - -vaddw -Rdd=vaddw(Rss,Rtt) Word64 Q6_P_vaddw_PP(Word64 Rss, Word64 Rtt) 433 -Rdd=vaddw(Rss,Rtt):sat Word64 Q6_P_vaddw_PP_sat(Word64 Rss, Word64 Rtt) 433 - -valignb -Rdd=valignb(Rtt,Rss,#u3) Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32 Iu3) 602 -Rdd=valignb(Rtt,Rss,Pu) Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte Pu) 602 - -vaslh -Rdd=vaslh(Rss,#u4) Word64 Q6_P_vaslh_PI(Word64 Rss, Word32 Iu4) 670 -Rdd=vaslh(Rss,Rt) Word64 Q6_P_vaslh_PR(Word64 Rss, Word32 Rt) 677 - -vaslw -Rdd=vaslw(Rss,#u5) Word64 Q6_P_vaslw_PI(Word64 Rss, Word32 Iu5) 678 -Rdd=vaslw(Rss,Rt) Word64 Q6_P_vaslw_PR(Word64 Rss, Word32 Rt) 681 - -vasrh -Rdd=vasrh(Rss,#u4) Word64 Q6_P_vasrh_PI(Word64 Rss, Word32 Iu4) 670 -Rdd=vasrh(Rss,#u4):rnd Word64 Q6_P_vasrh_PI_rnd(Word64 Rss, Word32 Iu4) 672 -Rdd=vasrh(Rss,Rt) Word64 Q6_P_vasrh_PR(Word64 Rss, Word32 Rt) 677 - -vasrhub -Rd=vasrhub(Rss,#u4):rnd:sat Word32 Q6_R_vasrhub_PI_rnd_sat(Word64 Rss, Word32 Iu4) 675 -Rd=vasrhub(Rss,#u4):sat Word32 Q6_R_vasrhub_PI_sat(Word64 Rss, Word32 Iu4) 675 - -vasrw -Rd=vasrw(Rss,#u5) Word32 Q6_R_vasrw_PI(Word64 Rss, Word32 Iu5) 682 -Rd=vasrw(Rss,Rt) Word32 Q6_R_vasrw_PR(Word64 Rss, Word32 Rt) 682 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 716 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Rdd=vasrw(Rss,#u5) Word64 Q6_P_vasrw_PI(Word64 Rss, Word32 Iu5) 678 -Rdd=vasrw(Rss,Rt) Word64 Q6_P_vasrw_PR(Word64 Rss, Word32 Rt) 681 - -vavgh -Rd=vavgh(Rs,Rt) Word32 Q6_R_vavgh_RR(Word32 Rs, Word32 Rt) 184 -Rd=vavgh(Rs,Rt):rnd Word32 Q6_R_vavgh_RR_rnd(Word32 Rs, Word32 Rt) 184 -Rdd=vavgh(Rss,Rtt) Word64 Q6_P_vavgh_PP(Word64 Rss, Word64 Rtt) 435 -Rdd=vavgh(Rss,Rtt):crnd Word64 Q6_P_vavgh_PP_crnd(Word64 Rss, Word64 Rtt) 435 -Rdd=vavgh(Rss,Rtt):rnd Word64 Q6_P_vavgh_PP_rnd(Word64 Rss, Word64 Rtt) 435 - -vavgub -Rdd=vavgub(Rss,Rtt) Word64 Q6_P_vavgub_PP(Word64 Rss, Word64 Rtt) 436 -Rdd=vavgub(Rss,Rtt):rnd Word64 Q6_P_vavgub_PP_rnd(Word64 Rss, Word64 Rtt) 436 - -vavguh -Rdd=vavguh(Rss,Rtt) Word64 Q6_P_vavguh_PP(Word64 Rss, Word64 Rtt) 435 -Rdd=vavguh(Rss,Rtt):rnd Word64 Q6_P_vavguh_PP_rnd(Word64 Rss, Word64 Rtt) 435 - -vavguw -Rdd=vavguw(Rss,Rtt) Word64 Q6_P_vavguw_PP(Word64 Rss, Word64 Rtt) 438 -Rdd=vavguw(Rss,Rtt):rnd Word64 Q6_P_vavguw_PP_rnd(Word64 Rss, Word64 Rtt) 438 - -vavgw -Rdd=vavgw(Rss,Rtt) Word64 Q6_P_vavgw_PP(Word64 Rss, Word64 Rtt) 438 -Rdd=vavgw(Rss,Rtt):crnd Word64 Q6_P_vavgw_PP_crnd(Word64 Rss, Word64 Rtt) 438 -Rdd=vavgw(Rss,Rtt):rnd Word64 Q6_P_vavgw_PP_rnd(Word64 Rss, Word64 Rtt) 438 - -vcmpb.eq -Pd=any8(vcmpb.eq(Rss,Rtt)) Byte Q6_p_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) 638 -Pd=vcmpb.eq(Rss,#u8) Byte Q6_p_vcmpb_eq_PI(Word64 Rss, Word32 Iu8) 640 -Pd=vcmpb.eq(Rss,Rtt) Byte Q6_p_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) 640 - -vcmpb.gt -Pd=vcmpb.gt(Rss,#s8) Byte Q6_p_vcmpb_gt_PI(Word64 Rss, Word32 Is8) 640 -Pd=vcmpb.gt(Rss,Rtt) Byte Q6_p_vcmpb_gt_PP(Word64 Rss, Word64 Rtt) 640 - -vcmpb.gtu -Pd=vcmpb.gtu(Rss,#u7) Byte Q6_p_vcmpb_gtu_PI(Word64 Rss, Word32 Iu7) 640 -Pd=vcmpb.gtu(Rss,Rtt) Byte Q6_p_vcmpb_gtu_PP(Word64 Rss, Word64 Rtt) 640 - -vcmph.eq -Pd=vcmph.eq(Rss,#s8) Byte Q6_p_vcmph_eq_PI(Word64 Rss, Word32 Is8) 637 -Pd=vcmph.eq(Rss,Rtt) Byte Q6_p_vcmph_eq_PP(Word64 Rss, Word64 Rtt) 637 - -vcmph.gt -Pd=vcmph.gt(Rss,#s8) Byte Q6_p_vcmph_gt_PI(Word64 Rss, Word32 Is8) 637 -Pd=vcmph.gt(Rss,Rtt) Byte Q6_p_vcmph_gt_PP(Word64 Rss, Word64 Rtt) 637 - -vcmph.gtu -Pd=vcmph.gtu(Rss,#u7) Byte Q6_p_vcmph_gtu_PI(Word64 Rss, Word32 Iu7) 637 -Pd=vcmph.gtu(Rss,Rtt) Byte Q6_p_vcmph_gtu_PP(Word64 Rss, Word64 Rtt) 637 - -vcmpw.eq -Pd=vcmpw.eq(Rss,#s8) Byte Q6_p_vcmpw_eq_PI(Word64 Rss, Word32 Is8) 642 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 717 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - -Pd=vcmpw.eq(Rss,Rtt) Byte Q6_p_vcmpw_eq_PP(Word64 Rss, Word64 Rtt) 642 - -vcmpw.gt -Pd=vcmpw.gt(Rss,#s8) Byte Q6_p_vcmpw_gt_PI(Word64 Rss, Word32 Is8) 642 -Pd=vcmpw.gt(Rss,Rtt) Byte Q6_p_vcmpw_gt_PP(Word64 Rss, Word64 Rtt) 642 - -vcmpw.gtu -Pd=vcmpw.gtu(Rss,#u7) Byte Q6_p_vcmpw_gtu_PI(Word64 Rss, Word32 Iu7) 642 -Pd=vcmpw.gtu(Rss,Rtt) Byte Q6_p_vcmpw_gtu_PP(Word64 Rss, Word64 Rtt) 642 - -vcmpyi -Rdd=vcmpyi(Rss,Rtt):<<1:sat Word64 Q6_P_vcmpyi_PP_s1_sat(Word64 Rss, Word64 Rtt) 498 -Rdd=vcmpyi(Rss,Rtt):sat Word64 Q6_P_vcmpyi_PP_sat(Word64 Rss, Word64 Rtt) 498 -Rxx+=vcmpyi(Rss,Rtt):sat Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 498 - -vcmpyr -Rdd=vcmpyr(Rss,Rtt):<<1:sat Word64 Q6_P_vcmpyr_PP_s1_sat(Word64 Rss, Word64 Rtt) 498 -Rdd=vcmpyr(Rss,Rtt):sat Word64 Q6_P_vcmpyr_PP_sat(Word64 Rss, Word64 Rtt) 498 -Rxx+=vcmpyr(Rss,Rtt):sat Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 498 - -vcnegh -Rdd=vcnegh(Rss,Rt) Word64 Q6_P_vcnegh_PR(Word64 Rss, Word32 Rt) 439 - -vconj -Rdd=vconj(Rss):sat Word64 Q6_P_vconj_P_sat(Word64 Rss) 500 - -vcrotate -Rdd=vcrotate(Rss,Rt) Word64 Q6_P_vcrotate_PR(Word64 Rss, Word32 Rt) 502 - -vdmpy -Rd=vdmpy(Rss,Rtt):<<1:rnd:sat Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) 576 -Rd=vdmpy(Rss,Rtt):rnd:sat Word32 Q6_R_vdmpy_PP_rnd_sat(Word64 Rss, Word64 Rtt) 576 -Rdd=vdmpy(Rss,Rtt):<<1:sat Word64 Q6_P_vdmpy_PP_s1_sat(Word64 Rss, Word64 Rtt) 573 -Rdd=vdmpy(Rss,Rtt):sat Word64 Q6_P_vdmpy_PP_sat(Word64 Rss, Word64 Rtt) 573 -Rxx+=vdmpy(Rss,Rtt):<<1:sat Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 573 -Rxx+=vdmpy(Rss,Rtt):sat Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 573 - -vdmpybsu -Rdd=vdmpybsu(Rss,Rtt):sat Word64 Q6_P_vdmpybsu_PP_sat(Word64 Rss, Word64 Rtt) 581 -Rxx+=vdmpybsu(Rss,Rtt):sat Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 581 - -vitpack -Rd=vitpack(Ps,Pt) Word32 Q6_R_vitpack_pp(Byte Ps, Byte Pt) 643 - -vlslh -Rdd=vlslh(Rss,Rt) Word64 Q6_P_vlslh_PR(Word64 Rss, Word32 Rt) 677 - -vlslw -Rdd=vlslw(Rss,Rt) Word64 Q6_P_vlslw_PR(Word64 Rss, Word32 Rt) 681 - -vlsrh -Rdd=vlsrh(Rss,#u4) Word64 Q6_P_vlsrh_PI(Word64 Rss, Word32 Iu4) 670 -Rdd=vlsrh(Rss,Rt) Word64 Q6_P_vlsrh_PR(Word64 Rss, Word32 Rt) 677 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 718 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -vlsrw -Rdd=vlsrw(Rss,#u5) Word64 Q6_P_vlsrw_PI(Word64 Rss, Word32 Iu5) 678 -Rdd=vlsrw(Rss,Rt) Word64 Q6_P_vlsrw_PR(Word64 Rss, Word32 Rt) 681 - -vmaxb -Rdd=vmaxb(Rtt,Rss) Word64 Q6_P_vmaxb_PP(Word64 Rtt, Word64 Rss) 441 - -vmaxh -Rdd=vmaxh(Rtt,Rss) Word64 Q6_P_vmaxh_PP(Word64 Rtt, Word64 Rss) 442 - -vmaxub -Rdd=vmaxub(Rtt,Rss) Word64 Q6_P_vmaxub_PP(Word64 Rtt, Word64 Rss) 441 - -vmaxuh -Rdd=vmaxuh(Rtt,Rss) Word64 Q6_P_vmaxuh_PP(Word64 Rtt, Word64 Rss) 442 - -vmaxuw -Rdd=vmaxuw(Rtt,Rss) Word64 Q6_P_vmaxuw_PP(Word64 Rtt, Word64 Rss) 447 - -vmaxw -Rdd=vmaxw(Rtt,Rss) Word64 Q6_P_vmaxw_PP(Word64 Rtt, Word64 Rss) 447 - -vminb -Rdd=vminb(Rtt,Rss) Word64 Q6_P_vminb_PP(Word64 Rtt, Word64 Rss) 448 - -vminh -Rdd=vminh(Rtt,Rss) Word64 Q6_P_vminh_PP(Word64 Rtt, Word64 Rss) 450 - -vminub -Rdd=vminub(Rtt,Rss) Word64 Q6_P_vminub_PP(Word64 Rtt, Word64 Rss) 448 - -vminuh -Rdd=vminuh(Rtt,Rss) Word64 Q6_P_vminuh_PP(Word64 Rtt, Word64 Rss) 450 - -vminuw -Rdd=vminuw(Rtt,Rss) Word64 Q6_P_vminuw_PP(Word64 Rtt, Word64 Rss) 455 - -vminw -Rdd=vminw(Rtt,Rss) Word64 Q6_P_vminw_PP(Word64 Rtt, Word64 Rss) 455 - -vmpybsu -Rdd=vmpybsu(Rs,Rt) Word64 Q6_P_vmpybsu_RR(Word32 Rs, Word32 Rt) 593 -Rxx+=vmpybsu(Rs,Rt) Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 593 - -vmpybu -Rdd=vmpybu(Rs,Rt) Word64 Q6_P_vmpybu_RR(Word32 Rs, Word32 Rt) 593 -Rxx+=vmpybu(Rs,Rt) Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 593 - -vmpyeh -Rdd=vmpyeh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpyeh_PP_s1_sat(Word64 Rss, Word64 Rtt) 583 -Rdd=vmpyeh(Rss,Rtt):sat Word64 Q6_P_vmpyeh_PP_sat(Word64 Rss, Word64 Rtt) 583 -Rxx+=vmpyeh(Rss,Rtt) Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 583 -Rxx+=vmpyeh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 583 -Rxx+=vmpyeh(Rss,Rtt):sat Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 583 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 719 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -vmpyh -Rd=vmpyh(Rs,Rt):<<1:rnd:sat Word32 Q6_R_vmpyh_RR_s1_rnd_sat(Word32 Rs, Word32 Rt) 587 -Rd=vmpyh(Rs,Rt):rnd:sat Word32 Q6_R_vmpyh_RR_rnd_sat(Word32 Rs, Word32 Rt) 587 -Rdd=vmpyh(Rs,Rt):<<1:sat Word64 Q6_P_vmpyh_RR_s1_sat(Word32 Rs, Word32 Rt) 585 -Rdd=vmpyh(Rs,Rt):sat Word64 Q6_P_vmpyh_RR_sat(Word32 Rs, Word32 Rt) 585 -Rxx+=vmpyh(Rs,Rt) Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 585 -Rxx+=vmpyh(Rs,Rt):<<1:sat Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 585 -Rxx+=vmpyh(Rs,Rt):sat Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 585 - -vmpyhsu -Rdd=vmpyhsu(Rs,Rt):<<1:sat Word64 Q6_P_vmpyhsu_RR_s1_sat(Word32 Rs, Word32 Rt) 588 -Rdd=vmpyhsu(Rs,Rt):sat Word64 Q6_P_vmpyhsu_RR_sat(Word32 Rs, Word32 Rt) 588 -Rxx+=vmpyhsu(Rs,Rt):<<1:sat Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 588 -Rxx+=vmpyhsu(Rs,Rt):sat Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) 588 - -vmpyweh -Rdd=vmpyweh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) 544 -Rdd=vmpyweh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpyweh_PP_s1_sat(Word64 Rss, Word64 Rtt) 544 -Rdd=vmpyweh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpyweh_PP_rnd_sat(Word64 Rss, Word64 Rtt) 544 -Rdd=vmpyweh(Rss,Rtt):sat Word64 Q6_P_vmpyweh_PP_sat(Word64 Rss, Word64 Rtt) 544 -Rxx+=vmpyweh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 544 -Rxx+=vmpyweh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 544 -Rxx+=vmpyweh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 544 -Rxx+=vmpyweh(Rss,Rtt):sat Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 544 - -vmpyweuh -Rdd=vmpyweuh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) 548 -Rdd=vmpyweuh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpyweuh_PP_s1_sat(Word64 Rss, Word64 Rtt) 548 -Rdd=vmpyweuh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64 Rtt) 548 -Rdd=vmpyweuh(Rss,Rtt):sat Word64 Q6_P_vmpyweuh_PP_sat(Word64 Rss, Word64 Rtt) 548 -Rxx+=vmpyweuh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 548 -Rxx+=vmpyweuh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 548 -Rxx+=vmpyweuh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 548 -Rxx+=vmpyweuh(Rss,Rtt):sat Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 548 - -vmpywoh -Rdd=vmpywoh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) 544 -Rdd=vmpywoh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywoh_PP_s1_sat(Word64 Rss, Word64 Rtt) 544 -Rdd=vmpywoh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywoh_PP_rnd_sat(Word64 Rss, Word64 Rtt) 544 -Rdd=vmpywoh(Rss,Rtt):sat Word64 Q6_P_vmpywoh_PP_sat(Word64 Rss, Word64 Rtt) 544 -Rxx+=vmpywoh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 544 -Rxx+=vmpywoh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 544 -Rxx+=vmpywoh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 544 -Rxx+=vmpywoh(Rss,Rtt):sat Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 544 - -vmpywouh -Rdd=vmpywouh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) 548 -Rdd=vmpywouh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywouh_PP_s1_sat(Word64 Rss, Word64 Rtt) 548 -Rdd=vmpywouh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64 Rtt) 548 -Rdd=vmpywouh(Rss,Rtt):sat Word64 Q6_P_vmpywouh_PP_sat(Word64 Rss, Word64 Rtt) 548 -Rxx+=vmpywouh(Rss,Rtt):<<1:rnd:sat Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 548 -Rxx+=vmpywouh(Rss,Rtt):<<1:sat Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 548 -Rxx+=vmpywouh(Rss,Rtt):rnd:sat Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 548 -Rxx+=vmpywouh(Rss,Rtt):sat Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) 548 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 720 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -vmux -Rdd=vmux(Pu,Rss,Rtt) Word64 Q6_P_vmux_pPP(Byte Pu, Word64 Rss, Word64 Rtt) 644 - -vnavgh -Rd=vnavgh(Rt,Rs) Word32 Q6_R_vnavgh_RR(Word32 Rt, Word32 Rs) 184 -Rdd=vnavgh(Rtt,Rss) Word64 Q6_P_vnavgh_PP(Word64 Rtt, Word64 Rss) 435 -Rdd=vnavgh(Rtt,Rss):crnd:sat Word64 Q6_P_vnavgh_PP_crnd_sat(Word64 Rtt, Word64 Rss) 435 -Rdd=vnavgh(Rtt,Rss):rnd:sat Word64 Q6_P_vnavgh_PP_rnd_sat(Word64 Rtt, Word64 Rss) 435 - -vnavgw -Rdd=vnavgw(Rtt,Rss) Word64 Q6_P_vnavgw_PP(Word64 Rtt, Word64 Rss) 438 -Rdd=vnavgw(Rtt,Rss):crnd:sat Word64 Q6_P_vnavgw_PP_crnd_sat(Word64 Rtt, Word64 Rss) 438 -Rdd=vnavgw(Rtt,Rss):rnd:sat Word64 Q6_P_vnavgw_PP_rnd_sat(Word64 Rtt, Word64 Rss) 438 - -vpmpyh -Rdd=vpmpyh(Rs,Rt) Word64 Q6_P_vpmpyh_RR(Word32 Rs, Word32 Rt) 595 -Rxx^=vpmpyh(Rs,Rt) Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) 595 - -vraddh -Rd=vraddh(Rss,Rtt) Word32 Q6_R_vraddh_PP(Word64 Rss, Word64 Rtt) 430 - -vraddub -Rdd=vraddub(Rss,Rtt) Word64 Q6_P_vraddub_PP(Word64 Rss, Word64 Rtt) 428 -Rxx+=vraddub(Rss,Rtt) Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 428 - -vradduh -Rd=vradduh(Rss,Rtt) Word32 Q6_R_vradduh_PP(Word64 Rss, Word64 Rtt) 430 - -vrcmpyi -Rdd=vrcmpyi(Rss,Rtt) Word64 Q6_P_vrcmpyi_PP(Word64 Rss, Word64 Rtt) 504 -Rdd=vrcmpyi(Rss,Rtt*) Word64 Q6_P_vrcmpyi_PP_conj(Word64 Rss, Word64 Rtt) 504 -Rxx+=vrcmpyi(Rss,Rtt) Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 504 -Rxx+=vrcmpyi(Rss,Rtt*) Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) 504 - -vrcmpyr -Rdd=vrcmpyr(Rss,Rtt) Word64 Q6_P_vrcmpyr_PP(Word64 Rss, Word64 Rtt) 504 -Rdd=vrcmpyr(Rss,Rtt*) Word64 Q6_P_vrcmpyr_PP_conj(Word64 Rss, Word64 Rtt) 504 -Rxx+=vrcmpyr(Rss,Rtt) Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 504 -Rxx+=vrcmpyr(Rss,Rtt*) Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) 504 - -vrcmpys -Rd=vrcmpys(Rss,Rt):<<1:rnd:sat Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) 510 -Rdd=vrcmpys(Rss,Rt):<<1:sat Word64 Q6_P_vrcmpys_PR_s1_sat(Word64 Rss, Word32 Rt) 508 -Rxx+=vrcmpys(Rss,Rt):<<1:sat Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64 Rss, Word32 Rt) 508 - -vrcnegh -Rxx+=vrcnegh(Rss,Rt) Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) 439 - -vrcrotate -Rdd=vrcrotate(Rss,Rt,#u2) Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt, Word32 Iu2) 513 -Rxx+=vrcrotate(Rss,Rt,#u2) Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss, Word32 Rt, Word32 Iu2) 513 - -vrmaxh -Rxx=vrmaxh(Rss,Ru) Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) 443 - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 721 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -vrmaxuh -Rxx=vrmaxuh(Rss,Ru) Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) 443 - -vrmaxuw -Rxx=vrmaxuw(Rss,Ru) Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) 445 - -vrmaxw -Rxx=vrmaxw(Rss,Ru) Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) 445 - -vrminh -Rxx=vrminh(Rss,Ru) Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) 451 - -vrminuh -Rxx=vrminuh(Rss,Ru) Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) 451 - -vrminuw -Rxx=vrminuw(Rss,Ru) Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) 453 - -vrminw -Rxx=vrminw(Rss,Ru) Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) 453 - -vrmpybsu -Rdd=vrmpybsu(Rss,Rtt) Word64 Q6_P_vrmpybsu_PP(Word64 Rss, Word64 Rtt) 578 -Rxx+=vrmpybsu(Rss,Rtt) Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 578 - -vrmpybu -Rdd=vrmpybu(Rss,Rtt) Word64 Q6_P_vrmpybu_PP(Word64 Rss, Word64 Rtt) 578 -Rxx+=vrmpybu(Rss,Rtt) Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 578 - -vrmpyh -Rdd=vrmpyh(Rss,Rtt) Word64 Q6_P_vrmpyh_PP(Word64 Rss, Word64 Rtt) 590 -Rxx+=vrmpyh(Rss,Rtt) Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 590 - -vrmpyweh -Rdd=vrmpyweh(Rss,Rtt) Word64 Q6_P_vrmpyweh_PP(Word64 Rss, Word64 Rtt) 566 -Rdd=vrmpyweh(Rss,Rtt):<<1 Word64 Q6_P_vrmpyweh_PP_s1(Word64 Rss, Word64 Rtt) 566 -Rxx+=vrmpyweh(Rss,Rtt) Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 566 -Rxx+=vrmpyweh(Rss,Rtt):<<1 Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt) 566 - -vrmpywoh -Rdd=vrmpywoh(Rss,Rtt) Word64 Q6_P_vrmpywoh_PP(Word64 Rss, Word64 Rtt) 566 -Rdd=vrmpywoh(Rss,Rtt):<<1 Word64 Q6_P_vrmpywoh_PP_s1(Word64 Rss, Word64 Rtt) 566 -Rxx+=vrmpywoh(Rss,Rtt) Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 566 -Rxx+=vrmpywoh(Rss,Rtt):<<1 Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt) 566 - -vrndwh -Rd=vrndwh(Rss) Word32 Q6_R_vrndwh_P(Word64 Rss) 604 -Rd=vrndwh(Rss):sat Word32 Q6_R_vrndwh_P_sat(Word64 Rss) 604 - -vrsadub -Rdd=vrsadub(Rss,Rtt) Word64 Q6_P_vrsadub_PP(Word64 Rss, Word64 Rtt) 457 -Rxx+=vrsadub(Rss,Rtt) Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 457 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 722 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -vsathb -Rd=vsathb(Rs) Word32 Q6_R_vsathb_R(Word32 Rs) 607 -Rd=vsathb(Rss) Word32 Q6_R_vsathb_P(Word64 Rss) 607 -Rdd=vsathb(Rss) Word64 Q6_P_vsathb_P(Word64 Rss) 610 - -vsathub -Rd=vsathub(Rs) Word32 Q6_R_vsathub_R(Word32 Rs) 607 -Rd=vsathub(Rss) Word32 Q6_R_vsathub_P(Word64 Rss) 607 -Rdd=vsathub(Rss) Word64 Q6_P_vsathub_P(Word64 Rss) 610 - -vsatwh -Rd=vsatwh(Rss) Word32 Q6_R_vsatwh_P(Word64 Rss) 607 -Rdd=vsatwh(Rss) Word64 Q6_P_vsatwh_P(Word64 Rss) 610 - -vsatwuh -Rd=vsatwuh(Rss) Word32 Q6_R_vsatwuh_P(Word64 Rss) 607 -Rdd=vsatwuh(Rss) Word64 Q6_P_vsatwuh_P(Word64 Rss) 610 - -vsplatb -Rd=vsplatb(Rs) Word32 Q6_R_vsplatb_R(Word32 Rs) 613 -Rdd=vsplatb(Rs) Word64 Q6_P_vsplatb_R(Word32 Rs) 613 - -vsplath -Rdd=vsplath(Rs) Word64 Q6_P_vsplath_R(Word32 Rs) 614 - -vspliceb -Rdd=vspliceb(Rss,Rtt,#u3) Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt, Word32 Iu3) 615 -Rdd=vspliceb(Rss,Rtt,Pu) Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte Pu) 615 - -vsubb -Rdd=vsubb(Rss,Rtt) Word64 Q6_P_vsubb_PP(Word64 Rss, Word64 Rtt) 460 - -vsubh -Rd=vsubh(Rt,Rs) Word32 Q6_R_vsubh_RR(Word32 Rt, Word32 Rs) 185 -Rd=vsubh(Rt,Rs):sat Word32 Q6_R_vsubh_RR_sat(Word32 Rt, Word32 Rs) 185 -Rdd=vsubh(Rtt,Rss) Word64 Q6_P_vsubh_PP(Word64 Rtt, Word64 Rss) 458 -Rdd=vsubh(Rtt,Rss):sat Word64 Q6_P_vsubh_PP_sat(Word64 Rtt, Word64 Rss) 458 - -vsubub -Rdd=vsubub(Rtt,Rss) Word64 Q6_P_vsubub_PP(Word64 Rtt, Word64 Rss) 460 -Rdd=vsubub(Rtt,Rss):sat Word64 Q6_P_vsubub_PP_sat(Word64 Rtt, Word64 Rss) 460 - -vsubuh -Rd=vsubuh(Rt,Rs):sat Word32 Q6_R_vsubuh_RR_sat(Word32 Rt, Word32 Rs) 185 -Rdd=vsubuh(Rtt,Rss):sat Word64 Q6_P_vsubuh_PP_sat(Word64 Rtt, Word64 Rss) 458 - -vsubw -Rdd=vsubw(Rtt,Rss) Word64 Q6_P_vsubw_PP(Word64 Rtt, Word64 Rss) 461 -Rdd=vsubw(Rtt,Rss):sat Word64 Q6_P_vsubw_PP_sat(Word64 Rtt, Word64 Rss) 461 - -vsxtbh -Rdd=vsxtbh(Rs) Word64 Q6_P_vsxtbh_R(Word32 Rs) 616 - - - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 723 - Hexagon V62 Programmer's Reference Manual Intrinsics Index - - - -vsxthw -Rdd=vsxthw(Rs) Word64 Q6_P_vsxthw_R(Word32 Rs) 616 - -vtrunehb -Rd=vtrunehb(Rss) Word32 Q6_R_vtrunehb_P(Word64 Rss) 619 -Rdd=vtrunehb(Rss,Rtt) Word64 Q6_P_vtrunehb_PP(Word64 Rss, Word64 Rtt) 619 - -vtrunewh -Rdd=vtrunewh(Rss,Rtt) Word64 Q6_P_vtrunewh_PP(Word64 Rss, Word64 Rtt) 619 - -vtrunohb -Rd=vtrunohb(Rss) Word32 Q6_R_vtrunohb_P(Word64 Rss) 619 -Rdd=vtrunohb(Rss,Rtt) Word64 Q6_P_vtrunohb_PP(Word64 Rss, Word64 Rtt) 619 - -vtrunowh -Rdd=vtrunowh(Rss,Rtt) Word64 Q6_P_vtrunowh_PP(Word64 Rss, Word64 Rtt) 619 - -vxaddsubh -Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt) 484 -Rdd=vxaddsubh(Rss,Rtt):sat Word64 Q6_P_vxaddsubh_PP_sat(Word64 Rss, Word64 Rtt) 484 - -vxaddsubw -Rdd=vxaddsubw(Rss,Rtt):sat Word64 Q6_P_vxaddsubw_PP_sat(Word64 Rss, Word64 Rtt) 486 - -vxsubaddh -Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt) 484 -Rdd=vxsubaddh(Rss,Rtt):sat Word64 Q6_P_vxsubaddh_PP_sat(Word64 Rss, Word64 Rtt) 484 - -vxsubaddw -Rdd=vxsubaddw(Rss,Rtt):sat Word64 Q6_P_vxsubaddw_PP_sat(Word64 Rss, Word64 Rtt) 486 - -vzxtbh -Rdd=vzxtbh(Rs) Word64 Q6_P_vzxtbh_R(Word32 Rs) 621 - -vzxthw -Rdd=vzxthw(Rs) Word64 Q6_P_vzxthw_R(Word32 Rs) 621 - -X -xor -Pd=xor(Ps,Pt) Byte Q6_p_xor_pp(Byte Ps, Byte Pt) 222 -Rd=xor(Rs,Rt) Word32 Q6_R_xor_RR(Word32 Rs, Word32 Rt) 173 -Rdd=xor(Rss,Rtt) Word64 Q6_P_xor_PP(Word64 Rss, Word64 Rtt) 398 -Rx^=xor(Rs,Rt) Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) 401 -Rx&=xor(Rs,Rt) Word32 Q6_R_xorand_RR(Word32 Rx, Word32 Rs, Word32 Rt) 401 -Rx|=xor(Rs,Rt) Word32 Q6_R_xoror_RR(Word32 Rx, Word32 Rs, Word32 Rt) 402 -Rxx^=xor(Rss,Rtt) Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) 400 - -Z -zxtb -Rd=zxtb(Rs) Word32 Q6_R_zxtb_R(Word32 Rs) 187 - -zxth -Rd=zxth(Rs) Word32 Q6_R_zxth_R(Word32 Rs) 187 - - -80-N2040-36 B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 724 - diff --git a/DuplexInstruction.py b/DuplexInstruction.py new file mode 100644 index 00000000..4457b182 --- /dev/null +++ b/DuplexInstruction.py @@ -0,0 +1,627 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import re +from enum import IntEnum + +import HexagonArchInfo +import PluginInfo +from Immediate import Immediate +from ImplementationException import ImplementationException +from Instruction import PredicateInfo, LoopMembership +from InstructionEncoding import InstructionEncoding +from InstructionTemplate import InstructionTemplate +from Operand import Operand, OperandType +from Register import Register +from SubInstruction import SubInstruction, SubInstrNamespace +from UnexpectedException import UnexpectedException +from helperFunctions import log, LogLevel, list_to_int, normalize_llvm_syntax +from copy import deepcopy + + +class DuplexIClass(IntEnum): + DuplexIClass0 = 0 + DuplexIClass1 = 1 + DuplexIClass2 = 2 + DuplexIClass3 = 3 + DuplexIClass4 = 4 + DuplexIClass5 = 5 + DuplexIClass6 = 6 + DuplexIClass7 = 7 + DuplexIClass8 = 8 + DuplexIClass9 = 9 + DuplexIClassA = 10 + DuplexIClassB = 11 + DuplexIClassC = 12 + DuplexIClassD = 13 + DuplexIClassE = 14 + DuplexIClassF = 15 + INVALID = -1 + + +class DuplexInstruction(InstructionTemplate): + """Class represents a Duplex instruction. It is constructed out of two Sub instructions.""" + + def __init__( + self, llvm_duplex_instr: dict, low: SubInstruction, high: SubInstruction + ): + if llvm_duplex_instr["!name"] == "DuplexIClassF": + raise ImplementationException("DuplexIClassF was reserved in the past.") + super(DuplexInstruction, self).__init__(llvm_duplex_instr) + # Qualcomm naming as in hexagon_iset_v5.h + self.name = "X2_AUTOJOIN_" + high.name.upper() + "_" + low.name.upper() + self.plugin_name = PluginInfo.INSTR_ENUM_PREFIX + self.name + self.duplex_type = llvm_duplex_instr["!name"] + self.constraints = high.constraints + " " + low.constraints + + # deepcopy() take much longer, but at least doesn't mess up our parsing algorithms + self.low_instr = deepcopy(low) + self.high_instr = deepcopy(high) + + self.is_duplex = True + self.encoding = self.combine_encodings() + self.update_syntax() + + # Order matters! + self.llvm_in_operands = ( + self.high_instr.llvm_in_operands + self.low_instr.llvm_in_operands + ) + # Order matters! + self.llvm_out_operands = ( + self.high_instr.llvm_out_operands + self.low_instr.llvm_out_operands + ) + # Order matters! + self.llvm_in_out_operands = ( + self.high_instr.llvm_out_operands + + self.high_instr.llvm_in_operands + + self.low_instr.llvm_out_operands + + self.low_instr.llvm_in_operands + ) + + # Predicates + self.set_duplex_predicate_info() + + # Register new values + self.set_register_new_values() + + # Set loop info + self.set_loop_info() + + # Immediate values + self.set_immediate_values() + + self.parse_instruction() + + self.check_for_operand_duplicates() + # log(self.syntax + "\n" + self.encoding.docs_mask, LogLevel.DEBUG) + + def parse_instruction(self) -> None: + """Parses all operands of the instruction which are encoded.""" + + # TODO A lot of duplicate code with Instruction::parse:instruction() + # Operand names seen during parsing the encoding. Twin operands (Operands which appear in high and low instr.) + # were renamed. + + all_ops = deepcopy( + self.high_instr.llvm_in_out_operands + self.low_instr.llvm_in_out_operands + ) + self.llvm_filtered_operands = self.remove_invisible_in_out_regs( + self.llvm_syntax, all_ops + ) + self.operand_indices = self.get_syntax_operand_indices( + self.llvm_syntax, self.llvm_filtered_operands + ) + + # Update syntax indices + if self.has_new_non_predicate: + op_name = self.llvm_in_out_operands[self.new_operand_index][1] + self.new_operand_index = self.operand_indices[op_name] + # log("{}\n new: {}".format(self.llvm_syntax, self.new_operand_index), LogLevel.DEBUG) + if self.has_extendable_imm: + op_name = self.llvm_in_out_operands[self.ext_operand_index][1] + self.ext_operand_index = self.operand_indices[op_name] + # log("{}\n ext: {}".format(self.llvm_syntax, self.ext_operand_index), LogLevel.DEBUG) + + if len(self.llvm_filtered_operands) > PluginInfo.MAX_OPERANDS: + warning = "{} instruction struct can only hold {} operands. This instruction has {} operands.".format( + PluginInfo.FRAMEWORK_NAME, + PluginInfo.MAX_OPERANDS, + len(self.llvm_filtered_operands), + ) + raise ImplementationException(warning) + + for in_out_operand in self.llvm_filtered_operands: + op_name = in_out_operand[1] + op_type = in_out_operand[0]["def"] + index = self.operand_indices[op_name] + + # Parse register operand + if Operand.get_operand_type(op_type) is OperandType.REGISTER: + # Indices of new values (stored in "opNewValue") are only for non predicates. + is_new_value = ( + self.new_operand_index == index and self.has_new_non_predicate + ) + operand = Register(op_name, op_type, is_new_value, index) + # Whether the predicate registers holds a new value is denoted in "isPredicatedNew". + if self.predicate_info.new_value and operand.is_predicate: + operand.is_new_value = True + + # Parse immediate operands + elif Operand.get_operand_type(op_type) is OperandType.IMMEDIATE: + extendable = self.has_extendable_imm and self.ext_operand_index == index + if self.extendable_alignment > 0: + log(str(self.extendable_alignment), op_type) + operand = Immediate( + op_name, op_type, extendable, self.extendable_alignment, index + ) + + else: + raise ImplementationException( + "Unknown operand type: {}, op_name: {}".format(op_type, op_name) + ) + + # Use lower() because we can get RX16in and Rx16in but constraints are always Rx16in. + if op_name.lower() in self.constraints.lower(): + operand.is_in_out_operand = True + operand.is_out_operand = True + operand.is_in_operand = True + elif in_out_operand in self.llvm_in_operands: + operand.is_in_operand = True + elif in_out_operand in self.llvm_out_operands: + operand.is_out_operand = True + + # Add opcode extraction code + if ( + operand.type == OperandType.IMMEDIATE and operand.is_constant + ): # Constants have no parsing code. + pass + else: + if ( + operand.is_in_out_operand and op_name[-2:] == "in" + ): # In/Out Register + mask = self.encoding.operand_masks[op_name[:-2]] # Ends with "in" + else: + mask = self.encoding.operand_masks[op_name] + operand.opcode_mask = mask + operand.add_code_for_opcode_parsing(Operand.make_sparse_mask(mask)) + + # On the fly check whether the new values have been assigned correctly. + if op_name + ".new" in self.llvm_syntax: + if not operand.is_new_value: + raise ImplementationException( + "Register has new value in syntax but not as object." + + "It has been parsed incorrectly! Are the indices correctly set?" + + "Affected instruction: {}".format(self.llvm_syntax) + ) + + # log("Add operand: {}".format(op_name), LogLevel.DEBUG) + # TODO This uses the llvm name as key. Maybe use normalized name? Rs16 -> Rs? + self.operands[op_name] = operand + + @staticmethod + def get_duplex_i_class_of_instr_pair( + low: SubInstruction, high: SubInstruction + ) -> DuplexIClass: + """Mapping of sub instruction pairs to its Duplex class. + Src: llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonDisassembler.cpp::getSingleInstruction() + + Args: + low: Low sub-instruction + high: High sub-instruction + + Returns: The Duplex class or the invalid duplex class if the instruction combination is not allowed. + + """ + if ( + low.namespace == SubInstrNamespace.SUBINSN_L1 + and high.namespace == SubInstrNamespace.SUBINSN_L1 + ): + return DuplexIClass.DuplexIClass0 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_L2 + and high.namespace == SubInstrNamespace.SUBINSN_L1 + ): + return DuplexIClass.DuplexIClass1 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_L2 + and high.namespace == SubInstrNamespace.SUBINSN_L2 + ): + return DuplexIClass.DuplexIClass2 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_A + and high.namespace == SubInstrNamespace.SUBINSN_A + ): + return DuplexIClass.DuplexIClass3 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_L1 + and high.namespace == SubInstrNamespace.SUBINSN_A + ): + return DuplexIClass.DuplexIClass4 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_L2 + and high.namespace == SubInstrNamespace.SUBINSN_A + ): + return DuplexIClass.DuplexIClass5 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_S1 + and high.namespace == SubInstrNamespace.SUBINSN_A + ): + return DuplexIClass.DuplexIClass6 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_S2 + and high.namespace == SubInstrNamespace.SUBINSN_A + ): + return DuplexIClass.DuplexIClass7 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_S1 + and high.namespace == SubInstrNamespace.SUBINSN_L1 + ): + return DuplexIClass.DuplexIClass8 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_S1 + and high.namespace == SubInstrNamespace.SUBINSN_L2 + ): + return DuplexIClass.DuplexIClass9 + elif ( + low.namespace == SubInstrNamespace.SUBINSN_S1 + and high.namespace == SubInstrNamespace.SUBINSN_S1 + ): + return DuplexIClass.DuplexIClassA + elif ( + low.namespace == SubInstrNamespace.SUBINSN_S2 + and high.namespace == SubInstrNamespace.SUBINSN_S1 + ): + return DuplexIClass.DuplexIClassB + elif ( + low.namespace == SubInstrNamespace.SUBINSN_S2 + and high.namespace == SubInstrNamespace.SUBINSN_L1 + ): + return DuplexIClass.DuplexIClassC + elif ( + low.namespace == SubInstrNamespace.SUBINSN_S2 + and high.namespace == SubInstrNamespace.SUBINSN_L2 + ): + return DuplexIClass.DuplexIClassD + elif ( + low.namespace == SubInstrNamespace.SUBINSN_S2 + and high.namespace == SubInstrNamespace.SUBINSN_S2 + ): + return DuplexIClass.DuplexIClassE + # DuplexIClassF is reserved + else: + return DuplexIClass.INVALID + + @staticmethod + def fulfill_constraints(low: SubInstruction, high: SubInstruction) -> bool: + """Sub-Instructions in a duplex instr have to fulfill some constraints, all of which are checked here. + Src: llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp::isOrderedDuplexPair + """ + + if not HexagonArchInfo.duplex_constrains_info_shown: + log( + "Checked Duplex constraints:" + + "\n\t- Max. one extendable sub instruction per duplex." + + "\n\t- Extendable instruction in slot 1 (high)." + + "\n\t- Same sub type: smaller instruction in slot 1 (high)." + + "\n\t- SL2_jumpr31 never in slot 1 (high)." + + "\n\t- S2_allocframe never in slot 1 (high).", + LogLevel.INFO, + ) + HexagonArchInfo.duplex_constrains_info_shown = True + + # Max. one extendable sub instruction per duplex. + # Extendable instruction in slot 1 (high) + if low.has_extendable_imm: + # log("low: {}, high: {} rejected because: low is extendable.".format( + # low.name, high.name), LogLevel.DEBUG) + return False + + # Same sub namespace (A, S1, S2, L1, L2...): smaller instruction in slot 1 (high) + if low.namespace == high.namespace: + if low.encoding.num_representation < high.encoding.num_representation: + # log("low: {}, high: {} rejected because: type is same but numerically smaller value is high.".format( + # low.name, high.name), LogLevel.DEBUG) + return False + + # SL2_jumpr31[...] never in slot 1 (high) + if "SL2_jumpr31" in high.name: + # log("low: {}, high: {} rejected because: SL2_jumpr31 is in slot 1.".format( + # low.name, high.name), LogLevel.DEBUG) + return False + + # S2_allocframe never in slot 1 (high). + if "SS2_allocframe" in high.name: + # log("low: {}, high: {} rejected because: S2_allocframe is in slot 1.".format( + # low.name, high.name), LogLevel.DEBUG) + return False + + return True + + def combine_encodings(self) -> InstructionEncoding: + """Combines the encoding of two sub instruction into one.""" + + encoding = list([0]) * 32 + for i in range(32): + if i < 13: # Set bit 12:0 + encoding[i] = self.low_instr.encoding.llvm_encoding[i] + elif i in range(16, 29): # Set bit 28:16 + encoding[i] = self.high_instr.encoding.llvm_encoding[i - 16] + elif i in [14, 15]: # Parse bits are 0 in a duplex instruction. + encoding[i] = 0 + + # Set IClass + i_class = DuplexIClass[self.duplex_type] + encoding[13] = i_class & 1 + encoding[31] = (i_class >> 3) & 1 + encoding[30] = (i_class >> 2) & 1 + encoding[29] = (i_class >> 1) & 1 + enc = InstructionEncoding(self.correct_operand_names_in_encoding(encoding)) + # log("Name: {}\n\tDuplex: {}\n\tSubLow: {}\n\tSubHigh: {}\n\tIClass: {}".format( + # self.name, + # enc.docs_mask, + # self.low_instr.encoding.docs_mask, + # self.high_instr.encoding.docs_mask, + # bin(i_class) + # ), LogLevel.DEBUG) + return enc + + def correct_operand_names_in_encoding(self, encoding_bits: list) -> list: + """The generated duplex instructions can have multiple operands with the same name + (e.g. high and low have both a Rs register). + Here we change the name so it does not make problems in the following parsing. + + Note: Here we change the name _only_ in the encoding. Not in the syntax pr the self.operands field! + """ + # Tracks all placeholder chars used by registers immediate values: d, s, t, i etc. + low_op_chars = list() + + for i in range(0, 32): + bit = encoding_bits[i] + if isinstance(bit, dict): + name = encoding_bits[i]["var"] + char = re.search(r"[IR]([dstxi])", name).group(1) + if char not in low_op_chars and i < 14: + low_op_chars.append(char) + elif char in low_op_chars and i < 14: # Still in lower instr. + continue + elif ( + char in low_op_chars and i > 14 + ): # Operand with same name as in the lower instr. + encoding_bits[i]["var_old"] = bit["var"] # Backup name + + if re.search(r"R([dstx]{1,2})\d+", name): # Register duplicate + pat = re.search(r"R([dstx]{1,2})\d+", name).group(1) + # TODO They use u and e to replace d and s letters. See: hexagon_iset_v5.h + replacement = pat.upper() + new_name = re.sub(pat, replacement, name) + elif re.search(r"I([i]{1,2})", name): # Immediate duplicate + pat = re.search(r"I([i]{1,2})", name).group(1) + replacement = pat.upper() + new_name = re.sub(pat, replacement, name) + else: + raise ImplementationException( + "Unhandled double occurrence of operand" + + " in Duplex instruction. Operand name: {} in {}".format( + name, self.high_instr.llvm_syntax + ) + ) + if new_name in low_op_chars: + raise ImplementationException( + "New operand is already present in the low instruction: {}" + + "Please fix this method by inventing a new operand name" + + "(Ii -> Il or Rs -> Re maybe?)".format(new_name) + ) + + encoding_bits[i]["var"] = new_name + encoding_bits[i]["printable"] = re.sub( + name, new_name, encoding_bits[i]["printable"] + ) + return encoding_bits + + def update_syntax(self) -> None: + """If the low and high instructions share an operand name (e.g. both have the register Rs in their syntax), + the operand name of the high instruction has been replaced in its encoding (Rs -> RS etc.). + Here we update the operand name in the syntax. + """ + + ops = ( + self.high_instr.llvm_instr["OutOperandList"]["args"] + + self.high_instr.llvm_instr["InOperandList"]["args"] + ) + operands = self.correct_not_encoded_operands(ops) + + new_high_llvm_syntax = self.high_instr.llvm_syntax + for i in range(0, 32): + bit = self.encoding.llvm_encoding[i] + # Key "var_old" is only present in the variable bit, if the name has been replaced. + if isinstance(bit, dict) and "var_old" in bit: + if re.search(bit["var_old"], new_high_llvm_syntax): + # Update the syntax + new_high_llvm_syntax = re.sub( + bit["var_old"], bit["var"], new_high_llvm_syntax + ) + + # Update operand name in the In/OutOperands object + for op in operands: + if op[1] == bit["var_old"]: + op[1] = bit["var"] + elif re.search(bit["var"], new_high_llvm_syntax): # Already replaced + continue + else: + raise UnexpectedException( + "{} not in syntax {}".format( + bit["var_old"], new_high_llvm_syntax + ) + ) + + if new_high_llvm_syntax != self.high_instr.llvm_syntax: + # log("Changed syntax: {} -> {}\n\t{}".format(self.high_instr.llvm_syntax, + # new_high_llvm_syntax, self.encoding.llvm_encoding), + # LogLevel.DEBUG) + self.high_instr.llvm_syntax = new_high_llvm_syntax + self.high_instr.syntax = normalize_llvm_syntax(self.high_instr.llvm_syntax) + self.llvm_syntax = ( + self.high_instr.llvm_syntax + " ; " + self.low_instr.llvm_syntax + ) + self.syntax = normalize_llvm_syntax(self.llvm_syntax) + + def correct_not_encoded_operands(self, llvm_high_operands: list) -> list: + """Constant immediate values are not encoded in the instruction but can occur in the low and high syntax. + + Therefore they are not renamed in correct_operand_names_in_encoding(). + Here we rename those constant operands (n1 -> N1) and update the syntax. + Same for Rx16in register. + """ + for op in llvm_high_operands: + name = op[1] + printable = op[0]["printable"] + if op[0]["def"][-5:] != "Const" and name[-2:] != "in": + continue + if ( + name in self.high_instr.llvm_syntax + and name in self.low_instr.llvm_syntax + ): + if name[-2:] == "in": + # The "in" should stay lower case. Therefore [:-2] + op[0]["printable"] = re.sub( + name[:-2], name[:-2].upper(), op[0]["printable"] + ) + op[1] = name[:-2].upper() + "in" + self.high_instr.llvm_syntax = re.sub( + name, op[1], self.high_instr.llvm_syntax + ) + elif op[0]["def"][-5:] == "Const": + op[0]["printable"] = re.sub( + printable[:-5], printable[:-5].upper(), printable + ) + op[1] = name.upper() + self.high_instr.llvm_syntax = re.sub( + name, op[1].upper(), self.high_instr.llvm_syntax + ) + else: + raise ImplementationException( + "Could not parse not encoded operand." + ) + # log("Update syntax with double constants: {}".format(self.high_instr.llvm_syntax), LogLevel.DEBUG) + return llvm_high_operands + + def check_for_operand_duplicates(self) -> None: + """Runtime check for duplicates of operand names (from self.operands) in the syntax.""" + + for op_name in self.operands.keys(): + c = self.llvm_syntax.count(op_name) + if op_name + "in" in self.llvm_syntax: + c -= 1 + if c != 1: + raise UnexpectedException( + "Operand has to appear exactly once in the syntax.\n" + + "{} appeared {} times.\nSyntax: {}\nOperands: {}".format( + op_name, c, self.llvm_syntax, self.operands + ) + ) + + def set_duplex_predicate_info(self): + """Sets the duplex instruction predicate info according to its sub instructions.""" + + low = self.low_instr + high = self.high_instr + + if low.llvm_instr["isPredicated"] == 1 and high.llvm_instr["isPredicated"] == 1: + raise ImplementationException( + "Both sub-instructions are predicated: {} ; {}".format( + low.llvm_syntax, high.llvm_syntax + ) + ) + self.predicated = ( + low.llvm_instr["isPredicated"] == 1 or high.llvm_instr["isPredicated"] == 1 + ) + if low.llvm_instr["isPredicated"] == 1: + self.predicate_info = PredicateInfo(low.llvm_instr) + elif high.llvm_instr["isPredicated"] == 1: + self.predicate_info = PredicateInfo(high.llvm_instr) + else: + self.predicate_info = PredicateInfo( + self.llvm_instr + ) # Duplex llvm instructions are empty. + + def set_register_new_values(self): + """Sets the duplex instruction register flags according to its sub instructions.""" + + low = self.low_instr + high = self.high_instr + + if low.has_new_non_predicate and high.has_new_non_predicate: + raise UnexpectedException( + "Both sub instructions have new values: {} ; {}".format( + low.llvm_syntax, high.llvm_syntax + ) + ) + + if low.has_new_non_predicate: + self.has_new_non_predicate = True + self.new_operand_index = low.new_operand_index + high.num_operands + elif high.has_new_non_predicate: + self.has_new_non_predicate = True + self.new_operand_index = high.new_operand_index + else: + self.has_new_non_predicate = False + self.new_operand_index = 0 + + def set_immediate_values(self): + """Sets the duplex instruction immediate flags according to its sub instructions.""" + + low = self.low_instr + high = self.high_instr + + if low.has_extendable_imm and high.has_extendable_imm: + raise UnexpectedException( + "Both sub instructions have extendable immediate values: {} ; {}".format( + low.llvm_syntax, high.llvm_syntax + ) + ) + + if low.has_extendable_imm: # Should never occur + raise UnexpectedException( + "Low sub-instructions should not contain extendable values." + ) + # self.has_extendable_imm = True + # self.must_be_extended = low.must_be_extended + # self.ext_operand_index = low.ext_operand_index + high.num_operands + # self.extendable_alignment = low.extendable_alignment + elif high.has_extendable_imm: + self.has_extendable_imm = True + self.must_be_extended = high.must_be_extended + self.ext_operand_index = high.ext_operand_index + self.extendable_alignment = high.extendable_alignment + else: + self.has_extendable_imm = False + self.must_be_extended = False + self.ext_operand_index = 0 + self.extendable_alignment = 0 + + def set_loop_info(self): + """Sets the duplex instruction loop info according to its sub instructions.""" + + self.loop_member = LoopMembership.HEX_NO_LOOP + self.is_loop_begin = False + self.is_endloop = False + self.is_loop = False + if ( + self.high_instr.loop_member != LoopMembership.HEX_NO_LOOP + and self.low_instr.loop_member != LoopMembership.HEX_NO_LOOP + ): + raise ImplementationException( + "Loop instructions in high and low sub instructions are not implemented." + ) + + if self.high_instr.loop_member != LoopMembership.HEX_NO_LOOP: + self.is_loop = self.high_instr.is_loop + self.is_endloop = self.high_instr.is_endloop + self.is_loop_begin = self.high_instr.is_loop_begin + self.loop_member = self.high_instr.loop_member + elif self.low_instr.loop_member != LoopMembership.HEX_NO_LOOP: + self.is_loop = self.low_instr.is_loop + self.is_endloop = self.low_instr.is_endloop + self.is_loop_begin = self.low_instr.is_loop_begin + self.loop_member = self.low_instr.loop_member diff --git a/HardwareRegister.py b/HardwareRegister.py new file mode 100644 index 00000000..b33afa2b --- /dev/null +++ b/HardwareRegister.py @@ -0,0 +1,130 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import re + +import HexagonArchInfo +import PluginInfo +from ImplementationException import ImplementationException +from Register import Register +from helperFunctions import list_to_int + + +class HardwareRegister(Register): + """Represents a concrete Hexagon hardware register. Like R13, C17, V4 etc.""" + + def __init__(self, llvm_reg_class: str, llvm_object: dict, name: str, size: int): + index = list_to_int(llvm_object["HWEncoding"], endian="little") + # We use the super class only to set all the register type flags. + super().__init__( + llvm_syntax=name, + llvm_reg_class=llvm_reg_class, + index=index, + is_new_value=False, + ) + self.name: str = name + self.enum_name = ( + PluginInfo.REGISTER_ENUM_PREFIX + + HardwareRegister.register_class_name_to_upper(llvm_reg_class) + + "_" + + self.name + ) + self.alias = llvm_object["AltNames"] + self.asm_name = llvm_object["AsmName"] + self.hw_encoding = index + self.size: int = size if not self.is_vector else size * 2 + self.sub_register_names: list = [ + r["def"] + for r in llvm_object["SubRegs"] + if r["def"] not in HexagonArchInfo.LLVM_FAKE_REGS + ] + + # RIZIN SPECIFIC + @staticmethod + def get_func_name_of_class(reg_class: str) -> str: + """Generates the function name for register name retrieval in the disassembler code.""" + reg_func = HardwareRegister.register_class_name_to_upper(reg_class).lower() + code = PluginInfo.GENERAL_ENUM_PREFIX.lower() + "get_" + reg_func + return code + + # RIZIN SPECIFIC + @staticmethod + def get_parse_code_reg_bits(reg_class: str, var: str) -> str: + """Sub register bits are encoded in a space saving way in the instruction encoding. + So we need to shift the bits around before we get the register ID. Here we generate the code for that. + """ + indent = PluginInfo.LINE_INDENT + code = "" + if ( + reg_class == "CtrRegs64" + or reg_class == "DoubleRegs" + or reg_class == "GuestRegs64" + or reg_class == "HvxVQR" + ): + # TODO Assumption: test with actual disassembly + # GuestRegs64 -> OK + # DoubleRegs -> OK + # CtrRegs64 -> MIXED (Missing regs in llvm) C21:20 - C29:28. But they follow the parsing pattern. + # HvxVQR -> FAILS Public HexagonSDK does not support those instructions yet. + # code += "{v} = {v};\n".format(v=var) + pass + elif reg_class == "GeneralDoubleLow8Regs": + code += "{v} = {v} << 1;\n".format(v=var) + code += "if ({} > 6) {{ // HEX_REG_D3 == 6\n".format(var) + code += "{}{} = ({} & 0x7) | 0x10;\n}}".format(indent, var, var) + pass + elif reg_class == "GeneralSubRegs": + code += "if ({} > 7) {{ // HEX_REG_R7 == 7\n".format(var) + code += "{}{} = ({} & 0x7) | 0x10;\n}}".format(indent, var, var) + return code + elif reg_class == "VectRegRev": + # TODO Assumption: test with actual disassembly + # No instructions in LLVM found yet. + # Public HexagonSDK does not support those instructions yet. + code += "{v} = ({v} << 1) + 1;\n".format(v=var) + elif reg_class == "ModRegs": + # ModRegs are effectively control registers. M0 = C6, M1 = C7 + code += "{} |= 6;\n".format(var) + return code + + # RIZIN SPECIFIC + def get_reg_profile(self, offset: int) -> str: + """Returns a one line register profile description. + + Parameters: + offset: The offset into the memory where the register bits are stored. + returns: "type name size mem-offset packed-size" + """ + indent = PluginInfo.LINE_INDENT + return '"{t}{i}{n}{i}.{s}{i}{o}{i}0\\n"'.format( + t=self.get_rz_reg_type(), + n=self.asm_name.lower(), + s=self.size, + o=str(offset), + i=indent, + ) + + # RIZIN SPECIFIC + def get_rz_reg_type(self) -> str: + return "gpr" + # if self.is_vector: + # return "vcr" + # elif self.is_control: + # return "ctr" + # elif self.is_general: + # return "gpr" + # elif self.is_guest: + # return "gst" + # else: + # raise ImplementationException("Rizin has no register type for the register {}".format(self.llvm_type)) + + @staticmethod + def register_class_name_to_upper(s: str) -> str: + """Separates words by an '_' and sets them upper case: IntRegsLow8 -> INT_REGS_LOW8""" + matches = re.findall(r"[A-Z][a-z0-9]+", s) + for match in matches: + s = re.sub(match, match.upper() + "_", s) + if s[-1] == "_": + s = s[:-1] + return s diff --git a/HexagonArchInfo.py b/HexagonArchInfo.py new file mode 100644 index 00000000..344381d9 --- /dev/null +++ b/HexagonArchInfo.py @@ -0,0 +1,18 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +ALL_REG_NAMES = list() # R0, ..., R30, R31, ..., C3, C1_0, ..., UPCYCLELO, VFR0, ... +LLVM_FAKE_REGS = list() +CALLEE_SAVED_REGS = list() +CC_REGS = ( + dict() +) # The register used in the calling convention. Argument and return regs. + +INSTRUCTION_LENGTH = 32 + +IMMEDIATE_TYPES = dict() +REG_CLASS_NAMES = dict() + +MAX_IMM_LEN = 32 +duplex_constrains_info_shown = False diff --git a/Immediate.py b/Immediate.py new file mode 100644 index 00000000..839b2be7 --- /dev/null +++ b/Immediate.py @@ -0,0 +1,202 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import re + +from bitarray import bitarray + +import HexagonArchInfo +import PluginInfo +from Operand import Operand +from ImplementationException import ImplementationException +from UnexpectedException import UnexpectedException +from helperFunctions import log, LogLevel + + +class Immediate(Operand): + """ + The immediates stored on the instruction encoding have a smaller bit size than + usually needed. The immediate gets extended by the processor. In the syntax + this is denoted by a apply_extention(x). + + + Args: + syntax_index (int): The index of the immediate in the syntax. + + scale (int): Immediates which will always have a value equal to some power of 2 + can be shifted to the right before they are encoded into the instruction + (which safes space). scale stores the number of bits the immediate has + to be shifted to the left before it is used. + """ + + __slots__ = [ + "scale", + "type", + "syntax", + "is_signed", + "is_extendable", + "extend_alignment", + "is_pc_relative", + "encoding_width", + "total_width", + "is_constant", + ] + + def __init__( + self, + llvm_syntax: str, + llvm_type: str, + is_extendable: bool, + extend_alignment: int, + syntax_index: int, + ): + super(Immediate, self).__init__(llvm_syntax, llvm_type, syntax_index) + self.is_signed = False + self.is_constant = False + + self.is_extendable = is_extendable + self.extend_alignment = extend_alignment # Extended immediate values are not scaled. But sometimes aligned. + self.is_pc_relative = False + + self.scale = 0 # Num bits shifted to the left. Is set to 0 if the immediate is extendable. + self.encoding_width = 0 # Num. bits stored in encoding. + self.total_width = 0 + + self.parse_imm_type(llvm_type) + + def parse_imm_type(self, llvm_imm_type: str) -> None: + """Parse immediate types like: u4_2Imm. This method sets all kinds of flags, the scale and total width.""" + type_letter = re.search(r"^([a-z]+)\d{1,2}", llvm_imm_type) + if not type_letter: + raise ImplementationException( + "Unhandled immediate type: {}".format(llvm_imm_type) + ) + else: + type_letter = type_letter.group(1) + + if type_letter == "s": + self.is_signed = True + elif type_letter == "u": + self.is_signed = False + # Address used in "call" and "jmp" instructions (a for call, b for jmp) is relative to PC. + elif type_letter == "a" or type_letter == "b": + self.is_signed = True + self.is_pc_relative = True + # Constant value -1 + elif type_letter == "n": + self.is_signed = True + self.is_constant = True + self.encoding_width = None # Is not encoded in the llvm instruction + width = re.search(r"[a-z](\d+)", llvm_imm_type) + if not width: + raise ImplementationException( + "Unhandled immediate type: {}".format(llvm_imm_type) + ) + else: + self.total_width = width.group(1) + self.is_extendable = False + # log("Parsed imm type: {}, width: {}".format(imm_type, self.total_width), LogLevel.DEBUG) + return + else: + raise ImplementationException( + "Unhandled immediate type: {}".format(llvm_imm_type) + ) + + # Value before _ represents number of encoded bits. + result = re.search(r"[a-z](\d+)\_", llvm_imm_type) + if result: + self.encoding_width = int(result.group(1)) + else: + raise ImplementationException( + "Could not parse encoding width of immediate type: {}".format( + llvm_imm_type + ) + ) + + # Value after the _ represents tells how often the immediate has to be shifted. + result = re.search(r"\_(\d+)Imm", llvm_imm_type) + if result: + self.scale = int(result.group(1)) + else: + raise ImplementationException( + "Could not find parse scale of immediate type: {}".format(llvm_imm_type) + ) + + self.total_width = self.encoding_width + self.scale + mx = HexagonArchInfo.MAX_IMM_LEN + nw = int((self.total_width - mx) / 4) + if self.total_width > mx: + log( + "Rizins hexagon_disas.c assumes that immediate values are not larger than {}bit.\n".format( + mx + ) + + "\tImmediate type: {} is {}bits long.\n".format( + self.llvm_type, self.total_width + ) + + "\tPlease increase the buffer hexagon_disas.c::signed_imm by at least {} bits.".format( + nw + ), + LogLevel.WARNING, + ) + + # The extended immediate should have always the op_type of a 32/64bit wide immediate. + if self.is_extendable and not ( + self.total_width == 32 or self.total_width == 64 + ): + raise UnexpectedException( + "Extendable immediate is not 32 or 64bits long!\n" + + "imm: {}".format(self.llvm_syntax) + ) + + # RIZIN SPECIFIC + def add_code_for_opcode_parsing(self, parsing_code: str) -> None: + """Overrides method of parent class. Here we add code which does specific parsing of the operand value on + disassembly. + If the immediate is scaled, has specific attributes or gets extended, the c code for this is added here. + """ + if self.is_constant: + return + + indent = PluginInfo.LINE_INDENT + self.code_opcode_parsing = parsing_code + if self.scale > 0: + self.code_opcode_parsing += " << {}; // scaled {}\n".format( + self.scale, self.llvm_syntax + ) + self.code_opcode_parsing += ( + "{}hi->ops[{}].attr = HEX_OP_IMM_SCALED;\n".format( + indent, self.syntax_index + ) + ) + self.code_opcode_parsing += "{}hi->ops[{}].shift = {};\n".format( + indent, self.syntax_index, self.scale + ) + else: + self.code_opcode_parsing += "; // {}\n".format(self.llvm_syntax) + + if self.is_signed: + op_bits = self.opcode_mask.count(1) + if op_bits <= 0: + raise ImplementationException( + "The bits encoding the immediate value should never be <= 0!\n" + "Operand type: {}, Mask: {}".format( + self.llvm_type, str(self.opcode_mask) + ) + ) + shift = (op_bits if self.scale <= 0 else op_bits + self.scale) - 1 + self.code_opcode_parsing += ( + "{}if (hi->ops[{}].op.imm & (1 << {})) {{ // signed\n".format( + indent, self.syntax_index, shift + ) + ) + self.code_opcode_parsing += ( + "{}{}hi->ops[{}].op.imm |= (0xffffffff << {});\n{}}}\n".format( + indent, indent, self.syntax_index, shift, indent + ) + ) + + if self.is_extendable: + self.code_opcode_parsing += "{}hex_op_extend(&(hi->ops[{}]), false); // Extension possible\n".format( + indent, self.syntax_index + ) diff --git a/ImplementationException.py b/ImplementationException.py new file mode 100644 index 00000000..4cf781ea --- /dev/null +++ b/ImplementationException.py @@ -0,0 +1,13 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + + +class ImplementationException(NotImplementedError): + def __init__(self, message): + message = ( + "\n\n" + + message + + "\nPlease update the implementation to cover this yet unknown case." + ) + super().__init__(message) diff --git a/Instruction.py b/Instruction.py new file mode 100644 index 00000000..52f605bb --- /dev/null +++ b/Instruction.py @@ -0,0 +1,255 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +from copy import deepcopy +from enum import IntFlag + +from Immediate import Immediate +from ImplementationException import ImplementationException +from InstructionTemplate import InstructionTemplate +from Operand import Operand, OperandType +from InstructionEncoding import InstructionEncoding +from Register import Register +from helperFunctions import * + + +class LoopMembership(IntFlag): + HEX_NO_LOOP = 0 + HEX_LOOP_0 = 1 + HEX_LOOP_1 = 2 + HEX_ENDS_LOOP_0 = 4 + HEX_ENDS_LOOP_1 = 8 + + +class Instruction(InstructionTemplate): + """ + Definition of the instruction with the maximum processing done before being used for disassembly. + """ + + __slots__ = [ + "encoding", + "llvm_instr", + "i_class", + "is_imm_ext", + "llvm_filtered_operands", + "mult_inst", + "is_duplex", + "duplex_type", + "imm_ops", + "reg_ops", + "opt_ops", + "branch", + "behavior", + "tokens", + "name", + "type", + "syntax", + "llvm_syntax", + "predicated", + "predicate_info", + "llvm_filtered_operands", + "is_sub_instruction", + "has_extendable_imm", + "llvm_ext_operand_index", + "must_be_extended", + "extendable_alignment", + "is_solo", + "addr_mode", + "access_size", + "has_new_non_predicate", + "llvm_new_operand_index", + ] + + def __init__(self, llvm_instruction): + super(Instruction, self).__init__(llvm_instruction) + + # Syntax and encoding + self.encoding = InstructionEncoding(self.llvm_instr["Inst"]) + self.llvm_syntax = self.llvm_instr["AsmString"] + self.syntax = normalize_llvm_syntax(self.llvm_instr["AsmString"]) + + # Packet and Duplex + # Has to be only instruction in packet. + self.is_solo = ( + self.llvm_instr["isSolo"][0] if "isSolo" in self.llvm_instr else None + ) + + self.is_sub_instruction = False + self.is_duplex = False + + # Operands + self.num_operands = self.get_num_operands( + self.llvm_syntax, self.llvm_in_out_operands + ) + + # Immediate operands + self.has_extendable_imm = self.llvm_instr["isExtendable"][0] == 1 + self.must_be_extended = self.llvm_instr["isExtended"][0] == 1 + self.ext_operand_index = list_to_int(self.llvm_instr["opExtendable"]) + self.extendable_alignment = list_to_int(self.llvm_instr["opExtentAlign"]) + + # Register operands + self.has_new_non_predicate = self.llvm_instr["isNewValue"][0] == 1 + self.new_operand_index = list_to_int(self.llvm_instr["opNewValue"]) + self.predicated = self.llvm_instr["isPredicated"][0] == 1 + self.predicate_info = PredicateInfo(self.llvm_instr) + + # Special + self.is_endloop = "endloop" in self.name + self.is_loop_begin = "loop" in self.name and not self.is_endloop + self.is_loop = self.is_endloop or self.is_loop_begin + self.loop_member = self.get_loop_membership(self.llvm_syntax) + + self.parse_instruction() + + def parse_instruction(self) -> None: + """Parses all operands of the instruction which are encoded.""" + + self.llvm_filtered_operands = self.remove_invisible_in_out_regs( + self.llvm_syntax, deepcopy(self.llvm_in_out_operands) + ) + self.operand_indices = self.get_syntax_operand_indices( + self.llvm_syntax, self.llvm_filtered_operands + ) + + # Update syntax indices + if self.has_new_non_predicate: + op_name = self.llvm_in_out_operands[self.new_operand_index][1] + self.new_operand_index = self.operand_indices[op_name] + # log("{}\nnew: {}".format(self.llvm_syntax, self.new_operand_index), LogLevel.DEBUG) + if self.has_extendable_imm: + op_name = self.llvm_in_out_operands[self.ext_operand_index][1] + self.ext_operand_index = self.operand_indices[op_name] + # log("{}\next: {}".format(self.llvm_syntax, self.ext_operand_index), LogLevel.DEBUG) + + if len(self.llvm_filtered_operands) > PluginInfo.MAX_OPERANDS: + warning = "{} instruction struct can only hold {} operands. This instruction has {} operands.".format( + PluginInfo.FRAMEWORK_NAME, + PluginInfo.MAX_OPERANDS, + len(self.llvm_filtered_operands), + ) + raise ImplementationException(warning) + + # TODO Some instructions encode some register explicitly in the syntax. At the moment we do not, + # but maybe should add them here somehow as registers. Example: J4_cmpeq_fp0_jump_t + # But note that they don't seem to have an index attached to them. + + # TODO Parse high/low access of registers. + + for in_out_operand in self.llvm_filtered_operands: + op_name = in_out_operand[1] + op_type = in_out_operand[0]["def"] + syntax_index = self.operand_indices[op_name] + + # Parse register operand + if Operand.get_operand_type(op_type) is OperandType.REGISTER: + # Indices of new values (stored in "opNewValue") are only for non predicates. + is_new_value = ( + self.new_operand_index == syntax_index + and self.has_new_non_predicate + ) + operand = Register(op_name, op_type, is_new_value, syntax_index) + # Whether the predicate registers holds a new value is denoted in "isPredicatedNew". + if self.predicate_info.new_value and operand.is_predicate: + operand.is_new_value = True + # Parse immediate operands + elif Operand.get_operand_type(op_type) is OperandType.IMMEDIATE: + extendable = ( + self.has_extendable_imm and self.ext_operand_index == syntax_index + ) + operand = Immediate( + op_name, + op_type, + extendable, + self.extendable_alignment, + syntax_index, + ) + + else: + raise ImplementationException( + "Unknown operand type: {}, op_name: {}".format(op_type, op_name) + ) + + if op_name in self.constraints: + operand.is_in_out_operand = True + operand.is_out_operand = True + operand.is_in_operand = True + elif in_out_operand in self.llvm_in_operands: + operand.is_in_operand = True + elif in_out_operand in self.llvm_out_operands: + operand.is_out_operand = True + + # Add opcode extraction code + if ( + operand.type == OperandType.IMMEDIATE and operand.is_constant + ): # Constants have no parsing code. + pass + else: + if ( + operand.is_in_out_operand and op_name[-2:] == "in" + ): # In/Out Register + mask = self.encoding.operand_masks[op_name[:-2]] # Ends with "in" + else: + mask = self.encoding.operand_masks[op_name] + operand.opcode_mask = mask + operand.add_code_for_opcode_parsing(Operand.make_sparse_mask(mask)) + + # On the fly check whether the new values have been assigned correctly. + if op_name + ".new" in self.llvm_syntax: + if not operand.is_new_value: + raise ImplementationException( + "Register has new value in syntax but not as object." + + "It has been parsed incorrectly! Are the indices correctly set?" + + "Affected instruction: {}".format(self.llvm_syntax) + ) + + self.operands[op_name] = operand + + @staticmethod + def get_num_operands(llvm_syntax: str, llvm_operands: list) -> int: + """Counts operands which actually appear in the syntax. This is necessary in case of + InOutRegisters like Rx/RxIn. + They are always listed in the LLVM instr. but not necessarily appear in the syntax. + """ + s = 0 + for op in llvm_operands: + name = op[1] + s += 1 if name in llvm_syntax else 0 + return s + + @staticmethod + def get_loop_membership(syntax: str) -> int: + """Returns loop membership to a loop name. + The syntax has to be parsed as some loops have the number not in the name (e.g. J2_ploop3sr). + """ + if re.search(r"loop0[^\d]", syntax): + return LoopMembership.HEX_LOOP_0 + elif re.search(r"loop1[^\d]", syntax): + return LoopMembership.HEX_LOOP_1 + elif re.search(r"endloop01", syntax): + return ( + LoopMembership.HEX_ENDS_LOOP_0 + | LoopMembership.HEX_ENDS_LOOP_1 + | LoopMembership.HEX_LOOP_0 + | LoopMembership.HEX_LOOP_1 + ) + elif re.search(r"enloop1[^\d]", syntax): + return LoopMembership.HEX_LOOP_1 | LoopMembership.HEX_ENDS_LOOP_1 + elif re.search(r"enloop0[^\d]", syntax): + return LoopMembership.HEX_LOOP_0 | LoopMembership.HEX_ENDS_LOOP_0 + else: + return LoopMembership.HEX_NO_LOOP + + +class PredicateInfo: + """Helper class to store the information about the predicate of the instruction.""" + + def __init__(self, llvm_instr: dict): + self.negative = llvm_instr["isPredicatedFalse"][0] + self.new_value = llvm_instr["isPredicatedNew"][0] + # What does isPredicateLate mean? + if "isPredicateLate" in llvm_instr: + self.late = llvm_instr["isPredicateLate"][0] + else: + self.late = None diff --git a/InstructionEncoding.py b/InstructionEncoding.py new file mode 100644 index 00000000..de7eca6c --- /dev/null +++ b/InstructionEncoding.py @@ -0,0 +1,128 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import re + +from bitarray import bitarray + +from ImplementationException import ImplementationException +from helperFunctions import log, LogLevel, bitarray_to_uint +import HexagonArchInfo +import PluginInfo + + +class InstructionEncoding: + """ + Represents the encoding of an instruction. + + Attributes: + llvm_encoding: The encoding of an instruction, as it is found in an instruction object of + the llvm-tblgen generated json file. + num_encoded_operands: The number of operands which are _encoded_ (Not all operands are encoded. E.g. n1Const). + docs_mask: The mask as it can be found in the Programmers Reference Manual. + llvm_operand_names: A list of llvm type operand names which are encoded in the instruction. + operand_masks: Masks of all operands encoded in the instruction. + num_representation: The first 13bits of the instruction interpreted as number. Variable bits are treated as 0. + Needed for sub instr. comparison. + op_code: The op code as number. + instruction_mask: The mask of the instruction. + """ + + __slots__ = [ + "docs_mask", + "llvm_operand_names", + "operand_masks", + "instruction_mask", + "num_encoded_operands", + "llvm_encoding", + "op_code", + "num_representation", + "duplex_encoding", + "parse_bits_mask", + ] + + def __init__(self, llvm_encoding: list): + self.llvm_operand_names = list() + self.operand_masks = dict() + self.instruction_mask: int = 0 + self.op_code: int = 0 + self.parse_bits_mask: int = 0 + self.num_encoded_operands = 0 + self.docs_mask = "" + self.llvm_encoding = llvm_encoding + # The first 13bit of the encoding as 13bit unsigned int. Variable fields are interpret as 0. + self.num_representation = 0 + self.duplex_encoding = False + + self.parse_encoding() + + def parse_encoding(self): + """Parses each bit in the LLVM encoding and extracts masks and operands from those bits.""" + + instruction_mask = bitarray(HexagonArchInfo.INSTRUCTION_LENGTH, endian="little") + instruction_mask.setall(0) + op_code = bitarray(HexagonArchInfo.INSTRUCTION_LENGTH, endian="little") + op_code.setall(0) + p_bits_mask = bitarray(HexagonArchInfo.INSTRUCTION_LENGTH, endian="little") + p_bits_mask.setall(0) + + # Bit 15:14 are only set if a duplex instruction is parsed. Else the parsing bits are None. + if self.llvm_encoding[14] == 0 and self.llvm_encoding[15] == 0: + self.duplex_encoding = True + + for i in range(0, 32): + bit = self.llvm_encoding[i] + # Instruction bits + if bit == 0 or bit == 1: + if ( + i < 13 + ): # Number representation for SubInstruction comparison (Duplex generation). + self.num_representation |= bit << i + + # Parsing bits in Duplex instructions are indicated by E. + if i == 14 or i == 15: + self.docs_mask = "E" + self.docs_mask + p_bits_mask[i] = 1 + else: + self.docs_mask = str(bit) + self.docs_mask + + # In the encoding of Qualcomm (see: hexagon_iset_v5.h) we can find some some irrelevant bits + # (depicted as '-'). In the LLVM encoding they are simply set to 0. So we include them in the mask + # and opcode anyways. + instruction_mask[i] = 1 + op_code[i] = bit + # The parse bits are set to null/None + elif bit is None: + if i == 14 or i == 15: + self.docs_mask = "P" + self.docs_mask + p_bits_mask[i] = 1 + # Variable bits encoding a register or immediate + else: + op_name = bit["var"] + # Not yet parsed operand in encoding found. Create new mask. + if op_name not in self.llvm_operand_names: + self.num_encoded_operands += 1 + self.llvm_operand_names.append(op_name) + self.operand_masks[op_name] = bitarray( + HexagonArchInfo.INSTRUCTION_LENGTH, endian="little" + ) + self.operand_masks[op_name].setall(0) + self.operand_masks[op_name][i] = 1 + + # We just assume that the second letter is the correct representative. Rd32 -> d, Ii -> i etc. + self.docs_mask = op_name[1] + self.docs_mask + + self.instruction_mask = bitarray_to_uint(instruction_mask, endian="little") + self.op_code = bitarray_to_uint(op_code, endian="little") + self.parse_bits_mask = bitarray_to_uint(p_bits_mask, endian="little") + + # log("Added encoding: {} with operands: {}".format(self.docs_mask, self.operands), LogLevel.VERBOSE) + + def get_i_class(self) -> int: + if self.duplex_encoding: + enc = self.llvm_encoding + return enc[31] << 3 | enc[30] << 2 | enc[29] << 1 | enc[13] + else: + i_class = self.llvm_encoding[28:32] + return i_class[3] << 3 | i_class[2] << 2 | i_class[1] << 1 | i_class[0] diff --git a/InstructionTemplate.py b/InstructionTemplate.py new file mode 100644 index 00000000..5ec45289 --- /dev/null +++ b/InstructionTemplate.py @@ -0,0 +1,351 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import re + +import HexagonArchInfo +import PluginInfo +from HardwareRegister import HardwareRegister +from Immediate import Immediate +from ImplementationException import ImplementationException +from InstructionEncoding import InstructionEncoding +from Operand import Operand, OperandType +from UnexpectedException import UnexpectedException +from helperFunctions import bitarray_to_uint, log, LogLevel + + +class InstructionTemplate: + """Fields, flags and methods which are shared by Duplex-, Sub- and normal instructions.""" + + def __init__(self, llvm_instruction): + # Meta info + self.llvm_instr: dict = llvm_instruction + self.name: str = self.llvm_instr["!name"] + self.plugin_name: str = PluginInfo.INSTR_ENUM_PREFIX + self.name.upper() + self.type: str = self.llvm_instr["Type"]["def"] + self.constraints = self.llvm_instr["Constraints"] + self.has_jump_target = self.name[:2] == "J2" or self.name[:2] == "J4" + if self.name[0] == "J" and not self.has_jump_target: + raise ImplementationException( + "Yet unknown jump instruction class: {}".format(self.name) + ) + + self.is_call = self.llvm_instr["isCall"] == 1 + self.is_branch = ( + self.llvm_instr["isBranch"] == 1 + ) # Not set for J2_loops, J2_trap, J2_pause + self.is_terminator = self.llvm_instr["isTerminator"] == 1 + self.is_return = self.llvm_instr["isReturn"] == 1 + # The parsing bits are not set in the encoding. Therefore we simply do this search. + self.is_pause = self.name == "J2_pause" + self.is_trap = "trap" in self.name + if self.is_trap or self.is_pause: + self.has_jump_target = False + + # Syntax and encoding + self.encoding: InstructionEncoding = None + self.llvm_syntax: str = None + self.syntax: str = None + + # Packet and Duplex + # Has to be only instruction in packet. + self.is_solo: bool = None + + self.is_sub_instruction: bool = None + self.is_duplex: bool = None + + # Operands + self.llvm_in_operands: list = self.llvm_instr["InOperandList"]["args"] + self.llvm_out_operands: list = self.llvm_instr["OutOperandList"]["args"] + # Order matters! + self.llvm_in_out_operands: list = self.llvm_out_operands + self.llvm_in_operands + self.llvm_filtered_operands: list = list() + self.operands = dict() + self.operand_indices = dict() + self.num_operands = 999 + self.llvm_operands = list() + self.new_operand_index = 999 + self.ext_operand_index = 999 + + # Immediate operands + self.has_extendable_imm: bool = None + self.must_be_extended: bool = None + self.llvm_ext_operand_index: bool = None + self.extendable_alignment: bool = None + + # Register operands + self.has_new_non_predicate: bool = None + self.llvm_new_operand_index: bool = None + self.predicated: bool = False + self.predicate_info: bool = None + + # Special + self.is_imm_ext: bool = self.type == "TypeEXTENDER" + self.is_endloop: bool = None + self.is_loop: bool = None + self.is_loop_begin: bool = None + self.loop_member = None + + # Execution specific (Interesting for decompiler plugin) + # The address mode of load/store instructions + self.addr_mode = None + # The access size of the load/store instruction + self.access_size = None + + def assign_syntax_indices_to_operands(self) -> None: + pass + + @staticmethod + def get_syntax_operand_indices(llvm_syntax: str, llvm_operands: list) -> dict: + """Gives the indices of the operands in the syntax, counted from left to right. + + LLVM indexing starts counting from the out-operands to the in-operands json objects. + If a Rx register is used in the syntax the position of the Register in the syntax does not represent the + index of the operand. Because there are always an Rx and RxIn operand in json. But RxIn is not necessarily + shown in the syntax (E.g. for Rx++). + This is why we here create our own indices. + See the test case for: V6_vS32b_nt_new_pred_ppu + + Args: + llvm_syntax: The syntax for which we need the + llvm_operands: List of operands from the llvm In/OutOperand list. + + Returns: Dictionary of {Reg_name : index} entries. + """ + + indices = dict() + for op in llvm_operands: + llvm_op_name = op[1] + if llvm_op_name not in indices and llvm_op_name in llvm_syntax: + indices[llvm_op_name] = re.search( + r"\b" + llvm_op_name + r"\b", llvm_syntax + ).start() + elif llvm_op_name in indices: + raise UnexpectedException( + "Two operands with the same name given.\nSyntax {}, op: {}".format( + llvm_syntax, llvm_op_name + ) + ) + + sorted_ops = dict( + sorted(indices.items(), key=lambda item: item[1]) + ) # Sort by value + for i, operand_name in enumerate(sorted_ops): + indices[operand_name] = i + + return indices + + @staticmethod + def remove_invisible_in_out_regs(llvm_syntax: str, llvm_ops: list) -> list: + """Removes registers from the llvm_ops list which does not appear in the syntax.""" + del_indices = list() + for i, op in enumerate(llvm_ops): + name = op[1] + if name not in llvm_syntax: + del_indices.append(i) + + for n, i in enumerate(del_indices): + del llvm_ops[i - n] + return llvm_ops + + def has_imm_jmp_target(self) -> bool: + """Returns true if the call or jump uses a immediate value to determine the target address. Otherwise false""" + + if self.has_jump_target: + op: Operand + for op in self.operands.values(): + if op.type == OperandType.IMMEDIATE: + op: Immediate + if op.is_pc_relative: + return True + elif len(self.operands) == 1: + return True # Assume true if it is the only operand. + return False + + def get_jmp_operand_syntax_index(self) -> int: + """Returns the index of the operand in the syntax or -1 if no PC relative operand exists.""" + for op in self.operands.values(): + if op.type != OperandType.IMMEDIATE: + continue + if op.is_pc_relative: + return op.syntax_index + elif len(self.operands) == 1: + return op.syntax_index # If it is the only operand it is the address. + + return -1 + + # RIZIN SPECIFIC + def get_instruction_init_in_c(self) -> str: + """Returns one big c code block which parses one binary instruction. The blocks are used in hexagon_disas.c""" + + indent = PluginInfo.LINE_INDENT + var = PluginInfo.HEX_INSTR_VAR_SYNTAX + code = "" + code += "if (({} & 0x{:x}) == 0x{:x}) {{\n".format( + var, self.encoding.instruction_mask, self.encoding.op_code + ) + code += "{}// {} | {}\n".format(indent, self.encoding.docs_mask, self.syntax) + code += "{}hi->instruction = {};\n".format(indent, self.plugin_name) + code += "{}hi->pkt_info.parse_bits = (({}) & 0x{:x}) >> 14;\n".format( + indent, var, self.encoding.parse_bits_mask + ) + code += "{}hi->pkt_info.loop_attr = {};\n".format(indent, self.loop_member.name) + code += "{}hex_set_pkt_info(&(hi->pkt_info));\n".format(indent) + + if self.is_duplex: + code += "{}hi->duplex = {};\n".format(indent, str(self.is_duplex).lower()) + + # TODO Set predicate state + + code += "{}hi->op_count = {};\n".format( + indent, self.encoding.num_encoded_operands + ) + mnemonic = '{}sprintf(hi->mnem, "%s {} %s"'.format(indent, self.syntax) + sprint_src = ", hi->pkt_info.syntax_prefix" + + op: Immediate + for op in self.operands.values(): + if op.type == OperandType.IMMEDIATE and op.is_constant: + mnemonic = re.sub(r"#[nN]1", r"#-1", mnemonic) + continue + + code += "{}hi->ops[{}].type = {};\n".format( + indent, op.syntax_index, op.type.value + ) + + if op.type == OperandType.REGISTER: + code += "{}hi->ops[{}].op.reg = {}".format( + indent, op.syntax_index, op.code_opcode_parsing + ) + mnemonic = re.sub(op.explicit_syntax, "%s", mnemonic) + src = "hi->ops[{}].op.reg".format(op.syntax_index) + sprint_src += ", {}({})".format( + HardwareRegister.get_func_name_of_class(op.llvm_type), src + ) + + elif op.type == OperandType.IMMEDIATE and not op.is_constant: + code += "{}hi->ops[{}].op.imm = {}".format( + indent, op.syntax_index, op.code_opcode_parsing + ) + + if op.is_pc_relative: + src = ", addr + (st32) hi->ops[{}].op.imm".format(op.syntax_index) + mnemonic = re.sub(op.explicit_syntax, "0x%x", mnemonic) + elif op.is_signed: + # TODO This is really complex and shouldn't be here + h = "#" if op.total_width != 32 else "##" + code += "{}if (((st32) hi->ops[{}].op.imm) < 0) {{\n".format( + indent, op.syntax_index + ) + code += ( + '{}sprintf(signed_imm, "%s%s0x%x", "'.format(indent * 2) + + h + + '", "-", abs((st32) hi->ops[{}].op.imm)); // Add a minus sign before hex number\n'.format( + op.syntax_index + ) + ) + code += "{}}}\n".format(indent) + code += "{}else {{\n".format(indent) + + code += ( + '{}sprintf(signed_imm, "%s0x%x", "'.format(indent * 2) + + h + + '", (st32) hi->ops[{}].op.imm);\n'.format(op.syntax_index) + ) + code += "{}}}\n".format(indent) + + src = ", signed_imm" + mnemonic = re.sub(r"#?" + op.explicit_syntax, "%s", mnemonic) + else: + src = ", hi->ops[{}].op.imm".format(op.syntax_index) + if op.total_width == 32: + # 32bit values are marked with ##. Non 32bit values with #. Don't care without. + # Add the second # to the syntax in case of 32bit value. + mnemonic = re.sub(op.explicit_syntax, "#0x%x", mnemonic) + else: + mnemonic = re.sub(op.explicit_syntax, "0x%x", mnemonic) + + sprint_src += src + else: + raise ImplementationException("Unhandled operand: {}".format(op.syntax)) + + mnemonic = self.register_names_to_upper(mnemonic) + + code += mnemonic + sprint_src + ", hi->pkt_info.syntax_postfix" + ");\n" + if self.name == "A4_ext": + code += "{}hex_op_extend(&(hi->ops[0]), true);\n".format(indent) + code += "{}break;\n}}\n".format(indent) + # log("\n" + code) + + return code + + # RIZIN SPECIFIC + def get_rizin_op_type(self) -> str: + op_type = "op->type = " + + if self.is_trap: + return op_type + "RZ_ANALYSIS_OP_TYPE_TRAP" + if not self.has_jump_target: + return op_type + "RZ_ANALYSIS_OP_TYPE_UNK;" + + if self.predicated: + if self.is_call: + # Immediate and register call + op_type += ( + "RZ_ANALYSIS_OP_TYPE_CCALL;" + if self.has_imm_jmp_target() + else "RZ_ANALYSIS_OP_TYPE_UCCALL;" + ) + elif self.is_return: + op_type += "RZ_ANALYSIS_OP_TYPE_CRET;" + elif self.is_branch or self.is_loop: + # Immediate and register jump + op_type += ( + "RZ_ANALYSIS_OP_TYPE_CJMP;" + if self.has_imm_jmp_target() + else "RZ_ANALYSIS_OP_TYPE_RCJMP;" + ) + else: + raise ImplementationException( + "Instruction is not of any known branch type: {}".format(self.name) + ) + else: + if self.is_call: + # Immediate and register call + op_type += ( + "RZ_ANALYSIS_OP_TYPE_CALL;" + if self.has_imm_jmp_target() + else "RZ_ANALYSIS_OP_TYPE_RCALL;" + ) + elif self.is_return: + op_type += "RZ_ANALYSIS_OP_TYPE_RET;" + elif self.is_branch or self.is_loop: + # Immediate and register jump + op_type += ( + "RZ_ANALYSIS_OP_TYPE_JMP;" + if self.has_imm_jmp_target() + else "RZ_ANALYSIS_OP_TYPE_RJMP;" + ) + else: + raise ImplementationException( + "Instruction is not of any known branch type: {}".format(self.name) + ) + + return op_type + + # RIZIN SPECIFIC + @staticmethod + def register_names_to_upper(mnemonic: str) -> str: + """The syntax can contain lower case register names. Here we convert them to upper case to enable syntax + highlighting in rizin. + """ + for reg_name in HexagonArchInfo.ALL_REG_NAMES: + if re.search(r"[^a-zA-Z]" + reg_name.lower(), mnemonic): + mnemonic = re.sub(reg_name.lower(), reg_name.upper(), mnemonic) + return mnemonic + + # RIZIN SPECIFIC + def get_pkt_info_code(self) -> str: + # Duplexes are always last instr. in packet. + pass diff --git a/LICENSE b/LICENSE deleted file mode 100644 index c0c90c88..00000000 --- a/LICENSE +++ /dev/null @@ -1,23 +0,0 @@ -Copyright (c) 2016, Fundación Dr. Manuel Sadosky -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. 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Name: {}".format(i_name), + LogLevel.VERBOSE, + ) + continue + log("{} | Parse {}".format(i, i_name), LogLevel.VERBOSE) + self.llvm_instructions[i_name] = llvm_instruction + + if llvm_instruction["Type"]["def"] == "TypeSUBINSN": + self.sub_instruction_names.append(i_name) + self.sub_instructions[i_name] = SubInstruction(llvm_instruction) + # log(i_name, LogLevel.DEBUG) + else: + self.normal_instruction_names.append(i_name) + self.normal_instructions[i_name] = Instruction(llvm_instruction) + + log("Parsed {} normal instructions.".format(len(self.normal_instructions))) + log("Parsed {} sub-instructions.".format(len(self.sub_instructions))) + + def generate_duplex_instructions(self) -> None: + sub_instr_pairs = itertools.product( + self.sub_instructions.values(), self.sub_instructions.values() + ) + for pair in sub_instr_pairs: + low_instr = pair[0] + high_instr = pair[1] + i_class = DuplexInstruction.get_duplex_i_class_of_instr_pair( + low=low_instr, high=high_instr + ) + if ( + i_class != DuplexIClass.INVALID + and DuplexInstruction.fulfill_constraints(low_instr, high_instr) + ): + llvm_dup_instr = self.hexArch[i_class.name] + dup_instr = DuplexInstruction( + llvm_duplex_instr=llvm_dup_instr, low=low_instr, high=high_instr + ) + self.duplex_instructions[dup_instr.name] = dup_instr + self.duplex_instructions_names.append(dup_instr.name) + # log("Duplex instruction generated: {}".format(dup_instr.name), LogLevel.DEBUG) + log("Generated {} duplex instructions.".format(len(self.duplex_instructions))) + + def parse_hardware_registers(self) -> None: + cc = 0 + cr = 0 + for reg_class_name in HexagonArchInfo.REG_CLASS_NAMES: + # LLVM fake register class; VectRegRev = reverse double register: V0:1 instead of V1:0 + if reg_class_name == "UsrBits" or reg_class_name == "VectRegRev": + continue + # Register class which holds all new register of an arch version. Irrelevant for us at the moment. + if reg_class_name == "V65Regs" or reg_class_name == "V62Regs": + continue + + self.hardware_regs[reg_class_name] = dict() + reg_class: dict = self.hexArch[reg_class_name] + # Use "Alignment" although a "Size" attribute exists. But Double Regs set that to 0. + size: int = ( + reg_class["Alignment"] if reg_class["Size"] == 0 else reg_class["Size"] + ) + + reg_names = list() + for a in reg_class["MemberList"]["args"]: + arg = a[0] + if "def" in arg: + # VTMP = LLVM fake register + if arg["def"] == "VTMP": + continue + if reg_class_name == "CtrRegs" and arg["def"] == "C8": + # For whatever reason this C8 occurs twice, but as USR reg. + # We better use the USR reg as it lists c8 als alternative name for itself. + continue + reg_names.append(arg["def"]) + elif "sequence" in arg["printable"]: + reg_names = reg_names + unfold_llvm_sequence(arg["printable"]) + # Remove registers whichs tart with WR; WR register are reverse double vector regs: V0:1 instead of V1:0 + # TODO This is not nice. Isn't there a simpler way? + reg_names = [ + name for name in reg_names if not re.search(r"WR\d{1,2}", name) + ] + + for name in reg_names: + llvm_reg = self.hexArch[name] + reg = HardwareRegister( + llvm_reg_class=reg_class_name, + name=name, + llvm_object=llvm_reg, + size=size, + ) + self.hardware_regs[reg_class_name][name] = reg + cr += 1 + # log("Added reg: {}::{} with hw encoding: {}".format(name, reg_class_name, + # reg.hw_encoding), LogLevel.DEBUG) + + cc += 1 + log( + "Parsed {} hardware registers of {} different register classes.".format( + cr, cc + ) + ) + + def check_insn_syntax_length(self): + for instr_set in [ + self.normal_instructions.values(), + self.duplex_instructions.values(), + ]: + for insn in instr_set: + if len(insn.syntax) >= 128: + sl = len(insn.syntax) + 1 # +1 for \0 in the string + raise ImplementationException( + "The mnemonic variable is at the moment only 128 byte." + + "This syntax takes at least {}+1 bytes.".format(sl) + ) + + @staticmethod + def print_todos() -> None: + log( + "CtrRegs64: C21:20, C23:22, C25:24, C27:C26, C29:28 recognition are not yet implemented by LLVM.\n" + "\tSo at the moment we don't have them either.", + LogLevel.TODO, + ) + log( + "HVX: HVX register classes and instructions can, at the moment, not be tested properly.\n" + "\tThe public SDK does not support them yet, so we can't compile reasonable test cases for them.", + LogLevel.TODO, + ) + log( + "All not generated files have to be moved to handwritten_files", + LogLevel.TODO, + ) + log( + "A lot of instruction types can be set in analyse like NOP etc.", + LogLevel.TODO, + ) + log("Syntax highlighting is weird.", LogLevel.TODO) + log("Analysis tests are missing.", LogLevel.TODO) + log("No UTF-8 free version yet.", LogLevel.TODO) + log( + "The support for 512bit Hardware registers was removed in V66 (replaced by 1024bit once).\n\t" + "But LLVM Vx registers still have a size of 512bit.\n\t" + "We multiply the size of all vector register by 2.", + LogLevel.TODO, + ) + log( + "Argument and return registers for the HVX calling convention are not described in the register profile.", + LogLevel.TODO, + ) + + def get_cc_regs(self) -> dict: + """Returns a list of register names which are argument or return register in the calling convention. + This part is a bit tricky. The register names are stored in objects named "anonymous_XXX" in Hexagon.json. + Since they do not have a explicit name, we can only check check the names against the source. + + Note: LLVM defines the calling convention in: HexagonCallingConv.td + + Returns: dict = {"GPR_args":list[str], "GPR_ret":list[str], "HVX_args":list[str], "HVX_ret":list[str],} + """ + cc_regs = dict() + anon_obj_names = self.hexArch["!instanceof"]["CCAssignToReg"] + arg_regs = [ + reg["def"] for reg in self.hexArch[anon_obj_names[0]]["RegList"] + ] # Single + arg_regs += [ + reg["def"] for reg in self.hexArch[anon_obj_names[1]]["RegList"] + ] # Double + cc_regs["GPR_args"] = arg_regs + + ret_regs = [ + reg["def"] for reg in self.hexArch[anon_obj_names[2]]["RegList"] + ] # Single + ret_regs += [ + reg["def"] for reg in self.hexArch[anon_obj_names[3]]["RegList"] + ] # Double + cc_regs["GPR_ret"] = ret_regs + + hvx_arg_regs = [ + reg["def"] for reg in self.hexArch[anon_obj_names[4]]["RegList"] + ] # Single + hvx_arg_regs += [ + reg["def"] for reg in self.hexArch[anon_obj_names[5]]["RegList"] + ] # Double + cc_regs["HVX_args"] = hvx_arg_regs + + hvx_ret_regs = [ + reg["def"] for reg in self.hexArch[anon_obj_names[6]]["RegList"] + ] # Single + hvx_ret_regs += [ + reg["def"] for reg in self.hexArch[anon_obj_names[7]]["RegList"] + ] # Double + cc_regs["HVX_ret"] = hvx_ret_regs + + return cc_regs + + # RIZIN SPECIFIC + def generate_asm_code(self) -> None: + self.build_hexagon_insn_enum_h() + self.build_hexagon_disas_c() + self.build_hexagon_c() + self.build_hexagon_h() + self.build_asm_hexagon_c() + self.copy_tests() + + # TODO hexagon.h: Gen - HexOpType, IClasses, Regs and its aliases (system = guest), + # + corresponding functions in hexagon.c: hex_get_sub_regpair etc. + + # RIZIN SPECIFIC + def generate_analysis_code(self) -> None: + self.build_hexagon_analysis_h() + self.build_hexagon_analysis_c() + self.build_hexagon_regs() + # TODO Register profiles: analysis_hexagon.c::set_reg_profile() + # TODO copy Calling convention: cc-hexagon_hexagon.c + pass + + # RIZIN SPECIFIC + # TODO Wouldn't it be a wonderful world... + def generate_decompiler_code(self) -> None: + pass + + # RIZIN SPECIFIC + @staticmethod + def add_license_header() -> None: + log("Add license headers") + for subdir, dirs, files in os.walk("rizin/"): + for file in files: + if file == "hexagon": # Tests + continue + p = os.path.join(subdir, file) + with open(p, "r+") as f: + content = f.read() + f.seek(0, 0) + f.write(get_license() + "\n" + content) + + # RIZIN SPECIFIC + def build_hexagon_insn_enum_h( + self, path: str = "./rizin/librz/asm/arch/hexagon/hexagon_insn.h" + ) -> None: + with open(path, "w+") as dest: + dest.write(get_generation_warning_c_code()) + dest.write("\n") + dest.write(get_include_guard("hexagon_insn.h")) + dest.write("\n") + dest.write("enum HEX_INS {\n") + for name in self.normal_instruction_names + self.duplex_instructions_names: + dest.write( + PluginInfo.LINE_INDENT + + PluginInfo.INSTR_ENUM_PREFIX + + name.upper() + + ",\n" + ) + dest.write("};\n\n") + dest.write("#endif") + log("Hexagon instruction enum written to: {}".format(path)) + + # RIZIN SPECIFIC + def build_hexagon_disas_c( + self, path: str = "./rizin/librz/asm/arch/hexagon/hexagon_disas.c" + ) -> None: + # TODO Clean up this method + indent = PluginInfo.LINE_INDENT + var = PluginInfo.HEX_INSTR_VAR_SYNTAX + with open(path, "w+") as dest: + dest.write(get_generation_warning_c_code()) + + with open("handwritten/hexagon_disas_c/include.c") as include: + set_pos_after_license(include) + dest.writelines(include.readlines()) + + header = ( + "int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) {\n" + + '{}char signed_imm[16] = "";\n'.format(indent) + + "{}// DUPLEXES\n".format(indent) + + "{}if ((({} >> 14) & 0x3) == 0) {{\n".format(indent, var) + + "{}switch (((({} >> 29) & 0xF) << 1) | (({} >> 13) & 1)) {{\n".format( + indent * 2, var, var + ) + ) + dest.write(header) + + # Duplexes + for c in range(0xF): # Class 0xf is reserved yet. + dest.write("{}case 0x{:x}:\n".format(indent * 3, c)) + for d_instr in self.duplex_instructions.values(): + if d_instr.encoding.get_i_class() == c: + dest.write( + indent_code_block(d_instr.get_instruction_init_in_c(), 4) + ) + dest.write("{}break;\n".format(indent * 4)) + + # Normal instructions + # Brackets for switch, if + dest.write("{}}}\n{}}}\n{}else {{\n".format(indent * 2, indent, indent)) + dest.write("{}switch (({} >> 28) & 0xF) {{\n".format(indent * 2, var)) + for c in range(0x10): + dest.write("{}case 0x{:x}:\n".format(indent * 3, c)) + for instr in self.normal_instructions.values(): + if instr.encoding.get_i_class() == c: + dest.write( + indent_code_block(instr.get_instruction_init_in_c(), 4) + ) + dest.write("{}break;\n".format(indent * 4)) + + # Closing brackets for switch, else, function + dest.write("{}}}\n{}}}\n{}return 4;\n}}".format(indent * 2, indent, indent)) + log("Hexagon instruction disassembler code written to: {}".format(path)) + + # RIZIN SPECIFIC + def build_hexagon_h( + self, path: str = "./rizin/librz/asm/arch/hexagon/hexagon.h" + ) -> None: + indent = PluginInfo.LINE_INDENT + general_prefix = PluginInfo.GENERAL_ENUM_PREFIX + + with open(path, "w+") as dest: + dest.write(get_generation_warning_c_code()) + dest.write("\n") + dest.write(get_include_guard("hexagon.h")) + + with open("handwritten/hexagon_h/typedefs.h") as typedefs: + set_pos_after_license(typedefs) + dest.writelines(typedefs.readlines()) + + reg_class: str + for reg_class in self.hardware_regs: + dest.write("\ntypedef enum {\n") + + hw_reg: HardwareRegister + for hw_reg in sorted( + self.hardware_regs[reg_class].values(), key=lambda x: x.hw_encoding + ): + alias = ",".join(hw_reg.alias) + dest.write( + "{}{} = {},{}\n".format( + indent, + hw_reg.enum_name, + hw_reg.hw_encoding, + " // " + alias if alias != "" else "", + ) + ) + dest.write( + "}} {}{}; // {}\n".format( + general_prefix, + HardwareRegister.register_class_name_to_upper(reg_class), + reg_class, + ) + ) + + with open("handwritten/hexagon_h/macros.h") as macros: + set_pos_after_license(macros) + dest.writelines(macros.readlines()) + dest.write("\n") + if len(self.reg_resolve_decl) == 0: + raise ImplementationException( + "Register resolve declarations missing" + "(They get generated together with hexagon.c)." + "Please generate hexagon.c before hexagon.h" + ) + for decl in self.reg_resolve_decl: + dest.write(decl + "\n") + with open("handwritten/hexagon_h/declarations.h") as decl: + set_pos_after_license(decl) + dest.writelines(decl.readlines()) + + dest.write("#endif") + + log("hexagon.h written to: {}".format(path)) + + # RIZIN SPECIFIC + def build_hexagon_c( + self, path: str = "./rizin/librz/asm/arch/hexagon/hexagon.c" + ) -> None: + indent = PluginInfo.LINE_INDENT + + with open(path, "w+") as dest: + dest.write(get_generation_warning_c_code()) + with open("handwritten/hexagon_c/include.c") as include: + set_pos_after_license(include) + dest.writelines(include.readlines()) + dest.write("\n") + + reg_class: str + for reg_class in self.hardware_regs: + func_name = HardwareRegister.get_func_name_of_class(reg_class) + function = "char* {}(int opcode_reg)".format(func_name) + self.reg_resolve_decl.append(function + ";") + dest.write("\n{} {{\n".format(function)) + + parsing_code = HardwareRegister.get_parse_code_reg_bits( + reg_class, "opcode_reg" + ) + parsing_code = indent_code_block(parsing_code, 1) + if parsing_code != "": + dest.write("{}\n".format(parsing_code)) + + dest.write("{}switch (opcode_reg) {{\n".format(indent)) + dest.write( + '{}default:\n{}rz_warn_if_reached();\n{}return "";\n'.format( + indent * 2, indent * 3, indent * 3 + ) + ) + + hw_reg: HardwareRegister + for hw_reg in self.hardware_regs[reg_class].values(): + dest.write( + '{}case {}:\n{}return "{}";\n'.format( + indent * 2, + hw_reg.enum_name, + indent * 3, + hw_reg.asm_name.upper(), + ) + ) + dest.write("{}}}\n}}\n".format(indent)) + + with open("handwritten/hexagon_c/functions.c") as func: + set_pos_after_license(func) + dest.writelines(func.readlines()) + dest.write("\n") + + log("hexagon.c written to: {}".format(path)) + + # RIZIN SPECIFIC + @staticmethod + def build_asm_hexagon_c(path: str = "rizin/librz/asm/p/asm_hexagon.c") -> None: + with open(path, "w+") as f: + f.write(get_generation_warning_c_code()) + + with open("handwritten/asm_hexagon_c/include.c") as include: + set_pos_after_license(include) + f.writelines(include.readlines()) + with open("handwritten/asm_hexagon_c/initialization.c") as init: + set_pos_after_license(init) + f.writelines(init.readlines()) + log("asm_hexagon.c written to {}".format(path)) + + # RIZIN SPECIFIC + @staticmethod + def copy_tests() -> None: + with open("handwritten/analysis-tests/hexagon") as f: + with open("./rizin/test/db/analysis/hexagon", "w+") as g: + set_pos_after_license(g) + g.writelines(f.readlines()) + + with open("handwritten/asm-tests/hexagon") as f: + with open("./rizin/test/db/asm/hexagon", "w+") as g: + set_pos_after_license(g) + g.writelines(f.readlines()) + log("Copied test files to ./rizin/test/db/") + + # RIZIN SPECIFIC + @staticmethod + def build_hexagon_analysis_h( + path: str = "./rizin/librz/analysis/arch/hexagon/hexagon_analysis.h", + ) -> None: + with open(path, "w+") as f: + f.write(get_generation_warning_c_code()) + with open("handwritten/hexagon_analysis_h/include.h") as include: + set_pos_after_license(include) + f.writelines(include.readlines()) + log("hexagon_analysis.h written to {}".format(path)) + + # RIZIN SPECIFIC + def build_hexagon_analysis_c( + self, path: str = "./rizin/librz/analysis/arch/hexagon/hexagon_analysis.c" + ) -> None: + indent = PluginInfo.LINE_INDENT + + with open(path, "w+") as f: + f.write(get_generation_warning_c_code()) + + with open("handwritten/hexagon_analysis_c/include.c") as include: + set_pos_after_license(include) + f.writelines(include.readlines()) + f.write("\n") + + f.write( + "int hexagon_analysis_instruction(HexInsn *hi, RzAnalysisOp *op) {\n" + ) + f.write("{}static ut32 hw_loop0_start = 0;\n".format(indent)) + f.write("{}static ut32 hw_loop1_start = 0;\n\n".format(indent)) + f.write("{}switch (hi->instruction) {{\n".format(indent)) + + default = "{}default:\n".format(indent * 2) + default += ( + "{}if (is_endloop01_instr(hi) && hi->pkt_info.last_insn) {{\n".format( + indent * 3 + ) + + "{}op->type = RZ_ANALYSIS_OP_TYPE_CJMP;\n".format(indent * 4) + + "{}op->fail = hw_loop0_start;\n".format(indent * 4) + + "{}op->jump = hw_loop1_start;\n".format(indent * 4) + + "{}hw_loop1_start = 0;\n".format(indent * 4) + + "{}hw_loop0_start = 0;\n{}}}\n".format(indent * 4, indent * 3) + ) + default += ( + "{}else if (is_endloop0_instr(hi) && hi->pkt_info.last_insn) {{\n".format( + indent * 3 + ) + + "{}op->type = RZ_ANALYSIS_OP_TYPE_CJMP;\n".format(indent * 4) + + "{}op->jump = hw_loop0_start;\n".format(indent * 4) + + "{}hw_loop0_start = 0;\n{}}}\n".format(indent * 4, indent * 3) + ) + default += ( + "{}else if (is_endloop1_instr(hi) && hi->pkt_info.last_insn) {{\n".format( + indent * 3 + ) + + "{}op->type = RZ_ANALYSIS_OP_TYPE_CJMP;\n".format(indent * 4) + + "{}op->jump = hw_loop1_start;\n".format(indent * 4) + + "{}hw_loop1_start = 0;\n{}}}\n".format(indent * 4, indent * 3) + ) + default += "{}break;\n".format(indent * 3) + + f.write(default) + + all_instr = [i for i in self.normal_instructions.values()] + for i in self.duplex_instructions.values(): + all_instr.append(i) + + i: Instruction + for i in all_instr: + if i.has_jump_target: + f.write("{}case {}:\n".format(indent * 2, i.plugin_name)) + f.write("{}// {}\n".format(indent * 3, i.syntax)) + f.write("{}{}\n".format(indent * 3, i.get_rizin_op_type())) + if i.has_imm_jmp_target(): + index = i.get_jmp_operand_syntax_index() + if index < 0: + raise ImplementationException( + "Not PC relative operand given. But the jump needs one." + "{}".format(i.llvm_syntax) + ) + + f.write( + "{}op->jump = op->addr + (st32) hi->ops[{}].op.imm;\n".format( + indent * 3, index + ) + ) + if i.predicated: + f.write( + "{}op->fail = op->addr + op->size;\n".format(indent * 3) + ) + if i.is_loop_begin: + f.write( + "{}if (is_loop0_begin(hi)) {{\n".format(indent * 3) + + "{}hw_loop0_start = op->jump;\n{}}}\n".format( + indent * 4, indent * 3 + ) + ) + f.write( + "{}else if (is_loop1_begin(hi)) {{\n".format(indent * 3) + + "{}hw_loop1_start = op->jump;\n{}}}\n".format( + indent * 4, indent * 3 + ) + ) + f.write("{}break;\n".format(indent * 3, indent * 2)) + + f.write("{i}}}\n{i}return op->size;\n}}".format(i=indent)) + log("hexagon_analysis.c written to: {}".format(path)) + + # RIZIN SPECIFIC + def build_hexagon_regs( + self, path: str = "rizin/librz/analysis/p/analysis_hexagon.c" + ) -> None: + profile = self.get_alias_profile().splitlines(keepends=True) + offset = 0 + + for hw_reg_classes in self.hardware_regs: + if hw_reg_classes in [ + "IntRegsLow8", + "GeneralSubRegs", + "GeneralDoubleLow8Regs", + "ModRegs", + ]: + continue # Those registers would only be duplicates. + hw_reg: HardwareRegister + for hw_reg in self.hardware_regs[hw_reg_classes].values(): + profile.append(hw_reg.get_reg_profile(offset) + "\n") + offset += int((hw_reg.size / 8)) + profile.append("\n") + profile = profile[:-1] # Remove line breaks + profile[-1] = profile[-1][:-1] + ";\n" # [:-1] to remove line break. + + with open(path, "w+") as f: + f.write(get_generation_warning_c_code()) + + with open("handwritten/analysis_hexagon_c/include.c") as include: + set_pos_after_license(include) + f.writelines(include.readlines()) + with open("handwritten/analysis_hexagon_c/functions.c") as functions: + set_pos_after_license(functions) + f.writelines(functions.readlines()) + f.write("\n") + + tmp = list() + tmp.append("const char *p =\n") + tmp += profile + tmp = make_c_block( + lines=tmp, + begin="static bool set_reg_profile(RzAnalysis *analysis)", + ret="return rz_reg_set_profile_string(analysis->reg, p);\n", + ) + f.writelines(tmp) + f.write("\n") + + with open( + "handwritten/analysis_hexagon_c/initialization.c" + ) as initialization: + set_pos_after_license(initialization) + f.writelines(initialization.readlines()) + f.write("\n") + + # RIZIN SPECIFC + def get_alias_profile(self) -> str: + """Returns the alias profile of register. A0 = R0, SP = R29 PC = pc etc.""" + indent = PluginInfo.LINE_INDENT + + p = "\n" + '"=PC{}pc\\n"'.format(indent) + "\n" + p += '"=SP{}r29\\n"'.format(indent) + "\n" + p += '"=BP{}r30\\n"'.format(indent) + "\n" + p += '"=LR{}r31\\n"'.format(indent) + "\n" + p += '"=SR{}usr\\n"'.format(indent) + "\n" + + arg_regs = "" + ret_regs = "" + + arguments = HexagonArchInfo.CC_REGS["GPR_args"] + returns = HexagonArchInfo.CC_REGS["GPR_ret"] + + general_ps = list(self.hardware_regs["IntRegs"].values()) + list( + self.hardware_regs["DoubleRegs"].values() + ) + gpr: HardwareRegister + for gpr in general_ps: + try: + i = arguments.index(gpr.name) + except ValueError: + continue + if i > 9 and gpr.name in HexagonArchInfo.CC_REGS["GPR_args"]: + log( + "Can not add register {} as argument reg to the register profile. ".format( + gpr.name + ) + + "Rizin only supports 10 argument registers. Check rz_reg.h if this changed.", + LogLevel.WARNING, + ) + if gpr.name in HexagonArchInfo.CC_REGS["GPR_args"]: + arg_regs += '"=A{}{}{}\\n"'.format(i, indent, gpr.asm_name) + "\n" + + for gpr in general_ps: + try: + i = returns.index(gpr.name) + except ValueError: + continue + if i > 3 and gpr.name in HexagonArchInfo.CC_REGS["GPR_ret"]: + log( + "Can not add register {} as return reg to the register profile. ".format( + gpr.name + ) + + "Rizin only supports 4 return registers. Check rz_reg.h if this changed.", + LogLevel.WARNING, + ) + if gpr.name in HexagonArchInfo.CC_REGS["GPR_ret"]: + ret_regs += '"=R{}{}{}\\n"'.format(i, indent, gpr.asm_name) + "\n" + + p += arg_regs + ret_regs + "\n" + + return p + + # RIZIN SPECIFIC + @staticmethod + def apply_clang_format() -> None: + for subdir, dirs, files in os.walk("rizin/librz/"): + for file in files: + os.system("./clang-format.py -f " + os.path.join(subdir, file)) + log("clang-format applied.") + + +if __name__ == "__main__": + interface = LLVMImporter("Hexagon.json") diff --git a/Operand.py b/Operand.py new file mode 100644 index 00000000..c1d8e074 --- /dev/null +++ b/Operand.py @@ -0,0 +1,143 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +from enum import Enum + +from bitarray import bitarray + +import HexagonArchInfo +import PluginInfo +from ImplementationException import ImplementationException +from helperFunctions import normalize_llvm_syntax + + +class OperandType(Enum): + REGISTER = "HEX_OP_TYPE_REG" + IMMEDIATE = "HEX_OP_TYPE_IMM" + + +class Operand: + """ + Attributes: + llvm_syntax: syntax of operand as found in the LLVM json (Rd32 etc.) + explicit_syntax: str The register name: R0, C1, V14 etc. + syntax_index: int The index in the syntax + llvm_syntax: str The syntax of operands in the LLVM encoding object: Rd -> Rd32, #s8 -> Ii + """ + + __slots__ = [ + "explicit_syntax", + "llvm_type", + "llvm_syntax", + "syntax_index", + "is_in_operand", + "is_out_operand", + "is_in_out_operand", + "code_opcode_parsing", + "type", + "opcode_mask", + ] + + def __init__(self, llvm_syntax: str, llvm_type: str, syntax_index: int): + self.llvm_syntax = llvm_syntax + self.llvm_type = llvm_type + self.type: OperandType = self.get_operand_type(llvm_type) + self.syntax_index = syntax_index + self.explicit_syntax = normalize_llvm_syntax(self.llvm_syntax) + self.code_opcode_parsing = "" + self.opcode_mask: bitarray = bitarray() + + self.is_in_operand = False + self.is_out_operand = False + self.is_in_out_operand = False + + def add_code_for_opcode_parsing(self, parsing_code: str) -> None: + raise ImplementationException("You need to override this method.") + + # RIZIN SPECIFIC + @staticmethod + def make_sparse_mask(mask: bitarray) -> str: + """ + Generates the C code which extracts the Z bits of each operand. + + Bits of an operand are scattered over the encoded instruction. + Here we assemble them by using the mask of the field. + + Simple example: + Let the input mask of an immediate be: 0b1111111110011111111111110 + The bits of the actual immediate in the instruction encoding + need to be concatenated ignoring bit 15:14 and bit 0 (the zeros in the example mask). + So this function returns C-code which shifts the bits of the immediate segments and ORs them + to represent a valid value. + + hi_u32 is the encoded instruction from which we want to concatenate bit 24:16 and bit 13:1 + (bit 31:25 are ignored here) + + 2 1 + 432109876 54 3210987654321 0 indices + + Mask: 111111111|00|1111111111111|0 + hi_u32: 100111101|00|1010000010011|0 + | | + | | bit[24:16] shifted three times to the right + +--+-----------------|-------> ((hi_u32 & 0x1ff0000) >> 3) + ____|____ | + 1001111010000000000000 | bit[13:1] shifted once to the right + OR 1010000010011 --+---------------------------------> ((hi_u32 & 0x3ffe) >> 1)) + _______________________ + imm = 1001111011010000010011 + + output: + imm = ((hi_u32 & 0x1ff0000) >> 3) | ((hi_u32 & 0x3ffe) >> 1)) + + Args: + mask: Mask of the immediate/register + + Returns: Returns the C code which does the bit masking + shifting. + + """ + + switch = False + ncount = 0 # counts how many bits were *not* set. + masks_count = 0 # How many parts the mask has + masks = {} + bshift = {} + for i in range(0, 32): + if mask[i]: + if not switch: + switch = True + masks_count += 1 + bshift[masks_count] = ncount + if masks_count in masks: + masks[masks_count] |= 1 << i + else: + masks[masks_count] = 1 << i + else: + switch = False + ncount += 1 + + outstrings = [] + for i in range(masks_count, 0, -1): + outstrings += [ + "((({0:s}) & 0x{1:x}) >> {2:d})".format( + PluginInfo.HEX_INSTR_VAR_SYNTAX, masks[i], bshift[i] + ) + ] + outstring = " | ".join(outstrings) + if "|" in outstring: + outstring = "({0:s})".format(outstring) + + # log("Generated mask C code: {}".format(outstring), LogLevel.VERBOSE) + return outstring + + @staticmethod + def get_operand_type(operand_type: str) -> OperandType: + if operand_type in HexagonArchInfo.REG_CLASS_NAMES: + return OperandType.REGISTER + elif operand_type in HexagonArchInfo.IMMEDIATE_TYPES: + return OperandType.IMMEDIATE + else: + raise ImplementationException( + "Unknown operand type: {}".format(operand_type) + ) diff --git a/PluginInfo.py b/PluginInfo.py new file mode 100644 index 00000000..ba2d532a --- /dev/null +++ b/PluginInfo.py @@ -0,0 +1,14 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +HEX_INSTR_VAR_SYNTAX = "hi_u32" +LINE_INDENT = "\t" +REPO_URL = "https://github.com/rizinorg/rz-hexagon" +GENERATION_WARNING_DELIMITER = "//" + "=" * 40 +GENERAL_ENUM_PREFIX = "HEX_" +INSTR_ENUM_PREFIX = GENERAL_ENUM_PREFIX + "INS_" +REGISTER_ENUM_PREFIX = GENERAL_ENUM_PREFIX + "REG_" + +FRAMEWORK_NAME = "rizin" +MAX_OPERANDS = 6 diff --git a/README.md b/README.md index d3c00752..831f8b83 100644 --- a/README.md +++ b/README.md @@ -1,25 +1,118 @@ -# Overview + -It processes the files and generate C code in `rizin` directory. Just run `importer.py`. +# rz-hexagon -The parsing part based largely on [hexag00n](https://github.com/programa-stic/hexag00n) importer. +This is a Hexagon disassembly and analysis plugin generator for `rizin`. +It uses the [LLVM target description source code](https://github.com/llvm/llvm-project/tree/main/llvm/lib/Target/Hexagon) +of the Hexagon architecture, and some additional handwritten code. -# Contributors +# Prerequisites -* Anton Kochkov +We take all the information about the Hexagon instructions and operands from the LLVM target description. +There are a lot of source files, which describe the Hexagon architecture. + +Luckily there is a tool which will combine all the information of thos files into one `.json` file which we name `Hexagon.json`. +So `Hexagon.json` will hold all information about the Hexagon instructions and operands. + +In order to generate the `Hexagon.json` file we need the `llvm-tblgen` binary. + +Unfortunately `llvm-tblgen` is usually not provided via the package manager. You have to compile LLVM by yourself. + +### Build LLVM + +Please follow the [LLVM docs](https://llvm.org/docs/GettingStarted.html#getting-the-source-code-and-building-llvm) +(Build the release version to save **a lot** of RAM). + +`llvm-tblgen` should be in `/llvm-project/bin/` after the build. + +### Build and move Hexagon.json + +```bash +cd llvm-project/llvm/lib/Target/Hexagon +llvm-tblgen -I ../../../include/ --dump-json -o Hexagon.json Hexagon.td +mv Hexagon.json /rz-hexagon/ +``` + +# Install -* Lucas Molas +```bash +cd rz-hexagon/ +pip install -r requirements.txt +# If you enjoy some colors +pip install -r optional_requirements.txt +# Run tests +cd Tests +python3 -m unittest discover -s . -t . +# Install as develop package +cd .. +pip install -e . +``` -* Iván Arce +# Generate PlugIn -* Juan Heguiabehere +Simply run: +``` +./LLVMImporter.py +``` -* Christian Heitman +It processes the files and generates C code in `./rizin` and its subdirectories. -* D.C. +Copy the generated files to the `rizin` directory with + ```commandline + rsync -a rizin/ / + ``` +# Porting + +Apart from some methods, which produce the C code for `rizin`, this code is `rizin` independent. +In theory, it shouldn't be that hard to use it for disassembler plugins of other reverse engineering frameworks. + +So here are some good to know points for porting: +- All `rizin` specific methods have the leading comment: `# RIZIN SPECIFIC`. +- Please open an issue if you start working on this code for another reverse engineering framework. + We could remove all `rizin` code from this repo and fork our framework specific plugins from it. +- Specifics about the framework code (line indent, variable names etc.) can be set in `PluginInfo.py` + +# Development info + +- The best way to start is to take a look at an instruction in `Hexagon.json`. + We take all information from there and knowing the different objects + makes it easier to understand the code. +- If you need any information about a llvm specific term or variable name from the `Hexagon.json` file a simple + `grep -rn "term" llvm-project/llvm/lib/Target/Hexagon/` will usually help. +- If you parse LLVM data always end it with an exception else statement: + ```python + if x: + ... + elif y: + ... + elif z: + ... + else: + raise ImplementationException("This case seems to be new, please add it.") + ``` +- Names of variables which holds data directly taken from the `Hexagon.json` file + should have a name which starts with +`llvm_`. + + For example: + + - `llvm_in_operands` holds a list with the content of `Hexagon.json::[Instr].InOperandList`. + - `llvm_syntax` holds: `$Rdd8 = combine(#0,#$Ii) ; $Rx16 = add($Rx16in,$Rs16)` (the syntax in LLVM style). + + In case of this duplex Instruction it is actually the LLVM-syntax of the high and + low instruction concatenated with a semicolon. + - `syntax` holds: `Rdd = combine(#0,#Ii) ; Rx = add(Rxin,Rs)` + - `Instruction.operands` is a dictionary which contains `Register` and `Immediate` Python objects. + + +# Contributors + +* Rot127 + +* Anton Kochkov diff --git a/Register.py b/Register.py new file mode 100644 index 00000000..55f47aca --- /dev/null +++ b/Register.py @@ -0,0 +1,155 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import re + +from bitarray import bitarray + +from ImplementationException import ImplementationException +from Operand import Operand + + +class Register(Operand): + """The class which represents a Hexagon Register. + + Attributes: + + - llvm_syntax_name: :class:`str` Name of the register as it is found in the llvm src: Rd32, Pu4, Vd32... + - llvm_reg_class: :class:`str` The register class this register belongs to (Double Register, General Register etc.) + + - is_general: :class:`bool` General registers: R0-R31 + - is_double: :class:`bool` True if pair of register: R0:1 etc. LLVM uses Dx syntax for them: R1:0 = D0, R3:2 = D2 + - is_control: :class:`bool` True if it is a control register. False otherwise. + - is_hvx: :class:`bool` True if it is an HVX register. False otherwise. + - is_guest :class:`bool` True if it is a register of the guest. False otherwise. Only accessible from Guest-Mode + - sub_instr_encoding: :class:`bool` Registers usable by sub instructions. + - is_lower8: :class:`bool` True if one of the lower 8 registers for sub instructions: R0-R7 and D11-D8 + D3-D0 + - is_mod: :class:`bool` True if it is a Mod control register. + - is_is_predicate :class:`bool` True if it is a predicate register. + - is_new_value: :class:`bool` True if it holds a new value within the instruction packet. In syntax: R8.new + """ + + __slots__ = [ + "is_double", + "is_predicate", + "is_control", + "is_system", + "is_new_value", + "llvm_syntax", + "syntax_index", + "is_hvx", + "alias", + "is_general", + "is_lower8", + "sub_instr_encoding", + "is_mod", + "is_guest", + "llvm_reg_class", + "is_vector", + "is_quadruple", + ] + + def __init__( + self, llvm_syntax: str, llvm_reg_class: str, is_new_value: bool, index: int + ): + super(Register, self).__init__(llvm_syntax, llvm_reg_class, index) + self.llvm_syntax = llvm_syntax + self.llvm_reg_class = llvm_reg_class + self.llvm_type = llvm_reg_class + + # Register types + self.is_general = False + self.is_double = False + self.is_quadruple = False + self.is_control = False + self.is_hvx = False + self.is_vector = False + # Register of the guest VM: GELR, GSR, GOSP, G3-15, GPMUCNT4-7, G20-23 etc. + self.is_guest = False + + # Registers usable by sub instructions. This implies a different encoding of the register number because of the + # space constrains for sub instructions. + # For example the use of only 4bits instead of 5: + # 0b0000 = R0, 0b1000 = R16, 0b1111 = R23 + # Once the register number is >0b111 we have to shift the encoding once to the left to get the correct + # register number. + # + # Same for DoubleRegs: + # R5:4 = D2 - Bit encoding: 0b010 + # R17:16 = D8 - Bit encoding: 0b100 + self.sub_instr_encoding = False + self.is_lower8 = False # Register R0-R7 and D11-D8 + D3-D0 + + # Control register sub-types + self.is_mod = False # Modifier register + self.is_predicate = False + + self.is_new_value = is_new_value + + self.parse_reg_type() + + def parse_reg_type(self) -> None: + """Sets flags according the register type.""" + if self.llvm_reg_class == "IntRegs": + self.is_general = True + elif self.llvm_reg_class == "IntRegsLow8": # Register R0-R7 + self.is_general = True + self.is_lower8 = True + elif self.llvm_reg_class == "GeneralSubRegs": # R0-R7, R16-R23 + self.is_general = True + self.sub_instr_encoding = True + elif self.llvm_reg_class == "DoubleRegs": # D0 = R1_0, + self.is_general = True + self.is_double = True + elif ( + self.llvm_reg_class == "GeneralDoubleLow8Regs" + ): # D0,D1,D2,D3,D8,D9,D10,D11 + self.is_general = True + self.sub_instr_encoding = True + self.is_double = True + self.is_lower8 = True + elif self.llvm_reg_class[:3] == "Hvx": + self.is_hvx = True + if self.llvm_reg_class == "HvxQR": + self.is_control = True + self.is_predicate = True + elif self.llvm_reg_class == "HvxVR": + self.is_vector = True + elif self.llvm_reg_class == "HvxWR": # Vector register + self.is_vector = True + self.is_double = True + elif self.llvm_reg_class == "HvxVQR": + self.is_vector = True + self.is_quadruple = True + else: + raise ImplementationException( + "Unhandled HVX register type: {}".format(self.llvm_reg_class) + ) + elif self.llvm_reg_class == "CtrRegs": + self.is_control = True + elif self.llvm_reg_class == "CtrRegs64": + self.is_control = True + self.is_double = True + elif self.llvm_reg_class == "PredRegs": + self.is_control = True + self.is_predicate = True + elif self.llvm_reg_class == "ModRegs": + self.is_control = True + self.is_mod = True + elif self.llvm_reg_class == "GuestRegs": + self.is_guest = True + elif self.llvm_reg_class == "GuestRegs64": # G1:0 = G1_0, G3:2 etc. + self.is_guest = True + self.is_double = True + else: + raise ImplementationException( + "Unhandled register type: {}".format(self.llvm_reg_class) + ) + + # RIZIN SPECIFIC + def add_code_for_opcode_parsing(self, parsing_code: str) -> None: + """Overrides method of parent class. Here we add code which does specific parsing of the operand value on + disassembly. + """ + self.code_opcode_parsing = parsing_code + "; // {}\n".format(self.llvm_syntax) diff --git a/SubInstruction.py b/SubInstruction.py new file mode 100644 index 00000000..53003ca6 --- /dev/null +++ b/SubInstruction.py @@ -0,0 +1,39 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +from enum import Enum, auto + +from ImplementationException import ImplementationException +from Instruction import Instruction +from UnexpectedException import UnexpectedException +from helperFunctions import log, LogLevel + + +class SubInstrNamespace(Enum): + SUBINSN_A = "SUBINSN_A" + SUBINSN_L1 = "SUBINSN_L1" + SUBINSN_L2 = "SUBINSN_L2" + SUBINSN_S1 = "SUBINSN_S1" + SUBINSN_S2 = "SUBINSN_S2" + + +class SubInstruction(Instruction): + def __init__(self, llvm_instruction: dict): + if llvm_instruction["Type"]["def"] != "TypeSUBINSN": + raise UnexpectedException( + "Can not initialize a sub instruction with a normal instruction object:" + + "{}".format(llvm_instruction["!name"]) + ) + super(SubInstruction, self).__init__(llvm_instruction) + + namespace = llvm_instruction["DecoderNamespace"] + try: + self.namespace = SubInstrNamespace[namespace] + # log(self.decoding_namespace, LogLevel.DEBUG) + except KeyError: + raise ImplementationException( + "Sub instruction namespace: {} is not in Enum".format(namespace) + ) + self.is_sub_instruction = True + self.enc_number_representation = None diff --git a/Tests/__init__.py b/Tests/__init__.py new file mode 100644 index 00000000..8f5244c6 --- /dev/null +++ b/Tests/__init__.py @@ -0,0 +1,3 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only diff --git a/Tests/testCodeGeneration.py b/Tests/testCodeGeneration.py new file mode 100644 index 00000000..85ca6a06 --- /dev/null +++ b/Tests/testCodeGeneration.py @@ -0,0 +1,19 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import unittest + +from Instruction import Instruction +from InstructionTemplate import InstructionTemplate +from LLVMImporter import LLVMImporter +from UnexpectedException import UnexpectedException + + +class TestInstruction(unittest.TestCase): + def setUp(self): + self.interface = LLVMImporter("../Hexagon.json", test_mode=True) + self.json = self.interface.hexArch + + def test_code_generation(self) -> None: + pass diff --git a/Tests/testDuplex.py b/Tests/testDuplex.py new file mode 100644 index 00000000..612ac101 --- /dev/null +++ b/Tests/testDuplex.py @@ -0,0 +1,218 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import unittest + +from DuplexInstruction import DuplexInstruction +from Immediate import Immediate +from LLVMImporter import LLVMImporter +from Register import Register +from SubInstruction import SubInstruction +from helperFunctions import log + + +class TestDuplex(unittest.TestCase): + def setUp(self) -> None: + self.interface = LLVMImporter("../Hexagon.json", test_mode=True) + self.json = self.interface.hexArch + + def test_encoding(self) -> None: + # Name: DUPLEX_HIGH_SL2_RETURN_TNEW_LOW_SS2_STOREWI1 + high = SubInstruction(self.json["SL2_return_tnew"]) + low = SubInstruction(self.json["SS2_storewi1"]) + d = DuplexInstruction.get_duplex_i_class_of_instr_pair(low=low, high=high) + + duplex = DuplexInstruction(self.json[d.name], low=low, high=high) + self.assertEqual("1101111101000110EE110001ssssiiii", duplex.encoding.docs_mask) + self.assertEqual( + "if (p0.new) dealloc_return:nt ; memw(Rs+#Ii) = #1", duplex.syntax + ) + self.assertTrue(duplex.encoding.duplex_encoding) + + # DUPLEX_HIGH_SA1_SETI_LOW_SL1_LOADRUB_IO + high = SubInstruction(self.json["SA1_seti"]) + low = SubInstruction(self.json["SL1_loadrub_io"]) + d = DuplexInstruction.get_duplex_i_class_of_instr_pair(low=low, high=high) + + duplex = DuplexInstruction(self.json[d.name], low=low, high=high) + self.assertEqual("010010IIIIIIDDDDEE01iiiissssdddd", duplex.encoding.docs_mask) + self.assertEqual("RD = #II ; Rd = memub(Rs+#Ii)", duplex.syntax) + self.assertTrue(duplex.encoding.duplex_encoding) + + # DUPLEX_HIGH_SA1_COMBINERZ_LOW_SA1_DEC + # $Rdd8 = combine($Rs16,#0) ; $Rd16 = add($Rs16,#$n1) + high = SubInstruction(self.json["SA1_combinezr"]) + low = SubInstruction(self.json["SA1_dec"]) + d = DuplexInstruction.get_duplex_i_class_of_instr_pair(low=low, high=high) + + duplex = DuplexInstruction(self.json[d.name], low=low, high=high) + self.assertEqual("RDD = combine(#0,RS) ; Rd = add(Rs,#n1)", duplex.syntax) + self.assertEqual("00111101SSSS0DDDEE110011ssssdddd", duplex.encoding.docs_mask) + self.assertTrue(duplex.encoding.duplex_encoding) + + def test_parse_instruction(self) -> None: + # TODO + # - actual vs. theoretical new operands, also predicates + # - Actual vs. theoretical indices + # - Operand attributes (new, extendable) + # - Op-type and scale values etc + # - Names + # - Rx and Rxin register + + # self.test_SA1_cmpeqi_SS1_storeb_io() + # self.test_SA1_setin1_SA1_addrx() + pass + + def test_SA1_cmpeqi_SS1_storeb_io(self) -> None: + # p0 = cmp.eq($RS16,#$II) ; memb($Rs16+#$Ii) = $Rt16 + high = SubInstruction(self.json["SA1_cmpeqi"]) + low = SubInstruction(self.json["SS1_storeb_io"]) + d = DuplexInstruction.get_duplex_i_class_of_instr_pair(low=low, high=high) + duplex = DuplexInstruction(self.json[d.name], low=low, high=high) + # Assert high instr. operands + op: Register = duplex.operands["RS16"] + self.assertTrue(op.is_in_operand) + self.assertTrue(op.is_general) + self.assertTrue(op.sub_instr_encoding) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(0, op.syntax_index) + op: Immediate = duplex.operands["II"] + self.assertTrue(op.is_in_operand) + self.assertFalse(op.is_extendable) + self.assertFalse(op.is_signed) + self.assertFalse(op.is_pc_relative) + self.assertFalse(op.is_constant) + self.assertEqual(2, op.encoding_width) + self.assertEqual(0, op.scale) + self.assertEqual(2, op.total_width) + self.assertEqual(1, op.syntax_index) + # Assert low instr. operands + op: Register = duplex.operands["Rs16"] + self.assertTrue(op.is_in_operand) + self.assertTrue(op.is_general) + self.assertTrue(op.sub_instr_encoding) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(2, op.syntax_index) + op: Immediate = duplex.operands["Ii"] + self.assertTrue(op.is_in_operand) + self.assertFalse(op.is_extendable) + self.assertFalse(op.is_signed) + self.assertFalse(op.is_pc_relative) + self.assertFalse(op.is_constant) + self.assertEqual(4, op.encoding_width) + self.assertEqual(0, op.scale) + self.assertEqual(4, op.total_width) + self.assertEqual(3, op.syntax_index) + op: Register = duplex.operands["Rt16"] + self.assertTrue(op.is_in_operand) + self.assertTrue(op.sub_instr_encoding) + self.assertTrue(op.is_general) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(4, op.syntax_index) + + def test_SA1_setin1_SA1_addrx(self) -> None: + # $Rd16 = #$n1 ; $Rx16 = add($Rx16in,$Rs16) + high = SubInstruction(self.json["SA1_setin1"]) + low = SubInstruction(self.json["SA1_addrx"]) + d = DuplexInstruction.get_duplex_i_class_of_instr_pair(low=low, high=high) + duplex = DuplexInstruction(self.json[d.name], low=low, high=high) + # Assert high instr. operands + op: Register = duplex.operands["Rd16"] + self.assertTrue(op.is_out_operand) + self.assertTrue(op.is_general) + self.assertTrue(op.sub_instr_encoding) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(0, op.syntax_index) + op: Immediate = duplex.operands["n1"] + self.assertTrue(op.is_in_operand) + self.assertTrue(op.is_constant) + self.assertFalse(op.is_extendable) + self.assertTrue(op.is_signed) + self.assertFalse(op.is_pc_relative) + self.assertEqual(1, op.syntax_index) + # Assert low instr. operands + op: Register = duplex.operands["Rx16"] + self.assertTrue(op.is_out_operand) + self.assertTrue(op.is_general) + self.assertTrue(op.sub_instr_encoding) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(2, op.syntax_index) + op: Register = duplex.operands["Rx16in"] + self.assertTrue(op.is_in_operand) + self.assertTrue(op.is_general) + self.assertTrue(op.sub_instr_encoding) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(3, op.syntax_index) + op: Register = duplex.operands["Rs16"] + self.assertTrue(op.is_in_operand) + self.assertTrue(op.sub_instr_encoding) + self.assertTrue(op.is_general) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(4, op.syntax_index) + + def test_SA1_addi_SL1_loadri_io(self) -> None: + # $Rx16 = add($Rx16in,#$II) ; $Rd16 = memw($Rs16+#$Ii) + high = SubInstruction(self.json["SA1_addi"]) + low = SubInstruction(self.json["SL1_loadri_io"]) + d = DuplexInstruction.get_duplex_i_class_of_instr_pair(low=low, high=high) + duplex = DuplexInstruction(self.json[d.name], low=low, high=high) + + # High instruction + op: Register = duplex.operands["Rx16"] + self.assertTrue(op.is_out_operand) + self.assertTrue(op.is_general) + self.assertTrue(op.sub_instr_encoding) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(0, op.syntax_index) + op: Register = duplex.operands["Rx16in"] + self.assertTrue(op.is_in_operand) + self.assertTrue(op.is_general) + self.assertTrue(op.sub_instr_encoding) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(1, op.syntax_index) + op: Immediate = duplex.operands["II"] + self.assertTrue(op.is_in_operand) + self.assertTrue(op.is_extendable) + self.assertTrue(op.is_signed) + self.assertFalse(op.is_pc_relative) + self.assertFalse(op.is_constant) + self.assertEqual(32, op.encoding_width) + self.assertEqual(0, op.scale) + self.assertEqual(32, op.total_width) + self.assertEqual(2, op.syntax_index) + + # Assert low instr. operands + op: Register = duplex.operands["Rd16"] + self.assertTrue(op.is_out_operand) + self.assertTrue(op.is_general) + self.assertTrue(op.sub_instr_encoding) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(3, op.syntax_index) + op: Register = duplex.operands["Rs16"] + self.assertTrue(op.is_in_operand) + self.assertTrue(op.sub_instr_encoding) + self.assertTrue(op.is_general) + self.assertFalse(op.is_lower8) + self.assertFalse(op.is_new_value) + self.assertEqual(4, op.syntax_index) + op: Immediate = duplex.operands["Ii"] + self.assertTrue(op.is_in_operand) + self.assertFalse(op.is_extendable) + self.assertFalse(op.is_signed) + self.assertFalse(op.is_pc_relative) + self.assertFalse(op.is_constant) + self.assertEqual(4, op.encoding_width) + self.assertEqual(2, op.scale) + self.assertEqual(6, op.total_width) + self.assertEqual(5, op.syntax_index) diff --git a/Tests/testEncoding.py b/Tests/testEncoding.py new file mode 100644 index 00000000..d068a72c --- /dev/null +++ b/Tests/testEncoding.py @@ -0,0 +1,126 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +from bitarray import bitarray +import unittest + +import PluginInfo +from DuplexInstruction import DuplexInstruction +from LLVMImporter import LLVMImporter +from InstructionEncoding import InstructionEncoding +from Operand import Operand +from SubInstruction import SubInstruction + + +class TestInstructionEncoding(unittest.TestCase): + def setUp(self) -> None: + self.interface = LLVMImporter("../Hexagon.json", test_mode=True) + self.json = self.interface.hexArch + + def test_manual_mask(self) -> None: + self.assertEqual( + "011111000IIIIIIIPPIiiiiiiiiddddd", + InstructionEncoding(self.json["A2_combineii"]["Inst"]).docs_mask, + ) + self.assertEqual( + "11110101000sssssPP0ttttt000ddddd", + InstructionEncoding(self.json["A2_combinew"]["Inst"]).docs_mask, + ) + self.assertEqual( + "1011iiiiiiisssssPPiiiiiiiiiddddd", + InstructionEncoding(self.json["A2_addi"]["Inst"]).docs_mask, + ) + self.assertEqual( + "0000iiiiiiiiiiiiPPiiiiiiiiiiiiii", + InstructionEncoding(self.json["A4_ext"]["Inst"]).docs_mask, + ) + + def test_bit_masks(self) -> None: + # Initializing a bitarray with a string, it interprets the bit most to the right as the MSB. + # In the manual the MSB is the left most. + # Therefore we reverse the string here. + self.assertEqual( + bitarray("00000000000000000000000000011111"[::-1], endian="little"), + InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks[ + "Rdd32" + ], + ) + self.assertEqual( + bitarray("00000000000000000001111111100000"[::-1], endian="little"), + InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks["Ii"], + ) + self.assertEqual( + bitarray("00000000011111110010000000000000"[::-1], endian="little"), + InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks["II"], + ) + + self.assertEqual( + bitarray("00000000000000000001111100000000"[::-1], endian="little"), + InstructionEncoding(self.json["A2_combinew"]["Inst"]).operand_masks["Rt32"], + ) + self.assertEqual( + bitarray("00000000000111110000000000000000"[::-1], endian="little"), + InstructionEncoding(self.json["A2_combinew"]["Inst"]).operand_masks["Rs32"], + ) + self.assertEqual( + bitarray("00001111111111110011111111111111"[::-1], endian="little"), + InstructionEncoding(self.json["A4_ext"]["Inst"]).operand_masks["Ii"], + ) + + def test_get_i_class(self) -> None: + self.assertEqual( + 0xD, InstructionEncoding(self.json["A2_addh_h16_hh"]["Inst"]).get_i_class() + ) + + high = SubInstruction(self.json["SL2_return_tnew"]) + low = SubInstruction(self.json["SS2_storewi1"]) + d = DuplexInstruction.get_duplex_i_class_of_instr_pair(low=low, high=high) + + duplex = DuplexInstruction(self.json[d.name], low=low, high=high) + + self.assertEqual(0xD, duplex.encoding.get_i_class()) + + def test_num_representation(self) -> None: + self.assertEqual( + 0b1111101000110, + InstructionEncoding( + self.json["SL2_return_tnew"]["Inst"] + ).num_representation, + ) + + def test_correct_operand_names(self) -> None: + # TODO + pass + + # RIZIN SPECIFIC + def test_shifting_c_code(self) -> None: + hex_insn = PluginInfo.HEX_INSTR_VAR_SYNTAX + + self.assertEqual( + "((({}) & 0x1fe0) >> 5)".format(hex_insn), + Operand.make_sparse_mask( + InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks[ + "Ii" + ] + ), + ) + self.assertEqual( + "(((({}) & 0x7f0000) >> 15) | ((({}) & 0x2000) >> 13))".format( + hex_insn, hex_insn + ), + Operand.make_sparse_mask( + InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks[ + "II" + ] + ), + ) + + self.assertEqual( + "(((({}) & 0xfff0000) >> 2) | ((({}) & 0x3fff) >> 0))".format( + hex_insn, hex_insn + ), + Operand.make_sparse_mask( + InstructionEncoding(self.json["A4_ext"]["Inst"]).operand_masks["Ii"] + ), + ) diff --git a/Tests/testHelperFunction.py b/Tests/testHelperFunction.py new file mode 100644 index 00000000..4d2c76e5 --- /dev/null +++ b/Tests/testHelperFunction.py @@ -0,0 +1,62 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import unittest + +from bitarray import bitarray + +from helperFunctions import bitarray_to_uint, list_to_bitarray, list_to_int + + +class TestHelperFunction(unittest.TestCase): + def test_list_to_bitarray(self): + array = list_to_bitarray([0, 0, 1], endian="little") + self.assertEqual(bitarray("001", endian="little"), array) + + array = list_to_bitarray([0, 0, 1], endian="big") + self.assertEqual(bitarray("001", endian="big"), array) + + array = list_to_bitarray([1, 0, 0], endian="little") + self.assertEqual(bitarray("100", endian="little"), array) + + array = list_to_bitarray([1, 0, 0], endian="big") + self.assertEqual(bitarray("100", endian="big"), array) + + def test_bitarray_to_int(self): + n = bitarray_to_uint(bitarray("001"), endian="little") + self.assertEqual(4, n) + + n = bitarray_to_uint(bitarray("001"), endian="big") + self.assertEqual(1, n) + + n = bitarray_to_uint(bitarray("010"), endian="little") + self.assertEqual(2, n) + + n = bitarray_to_uint(bitarray("010"), endian="big") + self.assertEqual(2, n) + + n = bitarray_to_uint(bitarray("011"), endian="little") + self.assertEqual(6, n) + + n = bitarray_to_uint(bitarray("011"), endian="big") + self.assertEqual(3, n) + + def test_list_to_int(self): + n = list_to_int([0, 0, 1], endian="little") + self.assertEqual(4, n) + + n = list_to_int([0, 0, 1], endian="big") + self.assertEqual(1, n) + + n = list_to_int([0, 1, 0], endian="little") + self.assertEqual(2, n) + + n = list_to_int([0, 1, 0], endian="big") + self.assertEqual(2, n) + + n = list_to_int([0, 1, 1], endian="little") + self.assertEqual(6, n) + + n = list_to_int([0, 1, 1], endian="big") + self.assertEqual(3, n) diff --git a/Tests/testImmediate.py b/Tests/testImmediate.py new file mode 100644 index 00000000..c441e8e3 --- /dev/null +++ b/Tests/testImmediate.py @@ -0,0 +1,92 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import unittest + +from DuplexInstruction import DuplexInstruction +from Immediate import Immediate +from Instruction import Instruction +from LLVMImporter import LLVMImporter +from Register import Register +from helperFunctions import log, LogLevel + + +class TestImmediate(unittest.TestCase): + def setUp(self) -> None: + self.interface = LLVMImporter("../Hexagon.json", test_mode=True) + self.json = self.interface.hexArch + + def test_immediate_initialization(self): + # Syntax (llvm): $Rd32 = mux($Pu4,#$Ii,#$II) + instr = Instruction(self.json["C2_muxii"]) + imm = instr.operands["Ii"] + self.assertTrue(imm.is_signed) + self.assertTrue(imm.is_extendable) + self.assertEqual(2, imm.syntax_index) + self.assertEqual(32, imm.total_width) + self.assertEqual(0, imm.scale) + self.assertEqual(32, imm.encoding_width) + self.assertEqual("s32_0Imm", imm.llvm_type) + self.assertEqual("Ii", imm.llvm_syntax) + + imm = instr.operands["II"] + self.assertTrue(imm.is_signed) + self.assertFalse(imm.is_extendable) + self.assertEqual(3, imm.syntax_index) + self.assertEqual(8, imm.total_width) + self.assertEqual(0, imm.scale) + self.assertEqual(8, imm.encoding_width) + self.assertEqual("s8_0Imm", imm.llvm_type) + self.assertEqual("II", imm.llvm_syntax) + + # J2_jump + instr = Instruction(self.json["J2_jump"]) + imm = instr.operands["Ii"] + self.assertTrue(imm.is_signed) + self.assertTrue(imm.is_extendable) + self.assertTrue(imm.is_pc_relative) + self.assertEqual(0, imm.syntax_index) + self.assertEqual(32, imm.total_width) + self.assertEqual(2, imm.scale) + self.assertEqual(30, imm.encoding_width) + self.assertEqual("b30_2Imm", imm.llvm_type) + self.assertEqual("Ii", imm.llvm_syntax) + + def test_extendable_imm_coverage(self): + for llvm_instr_name in [ + name + for name, i in self.interface.llvm_instructions.items() + if i["isExtendable"][0] and "OpcodeDuplex" not in i["!superclasses"] + ]: + c = 0 + instructions = self.interface.normal_instructions + instructions.update(self.interface.sub_instructions) + for op_name, op in instructions[llvm_instr_name].operands.items(): + if isinstance(op, Immediate) and op.is_extendable: + c += 1 + if c != 1: + log( + "Extendable immediate not set in instruction: {}".format( + llvm_instr_name + ), + LogLevel.ERROR, + ) + self.assertEqual(1, c) + + # Duplex instructions + for duplex_name in self.interface.duplex_instructions_names: + d_instr: DuplexInstruction = self.interface.duplex_instructions[duplex_name] + if d_instr.has_extendable_imm: + c = 0 + for op_name, op in d_instr.operands.items(): + if isinstance(op, Immediate) and op.is_extendable: + c += 1 + if c != 1: + log( + "Extendable immediate not set in instruction: {}".format( + d_instr.llvm_syntax + ), + LogLevel.ERROR, + ) + self.assertEqual(1, c) diff --git a/Tests/testInstruction.py b/Tests/testInstruction.py new file mode 100644 index 00000000..890001dc --- /dev/null +++ b/Tests/testInstruction.py @@ -0,0 +1,101 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import unittest + +from Instruction import Instruction +from InstructionTemplate import InstructionTemplate +from UnexpectedException import UnexpectedException +from helperFunctions import normalize_llvm_syntax + + +class TestInstruction(unittest.TestCase): + + # TODO Indices for: V6_vS32b_nt_new_pred_ppu: "if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new" + + # TODO + # - actual vs. theoretical new operands, also predicates + # - Actual vs. theoretical indices + # - Operand attributes (new, extendable) + # - Op-type and scale values etc + # - Names + # - Rx and Rxin register + + def test_normalize_llvm_syntax(self) -> None: + self.assertEqual( + "Rdd = add(Rs,Rtt)", normalize_llvm_syntax("$Rdd32 = add($Rs32,$Rtt32)") + ) + self.assertEqual( + "RDD = add(RS,RTT)", normalize_llvm_syntax("$RDD32 = add($RS32,$RTT32)") + ) + self.assertEqual( + "Vxx.w += vmpy(Vu.h,Vv.h)", + normalize_llvm_syntax("$Vxx32.w += vmpy($Vu32.h,$Vv32.h)"), + ) + self.assertEqual( + "Rd = add(Rt.h,Rs.h):<<16", + normalize_llvm_syntax("$Rd32 = add($Rt32.h,$Rs32.h):<<16"), + ) + self.assertEqual( + "if (!Pu) Rd = add(Rs,Rt)", + normalize_llvm_syntax("if (!$Pu4) $Rd32 = add($Rs32,$Rt32)"), + ) + # Specifically named registers + self.assertEqual( + "if (p0.new) dealloc_return:nt", + normalize_llvm_syntax("if (p0.new) dealloc_return:nt"), + ) + self.assertEqual( + "if (!p0.new) jumpr:nt r31", + normalize_llvm_syntax("if (!p0.new) jumpr:nt r31"), + ) + # Duplex + self.assertEqual( + "Rx = add(Rxin,#II) ; Rd = memw(Rs+#Ii)", + normalize_llvm_syntax( + "$Rx16 = add($Rx16in,#$II) ; $Rd16 = memw($Rs16+#$Ii)" + ), + ) + + def test_get_syntax_operand_indices(self) -> None: + syntax = "$RDD8 = combine($RS16,#0) ; $Rd16 = add($Rs16,#$n1)" + operands = [["", "Rd16"], ["", "Rs16"], ["", "RDD8"], ["", "RS16"], ["", "n1"]] + correct_order = {"RDD8": 0, "RS16": 1, "Rd16": 2, "Rs16": 3, "n1": 4} + self.assertEqual( + correct_order, + InstructionTemplate.get_syntax_operand_indices(syntax, operands), + ) + + syntax = "$Rd32 = add($Rs32,#$Ii)" + operands = [["", "Rd32"], ["", "Ii"], ["", "Rs32"]] + correct_order = {"Rd32": 0, "Rs32": 1, "Ii": 2} + self.assertEqual( + correct_order, + InstructionTemplate.get_syntax_operand_indices(syntax, operands), + ) + + syntax = "$Rx16 = add($Rx16in,#$II) ; $Rd16 = memw($Rs16+#$Ii)" + operands = [ + ["", "Rx16"], + ["", "Rx16in"], + ["", "II"], + ["", "Rd16"], + ["", "Rs16"], + ["", "Ii"], + ] + correct_order = {"Rx16": 0, "Rx16in": 1, "II": 2, "Rd16": 3, "Rs16": 4, "Ii": 5} + self.assertEqual( + correct_order, + InstructionTemplate.get_syntax_operand_indices(syntax, operands), + ) + + syntax = "$Rd32 = add($Rs32,#$Ii)" + operands = [["", "Ii"], ["", "Ii"], ["", "Rs32"]] + with self.assertRaises(UnexpectedException) as context: + InstructionTemplate.get_syntax_operand_indices(syntax, operands) + self.assertTrue( + "Two operands with the same name given.\n" + + "Syntax $Rd32 = add($Rs32,#$Ii), op: Ii" + in str(context.exception) + ) diff --git a/Tests/testRegister.py b/Tests/testRegister.py new file mode 100644 index 00000000..f4341113 --- /dev/null +++ b/Tests/testRegister.py @@ -0,0 +1,44 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import unittest + +from Instruction import Instruction +from LLVMImporter import LLVMImporter +from helperFunctions import log + + +class TestRegister(unittest.TestCase): + def setUp(self) -> None: + self.interface = LLVMImporter("../Hexagon.json", test_mode=True) + self.json = self.interface.hexArch + + def test_parse_reg_type(self): + # Syntax (llvm): "if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new" + instr = Instruction(self.json["V6_vS32b_nt_new_pred_ppu"]) + operand = instr.operands["Os8"] + self.assertEqual(0, instr.operands["Pv4"].syntax_index) + self.assertEqual( + 1, instr.operands["Rx32"].syntax_index + ) # Rx32 is also an out operand because of the ++ + # self.assertEqual(2, instr.operands["Rx32in"].index) + self.assertEqual(2, instr.operands["Mu2"].syntax_index) + self.assertEqual(3, instr.operands["Os8"].syntax_index) + self.assertEqual(3, instr.new_operand_index) + self.assertTrue(operand.is_new_value) + + # Syntax (llvm): "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new" + instr = Instruction(self.json["S4_pstorerinewtnew_rr"]) + operand = instr.operands["Pv4"] + self.assertTrue(operand.is_new_value) + self.assertTrue(operand.is_predicate) + + operand = instr.operands["Nt8"] + self.assertTrue(operand.is_new_value) + + self.assertEqual(0, instr.operands["Pv4"].syntax_index) + self.assertEqual(1, instr.operands["Rs32"].syntax_index) + self.assertEqual(2, instr.operands["Ru32"].syntax_index) + self.assertEqual(3, instr.operands["Ii"].syntax_index) + self.assertEqual(4, instr.operands["Nt8"].syntax_index) diff --git a/UnexpectedException.py b/UnexpectedException.py new file mode 100644 index 00000000..66efe285 --- /dev/null +++ b/UnexpectedException.py @@ -0,0 +1,8 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + + +class UnexpectedException(Exception): + def __init__(self, message): + super().__init__(message) diff --git a/__init__.py b/__init__.py new file mode 100644 index 00000000..8f5244c6 --- /dev/null +++ b/__init__.py @@ -0,0 +1,3 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only diff --git a/clang-format.py b/clang-format.py new file mode 100755 index 00000000..ddb9ca25 --- /dev/null +++ b/clang-format.py @@ -0,0 +1,140 @@ +#!/usr/bin/env python3 +# +# SPDX-FileCopyrightText: 2021 Anton Kochkov +# SPDX-License-Identifier: LGPL-3.0-only + +import argparse +import glob +import itertools +import subprocess +import sys + +from git import Repo + +dirlist = [ + "binrz", + "librz", + "shlr/ar", + "shlr/bochs", + "shlr/gdb", + "shlr/java", + "shlr/ptrace-wrap", + "shlr/qnx", + "shlr/rar", + "shlr/tcc", + "shlr/w32dbg_wrap", + "shlr/winkd", + "test/unit", +] + +skiplist = [ + "/gnu/", + "librz/asm/arch/vax/", + "librz/asm/arch/riscv/", + "librz/asm/arch/sh/gnu/", + "librz/asm/arch/i8080/", + "librz/asm/arch/z80/", + "librz/asm/arch/avr/", + "librz/asm/arch/arm/aarch64/", + "librz/hash/xxhash/", + "librz/bin/mangling/cxx/", + "librz/util/bdiff.c", + "librz/asm/arch/tms320/c55x/table.h", +] + +patterns = ["*.c", "*.cpp", "*.h", "*.hpp", "*.inc"] + + +def should_scan(filename): + return any(directory in filename for directory in dirlist) and any( + pattern[1:] in filename for pattern in patterns + ) + + +def skip(filename): + return any(skipfile in filename for skipfile in skiplist) + + +def get_matching_files(): + for directory, pattern in itertools.product(dirlist, patterns): + for filename in glob.iglob(directory + "/**/" + pattern, recursive=True): + if not skip(filename): + yield filename + + +def get_edited_files(args): + repo = Repo() + + for diff in repo.index.diff(args.diff): + filename = diff.a_path + if should_scan(filename) and not skip(filename): + yield filename + + +def build_command(check, filenames): + if check: + return ["clang-format", "--style=file", "--Werror", "--dry-run"] + filenames + + return ["clang-format", "--style=file", "-i"] + filenames + + +def format_files(args, files): + if len(files) == 0: + print("No C files to format.") + sys.exit(0) + cmd = build_command(args.check, files) + if args.verbose: + print(cmd) + r = subprocess.run(cmd, check=False) + sys.exit(r.returncode) + + +def get_file(args): + filename = args.file + if should_scan(filename) and not skip(filename): + return [filename] + + return [] + + +def get_files(args): + if args.diff: + return get_edited_files(args) + + if args.file: + return get_file(args) + + return get_matching_files() + + +def process(args): + files = get_files(args) + format_files(args, list(files)) + + +def parse(): + parser = argparse.ArgumentParser(description="Clang format the rizin project") + parser.add_argument( + "-c", "--check", action="store_true", help="enable the check mode" + ) + parser.add_argument( + "-v", "--verbose", action="store_true", help="use verbose output" + ) + parser.add_argument("-f", "--file", help="formats (or checks) only the given file") + parser.add_argument( + "-d", + "--diff", + type=str, + default=None, + help="format all modified file related to branch", + ) + return parser.parse_args() + + +def main(): + args = parse() + process(args) + + +if __name__ == "__main__": + main() diff --git a/const_extenders.txt b/const_extenders.txt deleted file mode 100644 index d34242d5..00000000 --- a/const_extenders.txt +++ /dev/null @@ -1,293 +0,0 @@ -call #r22:2 // + -if (!cmp.eq(Ns.new,#U5)) jump:nt #r9:2 // + -if (cmp.eq(Ns.new,#U5)) jump:nt #r9:2 // + -if (!cmp.eq(Ns.new,#U5)) jump:t #r9:2 // + -if (cmp.eq(Ns.new,#U5)) jump:t #r9:2 // + -if (!cmp.gt(Ns.new,#U5)) jump:nt #r9:2 // + -if (cmp.gt(Ns.new,#U5)) jump:nt #r9:2 // + -if (!cmp.gt(Ns.new,#U5)) jump:t #r9:2 // + -if (cmp.gt(Ns.new,#U5)) jump:t #r9:2 // + -if (!cmp.gtu(Ns.new,##U5)) jump:nt #r9:2 // + -if (cmp.gtu(Ns.new,##U5)) jump:nt #r9:2 // + -if (!cmp.gtu(Ns.new,##U5)) jump:t #r9:2 // + -if (cmp.gtu(Ns.new,##U5)) jump:t #r9:2 // + -if !Ps memw(Rs + #u6) = ##U32 // + -if Ps memw(Rs + #u6) = ##U32 // + -if (!Pt) memb(#u6) = Nt.new // + -if (Pt) memb(#u6) = Nt.new // + -if (!Pt) memb(#u6) = Rt // + -if (Pt) memb(#u6) = Rt // + -if (!Pt) memd(Rs + ##U32) = Ntt.new // + -if (Pt) memd(Rs + ##U32) = Ntt.new // + -if (!Pt) memd(#u6) = Rt.new // + -if (Pt) memd(#u6) = Rt.new // + -if (!Pt) memd(#u6) = Rtt // + -if (Pt) memd(#u6) = Rtt // + -if (!Pt) memh(#u6) = Nt.new // + -if (Pt) memh(#u6) = Nt.new // + -if (!Pt) memh(#u6) = Rt // + -if (Pt) memh(#u6) = Rt // + -if (!Pt) memw(Rs + ##U32) = Rt.new // + -if (Pt) memw(Rs + ##U32) = Rt.new // + -if (!Pt) memw(#u6) = Nt.new // + -if (Pt) memw(#u6) = Nt.new // + -if (!Pt) memw(#u6) = Rt // + -if (Pt) memw(#u6) = Rt // + -if (!Pt.new) memd(Rs + ##U32) = Ntt.new // + -if (Pt.new) memd(Rs + ##U32) = Ntt.new // + -if (!Pt.new) memw(Rs + ##U32) = Rt.new // + -if (Pt.new) memw(Rs + ##U32) = Rt.new // + -if (!Pt.new) memw(Rs + #u6:2) = Rt // + -if (Pt.new) memw(Rs + #u6:2) = Rt // + -if (!Pt.new) Rdd = memd (Rs + #u6:3) // + -if (Pt.new) Rdd = memd (Rs + #u6:3) // + -if (!Pt.new) Rdd = memd (#u6) // + -if (Pt.new) Rdd = memd (#u6) // + -if (!Pt.new) Rd = memb (Rs + #u6:0) // + -if (Pt.new) Rd = memb (Rs + #u6:0) // + -if (!Pt.new) Rd = memb (#u6) // + -if (Pt.new) Rd = memb (#u6) // + -if (!Pt.new) Rd = memh (Rs + #u6:1) // + -if (Pt.new) Rd = memh (Rs + #u6:1) // + -if (!Pt.new) Rd = memh (#u6) // + -if (Pt.new) Rd = memh (#u6) // + -if (!Pt.new) Rd = memub (Rs + #u6:0) // + -if (Pt.new) Rd = memub (Rs + #u6:0) // + -if (!Pt.new) Rd = memub (#u6) // + -if (Pt.new) Rd = memub (#u6) // + -if (!Pt.new) Rd = memuh (Rs + #u6:1) // + -if (Pt.new) Rd = memuh (Rs + #u6:1) // + -if (!Pt.new) Rd = memuh (#u6) // + -if (Pt.new) Rd = memuh (#u6) // + -if (!Pt.new) Rd = memw (Rs + #u6:2) // + -if (Pt.new) Rd = memw (Rs + #u6:2) // + -if (!Pt.new) Rd = memw (#u6) // + -if (Pt.new) Rd = memw (#u6) // + -if (!Pt) Rdd = memd (Rs + #u6:3) // + -if (Pt) Rdd = memd (Rs + #u6:3) // + -if (!Pt) Rdd = memd (#u6) // + -if (Pt) Rdd = memd (#u6) // + -if (!Pt) Rd = memb (Rs + #u6:0) // + -if (Pt) Rd = memb (Rs + #u6:0) // + -if (!Pt) Rd = memb (#u6) // + -if (Pt) Rd = memb (#u6) // + -if (!Pt) Rd = memh (Rs + #u6:1) // + -if (Pt) Rd = memh (Rs + #u6:1) // + -if (!Pt) Rd = memh (#u6) // + -if (Pt) Rd = memh (#u6) // + -if (!Pt) Rd = memub (Rs + #u6:0) // + -if (Pt) Rd = memub (Rs + #u6:0) // + -if (!Pt) Rd = memub (#u6) // + -if (Pt) Rd = memub (#u6) // + -if (!Pt) Rd = memuh (Rs + #u6:1) // + -if (Pt) Rd = memuh (Rs + #u6:1) // + -if (!Pt) Rd = memuh (#u6) // + -if (Pt) Rd = memuh (#u6) // + -if (!Pt) Rd = memw (Rs + #u6:2) // + -if (Pt) Rd = memw (Rs + #u6:2) // + -if (!Pt) Rd = memw (#u6) // + -if (Pt) Rd = memw (#u6) // + -if (!Pu) call #r15:2 // + -if (Pu) call #r15:2 // + -if (!Pu.new) Rd = add(Rs,#s8) // + -if (Pu.new) Rd = add(Rs,#s8) // + -if (!Pu.new) Rd = #s12 // + -if (Pu.new) Rd = #s12 // + -if (!Pu) Rd = add(Rs,#s8) // + -if (Pu) Rd = add(Rs,#s8) // + -if (!Pu) Rd = #s12 // + -if (Pu) Rd = #s12 // + -if (!Pv) memw(#u6) = Rt // + -if (Pv) memw(#u6) = Rt // + -if (!Pv) memw(#u6) = Nt.new // + -if (Pv) memw(#u6) = Nt.new // + -if (!Pv) memb(Rs + #u6:0) = Rt // + -if (Pv) memb(Rs + #u6:0) = Rt // + -if (!Pv) memb(Rs + #u6:0) = Rt.new // + -if (Pv) memb(Rs + #u6:0) = Rt.new // + -if (!Pv) memd(Rs + #u6:3) = Rtt // + -if (Pv) memd(Rs + #u6:3) = Rtt // + -if (!Pv) memh(Rs + #u6:1) = Rt // + -if (Pv) memh(Rs + #u6:1) = Rt // + -if (!Pv) memh(Rs + #u6:1) = Rt.new // + -if (Pv) memh(Rs + #u6:1) = Rt.new // + -if (!Pv) memw(Rs + #u6:2) = Rt // + -if (Pv) memw(Rs + #u6:2) = Rt // + -if (!Pv.new) memw(#u6) = Rt // + -if (Pv.new) memw(#u6) = Rt // + -if (!Pv.new) memw(#u6) = Nt.new // + -if (Pv.new) memw(#u6) = Nt.new // + -if (!Pv.new) memb(Rs + #u6:0) = Rt // + -if (Pv.new) memb(Rs + #u6:0) = Rt // + -if (!Pv.new) memb(Rs + #u6:0) = Rt.new // + -if (Pv.new) memb(Rs + #u6:0) = Rt.new // + -if (!Pv.new) memd(Rs + #u6:3) = Rtt // + -if (Pv.new) memd(Rs + #u6:3) = Rtt // + -if (!Pv.new) memh(Rs + #u6:1) = Rt // + -if (Pv.new) memh(Rs + #u6:1) = Rt // + -if (!Pv.new) memh(Rs + #u6:1) = Rt.new // + -if (Pv.new) memh(Rs + #u6:1) = Rt.new // + -if (!Pv.new) memw(Rs + #u6:2) = Rt // + -if (Pv.new) memw(Rs + #u6:2) = Rt // + -jump #r22:2 // + -loop0 (#r7:2,Rs) // + -loop0 (#r7:2,#U10) // + -loop1 (#r7:2,Rs) // + -loop1 (#r7:2,#U10) // + -memb(gp+#u16:0) = Nt.new // + -memb(gp+#u16:0) = Rt // + -memb(Re=##U32) = Rt.new // + -memb(Re=#U6) = Rt // + -memb(Rs + #s11:0) = Nt.new // + -memb(Rs + #s11:0) = Rt // + -memb(Rs + #u6:0) = #S8 // + -memb(Ru<<#u2 + #U6) = Nt.new // + -memb(Ru<<#u2 + #U6) = Rt // + -memd(gp+#u16:0) = Nt.new // + -memd(gp+#u16:0) = Rtt // + -memd(Re=##U32) = Rt.new // + -memd(Re=#U6) = Rtt // + -memd(Rs + #s11:3) = Ntt.new // + -memd(Rs + #s11:3) = Rtt // + -memd(Ru<<#u2 + #U6) = Nt.new // + -memd(Ru<<#u2 + #U6) = Rtt // + -memh(gp+#u16:0) = Nt.new // + -memh(gp+#u16:0) = Rt // + -memh(Re=##U32) = Rt.new // + -memh(Re=#U6) = Rt // + -memh(Rs + #s11:1) = Nt.new // + -memh(Rs + #s11:1) = Rt // + -memh(Rs + #u6:1) = #S8 // + -memh(Ru<<#u2 + #U6) = Nt.new // + -memh(Ru<<#u2 + #U6) = Rt // + -memw(gp+#u16:0) = Nt.new // + -memw(gp+#u16:0) = Rt // + -memw(Re=##U32) = Rt.new // + -memw(Re=#U6) = Rt // + -memw(Rs + Rt<<#u2) = ##U32 // + -memw(Rs + #s11:2) = Nt.new // + -memw(Rs + #s11:2) = Rt // + -memw(Rs + #u6:2) = #S8 // + -memw(Rs + #u6) = ##U32 // + -memw(Ru<<#u2 + #U6) = Nt.new // + -memw(Ru<<#u2 + #U6) = Rt // + -Pd = cmpb.eq (Rs,#u8) // + -Pd = cmpb.gt (Rs,#s8) // + -Pd = cmpb.gtu (Rs,#u7) // + -Pd = !cmp.eq (Rs,#s10) // + -Pd = cmp.eq (Rs,#s10) // + -Pd = !cmp.gt (Rs,#s10) // + -Pd = cmp.gt (Rs,#s10) // + -Pd = !cmp.gtu (Rs,#u9) // + -Pd = cmp.gtu (Rs,#u9) // + -Pd = cmph.eq (Rs,#s8) // + -Pd = cmph.gt (Rs,#s8) // + -Pd = cmph.gtu (Rs,#u7) // + -Pd = sp1loop0(#r7:2,Rs) // + -Pd = sp1loop0(#r7:2,#U10) // + -Pd = sp2loop0(#r7:2,Rs) // + -Pd = sp2loop0(#r7:2,#U10) // + -Pd = sp3loop0(#r7:2,Rs) // + -Pd = sp3loop0(#r7:2,#U10) // + -Rd = add(#6,mpyi(Rs,Rt)) // + -Rd = add(pc,#u6) // + -Rd = add(Rs,add(Ru,#s6)) // + -Rd = add(Rs,#s16) // + -Rd = add(Rs,sub(#s6,Ru)) // + -Rd = add(#u6,mpyi(Rs,#u6)) // + -Rd = and(Rs,#s10) // + -Rd = !cmp.eq(Rs,#s8) // + -Rd = cmp.eq(Rs,#s8) // + -Rdd = combine(Rs,#s8) // + -Rdd = combine(#s8,Rs) // + -Rdd = combine(#s8,#s8) // + -Rdd = combine (#s8,#S8) // + -Rdd = combine(#s8,#U6) // + -Rdd = memd (Re=#U6) // + -Rdd = memd (Rs + #s11:3) // + -Rdd = memd (Rt<<#u2 + #U6) // + -Rd = memb (Re=#U6) // + -Rd = memb (Rs + #s11:0) // + -Rd = memb (Rt<<#u2 + #U6) // + -Rd = memb(##U32) // + -Rd = memd(##U32) // + -Rd = memh (Re=#U6) // + -Rd = memh (Rs + #s11:1) // + -Rd = memh (Rt<<#u2 + #U6) // + -Rd = memh(##U32) // + -Rd = memub (Re=#U6) // + -Rd = memub (Rs + #s11:0) // + -Rd = memub (Rt<<#u2 + #U6) // + -Rd = memub(##U32) // + -Rd = memuh (Re=#U6) // + -Rd = memuh (Rs + #s11:1) // + -Rd = memuh (Rt<<#u2 + #U6) // + -Rd = memuh(##U32) // + -Rd = memw (Re=#U6) // + -Rd = memw (Rs + #s11:2) // + -Rd = memw (Rt<<#u2 + #U6) // + -Rd = memw(##U32) // + -Rd = memw (gp + #u16:2) // + -Rd = memw (Re=#U6) // + -Rd = memw (Rs + #s11:2) // + -Rd = mpyi(Rs,#m9) // + -Rd -= mpyi(Rs,#u8) // + -Rd += mpyi(Rs,#u8) // + -Rd = mux (Pu, Rs,#s8) // + -Rd = mux (Pu, #s8, Rs) // + -Rd = mux(Pu,#s8,#S8) // + -Rd = or(Rs,#s10) // + -Rd = #s16 // + -Rd = sub(#s10,Rs) // + -Rd = sub(##u32,add(Rs,Rt)) // Not in the manual -Rx -= add(Rs,#s8) // + -Rx += add(Rs,#s8) // + -Rx = add (#u8,asl(Rs,Rx)) // + -Rx = add (#u8,asl(Rx,Rs)) // Not in the manual -Rx = add (#u8,asl(Rx,#U5)) // + -Rx = add (#u8,asr(Rs,Rx)) // + -Rx = add (#u8,asr(Rx,Rs)) // Not in the manual -Rx = add (#u8,asr(Rx,#U5)) // + -Rx = add (#u8,lsr(Rs,Rx)) // + -Rx = add (#u8,lsr(Rx,Rs)) // Not in the manual -Rx = add (#u8,lsr(Rx,#U5)) // + -Rx = and (#u8,asl(Rs,Rx)) // + -Rx = and (#u8,asl(Rx,Rs)) // Not in the manual -Rx = and (#u8,asl(Rx,#U5)) // + -Rx = and (#u8,asr(Rs,Rx)) // + -Rx = and (#u8,asr(Rx,Rs)) // Not in the manual -Rx = and (#u8,asr(Rx,#U5)) // + -Rx = and (#u8,lsr(Rs,Rx)) // + -Rx = and (#u8,lsr(Rx,Rs)) // Not in the manual -Rx = and (#u8,lsr(Rx,#U5)) // + -Rx = or(Rs,and(Rx,#s10)) // + -Rx = or (#u8,asl(Rs,Rx)) // + -Rx = or (#u8,asl(Rx,Rs)) // Not in the manual -Rx = or (#u8,asl(Rx,#U5)) // + -Rx = or (#u8,asr(Rs,Rx)) // + -Rx = or (#u8,asr(Rx,Rs)) // Not in the manual -Rx = or (#u8,asr(Rx,#U5)) // + -Rx = or (#u8,lsr(Rs,Rx)) // + -Rx = or (#u8,lsr(Rx,Rs)) // Not in the manual -Rx = or (#u8,lsr(Rx,#U5)) // + -Rx = sub (#u8,asl(Rs,Rx)) // + -Rx = sub (#u8,asl(Rx,Rs)) // Not in the manual -Rx = sub (#u8,asl(Rx,#U5)) // + -Rx = sub (#u8,asr(Rs,Rx)) // Not in the manual -Rx = sub (#u8,asr(Rx,Rs)) // + -Rx = sub (#u8,asr(Rx,#U5)) // + -Rx = sub (#u8,lsr(Rs,Rx)) // + -Rx = sub (#u8,lsr(Rx,Rs)) // Not in the manual -Rx = sub (#u8,lsr(Rx,#U5)) // + -Rd = #u6 // Slot 1 duplex -Rd = #U6 // Slot 1 duplex -Re = #u6 // Slot 1 duplex -Re = #U6 // Slot 1 duplex -Rx = #u6 // Slot 1 duplex -Rx = #U6 // Slot 1 duplex -Rd = add (Rx, #s7) // Slot 1 duplex -Rd = add (Rx, #S7) // Slot 1 duplex -Re = add (Rx, #s7) // Slot 1 duplex -Re = add (Rx, #S7) // Slot 1 duplex -Rx = add (Rx, #s7) // Slot 1 duplex -Rx = add (Rx, #S7) // Slot 1 duplex diff --git a/handwritten/analysis-tests/hexagon b/handwritten/analysis-tests/hexagon new file mode 100644 index 00000000..1239bb45 --- /dev/null +++ b/handwritten/analysis-tests/hexagon @@ -0,0 +1,19 @@ +NAME=hexagon jumps +FILE=bins/elf/analysis/hexagon-hello-loop +CMDS=< 0x00005128 jump 0x5128 +c 0x00005134 -> 0x00005138 jump 0x5138 +C 0x00005138 -> 0x000050e0 call sym.pHello +C 0x0000513c -> 0x000050f8 call sym.pWorld +c 0x00005140 -> 0x00005144 jump 0x5144 +c 0x00005150 -> 0x00005128 jump 0x5128 +call sym.pHello +call sym.pWorld +EOF +RUN diff --git a/handwritten/analysis_hexagon_c/functions.c b/handwritten/analysis_hexagon_c/functions.c new file mode 100644 index 00000000..5810c152 --- /dev/null +++ b/handwritten/analysis_hexagon_c/functions.c @@ -0,0 +1,20 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +static int hexagon_v6_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) { + HexInsn hi = {0};; + ut32 data = 0; + memset (op, 0, sizeof (RzAnalysisOp)); + data = rz_read_le32 (buf); + int size = hexagon_disasm_instruction (data, &hi, (ut32) addr); + op->size = size; + if (size <= 0) { + return size; + } + + op->addr = addr; + op->jump = op->fail = -1; + op->ptr = op->val = -1; + return hexagon_analysis_instruction (&hi, op); +} diff --git a/handwritten/analysis_hexagon_c/include.c b/handwritten/analysis_hexagon_c/include.c new file mode 100644 index 00000000..23e044f7 --- /dev/null +++ b/handwritten/analysis_hexagon_c/include.c @@ -0,0 +1,12 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include +#include +#include +#include "hexagon.h" +#include "hexagon_insn.h" +#include "hexagon_analysis.h" diff --git a/handwritten/analysis_hexagon_c/initialization.c b/handwritten/analysis_hexagon_c/initialization.c new file mode 100644 index 00000000..a8d90811 --- /dev/null +++ b/handwritten/analysis_hexagon_c/initialization.c @@ -0,0 +1,22 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +RzAnalysisPlugin rz_analysis_plugin_hexagon = { + .name = "hexagon", + .desc = "Qualcomm Hexagon (QDSP6) V6", + .license = "LGPL3", + .arch = "hexagon", + .bits = 32, + .op = hexagon_v6_op, + .esil = true, + .set_reg_profile = set_reg_profile, +}; + +#ifndef RZ_PLUGIN_INCORE +RZ_API RzLibStruct rizin_plugin = { + .type = RZ_LIB_TYPE_ANAL, + .data = &rz_analysis_plugin_hexagon_v6, + .version = RZ_VERSION +}; +#endif diff --git a/handwritten/asm-tests/hexagon b/handwritten/asm-tests/hexagon new file mode 100644 index 00000000..d0358908 --- /dev/null +++ b/handwritten/asm-tests/hexagon @@ -0,0 +1,32 @@ +d "/ immext(##0x0)" 00400000 0x0 +d "/ immext(##0x40)" 01400000 0x0 +d "/ immext(##0xffffffc0)" ff7fff0f 0x0 + +d "[ R0 = ##0x101" 20e00078 +d "[ R5 = add(clb(R31),#-0x1)" 05ff3f8c +d "[ R4 = add(R19,##0x33)" 64c613b0 + +d "[ nop" 00c0007f 0x10000000 +d "/ R31 = add(R0,##0x2)" 5f4000b0 + +d "[ P0 = tstbit(R6,#0); if (!P0.new) jump:t 0x14" 04e3c611 0xc +d "[ P0 = tstbit(R6,#0); if (!P0.new) jump:t 0x8" fce3f611 0x10 + +d "[ R7 = ##0x4 ; R0 = #-1" 003a4728 0x0 +d "[ R1:0 = memd(R29+#0x40) ; if (P0) dealloc_return" 441f403e +d "[ R7:6 = memd(R29+#0x40) ; if (!P0) dealloc_return" 451f433e +d "[ R23:22 = combine(#0,#0x2) ; R17:16 = memd(R29+#0x40)" 443e475c +d "[ if (!P0.new) R23 = #0 ; jumpr R31" c03f5f5a + +d "[ G9:8 = R9:8" 08c00863 +d "[ GELR = R31" 00c01f62 + +d "/ R11:10 = memb_fifo(R12++M0:brev)" 0a408c9e +d "[ R15:14 = memb_fifo(R7=##0x3)" 6ed0879a +dB "[ C21:20 = R19:18" 14c03263 +d "[ C17:16 = R19:18" 10c03263 +d "[ C19:18 = R31:30" 12c03e63 + +dB "HVX MISSING" 4160d719 + +d "[ loop0(0x6c,#0x10)" 88c00069 0x68 diff --git a/handwritten/asm-tests/test-code.S b/handwritten/asm-tests/test-code.S new file mode 100644 index 00000000..1e921b2f --- /dev/null +++ b/handwritten/asm-tests/test-code.S @@ -0,0 +1,140 @@ +// Please use the Hexagon SDK to write those tests and hexagon-llvm-objdump to confirm the disassembly. +// This prevents mistakes. +asmTest: + { // General instr., immext(##0) + R31 = add(R0, ##0x2) + R0 = #0x101 + } + { // Compund instr. pos. jump + p0 = tstbit(R6,#0); if (!p0.new) jump:t 8 + } + { // Compund instr. neg. jump + p0 = tstbit(R6,#0); if (!p0.new) jump:t #-8 + } + { // Nop, immext. + R31 = add(R0, ##0x40) + R0 = #0x101 + nop + } + { // Duplex + R0 = #-1 + R7 = #4 + } + { // Duplex, GeneralDoubleLow8Regs, predicate + if (P0) dealloc_return + R1:0 = memd(r29+#64) + } + { // Duplex, GeneralDoubleLow8Regs + if (!P0) dealloc_return + R7:6 = memd(r29+#64) + } + { // Duplex, GeneralDoubleLow8Regs + jumpr R4 + R23:22 = combine(#0,#2) + R17:16 = memd(r29+#64) + } + { // Duplex, predicates, .new + P0 = R13 + if (!P0.new) R23 = #0 + jumpr R31 + } + { // n1Const + R5=add(clb(R31),#-1) + } + { // Negative numbers + R4=add(R19,#-0xabcd) + } + { // GuestRegs64, GuestRegs + G9:8 = R9:8 + } + { // GuestRegs + GELR = R31 + } + { // ModRegs + R11:10 = memb_fifo(R12++M0:brev) + R15:14 = memb_fifo(R7=#0x3) + } + { // Failes: CtrRegs64 + C21:20 = R19:18 + } + { // CtrRegs64 + C17:16 = R19:18 + } + { // CtrRegs64. Alias + C19:18 = R31:30 + } + { // Loop + loop0(#4, #16) + } + { + nop + } + { + nop + }:endloop0 + + loop0(#4, #3) + { + P0 = R13 + R23:22 = memb_fifo(R27=#0x3) + } + loop1(#4, #2) + { + nop + R7=R28 + memb(R10=#7)=R4 + } + { + R4=R3 + }:endloop01 + jump #0 + jump #0 + jump #0 + loop0(#4, #3) + { + P0 = R13 + R23:22 = memb_fifo(R27=#0x3) + } + jump #0 + + + loop1(#4, #2) + { + nop + R7=R28 + }:endloop1 + { + R4=R3 + }:endloop0 + + loop1(#4, #3) + { + P0 = R13 + R23:22 = memb_fifo(R27=#0x3) + } + jump #0 + + + loop0(#4, #2) + { + R7=R28 + }:endloop0 + { + R4=R3 + }:endloop1 + + /* + { // HVX Instructions which are missing in the public documentation. + // HvxVR, HvxVQR (InOutRegs: Vy), IntRegsLow8, InOutRegs (Rx) + // Also, it seems that the SDK does not support that man HVX isntructions. + V3.w += vr8mpyz(V1.n,R7.b++) + } + { + V15:14.w += vmpy(V2.h,R27.h):sat + V15:14.uw = vmpy(V31.uh,V14.uh) + } + { + vhist128 + }*/ + + .falign diff --git a/handwritten/asm_hexagon_c/include.c b/handwritten/asm_hexagon_c/include.c new file mode 100644 index 00000000..99bb426d --- /dev/null +++ b/handwritten/asm_hexagon_c/include.c @@ -0,0 +1,10 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include +#include +#include "hexagon.h" +#include "hexagon_insn.h" diff --git a/rizin/asm_hexagon.c b/handwritten/asm_hexagon_c/initialization.c similarity index 75% rename from rizin/asm_hexagon.c rename to handwritten/asm_hexagon_c/initialization.c index e19e52ed..6b375442 100644 --- a/rizin/asm_hexagon.c +++ b/handwritten/asm_hexagon_c/initialization.c @@ -1,13 +1,7 @@ -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov +// SPDX-FileCopyrightText: 2021 Rot127 +// // SPDX-License-Identifier: LGPL-3.0-only -#include -#include -#include -#include -#include "hexagon.h" -#include "hexagon_insn.h" - static int disassemble (RzAsm *a, RzAsmOp *op, const ut8 *buf, int l) { HexInsn hi = {0}; ut32 data = rz_read_le32 (buf); diff --git a/handwritten/hexagon_analysis_c/include.c b/handwritten/hexagon_analysis_c/include.c new file mode 100644 index 00000000..4db53506 --- /dev/null +++ b/handwritten/hexagon_analysis_c/include.c @@ -0,0 +1,32 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include +#include +#include +#include +#include "hexagon.h" +#include "hexagon_insn.h" + +static inline bool is_endloop01_instr(const HexInsn* hi) { + return (hi->pkt_info.loop_attr & HEX_ENDS_LOOP_0) && (hi->pkt_info.loop_attr & HEX_ENDS_LOOP_1); +} + +static inline bool is_endloop0_instr(const HexInsn* hi) { + return (hi->pkt_info.loop_attr & HEX_ENDS_LOOP_0); +} + +static inline bool is_endloop1_instr(const HexInsn* hi) { + return (hi->pkt_info.loop_attr & HEX_ENDS_LOOP_1); +} + +static inline bool is_loop0_begin(const HexInsn* hi) { + return ((hi->pkt_info.loop_attr & HEX_LOOP_0) && !(hi->pkt_info.loop_attr & 0xc)); +} + +static inline bool is_loop1_begin(const HexInsn* hi) { + return ((hi->pkt_info.loop_attr & HEX_LOOP_1) && !(hi->pkt_info.loop_attr & 0xc)); +} diff --git a/rizin/hexagon_analysis.h b/handwritten/hexagon_analysis_h/include.h similarity index 58% rename from rizin/hexagon_analysis.h rename to handwritten/hexagon_analysis_h/include.h index f389fd1d..186e97e4 100644 --- a/rizin/hexagon_analysis.h +++ b/handwritten/hexagon_analysis_h/include.h @@ -1,5 +1,5 @@ -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov +// SPDX-FileCopyrightText: 2021 Rot127 +// // SPDX-License-Identifier: LGPL-3.0-only int hexagon_analysis_instruction(HexInsn *hi, RzAnalysisOp *op); - diff --git a/handwritten/hexagon_c/functions.c b/handwritten/hexagon_c/functions.c new file mode 100644 index 00000000..0536168a --- /dev/null +++ b/handwritten/hexagon_c/functions.c @@ -0,0 +1,111 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +inline bool hex_if_duplex(uint32_t insn_word) { + if (((insn_word & 0xc000) >> 18) == 0) { + return true; + } + return false; +} + +static inline bool is_last_instr(const ut8 parse_bits) { + // Duplex instr. (parse bits = 0) are always the last. + return ((parse_bits == 0x3) || (parse_bits == 0x0)); +} + +static inline bool is_endloop0_pkt(const ut8 pi_0, const ut8 pi_1) { + return ((pi_0 == 0x2) && ((pi_1 == 0x1) || (pi_1 == 0x3))); +} + +static inline bool is_endloop1_pkt(const ut8 pi_0, const ut8 pi_1) { + return ((pi_0 == 0x1) && (pi_1 == 0x2)); +} + +static inline bool is_endloop01_pkt(const ut8 pi_0, const ut8 pi_1) { + return ((pi_0 == 0x2) && (pi_1 == 0x2)); +} + +void hex_set_pkt_info(HexPktInfo* i_pkt_info) { + static HexPkt pkt = {0}; // Current packet + static ut8 i = 0; // Index of the instruction in the current packet. + static ut8 p0 = 255; + static ut8 p1 = 255; + static bool new_pkt_starts = true; + + memcpy(&pkt.i_infos[i], i_pkt_info, sizeof(HexPktInfo)); + + // Parse instr. position in pkt + if (new_pkt_starts && is_last_instr(i_pkt_info->parse_bits)) { // Single instruction packet. + // TODO No indent in visual mode for "[" without spaces. + // Possible cause: 2 extra bytes in UTF-8 chars are printed as spaces? + strncpy(i_pkt_info->syntax_prefix, "[ ", 8); + i_pkt_info->first_insn = true; + i_pkt_info->last_insn = true; + new_pkt_starts = true; + i = 0; + } + else if (new_pkt_starts) { + strncpy(i_pkt_info->syntax_prefix, "/", 8); // TODO Add utf8 option "┌" + i_pkt_info->first_insn = true; + new_pkt_starts = false; + // Just in case evil persons set the parsing bits incorrectly and pkts with more than 4 instr. occur. + i = (i + 1) % 4; + } + else if (is_last_instr(i_pkt_info->parse_bits)) { + strncpy(i_pkt_info->syntax_prefix, "\\", 8); // TODO Add utf8 option "└" + i_pkt_info->last_insn = true; + new_pkt_starts = true; + + p0 = pkt.i_infos[0].parse_bits; + p1 = pkt.i_infos[1].parse_bits; + + if (is_endloop01_pkt(p0, p1)) { + strncpy(i_pkt_info->syntax_postfix, " < endloop01", 16); // TODO Add utf8 option "∎" + i_pkt_info->loop_attr |= (HEX_ENDS_LOOP_0 | HEX_ENDS_LOOP_1); + } + else if (is_endloop0_pkt(p0, p1)) { + strncpy(i_pkt_info->syntax_postfix, " < endloop0", 16); + i_pkt_info->loop_attr |= HEX_ENDS_LOOP_0; + } + else if (is_endloop1_pkt(p0, p1)) { + strncpy(i_pkt_info->syntax_postfix, " < endloop1", 16); + i_pkt_info->loop_attr |= HEX_ENDS_LOOP_1; + } + i = 0; + } + else { + strncpy(i_pkt_info->syntax_prefix, "|", 8); // TODO Add utf8 option "│" + new_pkt_starts = false; + i = (i + 1) % 4; + } + + +} + +static inline bool imm_is_extendable(ut32 const_ext, ut8 type) { + return ((const_ext != 0) && (type == HEX_OP_TYPE_IMM)); +} + +static inline bool imm_is_scaled(HexOpAttr attr) { + return (attr & HEX_OP_IMM_SCALED); +} + +void hex_op_extend(RZ_INOUT HexOp *op, bool set_new_extender) +{ + // Constant extender value + static ut32 constant_extender = 0; + + if (set_new_extender) { + constant_extender = op->op.imm; + return; + } + + if (imm_is_extendable(constant_extender, op->type)) { + if (imm_is_scaled(op->attr)) { + op->op.imm = (op->op.imm >> op->shift); // Extended immediate values won't get scaled. Redo it. + } + op->op.imm = ((op->op.imm) & 0x3F) | (constant_extender); + } + constant_extender = 0; +} diff --git a/handwritten/hexagon_c/include.c b/handwritten/hexagon_c/include.c new file mode 100644 index 00000000..0791e4c4 --- /dev/null +++ b/handwritten/hexagon_c/include.c @@ -0,0 +1,12 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include +#include +#include +#include +#include +#include "hexagon.h" \ No newline at end of file diff --git a/handwritten/hexagon_disas_c/include.c b/handwritten/hexagon_disas_c/include.c new file mode 100644 index 00000000..816f0dcb --- /dev/null +++ b/handwritten/hexagon_disas_c/include.c @@ -0,0 +1,14 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include +#include +#include +#include "hexagon.h" +#include "hexagon_insn.h" + +extern ut32 constant_extender; + diff --git a/handwritten/hexagon_h/declarations.h b/handwritten/hexagon_h/declarations.h new file mode 100644 index 00000000..9aa743cb --- /dev/null +++ b/handwritten/hexagon_h/declarations.h @@ -0,0 +1,9 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +bool hex_if_duplex(ut32 insn_word); +void hex_op_extend(HexOp *op, bool set_new_extender); +void hex_set_pkt_info(RZ_INOUT HexPktInfo* pkt_info); +int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr); + diff --git a/handwritten/hexagon_h/macros.h b/handwritten/hexagon_h/macros.h new file mode 100644 index 00000000..33f37724 --- /dev/null +++ b/handwritten/hexagon_h/macros.h @@ -0,0 +1,9 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +#define BIT_MASK(len) (BIT(len)-1) +#define BF_MASK(start, len) (BIT_MASK(len)<<(start)) +#define BF_PREP(x, start, len) (((x)&BIT_MASK(len))<<(start)) +#define BF_GET(y, start, len) (((y)>>(start)) & BIT_MASK(len)) +#define BF_GETB(y, start, end) (BF_GET((y), (start), (end) - (start) + 1) diff --git a/handwritten/hexagon_h/typedefs.h b/handwritten/hexagon_h/typedefs.h new file mode 100644 index 00000000..069c932b --- /dev/null +++ b/handwritten/hexagon_h/typedefs.h @@ -0,0 +1,102 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +// TODO NOT IN USE +// Predicates - declare the predicate state +typedef enum { + HEX_NOPRED, // no conditional execution + HEX_PRED_TRUE, // if (Pd) ... + HEX_PRED_FALSE, // if (!Pd) ... + HEX_PRED_TRUE_NEW, // if (Pd.new) ... + HEX_PRED_FALSE_NEW, // if (!Pd.new) ... +} HexPred; + +// TODO NOT IN USE +// Pre/post-fixes, different types +typedef enum { + HEX_PF_RND = 1, // :rnd + HEX_PF_CRND = 1<<1, // :crnd + HEX_PF_RAW = 1<<2, // :raw + HEX_PF_CHOP = 1<<3, // :chop + HEX_PF_SAT = 1<<4, // :sat + HEX_PF_HI = 1<<5, // :hi + HEX_PF_LO = 1<<6, // :lo + HEX_PF_LSH1 = 1<<7, // :<<1 + HEX_PF_LSH16 = 1<<8, // :<<16 + HEX_PF_RSH1 = 1<<9, // :>>1 + HEX_PF_NEG = 1<<10, // :neg + HEX_PF_POS = 1<<11, // :pos + HEX_PF_SCALE = 1<<12, // :scale, for FMA instructions + HEX_PF_DEPRECATED = 1<<15, // :deprecated +} HexPf; + +typedef enum { + HEX_OP_TYPE_IMM, + HEX_OP_TYPE_REG, + // TODO It might be useful to differ between control, HVX, guest regs etc. Also see HexOp +} HexOpType; + +// Attributes - .H/.L, const extender +typedef enum { + HEX_OP_CONST_EXT = 1 << 0, // Constant extender marker for Immediate + HEX_OP_REG_HI = 1 << 1, // Rn.H marker + HEX_OP_REG_LO = 1 << 2, // Rn.L marker + HEX_OP_REG_PAIR = 1 << 3, // Is this a register pair? + HEX_OP_IMM_SCALED = 1 << 4 // Is the immediate shifted? +} HexOpAttr; + +typedef enum { + HEX_NO_LOOP = 0, + HEX_LOOP_0 = 1, // Is packet of loop0 + HEX_LOOP_1 = 1 << 1, // Is packet of loop1 + HEX_ENDS_LOOP_0 = 1 << 2, // Packet ends loop0? + HEX_ENDS_LOOP_1 = 1 << 3, // Packet ends loop1? +} HexLoopAttr; + +typedef struct { + bool first_insn; + bool last_insn; + char syntax_prefix[8]; // Package indicator + char syntax_postfix[16]; // for ":endloop" string. + unsigned int parse_bits; + HexLoopAttr loop_attr; +} HexPktInfo; + +typedef struct { + ut8 type; + union { + ut8 reg; // + additional Hi or Lo selector // + additional shift // + additional :brev // + ut32 imm; + } op; + ut8 attr; + ut8 shift; +} HexOp; + +typedef struct { + int instruction; + ut32 mask; + // TODO + // ut16 pf; // additional prefixes (bitmap) + // TODO + // HexPred pred; // Predicate type + bool duplex; // is part of duplex container? + bool compound; // is part of compound instruction? + int shift; // Optional shift left is it true? + HexPktInfo pkt_info; + ut8 op_count; + HexOp ops[6]; + char mnem[128]; // Instruction mnemonic +} HexInsn; + +typedef struct { + HexPktInfo i_infos[4]; +} HexPkt; + +// Instruction container (currently only 2 instructions) +// Can handle duplexes +typedef struct { + bool duplex; + HexInsn ins[2]; // Or make it pointer + size? +} HexInsnCont; + diff --git a/helperFunctions.py b/helperFunctions.py new file mode 100644 index 00000000..fe6f869f --- /dev/null +++ b/helperFunctions.py @@ -0,0 +1,304 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +import re + +from bitarray import bitarray +from enum import IntEnum + +from typing.io import TextIO + +import PluginInfo +from UnexpectedException import UnexpectedException + +try: + from colorama import init, Fore, Style + + init() + colorama_imported = True +except ImportError: + print("colorama package not found. Enjoy your Script Noire :)") + colorama_imported = False + + +class LogLevel(IntEnum): + TODO = 0 + ERROR = 1 + WARNING = 2 + INFO = 3 + DEBUG = 4 + VERBOSE = 5 + + +LOG_LEVEL = LogLevel.DEBUG + + +def log(msg: str, verbosity: LogLevel = LogLevel.INFO) -> None: + """ + + Args: + msg: The message to log + verbosity: msg level: error, log + + Returns: None + + """ + if verbosity > LOG_LEVEL: + return + + if colorama_imported: + if verbosity == LogLevel.ERROR: + print( + "[" + + Fore.RED + + "X" + + Style.RESET_ALL + + "] {}".format(Fore.RED + msg + Style.RESET_ALL) + ) + elif verbosity == LogLevel.WARNING: + print( + "[" + + Fore.LIGHTYELLOW_EX + + "!" + + Style.RESET_ALL + + "] {}".format(Fore.LIGHTYELLOW_EX + msg + Style.RESET_ALL) + ) + elif verbosity == LogLevel.INFO: + print("[" + Fore.BLUE + "*" + Style.RESET_ALL + "] {}".format(msg)) + elif verbosity == LogLevel.DEBUG: + print( + "[" + Fore.LIGHTMAGENTA_EX + "#" + Style.RESET_ALL + "] {}".format(msg) + ) + elif verbosity == LogLevel.VERBOSE: + print("[" + Fore.LIGHTWHITE_EX + "-" + Style.RESET_ALL + "] {}".format(msg)) + elif verbosity == LogLevel.TODO: + print("[" + Fore.GREEN + "T" + Style.RESET_ALL + "] {}".format(msg)) + + else: + if verbosity == LogLevel.ERROR: + print("[X] {}".format(msg)) + elif verbosity == LogLevel.WARNING: + print("[!] {}".format(msg)) + elif verbosity == LogLevel.INFO: + print("[*] {}".format(msg)) + elif verbosity == LogLevel.DEBUG: + print("[#] {}".format(msg)) + elif verbosity == LogLevel.VERBOSE: + print("[-] {}".format(msg)) + elif verbosity == LogLevel.TODO: + print("[T] {}".format(msg)) + + +def standardize_syntax_objdump(syntax: str) -> str: + """Change instruction syntax to match Qualcomm's objdump output. + + Args: + syntax (str): instruction syntax, probably as was obtained from the parsed manual. + + Returns: + str: matching objdump syntax (as close as possible). + + TODO: + * Care should be taken not to modify the syntax patterns used in the decoder + to recognize different attributes of the instruction, e.g., ``Rd`` can + be split with a space like ``R d``. + + * Document the most complex regex. + + """ + + # Add spaces to certain chars like '=' and '()' + + both_spaces = ["=", "+", "-", "*", "/", "&", "|", "<<", "^"] + left_space = ["(", "!"] + right_space = [")", ","] + for c in both_spaces: + syntax = syntax.replace(c, " " + c + " ") + for c in left_space: + syntax = syntax.replace(c, " " + c) + for c in right_space: + syntax = syntax.replace(c, c + " ") + + syntax = re.sub(r"\s{2,}", " ", syntax) + + # TODO: Special hack for the unary minus. + syntax = re.sub(r"\#\s-\s", "#-", syntax) + + syntax = re.sub(r"\(\s*", "(", syntax) + syntax = re.sub(r"\s*\)", ")", syntax) + + # Compound assignment + syntax = re.sub(r"([\+\-\*\/\&\|\^\!]) =", r"\1=", syntax) + + syntax = syntax.replace(" ,", ",") + syntax = syntax.replace(" .", ".") + + # Remove parenthesis from (!p0.new). just to match objdump, + # but I prefer it with parenthesis. + if ";" not in syntax: + m = re.search(r"\( (\s* ! \s* [pP]\w(.new)? \s*) \)", syntax, re.X) + + if m: + syntax = syntax.replace("(" + m.group(1) + ")", m.group(1)) + # syntax = re.sub(r'\( (\s* ! \s* [pP]\w(.new)? \s*) \)', r'\1', syntax, re.X) + # TODO: The re.sub is not working, don't know why.. + + syntax = syntax.replace("dfcmp", "cmp") + syntax = syntax.replace("sfcmp", "cmp") + + # Special cases: ++, ==, != + syntax = syntax.replace("+ +", "++") + syntax = syntax.replace("= =", "==") + syntax = syntax.replace("! =", "!=") + + # Special cases: <>1 + syntax = syntax.replace(": << N", ":<> 1", ":>>1") + + syntax = syntax.strip() + + return syntax + + +def bitarray_to_uint(array: bitarray, endian: str = "little") -> int: + if endian == "little": + bits = array.to01() + return int(bits[::-1], 2) + elif endian == "big": + return int(array.to01(), 2) + else: + raise UnexpectedException( + "Endian can only be 'little' or 'big'. Was: {}".format(endian) + ) + + +def list_to_bitarray(bit_list: list, endian="little") -> bitarray: + """Converts a list to the bitarray. + The element at the list index 0 corresponds to the element at the lowest position/address. + Example: [0, 0, 1] -> "001" + The left most bit is at the lowest address. + + Args: + bit_list: The list with bits set. + endian: The endian of the list. [0, 0, 1] in little = 4 in big = 1 + + Returns: For [0, 0, 1], endian=big: bitarray("001", big) + + """ + s = "" + for bit in bit_list: + s += str(bit) + return bitarray(s, endian) + + +def list_to_int(bit_list: list, endian="little") -> int: + ret = 0 + if endian == "big": + for bit in bit_list: + ret = (ret << 1) | bit + else: + for bit in bit_list[::-1]: + ret = (ret << 1) | bit + return ret + + +# TODO: support more syntax constructs +def make_c_block( + lines: list, begin: str = "", end: str = "", ret: str = "", indent_depth: int = 1 +) -> list: + """ + Args: Creates a C code block with curly braces (useful for if/else or switch cases). + lines: The lines of code. + begin: The statement before the opening curly bracket. + ret: The statement before the closing curly bracket. + end: The statement after the closing curly bracket. + indent_depth: The indention depth of the code block. If >1 the begin statement and all brackets will be indented + as well. + + Returns: List with the formatted lines of code. + """ + + new = [] + indent: str = PluginInfo.LINE_INDENT * indent_depth + p_ind: str = PluginInfo.LINE_INDENT * (indent_depth - 1) + + if begin != "": + new += [p_ind + begin + " {\n"] + else: + new += ["{"] + for line in lines: + new += [indent + line] + if ret != "": + new += [indent + ret] + if end != "": + new += [p_ind + "} " + end] + else: + new += [p_ind + "}"] + return new + + +def set_pos_after_license(file: TextIO) -> None: + for line in file: + if re.search(r"SPDX-License-Identifier", line): + return + file.seek(0, 0) + return + + +def get_generation_warning_c_code() -> str: + url = PluginInfo.REPO_URL + msg = "{}\n".format(PluginInfo.GENERATION_WARNING_DELIMITER) + msg += "// The following code is generated.\n" + msg += "// Do not edit. Repository of code generator:\n" + msg += "// {}\n".format(url) + return msg + + +def get_license() -> str: + lcs = "// SPDX-FileCopyrightText: 2021 Rot127 \n//\n" + lcs += "// SPDX-License-Identifier: LGPL-3.0-only\n" + return lcs + + +def indent_code_block(code: str, indent_depth: int) -> str: + ret = "" + indent: str = PluginInfo.LINE_INDENT + for line in code.splitlines(keepends=True): + ret += (indent * indent_depth) + line + return ret + + +def unfold_llvm_sequence(sequence: str) -> list: + """In the LLVM code generator one can define sequences of values. + Here we build a given sequence and return the result as list. + E.g.: (sequence "D%u", 0, 4) -> [D0, D1, D2, D3, D4] + """ + + s = re.search(r"\"(.+)\"", sequence).group(1) + start = int(re.search(r", (\d*),", sequence).group(1)) + end = int(re.search(r", (\d*)\)", sequence).group(1)) + + result = [re.sub(r"%[a-z]", str(x), s) for x in range(start, end + 1)] + return result + + +def get_include_guard(filename: str) -> str: + name = re.sub(r"\.", r"_", filename) + name = name.upper() + return "#ifndef {}\n#define {}\n".format(name, name) + + +def surround_with_include_guard(filename: str, lines: list) -> list: + lines.insert(0, get_include_guard(filename)) + lines.append("\n\n#endif\n") + return lines + + +def normalize_llvm_syntax(llvm_syntax: str) -> str: + syntax = re.sub(r"\$", "", llvm_syntax) + # Any number which stands before a register or immediate letter. + syntax = re.sub(r"([A-Z][a-z,A-Z]+)[0-9]+", r"\1", syntax) + # log("Normalized syntax: {} -> {}".format(llvm_syntax, syntax), LogLevel.DEBUG) + return syntax diff --git a/hexagon_insn.h b/hexagon_insn.h deleted file mode 100644 index aa88c00f..00000000 --- a/hexagon_insn.h +++ /dev/null @@ -1,2800 +0,0 @@ -enum HEX_INS { - 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HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RD___SXTB__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RS__RX_, - HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RX__RS_, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RD___SXTB__RU____P0___CMP_EQ__RS___U2_, - HEX_INS_DUPLEX_RD___SXTH__RS____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RD___SXTH__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RS__RX_, - HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RX__RS_, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RD___SXTH__RU____P0___CMP_EQ__RS___U2_, - HEX_INS_DUPLEX_RD___ZXTH__RS____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____JUMPR_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RD___ZXTH__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RS__RX_, - HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RX__RS_, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RD___ZXTH__RU____P0___CMP_EQ__RS___U2_, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0_____0, - 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HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RDD___COMBINE___0__RS_, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RDD___COMBINE__RS___0_, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____P0___CMP_EQ__RS___U2_, -}; diff --git a/hexagon_iset_v5.h b/hexagon_iset_v5.h deleted file mode 100644 index 56474360..00000000 --- a/hexagon_iset_v5.h +++ /dev/null @@ -1,3892 +0,0 @@ -{ "Cd32 = Rs32" , "0110 0010 001sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0, NULL} /* A2_tfrrcr */, -{ "Cdd32 = Rss32" , "0110 0011 001sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0, NULL} /* A4_tfrpcp */, -{ "Gd32 = Rs32" , "0110 0010 000sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_GUEST|A_NOTE_GUEST, NULL} /* G4_tfrgrcr */, -{ "Gdd32 = Rss32" , "0110 0011 000sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_GUEST|A_NOTE_GUEST, NULL} /* G4_tfrgpcp */, -{ "Pd4 = ! bitsclr ( Rs32 , #u6 )" , "10000101 101sssss PPiiiiii ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* C4_nbitsclri */, -{ "Pd4 = ! bitsclr ( Rs32 , Rt32 )" , "1100 0111 101sssss PP-ttttt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* C4_nbitsclr */, -{ "Pd4 = ! bitsset ( Rs32 , Rt32 )" , "1100 0111 011sssss PP-ttttt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* C4_nbitsset */, -{ "Pd4 = ! cmp.eq ( Rs32 , #s10 )" , "0111 0101 00isssss PPiiiiii iii100dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C4_cmpneqi */, -{ "Pd4 = ! cmp.eq ( Rs32 , Rt32 )" , "1111 0010 -00sssss PP-ttttt ---100dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* C4_cmpneq */, -{ "Pd4 = ! cmp.gt ( Rs32 , #s10 )" , "0111 0101 01isssss PPiiiiii iii100dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C4_cmpltei */, -{ "Pd4 = ! cmp.gt ( Rs32 , Rt32 )" , "1111 0010 -10sssss PP-ttttt ---100dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* C4_cmplte */, -{ "Pd4 = ! cmp.gtu ( Rs32 , #u9 )" , "0111 0101 100sssss PPiiiiii iii100dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C4_cmplteui */, -{ "Pd4 = ! cmp.gtu ( Rs32 , Rt32 )" , "1111 0010 -11sssss PP-ttttt ---100dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* C4_cmplteu */, -{ "Pd4 = ! fastcorner9 ( Ps4 , Pt4 )" , "01101011 0001--ss PP1---tt 1--1--dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_fastcorner9_not */, -{ "Pd4 = ! tstbit ( Rs32 , #u5 )" , "10000101 001sssss PP0iiiii ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S4_ntstbit_i */, -{ "Pd4 = ! tstbit ( Rs32 , Rt32 )" , "1100 0111 001sssss PP-ttttt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S4_ntstbit_r */, -{ "Pd4 = Ps4" , "0000ddss000000000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(C2_pxfer_map)}, /* mapped to Pd4=or(Ps4,Ps4) */ -{ "Pd4 = Rs32" , "1000 0101 010sssss PP------ ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* C2_tfrrp */, -{ "Pd4 = all8 ( Ps4 )" , "0110 1011 1010--ss PP0----- ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C2_all8 */, -{ "Pd4 = and ( Ps4 , and ( Pt4 , ! Pu4 ) )" , "0110 1011 1001--ss PP0---tt uu----dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_and_andn */, -{ "Pd4 = and ( Ps4 , and ( Pt4 , Pu4 ) )" , "0110 1011 0001--ss PP0---tt uu----dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_and_and */, -{ "Pd4 = and ( Ps4 , or ( Pt4 , ! Pu4 ) )" , "0110 1011 1011--ss PP0---tt uu----dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_and_orn */, -{ "Pd4 = and ( Ps4 , or ( Pt4 , Pu4 ) )" , "0110 1011 0011--ss PP0---tt uu----dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_and_or */, -{ "Pd4 = and ( Pt4 , ! Ps4 )" , "0110 1011 0110--ss PP0---tt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C2_andn */, -{ "Pd4 = and ( Pt4 , Ps4 )" , "0110 1011 0000--ss PP0---tt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C2_and */, -{ "Pd4 = any8 ( Ps4 )" , "0110 1011 1000--ss PP0----- ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C2_any8 */, -{ "Pd4 = any8 ( vcmpb.eq ( Rss32 , Rtt32 ) )" , "1101 0010 0--sssss PP1ttttt 000---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmpbeq_any */, -{ "Pd4 = bitsclr ( Rs32 , #u6 )" , "1000 0101 100sssss PPiiiiii ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* C2_bitsclri */, -{ "Pd4 = bitsclr ( Rs32 , Rt32 )" , "1100 0111 100sssss PP-ttttt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* C2_bitsclr */, -{ "Pd4 = bitsset ( Rs32 , Rt32 )" , "1100 0111 010sssss PP-ttttt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* C2_bitsset */, -{ "Pd4 = boundscheck ( Rs32 , Rtt32 )" , "0000ddsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A4_boundscheck)}, /* mapped to Pd4=boundscheck(Rss32,Rtt32):raw:hi or Pd4=boundscheck(Rss32,Rtt32):raw:lo */ -{ "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :hi" , "1101 0010 0--sssss PP1ttttt 101---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_boundscheck_hi */, -{ "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :lo" , "1101 0010 0--sssss PP1ttttt 100---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_boundscheck_lo */, -{ "Pd4 = cmp.eq ( Rs32 , #s10 )" , "0111 0101 00isssss PPiiiiii iii000dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmpeqi */, -{ "Pd4 = cmp.eq ( Rs32 , Rt32 )" , "1111 0010 -00sssss PP-ttttt ---000dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* C2_cmpeq */, -{ "Pd4 = cmp.eq ( Rss32 , Rtt32 )" , "1101 0010 100sssss PP-ttttt 000---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* C2_cmpeqp */, -{ "Pd4 = cmp.ge ( Rs32 , #s8 )" , "0000ddsssssiiiiiiii0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(C2_cmpgei)}, /* mapped to Pd4=cmp.gt(Rs32,#s8-1) */ -{ "Pd4 = cmp.geu ( Rs32 , #u8 )" , "0000ddsssssiiiiiiii0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(C2_cmpgeui)}, /* mapped to Pd4=cmp.eq(Rs32,Rs32) or Pd4=cmp.gtu(Rs32,#u8-1) */ -{ "Pd4 = cmp.gt ( Rs32 , #s10 )" , "0111 0101 01isssss PPiiiiii iii000dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmpgti */, -{ "Pd4 = cmp.gt ( Rs32 , Rt32 )" , "1111 0010 -10sssss PP-ttttt ---000dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* C2_cmpgt */, -{ "Pd4 = cmp.gt ( Rss32 , Rtt32 )" , "1101 0010 100sssss PP-ttttt 010---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* C2_cmpgtp */, -{ "Pd4 = cmp.gtu ( Rs32 , #u9 )" , "0111 0101 100sssss PPiiiiii iii000dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmpgtui */, -{ "Pd4 = cmp.gtu ( Rs32 , Rt32 )" , "1111 0010 -11sssss PP-ttttt ---000dd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* C2_cmpgtu */, -{ "Pd4 = cmp.gtu ( Rss32 , Rtt32 )" , "1101 0010 100sssss PP-ttttt 100---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* C2_cmpgtup */, -{ "Pd4 = cmp.lt ( Rs32 , Rt32 )" , "0000ddsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(C2_cmplt)}, /* mapped to Pd4=cmp.gt(Rt32,Rs32) */ -{ "Pd4 = cmp.ltu ( Rs32 , Rt32 )" , "0000ddsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(C2_cmpltu)}, /* mapped to Pd4=cmp.gtu(Rt32,Rs32) */ -{ "Pd4 = cmpb.eq ( Rs32 , #u8 )" , "11011101 -00sssss PP-iiiii iii00-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cmpbeqi */, -{ "Pd4 = cmpb.eq ( Rs32 , Rt32 )" , "1100 0111 110sssss PP-ttttt 110---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cmpbeq */, -{ "Pd4 = cmpb.gt ( Rs32 , #s8 )" , "11011101 -01sssss PP-iiiii iii00-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cmpbgti */, -{ "Pd4 = cmpb.gt ( Rs32 , Rt32 )" , "1100 0111 110sssss PP-ttttt 010---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cmpbgt */, -{ "Pd4 = cmpb.gtu ( Rs32 , #u7 )" , "11011101 -10sssss PP-0iiii iii00-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A4_cmpbgtui */, -{ "Pd4 = cmpb.gtu ( Rs32 , Rt32 )" , "1100 0111 110sssss PP-ttttt 111---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cmpbgtu */, -{ "Pd4 = cmph.eq ( Rs32 , #s8 )" , "11011101 -00sssss PP-iiiii iii01-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A4_cmpheqi */, -{ "Pd4 = cmph.eq ( Rs32 , Rt32 )" , "1100 0111 110sssss PP-ttttt 011---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cmpheq */, -{ "Pd4 = cmph.gt ( Rs32 , #s8 )" , "11011101 -01sssss PP-iiiii iii01-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A4_cmphgti */, -{ "Pd4 = cmph.gt ( Rs32 , Rt32 )" , "1100 0111 110sssss PP-ttttt 100---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cmphgt */, -{ "Pd4 = cmph.gtu ( Rs32 , #u7 )" , "11011101 -10sssss PP-0iiii iii01-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A4_cmphgtui */, -{ "Pd4 = cmph.gtu ( Rs32 , Rt32 )" , "1100 0111 110sssss PP-ttttt 101---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cmphgtu */, -{ "Pd4 = dfclass ( Rss32 , #u5 )" , "11011100 100sssss PP-000ii iii10-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE|A_CONDEXEC, NULL} /* F2_dfclass */, -{ "Pd4 = dfcmp.eq ( Rss32 , Rtt32 )" , "1101 0010 111sssss PP-ttttt 000---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dfcmpeq */, -{ "Pd4 = dfcmp.ge ( Rss32 , Rtt32 )" , "1101 0010 111sssss PP-ttttt 010---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dfcmpge */, -{ "Pd4 = dfcmp.gt ( Rss32 , Rtt32 )" , "1101 0010 111sssss PP-ttttt 001---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dfcmpgt */, -{ "Pd4 = dfcmp.uo ( Rss32 , Rtt32 )" , "1101 0010 111sssss PP-ttttt 011---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dfcmpuo */, -{ "Pd4 = fastcorner9 ( Ps4 , Pt4 )" , "01101011 0000--ss PP1---tt 1--1--dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_fastcorner9 */, -{ "Pd4 = not ( Ps4 )" , "0110 1011 1100--ss PP0----- ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C2_not */, -{ "Pd4 = or ( Ps4 , and ( Pt4 , ! Pu4 ) )" , "0110 1011 1101--ss PP0---tt uu----dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_or_andn */, -{ "Pd4 = or ( Ps4 , and ( Pt4 , Pu4 ) )" , "0110 1011 0101--ss PP0---tt uu----dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_or_and */, -{ "Pd4 = or ( Ps4 , or ( Pt4 , ! Pu4 ) )" , "0110 1011 1111--ss PP0---tt uu----dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_or_orn */, -{ "Pd4 = or ( Ps4 , or ( Pt4 , Pu4 ) )" , "0110 1011 0111--ss PP0---tt uu----dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C4_or_or */, -{ "Pd4 = or ( Pt4 , ! Ps4 )" , "0110 1011 1110--ss PP0---tt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C2_orn */, -{ "Pd4 = or ( Pt4 , Ps4 )" , "0110 1011 0010--ss PP0---tt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C2_or */, -{ "Pd4 = sfclass ( Rs32 , #u5 )" , "10000101 111sssss PP0iiiii ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CONDEXEC|A_FPOP|A_FPSINGLE, NULL} /* F2_sfclass */, -{ "Pd4 = sfcmp.eq ( Rs32 , Rt32 )" , "1100 0111 111sssss PP-ttttt 011---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sfcmpeq */, -{ "Pd4 = sfcmp.ge ( Rs32 , Rt32 )" , "1100 0111 111sssss PP-ttttt 000---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sfcmpge */, -{ "Pd4 = sfcmp.gt ( Rs32 , Rt32 )" , "1100 0111 111sssss PP-ttttt 100---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sfcmpgt */, -{ "Pd4 = sfcmp.uo ( Rs32 , Rt32 )" , "1100 0111 111sssss PP-ttttt 001---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sfcmpuo */, -{ "Pd4 = tlbmatch ( Rss32 , Rt32 )" , "1101 0010 0--sssss PP1ttttt 011---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_LATEPRED|A_RESTRICT_LATEPRED, NULL} /* A4_tlbmatch */, -{ "Pd4 = tstbit ( Rs32 , #u5 )" , "1000 0101 000sssss PP0iiiii ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_tstbit_i */, -{ "Pd4 = tstbit ( Rs32 , Rt32 )" , "1100 0111 000sssss PP-ttttt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S2_tstbit_r */, -{ "Pd4 = vcmpb.eq ( Rss32 , #u8 )" , "11011100 000sssss PP-iiiii iii00-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmpbeqi */, -{ "Pd4 = vcmpb.eq ( Rss32 , Rtt32 )" , "1101 0010 0--sssss PP0ttttt 110---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vcmpbeq */, -{ "Pd4 = vcmpb.gt ( Rss32 , #s8 )" , "11011100 001sssss PP-iiiii iii00-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmpbgti */, -{ "Pd4 = vcmpb.gt ( Rss32 , Rtt32 )" , "1101 0010 0--sssss PP1ttttt 010---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmpbgt */, -{ "Pd4 = vcmpb.gtu ( Rss32 , #u7 )" , "11011100 010sssss PP-0iiii iii00-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmpbgtui */, -{ "Pd4 = vcmpb.gtu ( Rss32 , Rtt32 )" , "1101 0010 0--sssss PP0ttttt 111---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vcmpbgtu */, -{ "Pd4 = vcmph.eq ( Rss32 , #s8 )" , "11011100 000sssss PP-iiiii iii01-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmpheqi */, -{ "Pd4 = vcmph.eq ( Rss32 , Rtt32 )" , "1101 0010 0--sssss PP0ttttt 011---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vcmpheq */, -{ "Pd4 = vcmph.gt ( Rss32 , #s8 )" , "11011100 001sssss PP-iiiii iii01-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmphgti */, -{ "Pd4 = vcmph.gt ( Rss32 , Rtt32 )" , "1101 0010 0--sssss PP0ttttt 100---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vcmphgt */, -{ "Pd4 = vcmph.gtu ( Rss32 , #u7 )" , "11011100 010sssss PP-0iiii iii01-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmphgtui */, -{ "Pd4 = vcmph.gtu ( Rss32 , Rtt32 )" , "1101 0010 0--sssss PP0ttttt 101---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vcmphgtu */, -{ "Pd4 = vcmpw.eq ( Rss32 , #s8 )" , "11011100 000sssss PP-iiiii iii10-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmpweqi */, -{ "Pd4 = vcmpw.eq ( Rss32 , Rtt32 )" , "1101 0010 0--sssss PP0ttttt 000---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vcmpweq */, -{ "Pd4 = vcmpw.gt ( Rss32 , #s8 )" , "11011100 001sssss PP-iiiii iii10-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmpwgti */, -{ "Pd4 = vcmpw.gt ( Rss32 , Rtt32 )" , "1101 0010 0--sssss PP0ttttt 001---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vcmpwgt */, -{ "Pd4 = vcmpw.gtu ( Rss32 , #u7 )" , "11011100 010sssss PP-0iiii iii10-dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vcmpwgtui */, -{ "Pd4 = vcmpw.gtu ( Rss32 , Rtt32 )" , "1101 0010 0--sssss PP0ttttt 010---dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vcmpwgtu */, -{ "Pd4 = xor ( Ps4 , Pt4 )" , "0110 1011 0100--ss PP0---tt ------dd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_CRSLOT23|A_NOTE_CRSLOT23, NULL} /* C2_xor */, -{ "Rd16 = #-1 ; allocframe ( #u5:3 )" , "0111101--0--ddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS2_allocframe */, -{ "Rd16 = #-1 ; dealloc_return" , "0101101--0--ddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_return */, -{ "Rd16 = #-1 ; deallocframe" , "0101101--0--ddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_deallocframe */, -{ "Rd16 = #-1 ; if ( ! p0 ) dealloc_return" , "0101101--0--ddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_return_f */, -{ "Rd16 = #-1 ; if ( ! p0 ) jumpr Lr" , "0101101--0--ddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_jumpr31_f */, -{ "Rd16 = #-1 ; if ( ! p0 .new ) dealloc_return:nt" , "0101101--0--ddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_return_fnew */, -{ "Rd16 = #-1 ; if ( ! p0 .new ) jumpr:nt Lr" , "0101101--0--ddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_jumpr31_fnew */, -{ "Rd16 = #-1 ; if ( p0 ) dealloc_return" , "0101101--0--ddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_return_t */, -{ "Rd16 = #-1 ; if ( p0 ) jumpr Lr" , "0101101--0--ddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_jumpr31_t */, -{ "Rd16 = #-1 ; if ( p0 .new ) dealloc_return:nt" , "0101101--0--ddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_return_tnew */, -{ "Rd16 = #-1 ; if ( p0 .new ) jumpr:nt Lr" , "0101101--0--ddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_jumpr31_tnew */, -{ "Rd16 = #-1 ; jumpr Lr" , "0101101--0--ddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_jumpr31 */, -{ "Rd16 = #-1 ; memb ( Rs16 + #u4:0 ) = #0" , "0111101--0--ddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS2_storebi0 */, -{ "Rd16 = #-1 ; memb ( Rs16 + #u4:0 ) = #1" , "0111101--0--ddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS2_storebi1 */, -{ "Rd16 = #-1 ; memb ( Rs16 + #u4:0 ) = Rt16" , "0111101--0--ddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS1_storeb_io */, -{ "Rd16 = #-1 ; memd ( Sp + #s6:3 ) = Rtt8" , "0111101--0--ddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS2_stored_sp */, -{ "Rd16 = #-1 ; memh ( Rs16 + #u3:1 ) = Rt16" , "0111101--0--ddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS2_storeh_io */, -{ "Rd16 = #-1 ; memw ( Rs16 + #u4:2 ) = #0" , "0111101--0--ddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS2_storewi0 */, -{ "Rd16 = #-1 ; memw ( Rs16 + #u4:2 ) = #1" , "0111101--0--ddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS2_storewi1 */, -{ "Rd16 = #-1 ; memw ( Rs16 + #u4:2 ) = Rt16" , "0111101--0--ddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS1_storew_io */, -{ "Rd16 = #-1 ; memw ( Sp + #u5:2 ) = Rt16" , "0111101--0--ddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SS2_storew_sp */, -{ "Rd16 = #U6 ; allocframe ( #u5:3 )" , "011010IIIIIIddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS2_allocframe */, -{ "Rd16 = #U6 ; jump #r9:2" , "0001 -110 --iidddd PPIIIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_jumpseti */, -{ "Rd16 = #U6 ; memb ( Rs16 + #u4:0 ) = #0" , "011010IIIIIIddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS2_storebi0 */, -{ "Rd16 = #U6 ; memb ( Rs16 + #u4:0 ) = #1" , "011010IIIIIIddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS2_storebi1 */, -{ "Rd16 = #U6 ; memb ( Rs16 + #u4:0 ) = Rt16" , "011010IIIIIIddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS1_storeb_io */, -{ "Rd16 = #U6 ; memd ( Sp + #s6:3 ) = Rtt8" , "011010IIIIIIddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS2_stored_sp */, -{ "Rd16 = #U6 ; memh ( Rs16 + #u3:1 ) = Rt16" , "011010IIIIIIddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS2_storeh_io */, -{ "Rd16 = #U6 ; memw ( Rs16 + #u4:2 ) = #0" , "011010IIIIIIddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS2_storewi0 */, -{ "Rd16 = #U6 ; memw ( Rs16 + #u4:2 ) = #1" , "011010IIIIIIddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS2_storewi1 */, -{ "Rd16 = #U6 ; memw ( Rs16 + #u4:2 ) = Rt16" , "011010IIIIIIddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS1_storew_io */, -{ "Rd16 = #U6 ; memw ( Sp + #u5:2 ) = Rt16" , "011010IIIIIIddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SS2_storew_sp */, -{ "Rd16 = #U6 ; p0 = cmp.eq ( Rs16 , #u2 )" , "001010IIIIIIddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_IMPLICIT_WRITES_P0|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_cmpeqi */, -{ "Rd16 = #u6 ; Rx16 = add ( Rs16 , Rx16 )" , "001010iiiiiiddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_COMMUTES|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_addrx_commuted */, -{ "Rd16 = #u6 ; Rx16 = add ( Rx16 , Rs16 )" , "001010iiiiiiddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_COMMUTES|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_addrx */, -{ "Rd16 = #u6 ; dealloc_return" , "010010iiiiiiddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_return */, -{ "Rd16 = #u6 ; deallocframe" , "010010iiiiiiddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_deallocframe */, -{ "Rd16 = #u6 ; if ( ! p0 ) dealloc_return" , "010010iiiiiiddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_return_f */, -{ "Rd16 = #u6 ; if ( ! p0 ) jumpr Lr" , "010010iiiiiiddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_jumpr31_f */, -{ "Rd16 = #u6 ; if ( ! p0 .new ) dealloc_return:nt" , "010010iiiiiiddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_return_fnew */, -{ "Rd16 = #u6 ; if ( ! p0 .new ) jumpr:nt Lr" , "010010iiiiiiddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_jumpr31_fnew */, -{ "Rd16 = #u6 ; if ( p0 ) dealloc_return" , "010010iiiiiiddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_return_t */, -{ "Rd16 = #u6 ; if ( p0 ) jumpr Lr" , "010010iiiiiiddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_jumpr31_t */, -{ "Rd16 = #u6 ; if ( p0 .new ) dealloc_return:nt" , "010010iiiiiiddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_return_tnew */, -{ "Rd16 = #u6 ; if ( p0 .new ) jumpr:nt Lr" , "010010iiiiiiddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_jumpr31_tnew */, -{ "Rd16 = #u6 ; jumpr Lr" , "010010iiiiiiddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_jumpr31 */, -{ "Rd16 = Rs16 ; allocframe ( #u5:3 )" , "01110000ssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS2_allocframe */, -{ "Rd16 = Rs16 ; dealloc_return" , "01010000ssssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_return */, -{ "Rd16 = Rs16 ; deallocframe" , "01010000ssssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_deallocframe */, -{ "Rd16 = Rs16 ; if ( ! p0 ) dealloc_return" , "01010000ssssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_return_f */, -{ "Rd16 = Rs16 ; if ( ! p0 ) jumpr Lr" , "01010000ssssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_jumpr31_f */, -{ "Rd16 = Rs16 ; if ( ! p0 .new ) dealloc_return:nt" , "01010000ssssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_return_fnew */, -{ "Rd16 = Rs16 ; if ( ! p0 .new ) jumpr:nt Lr" , "01010000ssssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_jumpr31_fnew */, -{ "Rd16 = Rs16 ; if ( p0 ) dealloc_return" , "01010000ssssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_return_t */, -{ "Rd16 = Rs16 ; if ( p0 ) jumpr Lr" , "01010000ssssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_jumpr31_t */, -{ "Rd16 = Rs16 ; if ( p0 .new ) dealloc_return:nt" , "01010000ssssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_return_tnew */, -{ "Rd16 = Rs16 ; if ( p0 .new ) jumpr:nt Lr" , "01010000ssssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_jumpr31_tnew */, -{ "Rd16 = Rs16 ; jump #r9:2" , "0001 -111 --iissss PP--dddd iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_jumpsetr */, -{ "Rd16 = Rs16 ; jumpr Lr" , "01010000ssssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_jumpr31 */, -{ "Rd16 = Rs16 ; memd ( Sp + #s6:3 ) = Rtt8" , "01110000ssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS2_stored_sp */, -{ "Rd16 = Rs16 ; memw ( Sp + #u5:2 ) = Rt16" , "01110000ssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS2_storew_sp */, -{ "Rd16 = Ru16 ; Rx16 = add ( Rs16 , Rx16 )" , "00110000uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_addrx_commuted */, -{ "Rd16 = Ru16 ; Rx16 = add ( Rx16 , Rs16 )" , "00110000uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_addrx */, -{ "Rd16 = Ru16 ; memb ( Rs16 + #u4:0 ) = #0" , "01110000uuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS2_storebi0 */, -{ "Rd16 = Ru16 ; memb ( Rs16 + #u4:0 ) = #1" , "01110000uuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS2_storebi1 */, -{ "Rd16 = Ru16 ; memb ( Rs16 + #u4:0 ) = Rt16" , "01110000uuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS1_storeb_io */, -{ "Rd16 = Ru16 ; memh ( Rs16 + #u3:1 ) = Rt16" , "01110000uuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS2_storeh_io */, -{ "Rd16 = Ru16 ; memw ( Rs16 + #u4:2 ) = #0" , "01110000uuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS2_storewi0 */, -{ "Rd16 = Ru16 ; memw ( Rs16 + #u4:2 ) = #1" , "01110000uuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS2_storewi1 */, -{ "Rd16 = Ru16 ; memw ( Rs16 + #u4:2 ) = Rt16" , "01110000uuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SS1_storew_io */, -{ "Rd16 = Ru16 ; p0 = cmp.eq ( Rs16 , #u2 )" , "00110000uuuuddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_cmpeqi */, -{ "Rd16 = add ( Rs16 , #-1 ) ; allocframe ( #u5:3 )" , "01110011ssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS2_allocframe */, -{ "Rd16 = add ( Rs16 , #-1 ) ; dealloc_return" , "01010011ssssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_return */, -{ "Rd16 = add ( Rs16 , #-1 ) ; deallocframe" , "01010011ssssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_deallocframe */, -{ "Rd16 = add ( Rs16 , #-1 ) ; if ( ! p0 ) dealloc_return" , "01010011ssssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_return_f */, -{ "Rd16 = add ( Rs16 , #-1 ) ; if ( ! p0 ) jumpr Lr" , "01010011ssssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_jumpr31_f */, -{ "Rd16 = add ( Rs16 , #-1 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01010011ssssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_return_fnew */, -{ "Rd16 = add ( Rs16 , #-1 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01010011ssssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_jumpr31_fnew */, -{ "Rd16 = add ( Rs16 , #-1 ) ; if ( p0 ) dealloc_return" , "01010011ssssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_return_t */, -{ "Rd16 = add ( Rs16 , #-1 ) ; if ( p0 ) jumpr Lr" , "01010011ssssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_jumpr31_t */, -{ "Rd16 = add ( Rs16 , #-1 ) ; if ( p0 .new ) dealloc_return:nt" , "01010011ssssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_return_tnew */, -{ "Rd16 = add ( Rs16 , #-1 ) ; if ( p0 .new ) jumpr:nt Lr" , "01010011ssssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_jumpr31_tnew */, -{ "Rd16 = add ( Rs16 , #-1 ) ; jumpr Lr" , "01010011ssssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_jumpr31 */, -{ "Rd16 = add ( Rs16 , #-1 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01110011ssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS2_stored_sp */, -{ "Rd16 = add ( Rs16 , #-1 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01110011ssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS2_storew_sp */, -{ "Rd16 = add ( Rs16 , #1 ) ; allocframe ( #u5:3 )" , "01110001ssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS2_allocframe */, -{ "Rd16 = add ( Rs16 , #1 ) ; dealloc_return" , "01010001ssssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_return */, -{ "Rd16 = add ( Rs16 , #1 ) ; deallocframe" , "01010001ssssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_deallocframe */, -{ "Rd16 = add ( Rs16 , #1 ) ; if ( ! p0 ) dealloc_return" , "01010001ssssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_return_f */, -{ "Rd16 = add ( Rs16 , #1 ) ; if ( ! p0 ) jumpr Lr" , "01010001ssssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_jumpr31_f */, -{ "Rd16 = add ( Rs16 , #1 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01010001ssssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_return_fnew */, -{ "Rd16 = add ( Rs16 , #1 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01010001ssssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_jumpr31_fnew */, -{ "Rd16 = add ( Rs16 , #1 ) ; if ( p0 ) dealloc_return" , "01010001ssssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_return_t */, -{ "Rd16 = add ( Rs16 , #1 ) ; if ( p0 ) jumpr Lr" , "01010001ssssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_jumpr31_t */, -{ "Rd16 = add ( Rs16 , #1 ) ; if ( p0 .new ) dealloc_return:nt" , "01010001ssssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_return_tnew */, -{ "Rd16 = add ( Rs16 , #1 ) ; if ( p0 .new ) jumpr:nt Lr" , "01010001ssssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_jumpr31_tnew */, -{ "Rd16 = add ( Rs16 , #1 ) ; jumpr Lr" , "01010001ssssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_jumpr31 */, -{ "Rd16 = add ( Rs16 , #1 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01110001ssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS2_stored_sp */, -{ "Rd16 = add ( Rs16 , #1 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01110001ssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS2_storew_sp */, -{ "Rd16 = add ( Ru16 , #-1 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00110011uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_addrx_commuted */, -{ "Rd16 = add ( Ru16 , #-1 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00110011uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_addrx */, -{ "Rd16 = add ( Ru16 , #-1 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01110011uuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS2_storebi0 */, -{ "Rd16 = add ( Ru16 , #-1 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01110011uuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS2_storebi1 */, -{ "Rd16 = add ( Ru16 , #-1 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01110011uuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS1_storeb_io */, -{ "Rd16 = add ( Ru16 , #-1 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01110011uuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS2_storeh_io */, -{ "Rd16 = add ( Ru16 , #-1 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01110011uuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS2_storewi0 */, -{ "Rd16 = add ( Ru16 , #-1 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01110011uuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS2_storewi1 */, -{ "Rd16 = add ( Ru16 , #-1 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01110011uuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SS1_storew_io */, -{ "Rd16 = add ( Ru16 , #-1 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00110011uuuuddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_cmpeqi */, -{ "Rd16 = add ( Ru16 , #1 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00110001uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_addrx_commuted */, -{ "Rd16 = add ( Ru16 , #1 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00110001uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_addrx */, -{ "Rd16 = add ( Ru16 , #1 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01110001uuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS2_storebi0 */, -{ "Rd16 = add ( Ru16 , #1 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01110001uuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS2_storebi1 */, -{ "Rd16 = add ( Ru16 , #1 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01110001uuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS1_storeb_io */, -{ "Rd16 = add ( Ru16 , #1 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01110001uuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS2_storeh_io */, -{ "Rd16 = add ( Ru16 , #1 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01110001uuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS2_storewi0 */, -{ "Rd16 = add ( Ru16 , #1 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01110001uuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS2_storewi1 */, -{ "Rd16 = add ( Ru16 , #1 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01110001uuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SS1_storew_io */, -{ "Rd16 = add ( Ru16 , #1 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00110001uuuuddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_cmpeqi */, -{ "Rd16 = add ( Sp , #U6:2 ) ; allocframe ( #u5:3 )" , "011011IIIIIIddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS2_allocframe */, -{ "Rd16 = add ( Sp , #U6:2 ) ; memb ( Rs16 + #u4:0 ) = #0" , "011011IIIIIIddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS2_storebi0 */, -{ "Rd16 = add ( Sp , #U6:2 ) ; memb ( Rs16 + #u4:0 ) = #1" , "011011IIIIIIddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS2_storebi1 */, -{ "Rd16 = add ( Sp , #U6:2 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "011011IIIIIIddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS1_storeb_io */, -{ "Rd16 = add ( Sp , #U6:2 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "011011IIIIIIddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS2_stored_sp */, -{ "Rd16 = add ( Sp , #U6:2 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "011011IIIIIIddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS2_storeh_io */, -{ "Rd16 = add ( Sp , #U6:2 ) ; memw ( Rs16 + #u4:2 ) = #0" , "011011IIIIIIddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS2_storewi0 */, -{ "Rd16 = add ( Sp , #U6:2 ) ; memw ( Rs16 + #u4:2 ) = #1" , "011011IIIIIIddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS2_storewi1 */, -{ "Rd16 = add ( Sp , #U6:2 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "011011IIIIIIddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS1_storew_io */, -{ "Rd16 = add ( Sp , #U6:2 ) ; memw ( Sp + #u5:2 ) = Rt16" , "011011IIIIIIddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SS2_storew_sp */, -{ "Rd16 = add ( Sp , #U6:2 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "001011IIIIIIddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_cmpeqi */, -{ "Rd16 = add ( Sp , #u6:2 ) ; Rx16 = add ( Rs16 , Rx16 )" , "001011iiiiiiddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_addrx_commuted */, -{ "Rd16 = add ( Sp , #u6:2 ) ; Rx16 = add ( Rx16 , Rs16 )" , "001011iiiiiiddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_addrx */, -{ "Rd16 = add ( Sp , #u6:2 ) ; dealloc_return" , "010011iiiiiiddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_return */, -{ "Rd16 = add ( Sp , #u6:2 ) ; deallocframe" , "010011iiiiiiddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_deallocframe */, -{ "Rd16 = add ( Sp , #u6:2 ) ; if ( ! p0 ) dealloc_return" , "010011iiiiiiddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_return_f */, -{ "Rd16 = add ( Sp , #u6:2 ) ; if ( ! p0 ) jumpr Lr" , "010011iiiiiiddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_jumpr31_f */, -{ "Rd16 = add ( Sp , #u6:2 ) ; if ( ! p0 .new ) dealloc_return:nt" , "010011iiiiiiddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_return_fnew */, -{ "Rd16 = add ( Sp , #u6:2 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "010011iiiiiiddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_jumpr31_fnew */, -{ "Rd16 = add ( Sp , #u6:2 ) ; if ( p0 ) dealloc_return" , "010011iiiiiiddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_return_t */, -{ "Rd16 = add ( Sp , #u6:2 ) ; if ( p0 ) jumpr Lr" , "010011iiiiiiddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_jumpr31_t */, -{ "Rd16 = add ( Sp , #u6:2 ) ; if ( p0 .new ) dealloc_return:nt" , "010011iiiiiiddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_return_tnew */, -{ "Rd16 = add ( Sp , #u6:2 ) ; if ( p0 .new ) jumpr:nt Lr" , "010011iiiiiiddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_jumpr31_tnew */, -{ "Rd16 = add ( Sp , #u6:2 ) ; jumpr Lr" , "010011iiiiiiddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_jumpr31 */, -{ "Rd16 = and ( Rs16 , #1 ) ; allocframe ( #u5:3 )" , "01110010ssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS2_allocframe */, -{ "Rd16 = and ( Rs16 , #1 ) ; dealloc_return" , "01010010ssssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_return */, -{ "Rd16 = and ( Rs16 , #1 ) ; deallocframe" , "01010010ssssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_deallocframe */, -{ "Rd16 = and ( Rs16 , #1 ) ; if ( ! p0 ) dealloc_return" , "01010010ssssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_return_f */, -{ "Rd16 = and ( Rs16 , #1 ) ; if ( ! p0 ) jumpr Lr" , "01010010ssssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_jumpr31_f */, -{ "Rd16 = and ( Rs16 , #1 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01010010ssssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_return_fnew */, -{ "Rd16 = and ( Rs16 , #1 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01010010ssssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_jumpr31_fnew */, -{ "Rd16 = and ( Rs16 , #1 ) ; if ( p0 ) dealloc_return" , "01010010ssssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_return_t */, -{ "Rd16 = and ( Rs16 , #1 ) ; if ( p0 ) jumpr Lr" , "01010010ssssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_jumpr31_t */, -{ "Rd16 = and ( Rs16 , #1 ) ; if ( p0 .new ) dealloc_return:nt" , "01010010ssssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_return_tnew */, -{ "Rd16 = and ( Rs16 , #1 ) ; if ( p0 .new ) jumpr:nt Lr" , "01010010ssssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_jumpr31_tnew */, -{ "Rd16 = and ( Rs16 , #1 ) ; jumpr Lr" , "01010010ssssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_jumpr31 */, -{ "Rd16 = and ( Rs16 , #1 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01110010ssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS2_stored_sp */, -{ "Rd16 = and ( Rs16 , #1 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01110010ssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS2_storew_sp */, -{ "Rd16 = and ( Rs16 , #255 ) ; allocframe ( #u5:3 )" , "01110111ssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS2_allocframe */, -{ "Rd16 = and ( Rs16 , #255 ) ; dealloc_return" , "01010111ssssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_return */, -{ "Rd16 = and ( Rs16 , #255 ) ; deallocframe" , "01010111ssssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_deallocframe */, -{ "Rd16 = and ( Rs16 , #255 ) ; if ( ! p0 ) dealloc_return" , "01010111ssssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_return_f */, -{ "Rd16 = and ( Rs16 , #255 ) ; if ( ! p0 ) jumpr Lr" , "01010111ssssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_jumpr31_f */, -{ "Rd16 = and ( Rs16 , #255 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01010111ssssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_return_fnew */, -{ "Rd16 = and ( Rs16 , #255 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01010111ssssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_jumpr31_fnew */, -{ "Rd16 = and ( Rs16 , #255 ) ; if ( p0 ) dealloc_return" , "01010111ssssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_return_t */, -{ "Rd16 = and ( Rs16 , #255 ) ; if ( p0 ) jumpr Lr" , "01010111ssssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_jumpr31_t */, -{ "Rd16 = and ( Rs16 , #255 ) ; if ( p0 .new ) dealloc_return:nt" , "01010111ssssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_return_tnew */, -{ "Rd16 = and ( Rs16 , #255 ) ; if ( p0 .new ) jumpr:nt Lr" , "01010111ssssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_jumpr31_tnew */, -{ "Rd16 = and ( Rs16 , #255 ) ; jumpr Lr" , "01010111ssssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_jumpr31 */, -{ "Rd16 = and ( Rs16 , #255 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01110111ssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS2_stored_sp */, -{ "Rd16 = and ( Rs16 , #255 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01110111ssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS2_storew_sp */, -{ "Rd16 = and ( Ru16 , #1 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00110010uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_addrx_commuted */, -{ "Rd16 = and ( Ru16 , #1 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00110010uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_addrx */, -{ "Rd16 = and ( Ru16 , #1 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01110010uuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS2_storebi0 */, -{ "Rd16 = and ( Ru16 , #1 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01110010uuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS2_storebi1 */, -{ "Rd16 = and ( Ru16 , #1 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01110010uuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS1_storeb_io */, -{ "Rd16 = and ( Ru16 , #1 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01110010uuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS2_storeh_io */, -{ "Rd16 = and ( Ru16 , #1 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01110010uuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS2_storewi0 */, -{ "Rd16 = and ( Ru16 , #1 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01110010uuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS2_storewi1 */, -{ "Rd16 = and ( Ru16 , #1 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01110010uuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SS1_storew_io */, -{ "Rd16 = and ( Ru16 , #1 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00110010uuuuddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_cmpeqi */, -{ "Rd16 = and ( Ru16 , #255 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00110111uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_addrx_commuted */, -{ "Rd16 = and ( Ru16 , #255 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00110111uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_addrx */, -{ "Rd16 = and ( Ru16 , #255 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01110111uuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS2_storebi0 */, -{ "Rd16 = and ( Ru16 , #255 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01110111uuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS2_storebi1 */, -{ "Rd16 = and ( Ru16 , #255 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01110111uuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS1_storeb_io */, -{ "Rd16 = and ( Ru16 , #255 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01110111uuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS2_storeh_io */, -{ "Rd16 = and ( Ru16 , #255 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01110111uuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS2_storewi0 */, -{ "Rd16 = and ( Ru16 , #255 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01110111uuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS2_storewi1 */, -{ "Rd16 = and ( Ru16 , #255 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01110111uuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SS1_storew_io */, -{ "Rd16 = and ( Ru16 , #255 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00110111uuuuddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_cmpeqi */, -{ "Rd16 = memb ( Rs16 + #U3:0 ) ; allocframe ( #u5:3 )" , "11010IIIssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS2_allocframe */, -{ "Rd16 = memb ( Rs16 + #U3:0 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "11010IIIssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS2_stored_sp */, -{ "Rd16 = memb ( Rs16 + #U3:0 ) ; memw ( Sp + #u5:2 ) = Rt16" , "11010IIIssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS2_storew_sp */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; dealloc_return" , "00110iiissssddddEE01111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_return */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; deallocframe" , "00110iiissssddddEE01111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_deallocframe */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; if ( ! p0 ) dealloc_return" , "00110iiissssddddEE01111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_return_f */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; if ( ! p0 ) jumpr Lr" , "00110iiissssddddEE01111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_jumpr31_f */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; if ( ! p0 .new ) dealloc_return:nt" , "00110iiissssddddEE01111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_return_fnew */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "00110iiissssddddEE01111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_jumpr31_fnew */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; if ( p0 ) dealloc_return" , "00110iiissssddddEE01111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_return_t */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; if ( p0 ) jumpr Lr" , "00110iiissssddddEE01111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_jumpr31_t */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; if ( p0 .new ) dealloc_return:nt" , "00110iiissssddddEE01111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_return_tnew */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; if ( p0 .new ) jumpr:nt Lr" , "00110iiissssddddEE01111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_jumpr31_tnew */, -{ "Rd16 = memb ( Rs16 + #u3:0 ) ; jumpr Lr" , "00110iiissssddddEE01111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_jumpr31 */, -{ "Rd16 = memb ( Ru16 + #U3:0 ) ; memb ( Rs16 + #u4:0 ) = #0" , "11010IIIuuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS2_storebi0 */, -{ "Rd16 = memb ( Ru16 + #U3:0 ) ; memb ( Rs16 + #u4:0 ) = #1" , "11010IIIuuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS2_storebi1 */, -{ "Rd16 = memb ( Ru16 + #U3:0 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "10010IIIuuuuddddEE11iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS1_storeb_io */, -{ "Rd16 = memb ( Ru16 + #U3:0 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "11010IIIuuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS2_storeh_io */, -{ "Rd16 = memb ( Ru16 + #U3:0 ) ; memw ( Rs16 + #u4:2 ) = #0" , "11010IIIuuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS2_storewi0 */, -{ "Rd16 = memb ( Ru16 + #U3:0 ) ; memw ( Rs16 + #u4:2 ) = #1" , "11010IIIuuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS2_storewi1 */, -{ "Rd16 = memb ( Ru16 + #U3:0 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "10010IIIuuuuddddEE10iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SS1_storew_io */, -{ "Rd16 = memh ( Rs16 + #U3:1 ) ; allocframe ( #u5:3 )" , "11000IIIssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS2_allocframe */, -{ "Rd16 = memh ( Rs16 + #U3:1 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "11000IIIssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS2_stored_sp */, -{ "Rd16 = memh ( Rs16 + #U3:1 ) ; memw ( Sp + #u5:2 ) = Rt16" , "11000IIIssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS2_storew_sp */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; dealloc_return" , "00100iiissssddddEE01111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_return */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; deallocframe" , "00100iiissssddddEE01111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_deallocframe */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; if ( ! p0 ) dealloc_return" , "00100iiissssddddEE01111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_return_f */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; if ( ! p0 ) jumpr Lr" , "00100iiissssddddEE01111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_jumpr31_f */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; if ( ! p0 .new ) dealloc_return:nt" , "00100iiissssddddEE01111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_return_fnew */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "00100iiissssddddEE01111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_jumpr31_fnew */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; if ( p0 ) dealloc_return" , "00100iiissssddddEE01111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_return_t */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; if ( p0 ) jumpr Lr" , "00100iiissssddddEE01111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_jumpr31_t */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; if ( p0 .new ) dealloc_return:nt" , "00100iiissssddddEE01111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_return_tnew */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; if ( p0 .new ) jumpr:nt Lr" , "00100iiissssddddEE01111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_jumpr31_tnew */, -{ "Rd16 = memh ( Rs16 + #u3:1 ) ; jumpr Lr" , "00100iiissssddddEE01111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_jumpr31 */, -{ "Rd16 = memh ( Ru16 + #U3:1 ) ; memb ( Rs16 + #u4:0 ) = #0" , "11000IIIuuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS2_storebi0 */, -{ "Rd16 = memh ( Ru16 + #U3:1 ) ; memb ( Rs16 + #u4:0 ) = #1" , "11000IIIuuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS2_storebi1 */, -{ "Rd16 = memh ( Ru16 + #U3:1 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "10000IIIuuuuddddEE11iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS1_storeb_io */, -{ "Rd16 = memh ( Ru16 + #U3:1 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "11000IIIuuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS2_storeh_io */, -{ "Rd16 = memh ( Ru16 + #U3:1 ) ; memw ( Rs16 + #u4:2 ) = #0" , "11000IIIuuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS2_storewi0 */, -{ "Rd16 = memh ( Ru16 + #U3:1 ) ; memw ( Rs16 + #u4:2 ) = #1" , "11000IIIuuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS2_storewi1 */, -{ "Rd16 = memh ( Ru16 + #U3:1 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "10000IIIuuuuddddEE10iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SS1_storew_io */, -{ "Rd16 = memub ( Rs16 + #U4:0 ) ; allocframe ( #u5:3 )" , "1101IIIIssssddddEE01110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS2_allocframe */, -{ "Rd16 = memub ( Rs16 + #U4:0 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "1101IIIIssssddddEE00101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS2_stored_sp */, -{ "Rd16 = memub ( Rs16 + #U4:0 ) ; memw ( Sp + #u5:2 ) = Rt16" , "1101IIIIssssddddEE00100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS2_storew_sp */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; dealloc_return" , "0001iiiissssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_return */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; deallocframe" , "0001iiiissssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_deallocframe */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; if ( ! p0 ) dealloc_return" , "0001iiiissssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_return_f */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; if ( ! p0 ) jumpr Lr" , "0001iiiissssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_jumpr31_f */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; if ( ! p0 .new ) dealloc_return:nt" , "0001iiiissssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_return_fnew */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "0001iiiissssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_jumpr31_fnew */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; if ( p0 ) dealloc_return" , "0001iiiissssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_return_t */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; if ( p0 ) jumpr Lr" , "0001iiiissssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_jumpr31_t */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; if ( p0 .new ) dealloc_return:nt" , "0001iiiissssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_return_tnew */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; if ( p0 .new ) jumpr:nt Lr" , "0001iiiissssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_jumpr31_tnew */, -{ "Rd16 = memub ( Rs16 + #u4:0 ) ; jumpr Lr" , "0001iiiissssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_jumpr31 */, -{ "Rd16 = memub ( Ru16 + #U4:0 ) ; memb ( Rs16 + #u4:0 ) = #0" , "1101IIIIuuuuddddEE010010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS2_storebi0 */, -{ "Rd16 = memub ( Ru16 + #U4:0 ) ; memb ( Rs16 + #u4:0 ) = #1" , "1101IIIIuuuuddddEE010011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS2_storebi1 */, -{ "Rd16 = memub ( Ru16 + #U4:0 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "1001IIIIuuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS1_storeb_io */, -{ "Rd16 = memub ( Ru16 + #U4:0 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "1101IIIIuuuuddddEE000iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS2_storeh_io */, -{ "Rd16 = memub ( Ru16 + #U4:0 ) ; memw ( Rs16 + #u4:2 ) = #0" , "1101IIIIuuuuddddEE010000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS2_storewi0 */, -{ "Rd16 = memub ( Ru16 + #U4:0 ) ; memw ( Rs16 + #u4:2 ) = #1" , "1101IIIIuuuuddddEE010001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS2_storewi1 */, -{ "Rd16 = memub ( Ru16 + #U4:0 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "1001IIIIuuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SS1_storew_io */, -{ "Rd16 = memuh ( Rs16 + #U3:1 ) ; allocframe ( #u5:3 )" , "11001IIIssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS2_allocframe */, -{ "Rd16 = memuh ( Rs16 + #U3:1 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "11001IIIssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS2_stored_sp */, -{ "Rd16 = memuh ( Rs16 + #U3:1 ) ; memw ( Sp + #u5:2 ) = Rt16" , "11001IIIssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS2_storew_sp */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; dealloc_return" , "00101iiissssddddEE01111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_return */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; deallocframe" , "00101iiissssddddEE01111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_deallocframe */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; if ( ! p0 ) dealloc_return" , "00101iiissssddddEE01111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_return_f */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; if ( ! p0 ) jumpr Lr" , "00101iiissssddddEE01111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_jumpr31_f */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; if ( ! p0 .new ) dealloc_return:nt" , "00101iiissssddddEE01111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_return_fnew */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "00101iiissssddddEE01111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_jumpr31_fnew */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; if ( p0 ) dealloc_return" , "00101iiissssddddEE01111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_return_t */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; if ( p0 ) jumpr Lr" , "00101iiissssddddEE01111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_jumpr31_t */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; if ( p0 .new ) dealloc_return:nt" , "00101iiissssddddEE01111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_return_tnew */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; if ( p0 .new ) jumpr:nt Lr" , "00101iiissssddddEE01111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_jumpr31_tnew */, -{ "Rd16 = memuh ( Rs16 + #u3:1 ) ; jumpr Lr" , "00101iiissssddddEE01111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_jumpr31 */, -{ "Rd16 = memuh ( Ru16 + #U3:1 ) ; memb ( Rs16 + #u4:0 ) = #0" , "11001IIIuuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS2_storebi0 */, -{ "Rd16 = memuh ( Ru16 + #U3:1 ) ; memb ( Rs16 + #u4:0 ) = #1" , "11001IIIuuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS2_storebi1 */, -{ "Rd16 = memuh ( Ru16 + #U3:1 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "10001IIIuuuuddddEE11iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS1_storeb_io */, -{ "Rd16 = memuh ( Ru16 + #U3:1 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "11001IIIuuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS2_storeh_io */, -{ "Rd16 = memuh ( Ru16 + #U3:1 ) ; memw ( Rs16 + #u4:2 ) = #0" , "11001IIIuuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS2_storewi0 */, -{ "Rd16 = memuh ( Ru16 + #U3:1 ) ; memw ( Rs16 + #u4:2 ) = #1" , "11001IIIuuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS2_storewi1 */, -{ "Rd16 = memuh ( Ru16 + #U3:1 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "10001IIIuuuuddddEE10iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SS1_storew_io */, -{ "Rd16 = memw ( Rs16 + #U4:2 ) ; allocframe ( #u5:3 )" , "1100IIIIssssddddEE01110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS2_allocframe */, -{ "Rd16 = memw ( Rs16 + #U4:2 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "1100IIIIssssddddEE00101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS2_stored_sp */, -{ "Rd16 = memw ( Rs16 + #U4:2 ) ; memw ( Sp + #u5:2 ) = Rt16" , "1100IIIIssssddddEE00100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS2_storew_sp */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; dealloc_return" , "0000iiiissssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_return */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; deallocframe" , "0000iiiissssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_deallocframe */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; if ( ! p0 ) dealloc_return" , "0000iiiissssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_return_f */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; if ( ! p0 ) jumpr Lr" , "0000iiiissssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_jumpr31_f */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; if ( ! p0 .new ) dealloc_return:nt" , "0000iiiissssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_return_fnew */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "0000iiiissssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_jumpr31_fnew */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; if ( p0 ) dealloc_return" , "0000iiiissssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_return_t */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; if ( p0 ) jumpr Lr" , "0000iiiissssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_jumpr31_t */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; if ( p0 .new ) dealloc_return:nt" , "0000iiiissssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_return_tnew */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; if ( p0 .new ) jumpr:nt Lr" , "0000iiiissssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_jumpr31_tnew */, -{ "Rd16 = memw ( Rs16 + #u4:2 ) ; jumpr Lr" , "0000iiiissssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_jumpr31 */, -{ "Rd16 = memw ( Ru16 + #U4:2 ) ; memb ( Rs16 + #u4:0 ) = #0" , "1100IIIIuuuuddddEE010010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS2_storebi0 */, -{ "Rd16 = memw ( Ru16 + #U4:2 ) ; memb ( Rs16 + #u4:0 ) = #1" , "1100IIIIuuuuddddEE010011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS2_storebi1 */, -{ "Rd16 = memw ( Ru16 + #U4:2 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "1000IIIIuuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS1_storeb_io */, -{ "Rd16 = memw ( Ru16 + #U4:2 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "1100IIIIuuuuddddEE000iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS2_storeh_io */, -{ "Rd16 = memw ( Ru16 + #U4:2 ) ; memw ( Rs16 + #u4:2 ) = #0" , "1100IIIIuuuuddddEE010000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS2_storewi0 */, -{ "Rd16 = memw ( Ru16 + #U4:2 ) ; memw ( Rs16 + #u4:2 ) = #1" , "1100IIIIuuuuddddEE010001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS2_storewi1 */, -{ "Rd16 = memw ( Ru16 + #U4:2 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "1000IIIIuuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SS1_storew_io */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; allocframe ( #u5:3 )" , "1101110IIIIIddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS2_allocframe */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; memb ( Rs16 + #u4:0 ) = #0" , "1101110IIIIIddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS2_storebi0 */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; memb ( Rs16 + #u4:0 ) = #1" , "1101110IIIIIddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS2_storebi1 */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "1001110IIIIIddddEE11iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS1_storeb_io */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "1101110IIIIIddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS2_stored_sp */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "1101110IIIIIddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS2_storeh_io */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; memw ( Rs16 + #u4:2 ) = #0" , "1101110IIIIIddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS2_storewi0 */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; memw ( Rs16 + #u4:2 ) = #1" , "1101110IIIIIddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS2_storewi1 */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "1001110IIIIIddddEE10iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS1_storew_io */, -{ "Rd16 = memw ( Sp + #U5:2 ) ; memw ( Sp + #u5:2 ) = Rt16" , "1101110IIIIIddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SS2_storew_sp */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; dealloc_return" , "0011110iiiiiddddEE01111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_return */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; deallocframe" , "0011110iiiiiddddEE01111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_deallocframe */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; if ( ! p0 ) dealloc_return" , "0011110iiiiiddddEE01111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_return_f */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; if ( ! p0 ) jumpr Lr" , "0011110iiiiiddddEE01111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_jumpr31_f */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; if ( ! p0 .new ) dealloc_return:nt" , "0011110iiiiiddddEE01111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_return_fnew */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "0011110iiiiiddddEE01111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_jumpr31_fnew */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; if ( p0 ) dealloc_return" , "0011110iiiiiddddEE01111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_return_t */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; if ( p0 ) jumpr Lr" , "0011110iiiiiddddEE01111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_jumpr31_t */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; if ( p0 .new ) dealloc_return:nt" , "0011110iiiiiddddEE01111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_return_tnew */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; if ( p0 .new ) jumpr:nt Lr" , "0011110iiiiiddddEE01111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_jumpr31_tnew */, -{ "Rd16 = memw ( Sp + #u5:2 ) ; jumpr Lr" , "0011110iiiiiddddEE01111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_jumpr31 */, -{ "Rd16 = sxtb ( Rs16 ) ; allocframe ( #u5:3 )" , "01110101ssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS2_allocframe */, -{ "Rd16 = sxtb ( Rs16 ) ; dealloc_return" , "01010101ssssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_return */, -{ "Rd16 = sxtb ( Rs16 ) ; deallocframe" , "01010101ssssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_deallocframe */, -{ "Rd16 = sxtb ( Rs16 ) ; if ( ! p0 ) dealloc_return" , "01010101ssssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_return_f */, -{ "Rd16 = sxtb ( Rs16 ) ; if ( ! p0 ) jumpr Lr" , "01010101ssssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_jumpr31_f */, -{ "Rd16 = sxtb ( Rs16 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01010101ssssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_return_fnew */, -{ "Rd16 = sxtb ( Rs16 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01010101ssssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_jumpr31_fnew */, -{ "Rd16 = sxtb ( Rs16 ) ; if ( p0 ) dealloc_return" , "01010101ssssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_return_t */, -{ "Rd16 = sxtb ( Rs16 ) ; if ( p0 ) jumpr Lr" , "01010101ssssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_jumpr31_t */, -{ "Rd16 = sxtb ( Rs16 ) ; if ( p0 .new ) dealloc_return:nt" , "01010101ssssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_return_tnew */, -{ "Rd16 = sxtb ( Rs16 ) ; if ( p0 .new ) jumpr:nt Lr" , "01010101ssssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_jumpr31_tnew */, -{ "Rd16 = sxtb ( Rs16 ) ; jumpr Lr" , "01010101ssssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_jumpr31 */, -{ "Rd16 = sxtb ( Rs16 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01110101ssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS2_stored_sp */, -{ "Rd16 = sxtb ( Rs16 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01110101ssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS2_storew_sp */, -{ "Rd16 = sxtb ( Ru16 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00110101uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_addrx_commuted */, -{ "Rd16 = sxtb ( Ru16 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00110101uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_addrx */, -{ "Rd16 = sxtb ( Ru16 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01110101uuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS2_storebi0 */, -{ "Rd16 = sxtb ( Ru16 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01110101uuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS2_storebi1 */, -{ "Rd16 = sxtb ( Ru16 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01110101uuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS1_storeb_io */, -{ "Rd16 = sxtb ( Ru16 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01110101uuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS2_storeh_io */, -{ "Rd16 = sxtb ( Ru16 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01110101uuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS2_storewi0 */, -{ "Rd16 = sxtb ( Ru16 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01110101uuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS2_storewi1 */, -{ "Rd16 = sxtb ( Ru16 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01110101uuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SS1_storew_io */, -{ "Rd16 = sxtb ( Ru16 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00110101uuuuddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_cmpeqi */, -{ "Rd16 = sxth ( Rs16 ) ; allocframe ( #u5:3 )" , "01110100ssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS2_allocframe */, -{ "Rd16 = sxth ( Rs16 ) ; dealloc_return" , "01010100ssssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_return */, -{ "Rd16 = sxth ( Rs16 ) ; deallocframe" , "01010100ssssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_deallocframe */, -{ "Rd16 = sxth ( Rs16 ) ; if ( ! p0 ) dealloc_return" , "01010100ssssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_return_f */, -{ "Rd16 = sxth ( Rs16 ) ; if ( ! p0 ) jumpr Lr" , "01010100ssssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_jumpr31_f */, -{ "Rd16 = sxth ( Rs16 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01010100ssssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_return_fnew */, -{ "Rd16 = sxth ( Rs16 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01010100ssssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_jumpr31_fnew */, -{ "Rd16 = sxth ( Rs16 ) ; if ( p0 ) dealloc_return" , "01010100ssssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_return_t */, -{ "Rd16 = sxth ( Rs16 ) ; if ( p0 ) jumpr Lr" , "01010100ssssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_jumpr31_t */, -{ "Rd16 = sxth ( Rs16 ) ; if ( p0 .new ) dealloc_return:nt" , "01010100ssssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_return_tnew */, -{ "Rd16 = sxth ( Rs16 ) ; if ( p0 .new ) jumpr:nt Lr" , "01010100ssssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_jumpr31_tnew */, -{ "Rd16 = sxth ( Rs16 ) ; jumpr Lr" , "01010100ssssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_jumpr31 */, -{ "Rd16 = sxth ( Rs16 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01110100ssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS2_stored_sp */, -{ "Rd16 = sxth ( Rs16 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01110100ssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS2_storew_sp */, -{ "Rd16 = sxth ( Ru16 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00110100uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_addrx_commuted */, -{ "Rd16 = sxth ( Ru16 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00110100uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_addrx */, -{ "Rd16 = sxth ( Ru16 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01110100uuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS2_storebi0 */, -{ "Rd16 = sxth ( Ru16 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01110100uuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS2_storebi1 */, -{ "Rd16 = sxth ( Ru16 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01110100uuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS1_storeb_io */, -{ "Rd16 = sxth ( Ru16 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01110100uuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS2_storeh_io */, -{ "Rd16 = sxth ( Ru16 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01110100uuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS2_storewi0 */, -{ "Rd16 = sxth ( Ru16 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01110100uuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS2_storewi1 */, -{ "Rd16 = sxth ( Ru16 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01110100uuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SS1_storew_io */, -{ "Rd16 = sxth ( Ru16 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00110100uuuuddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_cmpeqi */, -{ "Rd16 = zxth ( Rs16 ) ; allocframe ( #u5:3 )" , "01110110ssssddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS2_allocframe */, -{ "Rd16 = zxth ( Rs16 ) ; dealloc_return" , "01010110ssssddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_return */, -{ "Rd16 = zxth ( Rs16 ) ; deallocframe" , "01010110ssssddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_deallocframe */, -{ "Rd16 = zxth ( Rs16 ) ; if ( ! p0 ) dealloc_return" , "01010110ssssddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_return_f */, -{ "Rd16 = zxth ( Rs16 ) ; if ( ! p0 ) jumpr Lr" , "01010110ssssddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_jumpr31_f */, -{ "Rd16 = zxth ( Rs16 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01010110ssssddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_return_fnew */, -{ "Rd16 = zxth ( Rs16 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01010110ssssddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_jumpr31_fnew */, -{ "Rd16 = zxth ( Rs16 ) ; if ( p0 ) dealloc_return" , "01010110ssssddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_return_t */, -{ "Rd16 = zxth ( Rs16 ) ; if ( p0 ) jumpr Lr" , "01010110ssssddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_jumpr31_t */, -{ "Rd16 = zxth ( Rs16 ) ; if ( p0 .new ) dealloc_return:nt" , "01010110ssssddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_return_tnew */, -{ "Rd16 = zxth ( Rs16 ) ; if ( p0 .new ) jumpr:nt Lr" , "01010110ssssddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_jumpr31_tnew */, -{ "Rd16 = zxth ( Rs16 ) ; jumpr Lr" , "01010110ssssddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_jumpr31 */, -{ "Rd16 = zxth ( Rs16 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01110110ssssddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS2_stored_sp */, -{ "Rd16 = zxth ( Rs16 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01110110ssssddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS2_storew_sp */, -{ "Rd16 = zxth ( Ru16 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00110110uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_addrx_commuted */, -{ "Rd16 = zxth ( Ru16 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00110110uuuuddddEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_addrx */, -{ "Rd16 = zxth ( Ru16 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01110110uuuuddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS2_storebi0 */, -{ "Rd16 = zxth ( Ru16 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01110110uuuuddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS2_storebi1 */, -{ "Rd16 = zxth ( Ru16 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01110110uuuuddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS1_storeb_io */, -{ "Rd16 = zxth ( Ru16 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01110110uuuuddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS2_storeh_io */, -{ "Rd16 = zxth ( Ru16 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01110110uuuuddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS2_storewi0 */, -{ "Rd16 = zxth ( Ru16 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01110110uuuuddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS2_storewi1 */, -{ "Rd16 = zxth ( Ru16 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01110110uuuuddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SS1_storew_io */, -{ "Rd16 = zxth ( Ru16 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00110110uuuuddddEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_cmpeqi */, -{ "Rd32 , Pe4 = sfinvsqrta ( Rs32 )" , "1000 1011 111sssss PP------ 0eeddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_COMPAT_ACCURACY|A_FPOP, NULL} /* F2_sfinvsqrta */, -{ "Rd32 , Pe4 = sfrecipa ( Rs32 , Rt32 )" , "11101011111sssss PP0ttttt 1eeddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_COMPAT_ACCURACY|A_FPOP, NULL} /* F2_sfrecipa */, -{ "Rd32 = ! cmp.eq ( Rs32 , #s8 )" , "0111 0011 -11sssss PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A4_rcmpneqi */, -{ "Rd32 = ! cmp.eq ( Rs32 , Rt32 )" , "1111 0011 011sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A4_rcmpneq */, -{ "Rd32 = #s16" , "0111 1000 ii-iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_tfrsi */, -{ "Rd32 = + mpyi ( Rs32 , #u8 )" , "111000000--sssss PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_ROPS_2|A_MPY|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* M2_mpysip */, -{ "Rd32 = - mpyi ( Rs32 , #u8 )" , "111000001--sssss PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_ROPS_2|A_MPY, NULL} /* M2_mpysin */, -{ "Rd32 = Cs32" , "0110 1010 000sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0, NULL} /* A2_tfrcrr */, -{ "Rd32 = Gs32" , "0110 1010 001sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_GUEST|A_NOTE_GUEST, NULL} /* G4_tfrgcrr */, -{ "Rd32 = Ps4" , "1000 1001 -1- ---ss PP------ --- ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* C2_tfrpr */, -{ "Rd32 = Rs32" , "0111 0000 011sssss PP0----- ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_tfr */, -{ "Rd32 = Ss64" , "0110 1110 1-ssssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV, NULL} /* Y2_tfrscrr */, -{ "Rd32 = abs ( Rs32 ) :sat" , "1000 1100 100sssss PP------ 1 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_abssat */, -{ "Rd32 = abs ( Rs32 )" , "1000 1100 100sssss PP------ 1 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_abs */, -{ "Rd32 = add ( #u6 , mpyi ( Rs32 , #U6 ) )" , "1101 1000 Iii sssss PPiddddd iiiIIIII" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_MPY|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* M4_mpyri_addi */, -{ "Rd32 = add ( #u6 , mpyi ( Rs32 , Rt32 ) )" , "1101 0111 0ii sssss PPittttt iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_MPY|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* M4_mpyrr_addi */, -{ "Rd32 = add ( Rs32 , #s16 )" , "1011 iiii iiisssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_addi */, -{ "Rd32 = add ( Rs32 , Rt32 ) :sat :deprecated" , "1101 0101 100sssss PP-ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* dep_A2_addsat */, -{ "Rd32 = add ( Rs32 , Rt32 ) :sat" , "1111 0110 010sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_addsat */, -{ "Rd32 = add ( Rs32 , Rt32 )" , "1111 0011 000sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_add */, -{ "Rd32 = add ( Rs32 , add ( Ru32 , #s6 ) )" , "1101 1011 0ii sssss PPiddddd iiiuuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_addaddi */, -{ "Rd32 = add ( Rs32 , sub ( #s6 , Ru32 ) )" , "1101 1011 1ii sssss PPiddddd iiiuuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_subaddi */, -{ "Rd32 = add ( Rt32.h , Rs32.h ) :<<16" , "1101 0101 010sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_addh_h16_hh */, -{ "Rd32 = add ( Rt32.h , Rs32.h ) :sat :<<16" , "1101 0101 010sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_addh_h16_sat_hh */, -{ "Rd32 = add ( Rt32.h , Rs32.l ) :<<16" , "1101 0101 010sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_addh_h16_hl */, -{ "Rd32 = add ( Rt32.h , Rs32.l ) :sat :<<16" , "1101 0101 010sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_addh_h16_sat_hl */, -{ "Rd32 = add ( Rt32.l , Rs32.h ) :<<16" , "1101 0101 010sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_addh_h16_lh */, -{ "Rd32 = add ( Rt32.l , Rs32.h ) :sat :<<16" , "1101 0101 010sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_addh_h16_sat_lh */, -{ "Rd32 = add ( Rt32.l , Rs32.h ) :sat" , "1101 0101 000sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_addh_l16_sat_hl */, -{ "Rd32 = add ( Rt32.l , Rs32.h )" , "1101 0101 000sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_addh_l16_hl */, -{ "Rd32 = add ( Rt32.l , Rs32.l ) :<<16" , "1101 0101 010sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_addh_h16_ll */, -{ "Rd32 = add ( Rt32.l , Rs32.l ) :sat :<<16" , "1101 0101 010sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_addh_h16_sat_ll */, -{ "Rd32 = add ( Rt32.l , Rs32.l ) :sat" , "1101 0101 000sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_addh_l16_sat_ll */, -{ "Rd32 = add ( Rt32.l , Rs32.l )" , "1101 0101 000sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_addh_l16_ll */, -{ "Rd32 = add ( Ru32 , mpyi ( #u6:2 , Rs32 ) )" , "1101 1111 0ii sssss PPiddddd iiiuuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_MPY, NULL} /* M4_mpyri_addr_u2 */, -{ "Rd32 = add ( Ru32 , mpyi ( Rs32 , #u6 ) )" , "1101 1111 1ii sssss PPiddddd iiiuuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_MPY|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* M4_mpyri_addr */, -{ "Rd32 = add ( clb ( Rs32 ) , #s6 )" , "1000 1100 001sssss PPiiiiii 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S4_clbaddi */, -{ "Rd32 = add ( clb ( Rss32 ) , #s6 )" , "1000 1000 011sssss PPiiiiii 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S4_clbpaddi */, -{ "Rd32 = add ( pc , #u6 )" , "0110 1010 01001001 PP-iiiii i--ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C4_addipc */, -{ "Rd32 = addasl ( Rt32 , Rs32 , #u3 )" , "1100 0100 000 sssss PP0ttttt iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_addasl_rrri */, -{ "Rd32 = and ( Rs32 , #s10 )" , "0111 0110 00isssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_andir */, -{ "Rd32 = and ( Rs32 , Rt32 )" , "1111 0001 000sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_and */, -{ "Rd32 = and ( Rt32 , ~ Rs32 )" , "1111 0001 100sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A4_andn */, -{ "Rd32 = asl ( Rs32 , #u5 ) :sat" , "1000 1100 010sssss PP0iiiii 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_asl_i_r_sat */, -{ "Rd32 = asl ( Rs32 , #u5 )" , "1000 1100 000sssss PP0iiiii 0 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asl_i_r */, -{ "Rd32 = asl ( Rs32 , Rt32 ) :sat" , "1100 0110 00-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_BIDIRSHIFTL|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_asl_r_r_sat */, -{ "Rd32 = asl ( Rs32 , Rt32 )" , "1100 0110 01-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S2_asl_r_r */, -{ "Rd32 = aslh ( Rs32 )" , "0111 0000 000sssss PP0----- ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_aslh */, -{ "Rd32 = asr ( Rs32 , #u5 ) :rnd" , "1000 1100 010sssss PP0iiiii 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asr_i_r_rnd */, -{ "Rd32 = asr ( Rs32 , #u5 )" , "1000 1100 000sssss PP0iiiii 0 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asr_i_r */, -{ "Rd32 = asr ( Rs32 , Rt32 ) :sat" , "1100 0110 00-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_BIDIRSHIFTR|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_asr_r_r_sat */, -{ "Rd32 = asr ( Rs32 , Rt32 )" , "1100 0110 01-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTR, NULL} /* S2_asr_r_r */, -{ "Rd32 = asrh ( Rs32 )" , "0111 0000 001sssss PP0----- ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_asrh */, -{ "Rd32 = asrrnd ( Rs32 , #u5 )" , "0000dddddsssssiiiii0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_asr_i_r_rnd_goodsyntax)}, /* mapped to Rd32=Rs32 or Rd32=asr(Rs32,#u5-1):rnd */ -{ "Rd32 = brev ( Rs32 )" , "1000 1100 010sssss PP------ 1 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_brev */, -{ "Rd32 = cl0 ( Rs32 )" , "1000 1100 000sssss PP------ 1 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_cl0 */, -{ "Rd32 = cl0 ( Rss32 )" , "1000 1000 010sssss PP------ 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_cl0p */, -{ "Rd32 = cl1 ( Rs32 )" , "1000 1100 000sssss PP------ 1 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_cl1 */, -{ "Rd32 = cl1 ( Rss32 )" , "1000 1000 010sssss PP------ 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_cl1p */, -{ "Rd32 = clb ( Rs32 )" , "1000 1100 000sssss PP------ 1 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_clb */, -{ "Rd32 = clb ( Rss32 )" , "1000 1000 010sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_clbp */, -{ "Rd32 = clrbit ( Rs32 , #u5 )" , "1000 1100 110sssss PP0iiiii 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_clrbit_i */, -{ "Rd32 = clrbit ( Rs32 , Rt32 )" , "1100 0110 10-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S2_clrbit_r */, -{ "Rd32 = cmp.eq ( Rs32 , #s8 )" , "0111 0011 -10sssss PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A4_rcmpeqi */, -{ "Rd32 = cmp.eq ( Rs32 , Rt32 )" , "1111 0011 010sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A4_rcmpeq */, -{ "Rd32 = cmpy ( Rs32 , Rt32 ) :<<1 :rnd :sat" , "11101101101sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmpyrs_s1 */, -{ "Rd32 = cmpy ( Rs32 , Rt32 ) :rnd :sat" , "11101101001sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmpyrs_s0 */, -{ "Rd32 = cmpy ( Rs32 , Rt32 * ) :<<1 :rnd :sat" , "11101101111sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmpyrsc_s1 */, -{ "Rd32 = cmpy ( Rs32 , Rt32 * ) :rnd :sat" , "11101101011sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmpyrsc_s0 */, -{ "Rd32 = cmpyiwh ( Rss32 , Rt32 ) :<<1 :rnd :sat" , "1100 0101 ---sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M4_cmpyi_wh */, -{ "Rd32 = cmpyiwh ( Rss32 , Rt32 * ) :<<1 :rnd :sat" , "1100 0101 ---sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M4_cmpyi_whc */, -{ "Rd32 = cmpyrwh ( Rss32 , Rt32 ) :<<1 :rnd :sat" , "1100 0101 ---sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M4_cmpyr_wh */, -{ "Rd32 = cmpyrwh ( Rss32 , Rt32 * ) :<<1 :rnd :sat" , "1100 0101 ---sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M4_cmpyr_whc */, -{ "Rd32 = combine ( Rt32.h , Rs32.h )" , "1111 0011 100sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_combine_hh */, -{ "Rd32 = combine ( Rt32.h , Rs32.l )" , "1111 0011 101sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_combine_hl */, -{ "Rd32 = combine ( Rt32.l , Rs32.h )" , "1111 0011 110sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_combine_lh */, -{ "Rd32 = combine ( Rt32.l , Rs32.l )" , "1111 0011 111sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_combine_ll */, -{ "Rd32 = convert_d2sf ( Rss32 )" , "1000 1000 010sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_d2sf */, -{ "Rd32 = convert_df2sf ( Rss32 )" , "1000 1000 000sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE|A_FPDOUBLE, NULL} /* F2_conv_df2sf */, -{ "Rd32 = convert_df2uw ( Rss32 ) :chop" , "1000 1000 101sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_df2uw_chop */, -{ "Rd32 = convert_df2uw ( Rss32 )" , "1000 1000 011sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_df2uw */, -{ "Rd32 = convert_df2w ( Rss32 ) :chop" , "1000 1000 111sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_df2w_chop */, -{ "Rd32 = convert_df2w ( Rss32 )" , "1000 1000 100sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_df2w */, -{ "Rd32 = convert_sf2uw ( Rs32 ) :chop" , "1000 1011 011sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_sf2uw_chop */, -{ "Rd32 = convert_sf2uw ( Rs32 )" , "1000 1011 011sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_sf2uw */, -{ "Rd32 = convert_sf2w ( Rs32 ) :chop" , "1000 1011 100sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_sf2w_chop */, -{ "Rd32 = convert_sf2w ( Rs32 )" , "1000 1011 100sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_sf2w */, -{ "Rd32 = convert_ud2sf ( Rss32 )" , "1000 1000 001sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_ud2sf */, -{ "Rd32 = convert_uw2sf ( Rs32 )" , "1000 1011 001sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_uw2sf */, -{ "Rd32 = convert_w2sf ( Rs32 )" , "1000 1011 010sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_w2sf */, -{ "Rd32 = cround ( Rs32 , #u5 )" , "1000 1100 111sssss PP0iiiii 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cround_ri */, -{ "Rd32 = cround ( Rs32 , Rt32 )" , "1100 0110 11-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_cround_rr */, -{ "Rd32 = ct0 ( Rs32 )" , "1000 1100 010sssss PP------ 1 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_ct0 */, -{ "Rd32 = ct0 ( Rss32 )" , "1000 1000 111sssss PP------ 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_ct0p */, -{ "Rd32 = ct1 ( Rs32 )" , "1000 1100 010sssss PP------ 1 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_ct1 */, -{ "Rd32 = ct1 ( Rss32 )" , "1000 1000 111sssss PP------ 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_ct1p */, -{ "Rd32 = ctlbw ( Rss32 , Rt32 )" , "0110 1100 110sssss PP0ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y5_ctlbw */, -{ "Rd32 = dctagr ( Rs32 )" , "1010 010 00 01sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP, NULL} /* Y2_dctagr */, -{ "Rd32 = extract ( Rs32 , #u5 , #U5 )" , "1000 1101 1IIsssss PP0iiiii IIIddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S4_extract */, -{ "Rd32 = extract ( Rs32 , Rtt32 )" , "1100 1001 00-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTR, NULL} /* S4_extract_rp */, -{ "Rd32 = extractu ( Rs32 , #u5 , #U5 )" , "1000 1101 0IIsssss PP0iiiii IIIddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_extractu */, -{ "Rd32 = extractu ( Rs32 , Rtt32 )" , "1100 1001 00-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTR, NULL} /* S2_extractu_rp */, -{ "Rd32 = getimask ( Rs32 )" , "0110 0110 000sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK, NULL} /* Y2_getimask */, -{ "Rd32 = iassignr ( Rs32 )" , "0110 0110 011sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK, NULL} /* Y2_iassignr */, -{ "Rd32 = icdatar ( Rs32 )" , "0101 0101 101sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_ICOP|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y2_icdatar */, -{ "Rd32 = ictagr ( Rs32 )" , "0101 0101 111sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_ICOP|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y2_ictagr */, -{ "Rd32 = l2tagr ( Rs32 )" , "1010 010 00 11sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP, NULL} /* Y4_l2tagr */, -{ "Rd32 = lsl ( #s6 , Rt32 )" , "1100 0110 10-iiiii PP-ttttt 11iddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S4_lsli */, -{ "Rd32 = lsl ( Rs32 , Rt32 )" , "1100 0110 01-sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_r */, -{ "Rd32 = lsr ( Rs32 , #u5 )" , "1000 1100 000sssss PP0iiiii 0 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_lsr_i_r */, -{ "Rd32 = lsr ( Rs32 , Rt32 )" , "1100 0110 01-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_r */, -{ "Rd32 = max ( Rs32 , Rt32 )" , "1101 0101 110sssss PP-ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_max */, -{ "Rd32 = maxu ( Rs32 , Rt32 )" , "1101 0101 110sssss PP-ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* A2_maxu */, -{ "Rd32 = memb ( gp + #u16:0 )" , "0100 1ii1 000 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrbgp */, -{ "Rd32 = memb ( #g16:0 )" , "0100 1ii1 000 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrbgp */, -{ "Rd32 = memb ( Rf32 = #U6 )" , "1001 1 01 1 000 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrb_ap */, -{ "Rd32 = memb ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadrb_zomap)}, /* mapped to Rd32=memb(Rs32+#0) */ -{ "Rd32 = memb ( Rs32 + #s11:0 )" , "1001 0 ii 1 000 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrb_io */, -{ "Rd32 = memb ( Rs32 + Rt32 << #0 )" , "0011 1010 000 sssss PP0ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrb_rr_expand_shamt_0 */, -{ "Rd32 = memb ( Rs32 + Rt32 << #1 )" , "0011 1010 000 sssss PP0ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrb_rr_expand_shamt_1 */, -{ "Rd32 = memb ( Rs32 + Rt32 << #2 )" , "0011 1010 000 sssss PP1ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrb_rr_expand_shamt_2 */, -{ "Rd32 = memb ( Rs32 + Rt32 << #3 )" , "0011 1010 000 sssss PP1ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrb_rr_expand_shamt_3 */, -{ "Rd32 = memb ( Rt32 << #0 + #U6 )" , "1001 1 10 1 000 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrb_ur_expand_shamt_0 */, -{ "Rd32 = memb ( Rt32 << #1 + #U6 )" , "1001 1 10 1 000 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrb_ur_expand_shamt_1 */, -{ "Rd32 = memb ( Rt32 << #2 + #U6 )" , "1001 1 10 1 000 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrb_ur_expand_shamt_2 */, -{ "Rd32 = memb ( Rt32 << #3 + #U6 )" , "1001 1 10 1 000 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrb_ur_expand_shamt_3 */, -{ "Rd32 = memb ( Rz32 ++ #s4:0 )" , "1001 1 01 1 000 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrb_pi */, -{ "Rd32 = memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" , "1001 1 00 1 000 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadrb_pci */, -{ "Rd32 = memb ( Rz32 ++ Mu2 )" , "1001 1 10 1 000 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrb_pr */, -{ "Rd32 = memb ( Rz32 ++ Mu2 :brev )" , "1001 1 11 1 000 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrb_pbr */, -{ "Rd32 = memb ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 1 000 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadrb_pcr */, -{ "Rd32 = membh ( Rf32 = #U6 )" , "1001 1 01 0 001 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw2_ap */, -{ "Rd32 = membh ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadbsw2_zomap)}, /* mapped to Rd32=membh(Rs32+#0) */ -{ "Rd32 = membh ( Rs32 + #s11:1 )" , "1001 0 ii 0 001 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadbsw2_io */, -{ "Rd32 = membh ( Rt32 << #0 + #U6 )" , "1001 1 10 0 001 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw2_ur_expand_shamt_0 */, -{ "Rd32 = membh ( Rt32 << #1 + #U6 )" , "1001 1 10 0 001 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw2_ur_expand_shamt_1 */, -{ "Rd32 = membh ( Rt32 << #2 + #U6 )" , "1001 1 10 0 001 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw2_ur_expand_shamt_2 */, -{ "Rd32 = membh ( Rt32 << #3 + #U6 )" , "1001 1 10 0 001 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw2_ur_expand_shamt_3 */, -{ "Rd32 = membh ( Rz32 ++ #s4:1 )" , "1001 1 01 0 001 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbsw2_pi */, -{ "Rd32 = membh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" , "1001 1 00 0 001 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadbsw2_pci */, -{ "Rd32 = membh ( Rz32 ++ Mu2 )" , "1001 1 10 0 001 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbsw2_pr */, -{ "Rd32 = membh ( Rz32 ++ Mu2 :brev )" , "1001 1 11 0 001 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbsw2_pbr */, -{ "Rd32 = membh ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 0 001 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadbsw2_pcr */, -{ "Rd32 = memh ( gp + #u16:1 )" , "0100 1ii1 010 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrhgp */, -{ "Rd32 = memh ( #g16:1 )" , "0100 1ii1 010 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrhgp */, -{ "Rd32 = memh ( Rf32 = #U6 )" , "1001 1 01 1 010 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrh_ap */, -{ "Rd32 = memh ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadrh_zomap)}, /* mapped to Rd32=memh(Rs32+#0) */ -{ "Rd32 = memh ( Rs32 + #s11:1 )" , "1001 0 ii 1 010 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrh_io */, -{ "Rd32 = memh ( Rs32 + Rt32 << #0 )" , "0011 1010 010 sssss PP0ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrh_rr_expand_shamt_0 */, -{ "Rd32 = memh ( Rs32 + Rt32 << #1 )" , "0011 1010 010 sssss PP0ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrh_rr_expand_shamt_1 */, -{ "Rd32 = memh ( Rs32 + Rt32 << #2 )" , "0011 1010 010 sssss PP1ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrh_rr_expand_shamt_2 */, -{ "Rd32 = memh ( Rs32 + Rt32 << #3 )" , "0011 1010 010 sssss PP1ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrh_rr_expand_shamt_3 */, -{ "Rd32 = memh ( Rt32 << #0 + #U6 )" , "1001 1 10 1 010 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrh_ur_expand_shamt_0 */, -{ "Rd32 = memh ( Rt32 << #1 + #U6 )" , "1001 1 10 1 010 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrh_ur_expand_shamt_1 */, -{ "Rd32 = memh ( Rt32 << #2 + #U6 )" , "1001 1 10 1 010 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrh_ur_expand_shamt_2 */, -{ "Rd32 = memh ( Rt32 << #3 + #U6 )" , "1001 1 10 1 010 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrh_ur_expand_shamt_3 */, -{ "Rd32 = memh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 010 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrh_pi */, -{ "Rd32 = memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" , "1001 1 00 1 010 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadrh_pci */, -{ "Rd32 = memh ( Rz32 ++ Mu2 )" , "1001 1 10 1 010 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrh_pr */, -{ "Rd32 = memh ( Rz32 ++ Mu2 :brev )" , "1001 1 11 1 010 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrh_pbr */, -{ "Rd32 = memh ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 1 010 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadrh_pcr */, -{ "Rd32 = memub ( gp + #u16:0 )" , "0100 1ii1 001 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrubgp */, -{ "Rd32 = memub ( #g16:0 )" , "0100 1ii1 001 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrubgp */, -{ "Rd32 = memub ( Rf32 = #U6 )" , "1001 1 01 1 001 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrub_ap */, -{ "Rd32 = memub ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadrub_zomap)}, /* mapped to Rd32=memub(Rs32+#0) */ -{ "Rd32 = memub ( Rs32 + #s11:0 )" , "1001 0 ii 1 001 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrub_io */, -{ "Rd32 = memub ( Rs32 + Rt32 << #0 )" , "0011 1010 001 sssss PP0ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrub_rr_expand_shamt_0 */, -{ "Rd32 = memub ( Rs32 + Rt32 << #1 )" , "0011 1010 001 sssss PP0ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrub_rr_expand_shamt_1 */, -{ "Rd32 = memub ( Rs32 + Rt32 << #2 )" , "0011 1010 001 sssss PP1ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrub_rr_expand_shamt_2 */, -{ "Rd32 = memub ( Rs32 + Rt32 << #3 )" , "0011 1010 001 sssss PP1ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrub_rr_expand_shamt_3 */, -{ "Rd32 = memub ( Rt32 << #0 + #U6 )" , "1001 1 10 1 001 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrub_ur_expand_shamt_0 */, -{ "Rd32 = memub ( Rt32 << #1 + #U6 )" , "1001 1 10 1 001 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrub_ur_expand_shamt_1 */, -{ "Rd32 = memub ( Rt32 << #2 + #U6 )" , "1001 1 10 1 001 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrub_ur_expand_shamt_2 */, -{ "Rd32 = memub ( Rt32 << #3 + #U6 )" , "1001 1 10 1 001 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrub_ur_expand_shamt_3 */, -{ "Rd32 = memub ( Rz32 ++ #s4:0 )" , "1001 1 01 1 001 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrub_pi */, -{ "Rd32 = memub ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" , "1001 1 00 1 001 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadrub_pci */, -{ "Rd32 = memub ( Rz32 ++ Mu2 )" , "1001 1 10 1 001 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrub_pr */, -{ "Rd32 = memub ( Rz32 ++ Mu2 :brev )" , "1001 1 11 1 001 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrub_pbr */, -{ "Rd32 = memub ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 1 001 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadrub_pcr */, -{ "Rd32 = memubh ( Rf32 = #U6 )" , "1001 1 01 0 011 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw2_ap */, -{ "Rd32 = memubh ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadbzw2_zomap)}, /* mapped to Rd32=memubh(Rs32+#0) */ -{ "Rd32 = memubh ( Rs32 + #s11:1 )" , "1001 0 ii 0 011 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadbzw2_io */, -{ "Rd32 = memubh ( Rt32 << #0 + #U6 )" , "1001 1 10 0 011 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw2_ur_expand_shamt_0 */, -{ "Rd32 = memubh ( Rt32 << #1 + #U6 )" , "1001 1 10 0 011 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw2_ur_expand_shamt_1 */, -{ "Rd32 = memubh ( Rt32 << #2 + #U6 )" , "1001 1 10 0 011 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw2_ur_expand_shamt_2 */, -{ "Rd32 = memubh ( Rt32 << #3 + #U6 )" , "1001 1 10 0 011 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw2_ur_expand_shamt_3 */, -{ "Rd32 = memubh ( Rz32 ++ #s4:1 )" , "1001 1 01 0 011 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbzw2_pi */, -{ "Rd32 = memubh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" , "1001 1 00 0 011 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadbzw2_pci */, -{ "Rd32 = memubh ( Rz32 ++ Mu2 )" , "1001 1 10 0 011 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbzw2_pr */, -{ "Rd32 = memubh ( Rz32 ++ Mu2 :brev )" , "1001 1 11 0 011 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbzw2_pbr */, -{ "Rd32 = memubh ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 0 011 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadbzw2_pcr */, -{ "Rd32 = memuh ( gp + #u16:1 )" , "0100 1ii1 011 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadruhgp */, -{ "Rd32 = memuh ( #g16:1 )" , "0100 1ii1 011 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadruhgp */, -{ "Rd32 = memuh ( Rf32 = #U6 )" , "1001 1 01 1 011 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadruh_ap */, -{ "Rd32 = memuh ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadruh_zomap)}, /* mapped to Rd32=memuh(Rs32+#0) */ -{ "Rd32 = memuh ( Rs32 + #s11:1 )" , "1001 0 ii 1 011 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadruh_io */, -{ "Rd32 = memuh ( Rs32 + Rt32 << #0 )" , "0011 1010 011 sssss PP0ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadruh_rr_expand_shamt_0 */, -{ "Rd32 = memuh ( Rs32 + Rt32 << #1 )" , "0011 1010 011 sssss PP0ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadruh_rr_expand_shamt_1 */, -{ "Rd32 = memuh ( Rs32 + Rt32 << #2 )" , "0011 1010 011 sssss PP1ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadruh_rr_expand_shamt_2 */, -{ "Rd32 = memuh ( Rs32 + Rt32 << #3 )" , "0011 1010 011 sssss PP1ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadruh_rr_expand_shamt_3 */, -{ "Rd32 = memuh ( Rt32 << #0 + #U6 )" , "1001 1 10 1 011 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadruh_ur_expand_shamt_0 */, -{ "Rd32 = memuh ( Rt32 << #1 + #U6 )" , "1001 1 10 1 011 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadruh_ur_expand_shamt_1 */, -{ "Rd32 = memuh ( Rt32 << #2 + #U6 )" , "1001 1 10 1 011 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadruh_ur_expand_shamt_2 */, -{ "Rd32 = memuh ( Rt32 << #3 + #U6 )" , "1001 1 10 1 011 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadruh_ur_expand_shamt_3 */, -{ "Rd32 = memuh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 011 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadruh_pi */, -{ "Rd32 = memuh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" , "1001 1 00 1 011 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadruh_pci */, -{ "Rd32 = memuh ( Rz32 ++ Mu2 )" , "1001 1 10 1 011 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadruh_pr */, -{ "Rd32 = memuh ( Rz32 ++ Mu2 :brev )" , "1001 1 11 1 011 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadruh_pbr */, -{ "Rd32 = memuh ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 1 011 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadruh_pcr */, -{ "Rd32 = memw ( gp + #u16:2 )" , "0100 1ii1 100 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrigp */, -{ "Rd32 = memw ( #g16:2 )" , "0100 1ii1 100 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrigp */, -{ "Rd32 = memw ( Rf32 = #U6 )" , "1001 1 01 1 100 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadri_ap */, -{ "Rd32 = memw ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadri_zomap)}, /* mapped to Rd32=memw(Rs32+#0) */ -{ "Rd32 = memw ( Rs32 + #s11:2 )" , "1001 0 ii 1 100 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadri_io */, -{ "Rd32 = memw ( Rs32 + Rt32 << #0 )" , "0011 1010 100 sssss PP0ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadri_rr_expand_shamt_0 */, -{ "Rd32 = memw ( Rs32 + Rt32 << #1 )" , "0011 1010 100 sssss PP0ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadri_rr_expand_shamt_1 */, -{ "Rd32 = memw ( Rs32 + Rt32 << #2 )" , "0011 1010 100 sssss PP1ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadri_rr_expand_shamt_2 */, -{ "Rd32 = memw ( Rs32 + Rt32 << #3 )" , "0011 1010 100 sssss PP1ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadri_rr_expand_shamt_3 */, -{ "Rd32 = memw ( Rt32 << #0 + #U6 )" , "1001 1 10 1 100 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadri_ur_expand_shamt_0 */, -{ "Rd32 = memw ( Rt32 << #1 + #U6 )" , "1001 1 10 1 100 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadri_ur_expand_shamt_1 */, -{ "Rd32 = memw ( Rt32 << #2 + #U6 )" , "1001 1 10 1 100 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadri_ur_expand_shamt_2 */, -{ "Rd32 = memw ( Rt32 << #3 + #U6 )" , "1001 1 10 1 100 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadri_ur_expand_shamt_3 */, -{ "Rd32 = memw ( Rz32 ++ #s4:2 )" , "1001 1 01 1 100 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadri_pi */, -{ "Rd32 = memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" , "1001 1 00 1 100 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadri_pci */, -{ "Rd32 = memw ( Rz32 ++ Mu2 )" , "1001 1 10 1 100 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadri_pr */, -{ "Rd32 = memw ( Rz32 ++ Mu2 :brev )" , "1001 1 11 1 100 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadri_pbr */, -{ "Rd32 = memw ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 1 100 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadri_pcr */, -{ "Rd32 = memw_locked ( Rs32 )" , "1001 001 0 000 sssss PP00---- ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_RESTRICT_SLOT0ONLY|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadw_locked */, -{ "Rd32 = memw_phys ( Rs32 , Rt32 )" , "1001 001 0 000 sssss PP1ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_RESTRICT_SLOT0ONLY|A_NOTE_PRIV|A_MEMSIZE_4B|A_LOAD|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadw_phys */, -{ "Rd32 = min ( Rt32 , Rs32 )" , "1101 0101 101sssss PP-ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_min */, -{ "Rd32 = minu ( Rt32 , Rs32 )" , "1101 0101 101sssss PP-ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* A2_minu */, -{ "Rd32 = modwrap ( Rs32 , Rt32 )" , "1101 0011 111sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_modwrapu */, -{ "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd :sat" , "11101100101sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_rnd_hh_s1 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd" , "11101100101sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_rnd_hh_s1 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :sat" , "11101100100sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_hh_s1 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1" , "11101100100sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_hh_s1 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.h ) :rnd :sat" , "11101100001sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_rnd_hh_s0 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.h ) :rnd" , "11101100001sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_rnd_hh_s0 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.h ) :sat" , "11101100000sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_hh_s0 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.h )" , "11101100000sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_hh_s0 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd :sat" , "11101100101sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_rnd_hl_s1 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd" , "11101100101sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_rnd_hl_s1 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :sat" , "11101100100sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_hl_s1 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1" , "11101100100sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_hl_s1 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.l ) :rnd :sat" , "11101100001sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_rnd_hl_s0 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.l ) :rnd" , "11101100001sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_rnd_hl_s0 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.l ) :sat" , "11101100000sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_hl_s0 */, -{ "Rd32 = mpy ( Rs32.h , Rt32.l )" , "11101100000sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_hl_s0 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd :sat" , "11101100101sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_rnd_lh_s1 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd" , "11101100101sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_rnd_lh_s1 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :sat" , "11101100100sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_lh_s1 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1" , "11101100100sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_lh_s1 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.h ) :rnd :sat" , "11101100001sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_rnd_lh_s0 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.h ) :rnd" , "11101100001sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_rnd_lh_s0 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.h ) :sat" , "11101100000sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_lh_s0 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.h )" , "11101100000sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_lh_s0 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd :sat" , "11101100101sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_rnd_ll_s1 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd" , "11101100101sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_rnd_ll_s1 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :sat" , "11101100100sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_ll_s1 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1" , "11101100100sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_ll_s1 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.l ) :rnd :sat" , "11101100001sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_rnd_ll_s0 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.l ) :rnd" , "11101100001sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_rnd_ll_s0 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.l ) :sat" , "11101100000sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_sat_ll_s0 */, -{ "Rd32 = mpy ( Rs32.l , Rt32.l )" , "11101100000sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_ll_s0 */, -{ "Rd32 = mpy ( Rs32 , Rt32.h ) :<<1 :rnd :sat" , "11101101101sssss PP0ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_hmmpyh_rs1 */, -{ "Rd32 = mpy ( Rs32 , Rt32.h ) :<<1 :sat" , "11101101101sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_hmmpyh_s1 */, -{ "Rd32 = mpy ( Rs32 , Rt32.l ) :<<1 :rnd :sat" , "11101101111sssss PP0ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_hmmpyl_rs1 */, -{ "Rd32 = mpy ( Rs32 , Rt32.l ) :<<1 :sat" , "11101101101sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_hmmpyl_s1 */, -{ "Rd32 = mpy ( Rs32 , Rt32 ) :<<1 :sat" , "11101101111sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_IT_MPY|A_IT_MPY_32|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_up_s1_sat */, -{ "Rd32 = mpy ( Rs32 , Rt32 ) :<<1" , "11101101101sssss PP0ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32, NULL} /* M2_mpy_up_s1 */, -{ "Rd32 = mpy ( Rs32 , Rt32 ) :rnd" , "11101101001sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32, NULL} /* M2_dpmpyss_rnd_s0 */, -{ "Rd32 = mpy ( Rs32 , Rt32 )" , "11101101000sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32, NULL} /* M2_mpy_up */, -{ "Rd32 = mpyi ( Rs32 , #m9 )" , "0000dddddsssssiiiiiiiii000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(M2_mpysmi)}, /* mapped to Rd32=-mpyi(Rs32,#m9*(-1)) or Rd32=+mpyi(Rs32,#m9) */ -{ "Rd32 = mpyi ( Rs32 , Rt32 )" , "11101101000sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32|A_MPY, NULL} /* M2_mpyi */, -{ "Rd32 = mpysu ( Rs32 , Rt32 )" , "11101101011sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32, NULL} /* M2_mpysu_up */, -{ "Rd32 = mpyu ( Rs32.h , Rt32.h ) :<<1" , "11101100110sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyu_hh_s1 */, -{ "Rd32 = mpyu ( Rs32.h , Rt32.h )" , "11101100010sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyu_hh_s0 */, -{ "Rd32 = mpyu ( Rs32.h , Rt32.l ) :<<1" , "11101100110sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyu_hl_s1 */, -{ "Rd32 = mpyu ( Rs32.h , Rt32.l )" , "11101100010sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyu_hl_s0 */, -{ "Rd32 = mpyu ( Rs32.l , Rt32.h ) :<<1" , "11101100110sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyu_lh_s1 */, -{ "Rd32 = mpyu ( Rs32.l , Rt32.h )" , "11101100010sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyu_lh_s0 */, -{ "Rd32 = mpyu ( Rs32.l , Rt32.l ) :<<1" , "11101100110sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyu_ll_s1 */, -{ "Rd32 = mpyu ( Rs32.l , Rt32.l )" , "11101100010sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyu_ll_s0 */, -{ "Rd32 = mpyu ( Rs32 , Rt32 )" , "11101101010sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyu_up */, -{ "Rd32 = mpyui ( Rs32 , Rt32 )" , "0000dddddsssssttttt0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(M2_mpyui)}, /* mapped to Rd32=mpyi(Rs32,Rt32) */ -{ "Rd32 = mux ( Pu4 , #s8 , #S8 )" , "0111 101u uIIIIIII PPIiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_muxii */, -{ "Rd32 = mux ( Pu4 , #s8 , Rs32 )" , "0111 0011 1uusssss PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_muxri */, -{ "Rd32 = mux ( Pu4 , Rs32 , #s8 )" , "0111 0011 0uusssss PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_muxir */, -{ "Rd32 = mux ( Pu4 , Rs32 , Rt32 )" , "1111 0100 ---sssss PP-ttttt -uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_DOTOLD, NULL} /* C2_mux */, -{ "Rd32 = neg ( Rs32 ) :sat" , "1000 1100 100sssss PP------ 1 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_negsat */, -{ "Rd32 = neg ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_neg)}, /* mapped to Rd32=sub(#0,Rs32) */ -{ "Rd32 = normamt ( Rs32 )" , "1000 1100 000sssss PP------ 1 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_clbnorm */, -{ "Rd32 = normamt ( Rss32 )" , "1000 1000 011sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S4_clbpnorm */, -{ "Rd32 = not ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_not)}, /* mapped to Rd32=sub(#-1,Rs32) */ -{ "Rd32 = or ( Rs32 , #s10 )" , "0111 0110 10isssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_orir */, -{ "Rd32 = or ( Rs32 , Rt32 )" , "1111 0001 001sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_or */, -{ "Rd32 = or ( Rt32 , ~ Rs32 )" , "1111 0001 101sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A4_orn */, -{ "Rd32 = parity ( Rs32 , Rt32 )" , "1101 0101 111sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S4_parity */, -{ "Rd32 = parity ( Rss32 , Rtt32 )" , "1101 0000 ---sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_parityp */, -{ "Rd32 = popcount ( Rss32 )" , "1000 1000 011sssss PP------ 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S5_popcountp */, -{ "Rd32 = round ( Rs32 , #u5 ) :sat" , "1000 1100 111sssss PP0iiiii 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A4_round_ri_sat */, -{ "Rd32 = round ( Rs32 , #u5 )" , "1000 1100 111sssss PP0iiiii 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_round_ri */, -{ "Rd32 = round ( Rs32 , Rt32 ) :sat" , "1100 0110 11-sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A4_round_rr_sat */, -{ "Rd32 = round ( Rs32 , Rt32 )" , "1100 0110 11-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_round_rr */, -{ "Rd32 = round ( Rss32 ) :sat" , "1000 1000 110sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_roundsat */, -{ "Rd32 = sat ( Rss32 )" , "1000 1000 110sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_sat */, -{ "Rd32 = satb ( Rs32 )" , "1000 1100 110sssss PP------ 1 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_satb */, -{ "Rd32 = sath ( Rs32 )" , "1000 1100 110sssss PP------ 1 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_sath */, -{ "Rd32 = satub ( Rs32 )" , "1000 1100 110sssss PP------ 1 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* A2_satub */, -{ "Rd32 = satuh ( Rs32 )" , "1000 1100 110sssss PP------ 1 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* A2_satuh */, -{ "Rd32 = setbit ( Rs32 , #u5 )" , "1000 1100 110sssss PP0iiiii 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_setbit_i */, -{ "Rd32 = setbit ( Rs32 , Rt32 )" , "1100 0110 10-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S2_setbit_r */, -{ "Rd32 = sfadd ( Rs32 , Rt32 )" , "11101011000sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sfadd */, -{ "Rd32 = sffixupd ( Rs32 , Rt32 )" , "11101011110sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP, NULL} /* F2_sffixupd */, -{ "Rd32 = sffixupn ( Rs32 , Rt32 )" , "11101011110sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP, NULL} /* F2_sffixupn */, -{ "Rd32 = sffixupr ( Rs32 )" , "1000 1011 101sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP, NULL} /* F2_sffixupr */, -{ "Rd32 = sfmake ( #u10 ) :neg" , "1101 0110 01i ----- PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* F2_sfimm_n */, -{ "Rd32 = sfmake ( #u10 ) :pos" , "1101 0110 00i ----- PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* F2_sfimm_p */, -{ "Rd32 = sfmax ( Rs32 , Rt32 )" , "11101011100sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sfmax */, -{ "Rd32 = sfmin ( Rs32 , Rt32 )" , "11101011100sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sfmin */, -{ "Rd32 = sfmpy ( Rs32 , Rt32 )" , "11101011010sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sfmpy */, -{ "Rd32 = sfsub ( Rs32 , Rt32 )" , "11101011000sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sfsub */, -{ "Rd32 = sub ( #s10 , Rs32 )" , "0111 0110 01isssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_subri */, -{ "Rd32 = sub ( Rt32.h , Rs32.h ) :<<16" , "1101 0101 011sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_subh_h16_hh */, -{ "Rd32 = sub ( Rt32.h , Rs32.h ) :sat :<<16" , "1101 0101 011sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_subh_h16_sat_hh */, -{ "Rd32 = sub ( Rt32.h , Rs32.l ) :<<16" , "1101 0101 011sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_subh_h16_hl */, -{ "Rd32 = sub ( Rt32.h , Rs32.l ) :sat :<<16" , "1101 0101 011sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_subh_h16_sat_hl */, -{ "Rd32 = sub ( Rt32.l , Rs32.h ) :<<16" , "1101 0101 011sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_subh_h16_lh */, -{ "Rd32 = sub ( Rt32.l , Rs32.h ) :sat :<<16" , "1101 0101 011sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_subh_h16_sat_lh */, -{ "Rd32 = sub ( Rt32.l , Rs32.h ) :sat" , "1101 0101 001sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_subh_l16_sat_hl */, -{ "Rd32 = sub ( Rt32.l , Rs32.h )" , "1101 0101 001sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_subh_l16_hl */, -{ "Rd32 = sub ( Rt32.l , Rs32.l ) :<<16" , "1101 0101 011sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_subh_h16_ll */, -{ "Rd32 = sub ( Rt32.l , Rs32.l ) :sat :<<16" , "1101 0101 011sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_subh_h16_sat_ll */, -{ "Rd32 = sub ( Rt32.l , Rs32.l ) :sat" , "1101 0101 001sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_subh_l16_sat_ll */, -{ "Rd32 = sub ( Rt32.l , Rs32.l )" , "1101 0101 001sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_subh_l16_ll */, -{ "Rd32 = sub ( Rt32 , Rs32 ) :sat :deprecated" , "1101 0101 100sssss PP-ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* dep_A2_subsat */, -{ "Rd32 = sub ( Rt32 , Rs32 ) :sat" , "1111 0110 110sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_subsat */, -{ "Rd32 = sub ( Rt32 , Rs32 )" , "1111 0011 001sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_sub */, -{ "Rd32 = swiz ( Rs32 )" , "1000 1100 100sssss PP------ 1 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* A2_swiz */, -{ "Rd32 = sxtb ( Rs32 )" , "0111 0000 101sssss PP0----- ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_sxtb */, -{ "Rd32 = sxth ( Rs32 )" , "0111 0000 111sssss PP0----- ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_sxth */, -{ "Rd32 = tlboc ( Rss32 )" , "0110 1100 111sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y5_tlboc */, -{ "Rd32 = tlbp ( Rs32 )" , "0110 1100 100sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_tlbp */, -{ "Rd32 = togglebit ( Rs32 , #u5 )" , "1000 1100 110sssss PP0iiiii 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_togglebit_i */, -{ "Rd32 = togglebit ( Rs32 , Rt32 )" , "1100 0110 10-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S2_togglebit_r */, -{ "Rd32 = vaddh ( Rs32 , Rt32 ) :sat" , "1111 0110 001sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_svaddhs */, -{ "Rd32 = vaddh ( Rs32 , Rt32 )" , "1111 0110 000sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_svaddh */, -{ "Rd32 = vaddhub ( Rss32 , Rtt32 ) :sat" , "1100 0001 01-sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* A5_vaddhubs */, -{ "Rd32 = vadduh ( Rs32 , Rt32 ) :sat" , "1111 0110 011sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* A2_svadduhs */, -{ "Rd32 = vasrhub ( Rss32 , #u4 ) :raw" , "1000 1000 011sssss PP00iiii 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* S5_asrhub_rnd_sat */, -{ "Rd32 = vasrhub ( Rss32 , #u4 ) :rnd :sat" , "0000dddddsssssiiii00000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S5_asrhub_rnd_sat_goodsyntax)}, /* mapped to Rd32=vsathub(Rss32) or Rd32=vasrhub(Rss32,#u4-1):raw */ -{ "Rd32 = vasrhub ( Rss32 , #u4 ) :sat" , "1000 1000 011sssss PP00iiii 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* S5_asrhub_sat */, -{ "Rd32 = vasrw ( Rss32 , #u5 )" , "1000 1000 110sssss PP0iiiii 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_asr_i_svw_trun */, -{ "Rd32 = vasrw ( Rss32 , Rt32 )" , "1100 0101 ---sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_svw_trun */, -{ "Rd32 = vavgh ( Rs32 , Rt32 ) :rnd" , "1111 0111 -01sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2, NULL} /* A2_svavghs */, -{ "Rd32 = vavgh ( Rs32 , Rt32 )" , "1111 0111 -00sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2, NULL} /* A2_svavgh */, -{ "Rd32 = vdmpy ( Rss32 , Rtt32 ) :<<1 :rnd :sat" , "111010011--sssss PP0ttttt -00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vdmpyrs_s1 */, -{ "Rd32 = vdmpy ( Rss32 , Rtt32 ) :rnd :sat" , "111010010--sssss PP0ttttt -00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vdmpyrs_s0 */, -{ "Rd32 = vitpack ( Ps4 , Pt4 )" , "1000 1001 -00 ---ss PP----tt --- ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* C2_vitpack */, -{ "Rd32 = vmpyh ( Rs32 , Rt32 ) :<<1 :rnd :sat" , "11101101101sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmpy2s_s1pack */, -{ "Rd32 = vmpyh ( Rs32 , Rt32 ) :rnd :sat" , "11101101001sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmpy2s_s0pack */, -{ "Rd32 = vnavgh ( Rt32 , Rs32 )" , "1111 0111 -11sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2, NULL} /* A2_svnavgh */, -{ "Rd32 = vraddh ( Rss32 , Rtt32 )" , "111010010-1sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV3, NULL} /* M2_vraddh */, -{ "Rd32 = vradduh ( Rss32 , Rtt32 )" , "111010010--sssss PP0ttttt -01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV3, NULL} /* M2_vradduh */, -{ "Rd32 = vrcmpys ( Rss32 , Rt32 ) :<<1 :rnd :sat" , "0000dddddsssssttttt0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(M2_vrcmpys_s1rp)}, /* mapped to Rd32=vrcmpys(Rss32,Rtt32):<<1:rnd:sat:raw:hi or Rd32=vrcmpys(Rss32,Rtt32):<<1:rnd:sat:raw:lo */ -{ "Rd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :rnd :sat :raw :hi" , "111010011-1sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV3|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vrcmpys_s1rp_h */, -{ "Rd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :rnd :sat :raw :lo" , "111010011-1sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV3|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vrcmpys_s1rp_l */, -{ "Rd32 = vrndwh ( Rss32 ) :sat" , "1000 1000 100sssss PP------ 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_vrndpackwhs */, -{ "Rd32 = vrndwh ( Rss32 )" , "1000 1000 100sssss PP------ 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vrndpackwh */, -{ "Rd32 = vsathb ( Rs32 )" , "1000 1100 10-sssss PP------ 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_svsathb */, -{ "Rd32 = vsathb ( Rss32 )" , "1000 1000 000sssss PP------ 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_vsathb */, -{ "Rd32 = vsathub ( Rs32 )" , "1000 1100 10-sssss PP------ 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* S2_svsathub */, -{ "Rd32 = vsathub ( Rss32 )" , "1000 1000 000sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* S2_vsathub */, -{ "Rd32 = vsatwh ( Rss32 )" , "1000 1000 000sssss PP------ 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_vsatwh */, -{ "Rd32 = vsatwuh ( Rss32 )" , "1000 1000 000sssss PP------ 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* S2_vsatwuh */, -{ "Rd32 = vsplatb ( Rs32 )" , "1000 1100 010sssss PP------ 1 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vsplatrb */, -{ "Rd32 = vsubh ( Rt32 , Rs32 ) :sat" , "1111 0110 101sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_svsubhs */, -{ "Rd32 = vsubh ( Rt32 , Rs32 )" , "1111 0110 100sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_svsubh */, -{ "Rd32 = vsubuh ( Rt32 , Rs32 ) :sat" , "1111 0110 111sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* A2_svsubuhs */, -{ "Rd32 = vtrunehb ( Rss32 )" , "1000 1000 100sssss PP------ 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vtrunehb */, -{ "Rd32 = vtrunohb ( Rss32 )" , "1000 1000 100sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_vtrunohb */, -{ "Rd32 = xor ( Rs32 , Rt32 )" , "1111 0001 011sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_xor */, -{ "Rd32 = zxtb ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_zxtb)}, /* mapped to Rd32=and(Rs32,#255) */ -{ "Rd32 = zxth ( Rs32 )" , "0111 0000 110sssss PP0----- ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_zxth */, -{ "Rdd32 , Pe4 = dfinvsqrta ( Rss32 )" , "1000 0000 111sssss PP1----- 0 eeddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_COMPAT_ACCURACY|A_FPOP, NULL} /* F2_dfinvsqrta */, -{ "Rdd32 , Pe4 = dfrecipa ( Rss32 , Rtt32 )" , "11101000111sssss PP0ttttt 0eeddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_COMPAT_ACCURACY|A_FPOP, NULL} /* F2_dfrecipa */, -{ "Rdd32 = #s8" , "0000dddddiiiiiiii000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrpi)}, /* mapped to Rdd32=combine(#-1,#s8) or Rdd32=combine(#0,#s8) */ -{ "Rdd32 = Css32" , "0110 1000 000sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0, NULL} /* A4_tfrcpp */, -{ "Rdd32 = Gss32" , "0110 1000 001sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_GUEST|A_NOTE_GUEST, NULL} /* G4_tfrgcpp */, -{ "Rdd32 = Rss32" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrp)}, /* mapped to Rdd32=combine(Rss.H32,Rss.L32) */ -{ "Rdd32 = Sss64" , "0110 1111 --ssssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV, NULL} /* Y4_tfrscpp */, -{ "Rdd32 = abs ( Rss32 )" , "1000 0000 100sssss PP------ 1 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_absp */, -{ "Rdd32 = add ( Rs32 , Rtt32 )" , "0000dddddsssssttttt0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_addsp)}, /* mapped to Rdd32=add(Rss32,Rtt32):raw:hi or Rdd32=add(Rss32,Rtt32):raw:lo */ -{ "Rdd32 = add ( Rss32 , Rtt32 ) :raw :hi" , "1101 0011 011sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV3, NULL} /* A2_addsph */, -{ "Rdd32 = add ( Rss32 , Rtt32 ) :raw :lo" , "1101 0011 011sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV3, NULL} /* A2_addspl */, -{ "Rdd32 = add ( Rss32 , Rtt32 ) :sat" , "1101 0011 011sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV3|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_addpsat */, -{ "Rdd32 = add ( Rss32 , Rtt32 )" , "1101 0011 000sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_addp */, -{ "Rdd32 = add ( Rss32 , Rtt32 , Px4 ) :carry" , "1100 0010 110sssss PP-ttttt -xxddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_DOTOLD, NULL} /* A4_addp_c */, -{ "Rdd32 = and ( Rss32 , Rtt32 )" , "1101 0011 111sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_andp */, -{ "Rdd32 = and ( Rtt32 , ~ Rss32 )" , "1101 0011 111sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_andnp */, -{ "Rdd32 = asl ( Rss32 , #u6 )" , "1000 0000 000sssss PPiiiiii 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asl_i_p */, -{ "Rdd32 = asl ( Rss32 , Rt32 )" , "1100 0011 10-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S2_asl_r_p */, -{ "Rdd32 = asr ( Rss32 , #u6 ) :rnd" , "1000 0000 110sssss PPiiiiii 1 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asr_i_p_rnd */, -{ "Rdd32 = asr ( Rss32 , #u6 )" , "1000 0000 000sssss PPiiiiii 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asr_i_p */, -{ "Rdd32 = asr ( Rss32 , Rt32 )" , "1100 0011 10-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTR, NULL} /* S2_asr_r_p */, -{ "Rdd32 = asrrnd ( Rss32 , #u6 )" , "0000dddddsssssiiiiii000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_asr_i_p_rnd_goodsyntax)}, /* mapped to Rdd32=Rss32 or Rdd32=asr(Rss32,#u5-1):rnd */ -{ "Rdd32 = bitsplit ( Rs32 , #u5 )" , "1000 1000 110sssss PP0iiiii 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_bitspliti */, -{ "Rdd32 = bitsplit ( Rs32 , Rt32 )" , "1101 0100 --1sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_bitsplit */, -{ "Rdd32 = brev ( Rss32 )" , "1000 0000 110sssss PP------ 1 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_brevp */, -{ "Rdd32 = cmpy ( Rs32 , Rt32 ) :<<1 :sat" , "11100101100sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmpys_s1 */, -{ "Rdd32 = cmpy ( Rs32 , Rt32 ) :sat" , "11100101000sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmpys_s0 */, -{ "Rdd32 = cmpy ( Rs32 , Rt32 * ) :<<1 :sat" , "11100101110sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmpysc_s1 */, -{ "Rdd32 = cmpy ( Rs32 , Rt32 * ) :sat" , "11100101010sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmpysc_s0 */, -{ "Rdd32 = cmpyi ( Rs32 , Rt32 )" , "11100101000sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_cmpyi_s0 */, -{ "Rdd32 = cmpyr ( Rs32 , Rt32 )" , "11100101000sssss PP0ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_cmpyr_s0 */, -{ "Rdd32 = combine ( #s8 , #S8 )" , "0111 1100 0IIIIIII PPIiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_ROPS_2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_combineii */, -{ "Rdd32 = combine ( #s8 , #U6 )" , "0111 1100 1--IIIII PPIiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ROPS_2|A_EXT_UPPER_IMMED|A_EXTENDABLE|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* A4_combineii */, -{ "Rdd32 = combine ( #s8 , Rs32 )" , "0111 0011 -01sssss PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ROPS_2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A4_combineir */, -{ "Rdd32 = combine ( Rs32 , #s8 )" , "0111 0011 -00sssss PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ROPS_2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A4_combineri */, -{ "Rdd32 = combine ( Rs32 , Rt32 )" , "1111 0101 0--sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ROPS_2, NULL} /* A2_combinew */, -{ "Rdd32 = convert_d2df ( Rss32 )" , "1000 0000 111sssss PP0----- 0 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_d2df */, -{ "Rdd32 = convert_df2d ( Rss32 ) :chop" , "1000 0000 111sssss PP0----- 1 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_df2d_chop */, -{ "Rdd32 = convert_df2d ( Rss32 )" , "1000 0000 111sssss PP0----- 0 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_df2d */, -{ "Rdd32 = convert_df2ud ( Rss32 ) :chop" , "1000 0000 111sssss PP0----- 1 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_df2ud_chop */, -{ "Rdd32 = convert_df2ud ( Rss32 )" , "1000 0000 111sssss PP0----- 0 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_df2ud */, -{ "Rdd32 = convert_sf2d ( Rs32 ) :chop" , "1000 0100 1--sssss PP------ 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_sf2d_chop */, -{ "Rdd32 = convert_sf2d ( Rs32 )" , "1000 0100 1--sssss PP------ 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_sf2d */, -{ "Rdd32 = convert_sf2df ( Rs32 )" , "1000 0100 1--sssss PP------ 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE|A_FPSINGLE, NULL} /* F2_conv_sf2df */, -{ "Rdd32 = convert_sf2ud ( Rs32 ) :chop" , "1000 0100 1--sssss PP------ 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_sf2ud_chop */, -{ "Rdd32 = convert_sf2ud ( Rs32 )" , "1000 0100 1--sssss PP------ 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_conv_sf2ud */, -{ "Rdd32 = convert_ud2df ( Rss32 )" , "1000 0000 111sssss PP0----- 0 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_ud2df */, -{ "Rdd32 = convert_uw2df ( Rs32 )" , "1000 0100 1--sssss PP------ 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_uw2df */, -{ "Rdd32 = convert_w2df ( Rs32 )" , "1000 0100 1--sssss PP------ 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_conv_w2df */, -{ "Rdd32 = decbin ( Rss32 , Rtt32 )" , "1100 0001 11-sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_P0, 0|A_ARCHV3|A_NOTE_LATEPRED|A_RESTRICT_LATEPRED|A_IMPLICIT_WRITES_P0, NULL} /* S2_cabacdecbin */, -{ "Rdd32 = deinterleave ( Rss32 )" , "1000 0000 110sssss PP------ 1 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_deinterleave */, -{ "Rdd32 = dfadd ( Rss32 , Rtt32 )" , "11101000000sssss PP0ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dfadd */, -{ "Rdd32 = dffixupd ( Rss32 , Rtt32 )" , "11101000011sssss PP0ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP, NULL} /* F2_dffixupd */, -{ "Rdd32 = dffixupn ( Rss32 , Rtt32 )" , "11101000101sssss PP0ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP, NULL} /* F2_dffixupn */, -{ "Rdd32 = dffixupr ( Rss32 )" , "1000 0000 111sssss PP0----- 1 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP, NULL} /* F2_dffixupr */, -{ "Rdd32 = dfmake ( #u10 ) :neg" , "1101 1001 01i ----- PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* F2_dfimm_n */, -{ "Rdd32 = dfmake ( #u10 ) :pos" , "1101 1001 00i ----- PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* F2_dfimm_p */, -{ "Rdd32 = dfmax ( Rss32 , Rtt32 )" , "11101000001sssss PP0ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dfmax */, -{ "Rdd32 = dfmin ( Rss32 , Rtt32 )" , "11101000110sssss PP0ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dfmin */, -{ "Rdd32 = dfmpy ( Rss32 , Rtt32 )" , "11101000010sssss PP0ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dfmpy */, -{ "Rdd32 = dfsub ( Rss32 , Rtt32 )" , "11101000100sssss PP0ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dfsub */, -{ "Rdd32 = extract ( Rss32 , #u6 , #U6 )" , "1000 1010 IIIsssss PPiiiiii IIIddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S4_extractp */, -{ "Rdd32 = extract ( Rss32 , Rtt32 )" , "1100 0001 11-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTR, NULL} /* S4_extractp_rp */, -{ "Rdd32 = extractu ( Rss32 , #u6 , #U6 )" , "1000 0001 IIIsssss PPiiiiii IIIddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_extractup */, -{ "Rdd32 = extractu ( Rss32 , Rtt32 )" , "1100 0001 00-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTR, NULL} /* S2_extractup_rp */, -{ "Rdd32 = interleave ( Rss32 )" , "1000 0000 110sssss PP------ 1 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_interleave */, -{ "Rdd32 = lfs ( Rss32 , Rtt32 )" , "1100 0001 10-sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_lfsp */, -{ "Rdd32 = lsl ( Rss32 , Rt32 )" , "1100 0011 10-sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_p */, -{ "Rdd32 = lsr ( Rss32 , #u6 )" , "1000 0000 000sssss PPiiiiii 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_lsr_i_p */, -{ "Rdd32 = lsr ( Rss32 , Rt32 )" , "1100 0011 10-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_p */, -{ "Rdd32 = mask ( Pt4 )" , "1000 0110 --- ----- PP----tt --- ddddd", HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* C2_mask */, -{ "Rdd32 = max ( Rss32 , Rtt32 )" , "1101 0011 110sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV3, NULL} /* A2_maxp */, -{ "Rdd32 = maxu ( Rss32 , Rtt32 )" , "1101 0011 110sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED|A_ARCHV3, NULL} /* A2_maxup */, -{ "Rdd32 = membh ( Rf32 = #U6 )" , "1001 1 01 0 111 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw4_ap */, -{ "Rdd32 = membh ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadbsw4_zomap)}, /* mapped to Rdd32=membh(Rs32+#0) */ -{ "Rdd32 = membh ( Rs32 + #s11:2 )" , "1001 0 ii 0 111 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadbsw4_io */, -{ "Rdd32 = membh ( Rt32 << #0 + #U6 )" , "1001 1 10 0 111 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw4_ur_expand_shamt_0 */, -{ "Rdd32 = membh ( Rt32 << #1 + #U6 )" , "1001 1 10 0 111 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw4_ur_expand_shamt_1 */, -{ "Rdd32 = membh ( Rt32 << #2 + #U6 )" , "1001 1 10 0 111 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw4_ur_expand_shamt_2 */, -{ "Rdd32 = membh ( Rt32 << #3 + #U6 )" , "1001 1 10 0 111 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbsw4_ur_expand_shamt_3 */, -{ "Rdd32 = membh ( Rz32 ++ #s4:2 )" , "1001 1 01 0 111 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbsw4_pi */, -{ "Rdd32 = membh ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" , "1001 1 00 0 111 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadbsw4_pci */, -{ "Rdd32 = membh ( Rz32 ++ Mu2 )" , "1001 1 10 0 111 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbsw4_pr */, -{ "Rdd32 = membh ( Rz32 ++ Mu2 :brev )" , "1001 1 11 0 111 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbsw4_pbr */, -{ "Rdd32 = membh ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 0 111 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadbsw4_pcr */, -{ "Rdd32 = memd ( gp + #u16:3 )" , "0100 1ii1 110 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrdgp */, -{ "Rdd32 = memd ( #g16:3 )" , "0100 1ii1 110 iiiii PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_GP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrdgp */, -{ "Rdd32 = memd ( Rf32 = #U6 )" , "1001 1 01 1 110 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrd_ap */, -{ "Rdd32 = memd ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadrd_zomap)}, /* mapped to Rdd32=memd(Rs32+#0) */ -{ "Rdd32 = memd ( Rs32 + #s11:3 )" , "1001 0 ii 1 110 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadrd_io */, -{ "Rdd32 = memd ( Rs32 + Rt32 << #0 )" , "0011 1010 110 sssss PP0ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrd_rr_expand_shamt_0 */, -{ "Rdd32 = memd ( Rs32 + Rt32 << #1 )" , "0011 1010 110 sssss PP0ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrd_rr_expand_shamt_1 */, -{ "Rdd32 = memd ( Rs32 + Rt32 << #2 )" , "0011 1010 110 sssss PP1ttttt 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrd_rr_expand_shamt_2 */, -{ "Rdd32 = memd ( Rs32 + Rt32 << #3 )" , "0011 1010 110 sssss PP1ttttt 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadrd_rr_expand_shamt_3 */, -{ "Rdd32 = memd ( Rt32 << #0 + #U6 )" , "1001 1 10 1 110 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrd_ur_expand_shamt_0 */, -{ "Rdd32 = memd ( Rt32 << #1 + #U6 )" , "1001 1 10 1 110 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrd_ur_expand_shamt_1 */, -{ "Rdd32 = memd ( Rt32 << #2 + #U6 )" , "1001 1 10 1 110 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrd_ur_expand_shamt_2 */, -{ "Rdd32 = memd ( Rt32 << #3 + #U6 )" , "1001 1 10 1 110 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadrd_ur_expand_shamt_3 */, -{ "Rdd32 = memd ( Rz32 ++ #s4:3 )" , "1001 1 01 1 110 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrd_pi */, -{ "Rdd32 = memd ( Rz32 ++ #s4:3 :circ ( Mu2 ) )" , "1001 1 00 1 110 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadrd_pci */, -{ "Rdd32 = memd ( Rz32 ++ Mu2 )" , "1001 1 10 1 110 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrd_pr */, -{ "Rdd32 = memd ( Rz32 ++ Mu2 :brev )" , "1001 1 11 1 110 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadrd_pbr */, -{ "Rdd32 = memd ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 1 110 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadrd_pcr */, -{ "Rdd32 = memd_locked ( Rs32 )" , "1001 001 0 000 sssss PP01---- ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_SLOT0ONLY|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L4_loadd_locked */, -{ "Rdd32 = memubh ( Rf32 = #U6 )" , "1001 1 01 0 101 fffff PP01IIII -IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw4_ap */, -{ "Rdd32 = memubh ( Rs32 )" , "0000dddddsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadbzw4_zomap)}, /* mapped to Rdd32=memubh(Rs32+#0) */ -{ "Rdd32 = memubh ( Rs32 + #s11:2 )" , "1001 0 ii 0 101 sssss PPiiiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadbzw4_io */, -{ "Rdd32 = memubh ( Rt32 << #0 + #U6 )" , "1001 1 10 0 101 ttttt PP01IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw4_ur_expand_shamt_0 */, -{ "Rdd32 = memubh ( Rt32 << #1 + #U6 )" , "1001 1 10 0 101 ttttt PP01IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw4_ur_expand_shamt_1 */, -{ "Rdd32 = memubh ( Rt32 << #2 + #U6 )" , "1001 1 10 0 101 ttttt PP11IIII 0IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw4_ur_expand_shamt_2 */, -{ "Rdd32 = memubh ( Rt32 << #3 + #U6 )" , "1001 1 10 0 101 ttttt PP11IIII 1IIddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadbzw4_ur_expand_shamt_3 */, -{ "Rdd32 = memubh ( Rz32 ++ #s4:2 )" , "1001 1 01 0 101 zzzzz PP00---i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbzw4_pi */, -{ "Rdd32 = memubh ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" , "1001 1 00 0 101 zzzzz PPu0--0i iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadbzw4_pci */, -{ "Rdd32 = memubh ( Rz32 ++ Mu2 )" , "1001 1 10 0 101 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbzw4_pr */, -{ "Rdd32 = memubh ( Rz32 ++ Mu2 :brev )" , "1001 1 11 0 101 zzzzz PPu0---- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadbzw4_pbr */, -{ "Rdd32 = memubh ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 0 101 zzzzz PPu0--1- 0--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadbzw4_pcr */, -{ "Rdd32 = min ( Rtt32 , Rss32 )" , "1101 0011 101sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV3, NULL} /* A2_minp */, -{ "Rdd32 = minu ( Rtt32 , Rss32 )" , "1101 0011 101sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED|A_ARCHV3, NULL} /* A2_minup */, -{ "Rdd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd" , "11100100101sssss PP-ttttt -11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_rnd_hh_s1 */, -{ "Rdd32 = mpy ( Rs32.h , Rt32.h ) :<<1" , "11100100100sssss PP-ttttt -11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_hh_s1 */, -{ "Rdd32 = mpy ( Rs32.h , Rt32.h ) :rnd" , "11100100001sssss PP-ttttt -11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_rnd_hh_s0 */, -{ "Rdd32 = mpy ( Rs32.h , Rt32.h )" , "11100100000sssss PP-ttttt -11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_hh_s0 */, -{ "Rdd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd" , "11100100101sssss PP-ttttt -10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_rnd_hl_s1 */, -{ "Rdd32 = mpy ( Rs32.h , Rt32.l ) :<<1" , "11100100100sssss PP-ttttt -10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_hl_s1 */, -{ "Rdd32 = mpy ( Rs32.h , Rt32.l ) :rnd" , "11100100001sssss PP-ttttt -10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_rnd_hl_s0 */, -{ "Rdd32 = mpy ( Rs32.h , Rt32.l )" , "11100100000sssss PP-ttttt -10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_hl_s0 */, -{ "Rdd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd" , "11100100101sssss PP-ttttt -01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_rnd_lh_s1 */, -{ "Rdd32 = mpy ( Rs32.l , Rt32.h ) :<<1" , "11100100100sssss PP-ttttt -01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_lh_s1 */, -{ "Rdd32 = mpy ( Rs32.l , Rt32.h ) :rnd" , "11100100001sssss PP-ttttt -01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_rnd_lh_s0 */, -{ "Rdd32 = mpy ( Rs32.l , Rt32.h )" , "11100100000sssss PP-ttttt -01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_lh_s0 */, -{ "Rdd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd" , "11100100101sssss PP-ttttt -00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_rnd_ll_s1 */, -{ "Rdd32 = mpy ( Rs32.l , Rt32.l ) :<<1" , "11100100100sssss PP-ttttt -00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_ll_s1 */, -{ "Rdd32 = mpy ( Rs32.l , Rt32.l ) :rnd" , "11100100001sssss PP-ttttt -00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_rnd_ll_s0 */, -{ "Rdd32 = mpy ( Rs32.l , Rt32.l )" , "11100100000sssss PP-ttttt -00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_ll_s0 */, -{ "Rdd32 = mpy ( Rs32 , Rt32 )" , "11100101000sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32, NULL} /* M2_dpmpyss_s0 */, -{ "Rdd32 = mpyu ( Rs32.h , Rt32.h ) :<<1" , "11100100110sssss PP-ttttt -11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyud_hh_s1 */, -{ "Rdd32 = mpyu ( Rs32.h , Rt32.h )" , "11100100010sssss PP-ttttt -11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyud_hh_s0 */, -{ "Rdd32 = mpyu ( Rs32.h , Rt32.l ) :<<1" , "11100100110sssss PP-ttttt -10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyud_hl_s1 */, -{ "Rdd32 = mpyu ( Rs32.h , Rt32.l )" , "11100100010sssss PP-ttttt -10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyud_hl_s0 */, -{ "Rdd32 = mpyu ( Rs32.l , Rt32.h ) :<<1" , "11100100110sssss PP-ttttt -01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyud_lh_s1 */, -{ "Rdd32 = mpyu ( Rs32.l , Rt32.h )" , "11100100010sssss PP-ttttt -01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyud_lh_s0 */, -{ "Rdd32 = mpyu ( Rs32.l , Rt32.l ) :<<1" , "11100100110sssss PP-ttttt -00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyud_ll_s1 */, -{ "Rdd32 = mpyu ( Rs32.l , Rt32.l )" , "11100100010sssss PP-ttttt -00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_mpyud_ll_s0 */, -{ "Rdd32 = mpyu ( Rs32 , Rt32 )" , "11100101010sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32|A_INTRINSIC_RETURNS_UNSIGNED, NULL} /* M2_dpmpyuu_s0 */, -{ "Rdd32 = neg ( Rss32 )" , "1000 0000 100sssss PP------ 1 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_negp */, -{ "Rdd32 = not ( Rss32 )" , "1000 0000 100sssss PP------ 1 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_notp */, -{ "Rdd32 = or ( Rss32 , Rtt32 )" , "1101 0011 111sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_orp */, -{ "Rdd32 = or ( Rtt32 , ~ Rss32 )" , "1101 0011 111sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_ornp */, -{ "Rdd32 = packhl ( Rs32 , Rt32 ) :deprecated" , "1101 0100 --0sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* dep_S2_packhl */, -{ "Rdd32 = packhl ( Rs32 , Rt32 )" , "1111 0101 1--sssss PP-ttttt ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* S2_packhl */, -{ "Rdd32 = pmpyw ( Rs32 , Rt32 )" , "11100101010sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_pmpyw */, -{ "Rdd32 = shuffeb ( Rss32 , Rtt32 )" , "1100 0001 00-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_shuffeb */, -{ "Rdd32 = shuffeh ( Rss32 , Rtt32 )" , "1100 0001 00-sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_shuffeh */, -{ "Rdd32 = shuffob ( Rtt32 , Rss32 )" , "1100 0001 00-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_shuffob */, -{ "Rdd32 = shuffoh ( Rtt32 , Rss32 )" , "1100 0001 10-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_shuffoh */, -{ "Rdd32 = sub ( Rss32 , Rtt32 , Px4 ) :carry" , "1100 0010 111sssss PP-ttttt -xxddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_DOTOLD, NULL} /* A4_subp_c */, -{ "Rdd32 = sub ( Rtt32 , Rss32 )" , "1101 0011 001sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_subp */, -{ "Rdd32 = sxtw ( Rs32 )" , "1000 0100 01-sssss PP------ 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_sxtw */, -{ "Rdd32 = tlbr ( Rs32 )" , "0110 1100 010sssss PP------ ---ddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_tlbr */, -{ "Rdd32 = vabsdiffh ( Rtt32 , Rss32 )" , "11101000011sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* M2_vabsdiffh */, -{ "Rdd32 = vabsdiffw ( Rtt32 , Rss32 )" , "11101000001sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* M2_vabsdiffw */, -{ "Rdd32 = vabsh ( Rss32 ) :sat" , "1000 0000 010sssss PP------ 1 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vabshsat */, -{ "Rdd32 = vabsh ( Rss32 )" , "1000 0000 010sssss PP------ 1 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vabsh */, -{ "Rdd32 = vabsw ( Rss32 ) :sat" , "1000 0000 010sssss PP------ 1 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vabswsat */, -{ "Rdd32 = vabsw ( Rss32 )" , "1000 0000 010sssss PP------ 1 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vabsw */, -{ "Rdd32 = vaddb ( Rss32 , Rtt32 )" , "0000dddddsssssttttt0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_vaddb_map)}, /* mapped to Rdd32=vaddub(Rss32,Rtt32) */ -{ "Rdd32 = vaddh ( Rss32 , Rtt32 ) :sat" , "1101 0011 000sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vaddhs */, -{ "Rdd32 = vaddh ( Rss32 , Rtt32 )" , "1101 0011 000sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vaddh */, -{ "Rdd32 = vaddub ( Rss32 , Rtt32 ) :sat" , "1101 0011 000sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* A2_vaddubs */, -{ "Rdd32 = vaddub ( Rss32 , Rtt32 )" , "1101 0011 000sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vaddub */, -{ "Rdd32 = vadduh ( Rss32 , Rtt32 ) :sat" , "1101 0011 000sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* A2_vadduhs */, -{ "Rdd32 = vaddw ( Rss32 , Rtt32 ) :sat" , "1101 0011 000sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vaddws */, -{ "Rdd32 = vaddw ( Rss32 , Rtt32 )" , "1101 0011 000sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vaddw */, -{ "Rdd32 = valignb ( Rtt32 , Rss32 , #u3 )" , "1100 0000 0--sssss PP-ttttt iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_valignib */, -{ "Rdd32 = valignb ( Rtt32 , Rss32 , Pu4 )" , "1100 0010 0--sssss PP-ttttt -uuddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_valignrb */, -{ "Rdd32 = vaslh ( Rss32 , #u4 )" , "1000 0000 100sssss PP00iiii 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asl_i_vh */, -{ "Rdd32 = vaslh ( Rss32 , Rt32 )" , "1100 0011 01-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_OOBVSHIFT|A_BIDIRSHIFTL, NULL} /* S2_asl_r_vh */, -{ "Rdd32 = vaslw ( Rss32 , #u5 )" , "1000 0000 010sssss PP0iiiii 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asl_i_vw */, -{ "Rdd32 = vaslw ( Rss32 , Rt32 )" , "1100 0011 00-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_OOBVSHIFT|A_BIDIRSHIFTL, NULL} /* S2_asl_r_vw */, -{ "Rdd32 = vasrh ( Rss32 , #u4 ) :raw" , "1000 0000 001sssss PP00iiii 0 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S5_vasrhrnd */, -{ "Rdd32 = vasrh ( Rss32 , #u4 ) :rnd" , "0000dddddsssssiiii00000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S5_vasrhrnd_goodsyntax)}, /* mapped to Rdd32=Rss32 or Rdd32=vasrh(Rss32,#u4-1):raw */ -{ "Rdd32 = vasrh ( Rss32 , #u4 )" , "1000 0000 100sssss PP00iiii 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asr_i_vh */, -{ "Rdd32 = vasrh ( Rss32 , Rt32 )" , "1100 0011 01-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_OOBVSHIFT|A_BIDIRSHIFTR, NULL} /* S2_asr_r_vh */, -{ "Rdd32 = vasrw ( Rss32 , #u5 )" , "1000 0000 010sssss PP0iiiii 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asr_i_vw */, -{ "Rdd32 = vasrw ( Rss32 , Rt32 )" , "1100 0011 00-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_OOBVSHIFT|A_BIDIRSHIFTR, NULL} /* S2_asr_r_vw */, -{ "Rdd32 = vavgh ( Rss32 , Rtt32 ) :crnd" , "1101 0011 010sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* A2_vavghcr */, -{ "Rdd32 = vavgh ( Rss32 , Rtt32 ) :rnd" , "1101 0011 010sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavghr */, -{ "Rdd32 = vavgh ( Rss32 , Rtt32 )" , "1101 0011 010sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavgh */, -{ "Rdd32 = vavgub ( Rss32 , Rtt32 ) :rnd" , "1101 0011 010sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavgubr */, -{ "Rdd32 = vavgub ( Rss32 , Rtt32 )" , "1101 0011 010sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavgub */, -{ "Rdd32 = vavguh ( Rss32 , Rtt32 ) :rnd" , "1101 0011 010sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavguhr */, -{ "Rdd32 = vavguh ( Rss32 , Rtt32 )" , "1101 0011 010sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavguh */, -{ "Rdd32 = vavguw ( Rss32 , Rtt32 ) :rnd" , "1101 0011 011sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavguwr */, -{ "Rdd32 = vavguw ( Rss32 , Rtt32 )" , "1101 0011 011sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavguw */, -{ "Rdd32 = vavgw ( Rss32 , Rtt32 ) :crnd" , "1101 0011 011sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* A2_vavgwcr */, -{ "Rdd32 = vavgw ( Rss32 , Rtt32 ) :rnd" , "1101 0011 011sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavgwr */, -{ "Rdd32 = vavgw ( Rss32 , Rtt32 )" , "1101 0011 011sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vavgw */, -{ "Rdd32 = vcmpyi ( Rss32 , Rtt32 ) :<<1 :sat" , "11101000110sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vcmpy_s1_sat_i */, -{ "Rdd32 = vcmpyi ( Rss32 , Rtt32 ) :sat" , "11101000010sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vcmpy_s0_sat_i */, -{ "Rdd32 = vcmpyr ( Rss32 , Rtt32 ) :<<1 :sat" , "11101000101sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vcmpy_s1_sat_r */, -{ "Rdd32 = vcmpyr ( Rss32 , Rtt32 ) :sat" , "11101000001sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vcmpy_s0_sat_r */, -{ "Rdd32 = vcnegh ( Rss32 , Rt32 )" , "1100 0011 11-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_vcnegh */, -{ "Rdd32 = vconj ( Rss32 ) :sat" , "1000 0000 100sssss PP------ 1 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vconj */, -{ "Rdd32 = vcrotate ( Rss32 , Rt32 )" , "1100 0011 11-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_vcrotate */, -{ "Rdd32 = vdmpy ( Rss32 , Rtt32 ) :<<1 :sat" , "11101000100sssss PP0ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vdmpys_s1 */, -{ "Rdd32 = vdmpy ( Rss32 , Rtt32 ) :sat" , "11101000000sssss PP0ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vdmpys_s0 */, -{ "Rdd32 = vdmpybsu ( Rss32 , Rtt32 ) :sat" , "11101000101sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M5_vdmpybsu */, -{ "Rdd32 = vlslh ( Rss32 , Rt32 )" , "1100 0011 01-sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_OOBVSHIFT|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_vh */, -{ "Rdd32 = vlslw ( Rss32 , Rt32 )" , "1100 0011 00-sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_OOBVSHIFT|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_vw */, -{ "Rdd32 = vlsrh ( Rss32 , #u4 )" , "1000 0000 100sssss PP00iiii 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_lsr_i_vh */, -{ "Rdd32 = vlsrh ( Rss32 , Rt32 )" , "1100 0011 01-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_OOBVSHIFT|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_vh */, -{ "Rdd32 = vlsrw ( Rss32 , #u5 )" , "1000 0000 010sssss PP0iiiii 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_lsr_i_vw */, -{ "Rdd32 = vlsrw ( Rss32 , Rt32 )" , "1100 0011 00-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_NOTE_OOBVSHIFT|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_vw */, -{ "Rdd32 = vmaxb ( Rtt32 , Rss32 )" , "1101 0011 110sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vmaxb */, -{ "Rdd32 = vmaxh ( Rtt32 , Rss32 )" , "1101 0011 110sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vmaxh */, -{ "Rdd32 = vmaxub ( Rtt32 , Rss32 )" , "1101 0011 110sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vmaxub */, -{ "Rdd32 = vmaxuh ( Rtt32 , Rss32 )" , "1101 0011 110sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vmaxuh */, -{ "Rdd32 = vmaxuw ( Rtt32 , Rss32 )" , "1101 0011 101sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vmaxuw */, -{ "Rdd32 = vmaxw ( Rtt32 , Rss32 )" , "1101 0011 110sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vmaxw */, -{ "Rdd32 = vminb ( Rtt32 , Rss32 )" , "1101 0011 110sssss PP-ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vminb */, -{ "Rdd32 = vminh ( Rtt32 , Rss32 )" , "1101 0011 101sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vminh */, -{ "Rdd32 = vminub ( Rtt32 , Rss32 )" , "1101 0011 101sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vminub */, -{ "Rdd32 = vminuh ( Rtt32 , Rss32 )" , "1101 0011 101sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vminuh */, -{ "Rdd32 = vminuw ( Rtt32 , Rss32 )" , "1101 0011 101sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vminuw */, -{ "Rdd32 = vminw ( Rtt32 , Rss32 )" , "1101 0011 101sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vminw */, -{ "Rdd32 = vmpybsu ( Rs32 , Rt32 )" , "11100101010sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M5_vmpybsu */, -{ "Rdd32 = vmpybu ( Rs32 , Rt32 )" , "11100101100sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M5_vmpybuu */, -{ "Rdd32 = vmpyeh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101000100sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmpy2es_s1 */, -{ "Rdd32 = vmpyeh ( Rss32 , Rtt32 ) :sat" , "11101000000sssss PP0ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmpy2es_s0 */, -{ "Rdd32 = vmpyh ( Rs32 , Rt32 ) :<<1 :sat" , "11100101100sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmpy2s_s1 */, -{ "Rdd32 = vmpyh ( Rs32 , Rt32 ) :sat" , "11100101000sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmpy2s_s0 */, -{ "Rdd32 = vmpyhsu ( Rs32 , Rt32 ) :<<1 :sat" , "11100101100sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmpy2su_s1 */, -{ "Rdd32 = vmpyhsu ( Rs32 , Rt32 ) :sat" , "11100101000sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmpy2su_s0 */, -{ "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" , "11101000101sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyl_rs1 */, -{ "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101000100sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyl_s1 */, -{ "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :rnd :sat" , "11101000001sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyl_rs0 */, -{ "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :sat" , "11101000000sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyl_s0 */, -{ "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" , "11101000111sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyul_rs1 */, -{ "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101000110sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyul_s1 */, -{ "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :rnd :sat" , "11101000011sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyul_rs0 */, -{ "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :sat" , "11101000010sssss PP0ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyul_s0 */, -{ "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" , "11101000101sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyh_rs1 */, -{ "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101000100sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyh_s1 */, -{ "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :rnd :sat" , "11101000001sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyh_rs0 */, -{ "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :sat" , "11101000000sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyh_s0 */, -{ "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" , "11101000111sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyuh_rs1 */, -{ "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101000110sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyuh_s1 */, -{ "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :rnd :sat" , "11101000011sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyuh_rs0 */, -{ "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :sat" , "11101000010sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmpyuh_s0 */, -{ "Rdd32 = vmux ( Pu4 , Rss32 , Rtt32 )" , "1101 0001 ---sssss PP-ttttt -uuddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* C2_vmux */, -{ "Rdd32 = vnavgh ( Rtt32 , Rss32 ) :crnd :sat" , "1101 0011 100sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vnavghcr */, -{ "Rdd32 = vnavgh ( Rtt32 , Rss32 ) :rnd :sat" , "1101 0011 100sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vnavghr */, -{ "Rdd32 = vnavgh ( Rtt32 , Rss32 )" , "1101 0011 100sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vnavgh */, -{ "Rdd32 = vnavgw ( Rtt32 , Rss32 ) :crnd :sat" , "1101 0011 100sssss PP-ttttt 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vnavgwcr */, -{ "Rdd32 = vnavgw ( Rtt32 , Rss32 ) :rnd :sat" , "1101 0011 100sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vnavgwr */, -{ "Rdd32 = vnavgw ( Rtt32 , Rss32 )" , "1101 0011 100sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* A2_vnavgw */, -{ "Rdd32 = vpmpyh ( Rs32 , Rt32 )" , "11100101110sssss PP0ttttt 111ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vpmpyh */, -{ "Rdd32 = vraddub ( Rss32 , Rtt32 )" , "11101000010sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vraddub */, -{ "Rdd32 = vrcmpyi ( Rss32 , Rtt32 )" , "11101000000sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_vrcmpyi_s0 */, -{ "Rdd32 = vrcmpyi ( Rss32 , Rtt32 * )" , "11101000010sssss PP0ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* M2_vrcmpyi_s0c */, -{ "Rdd32 = vrcmpyr ( Rss32 , Rtt32 )" , "11101000000sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_vrcmpyr_s0 */, -{ "Rdd32 = vrcmpyr ( Rss32 , Rtt32 * )" , "11101000011sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* M2_vrcmpyr_s0c */, -{ "Rdd32 = vrcmpys ( Rss32 , Rt32 ) :<<1 :sat" , "0000dddddsssssttttt0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(M2_vrcmpys_s1)}, /* mapped to Rdd32=vrcmpys(Rss32,Rtt32):<<1:sat:raw:hi or Rdd32=vrcmpys(Rss32,Rtt32):<<1:sat:raw:lo */ -{ "Rdd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :hi" , "11101000101sssss PP0ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV3|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vrcmpys_s1_h */, -{ "Rdd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :lo" , "11101000111sssss PP0ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV3|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vrcmpys_s1_l */, -{ "Rdd32 = vrcrotate ( Rss32 , Rt32 , #u2 )" , "1100 0011 11-sssss PPittttt 11iddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S4_vrcrotate */, -{ "Rdd32 = vrmpybsu ( Rss32 , Rtt32 )" , "11101000110sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M5_vrmpybsu */, -{ "Rdd32 = vrmpybu ( Rss32 , Rtt32 )" , "11101000100sssss PP0ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M5_vrmpybuu */, -{ "Rdd32 = vrmpyh ( Rss32 , Rtt32 )" , "11101000000sssss PP0ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_vrmpy_s0 */, -{ "Rdd32 = vrmpyweh ( Rss32 , Rtt32 ) :<<1" , "11101000110sssss PP0ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vrmpyeh_s1 */, -{ "Rdd32 = vrmpyweh ( Rss32 , Rtt32 )" , "11101000010sssss PP0ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vrmpyeh_s0 */, -{ "Rdd32 = vrmpywoh ( Rss32 , Rtt32 ) :<<1" , "11101000101sssss PP0ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vrmpyoh_s1 */, -{ "Rdd32 = vrmpywoh ( Rss32 , Rtt32 )" , "11101000001sssss PP0ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vrmpyoh_s0 */, -{ "Rdd32 = vrsadub ( Rss32 , Rtt32 )" , "11101000010sssss PP0ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vrsadub */, -{ "Rdd32 = vsathb ( Rss32 )" , "1000 0000 000sssss PP------ 1 11ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_vsathb_nopack */, -{ "Rdd32 = vsathub ( Rss32 )" , "1000 0000 000sssss PP------ 1 00ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* S2_vsathub_nopack */, -{ "Rdd32 = vsatwh ( Rss32 )" , "1000 0000 000sssss PP------ 1 10ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S2_vsatwh_nopack */, -{ "Rdd32 = vsatwuh ( Rss32 )" , "1000 0000 000sssss PP------ 1 01ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* S2_vsatwuh_nopack */, -{ "Rdd32 = vsplath ( Rs32 )" , "1000 0100 01-sssss PP------ 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vsplatrh */, -{ "Rdd32 = vspliceb ( Rss32 , Rtt32 , #u3 )" , "1100 0000 1--sssss PP-ttttt iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vspliceib */, -{ "Rdd32 = vspliceb ( Rss32 , Rtt32 , Pu4 )" , "1100 0010 10-sssss PP-ttttt -uuddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vsplicerb */, -{ "Rdd32 = vsubb ( Rss32 , Rtt32 )" , "0000dddddsssssttttt0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_vsubb_map)}, /* mapped to Rdd32=vsubub(Rss32,Rtt32) */ -{ "Rdd32 = vsubh ( Rtt32 , Rss32 ) :sat" , "1101 0011 001sssss PP-ttttt 011ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vsubhs */, -{ "Rdd32 = vsubh ( Rtt32 , Rss32 )" , "1101 0011 001sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vsubh */, -{ "Rdd32 = vsubub ( Rtt32 , Rss32 ) :sat" , "1101 0011 001sssss PP-ttttt 001ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* A2_vsububs */, -{ "Rdd32 = vsubub ( Rtt32 , Rss32 )" , "1101 0011 001sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vsubub */, -{ "Rdd32 = vsubuh ( Rtt32 , Rss32 ) :sat" , "1101 0011 001sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE|A_USATURATE, NULL} /* A2_vsubuhs */, -{ "Rdd32 = vsubw ( Rtt32 , Rss32 ) :sat" , "1101 0011 001sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* A2_vsubws */, -{ "Rdd32 = vsubw ( Rtt32 , Rss32 )" , "1101 0011 001sssss PP-ttttt 101ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vsubw */, -{ "Rdd32 = vsxtbh ( Rs32 )" , "1000 0100 00-sssss PP------ 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_vsxtbh */, -{ "Rdd32 = vsxthw ( Rs32 )" , "1000 0100 00-sssss PP------ 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vsxthw */, -{ "Rdd32 = vtrunewh ( Rss32 , Rtt32 )" , "1100 0001 10-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_vtrunewh */, -{ "Rdd32 = vtrunowh ( Rss32 , Rtt32 )" , "1100 0001 10-sssss PP-ttttt 10-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* S2_vtrunowh */, -{ "Rdd32 = vxaddsubh ( Rss32 , Rtt32 ) :rnd :>>1 :sat" , "1100 0001 11-sssss PP-ttttt 00-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S4_vxaddsubhr */, -{ "Rdd32 = vxaddsubh ( Rss32 , Rtt32 ) :sat" , "1100 0001 01-sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S4_vxaddsubh */, -{ "Rdd32 = vxaddsubw ( Rss32 , Rtt32 ) :sat" , "1100 0001 01-sssss PP-ttttt 000ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S4_vxaddsubw */, -{ "Rdd32 = vxsubaddh ( Rss32 , Rtt32 ) :rnd :>>1 :sat" , "1100 0001 11-sssss PP-ttttt 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S4_vxsubaddhr */, -{ "Rdd32 = vxsubaddh ( Rss32 , Rtt32 ) :sat" , "1100 0001 01-sssss PP-ttttt 110ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S4_vxsubaddh */, -{ "Rdd32 = vxsubaddw ( Rss32 , Rtt32 ) :sat" , "1100 0001 01-sssss PP-ttttt 010ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* S4_vxsubaddw */, -{ "Rdd32 = vzxtbh ( Rs32 )" , "1000 0100 00-sssss PP------ 01-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vzxtbh */, -{ "Rdd32 = vzxthw ( Rs32 )" , "1000 0100 00-sssss PP------ 11-ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vzxthw */, -{ "Rdd32 = xor ( Rss32 , Rtt32 )" , "1101 0011 111sssss PP-ttttt 100ddddd" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_xorp */, -{ "Rdd8 = combine ( #0 , #U2 ) ; allocframe ( #u5:3 )" , "011111-0-II00dddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS2_allocframe */, -{ "Rdd8 = combine ( #0 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #0" , "011111-0-II00dddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS2_storebi0 */, -{ "Rdd8 = combine ( #0 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #1" , "011111-0-II00dddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS2_storebi1 */, -{ "Rdd8 = combine ( #0 , #U2 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "011111-0-II00dddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS1_storeb_io */, -{ "Rdd8 = combine ( #0 , #U2 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "011111-0-II00dddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS2_stored_sp */, -{ "Rdd8 = combine ( #0 , #U2 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "011111-0-II00dddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS2_storeh_io */, -{ "Rdd8 = combine ( #0 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #0" , "011111-0-II00dddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS2_storewi0 */, -{ "Rdd8 = combine ( #0 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #1" , "011111-0-II00dddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS2_storewi1 */, -{ "Rdd8 = combine ( #0 , #U2 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "011111-0-II00dddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS1_storew_io */, -{ "Rdd8 = combine ( #0 , #U2 ) ; memw ( Sp + #u5:2 ) = Rt16" , "011111-0-II00dddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SS2_storew_sp */, -{ "Rdd8 = combine ( #0 , #u2 ) ; dealloc_return" , "010111-0-ii00dddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_return */, -{ "Rdd8 = combine ( #0 , #u2 ) ; deallocframe" , "010111-0-ii00dddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_deallocframe */, -{ "Rdd8 = combine ( #0 , #u2 ) ; if ( ! p0 ) dealloc_return" , "010111-0-ii00dddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_return_f */, -{ "Rdd8 = combine ( #0 , #u2 ) ; if ( ! p0 ) jumpr Lr" , "010111-0-ii00dddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_jumpr31_f */, -{ "Rdd8 = combine ( #0 , #u2 ) ; if ( ! p0 .new ) dealloc_return:nt" , "010111-0-ii00dddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_return_fnew */, -{ "Rdd8 = combine ( #0 , #u2 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "010111-0-ii00dddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_jumpr31_fnew */, -{ "Rdd8 = combine ( #0 , #u2 ) ; if ( p0 ) dealloc_return" , "010111-0-ii00dddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_return_t */, -{ "Rdd8 = combine ( #0 , #u2 ) ; if ( p0 ) jumpr Lr" , "010111-0-ii00dddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_jumpr31_t */, -{ "Rdd8 = combine ( #0 , #u2 ) ; if ( p0 .new ) dealloc_return:nt" , "010111-0-ii00dddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_return_tnew */, -{ "Rdd8 = combine ( #0 , #u2 ) ; if ( p0 .new ) jumpr:nt Lr" , "010111-0-ii00dddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_jumpr31_tnew */, -{ "Rdd8 = combine ( #0 , #u2 ) ; jumpr Lr" , "010111-0-ii00dddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_jumpr31 */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; allocframe ( #u5:3 )" , "011111-1ssss0dddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS2_allocframe */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; dealloc_return" , "010111-1ssss0dddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_return */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; deallocframe" , "010111-1ssss0dddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_deallocframe */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; if ( ! p0 ) dealloc_return" , "010111-1ssss0dddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_return_f */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; if ( ! p0 ) jumpr Lr" , "010111-1ssss0dddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_jumpr31_f */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; if ( ! p0 .new ) dealloc_return:nt" , "010111-1ssss0dddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_return_fnew */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "010111-1ssss0dddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_jumpr31_fnew */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; if ( p0 ) dealloc_return" , "010111-1ssss0dddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_return_t */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; if ( p0 ) jumpr Lr" , "010111-1ssss0dddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_jumpr31_t */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; if ( p0 .new ) dealloc_return:nt" , "010111-1ssss0dddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_return_tnew */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; if ( p0 .new ) jumpr:nt Lr" , "010111-1ssss0dddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_jumpr31_tnew */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; jumpr Lr" , "010111-1ssss0dddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_jumpr31 */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "011111-1ssss0dddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS2_stored_sp */, -{ "Rdd8 = combine ( #0 , Rs16 ) ; memw ( Sp + #u5:2 ) = Rt16" , "011111-1ssss0dddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS2_storew_sp */, -{ "Rdd8 = combine ( #0 , Ru16 ) ; memb ( Rs16 + #u4:0 ) = #0" , "011111-1uuuu0dddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS2_storebi0 */, -{ "Rdd8 = combine ( #0 , Ru16 ) ; memb ( Rs16 + #u4:0 ) = #1" , "011111-1uuuu0dddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS2_storebi1 */, -{ "Rdd8 = combine ( #0 , Ru16 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "011111-1uuuu0dddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS1_storeb_io */, -{ "Rdd8 = combine ( #0 , Ru16 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "011111-1uuuu0dddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS2_storeh_io */, -{ "Rdd8 = combine ( #0 , Ru16 ) ; memw ( Rs16 + #u4:2 ) = #0" , "011111-1uuuu0dddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS2_storewi0 */, -{ "Rdd8 = combine ( #0 , Ru16 ) ; memw ( Rs16 + #u4:2 ) = #1" , "011111-1uuuu0dddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS2_storewi1 */, -{ "Rdd8 = combine ( #0 , Ru16 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "011111-1uuuu0dddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SS1_storew_io */, -{ "Rdd8 = combine ( #1 , #U2 ) ; allocframe ( #u5:3 )" , "011111-0-II01dddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS2_allocframe */, -{ "Rdd8 = combine ( #1 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #0" , "011111-0-II01dddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS2_storebi0 */, -{ "Rdd8 = combine ( #1 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #1" , "011111-0-II01dddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS2_storebi1 */, -{ "Rdd8 = combine ( #1 , #U2 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "011111-0-II01dddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS1_storeb_io */, -{ "Rdd8 = combine ( #1 , #U2 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "011111-0-II01dddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS2_stored_sp */, -{ "Rdd8 = combine ( #1 , #U2 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "011111-0-II01dddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS2_storeh_io */, -{ "Rdd8 = combine ( #1 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #0" , "011111-0-II01dddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS2_storewi0 */, -{ "Rdd8 = combine ( #1 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #1" , "011111-0-II01dddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS2_storewi1 */, -{ "Rdd8 = combine ( #1 , #U2 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "011111-0-II01dddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS1_storew_io */, -{ "Rdd8 = combine ( #1 , #U2 ) ; memw ( Sp + #u5:2 ) = Rt16" , "011111-0-II01dddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SS2_storew_sp */, -{ "Rdd8 = combine ( #1 , #u2 ) ; dealloc_return" , "010111-0-ii01dddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_return */, -{ "Rdd8 = combine ( #1 , #u2 ) ; deallocframe" , "010111-0-ii01dddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_deallocframe */, -{ "Rdd8 = combine ( #1 , #u2 ) ; if ( ! p0 ) dealloc_return" , "010111-0-ii01dddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_return_f */, -{ "Rdd8 = combine ( #1 , #u2 ) ; if ( ! p0 ) jumpr Lr" , "010111-0-ii01dddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_jumpr31_f */, -{ "Rdd8 = combine ( #1 , #u2 ) ; if ( ! p0 .new ) dealloc_return:nt" , "010111-0-ii01dddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_return_fnew */, -{ "Rdd8 = combine ( #1 , #u2 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "010111-0-ii01dddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_jumpr31_fnew */, -{ "Rdd8 = combine ( #1 , #u2 ) ; if ( p0 ) dealloc_return" , "010111-0-ii01dddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_return_t */, -{ "Rdd8 = combine ( #1 , #u2 ) ; if ( p0 ) jumpr Lr" , "010111-0-ii01dddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_jumpr31_t */, -{ "Rdd8 = combine ( #1 , #u2 ) ; if ( p0 .new ) dealloc_return:nt" , "010111-0-ii01dddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_return_tnew */, -{ "Rdd8 = combine ( #1 , #u2 ) ; if ( p0 .new ) jumpr:nt Lr" , "010111-0-ii01dddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_jumpr31_tnew */, -{ "Rdd8 = combine ( #1 , #u2 ) ; jumpr Lr" , "010111-0-ii01dddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_jumpr31 */, -{ "Rdd8 = combine ( #2 , #U2 ) ; allocframe ( #u5:3 )" , "011111-0-II10dddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS2_allocframe */, -{ "Rdd8 = combine ( #2 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #0" , "011111-0-II10dddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS2_storebi0 */, -{ "Rdd8 = combine ( #2 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #1" , "011111-0-II10dddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS2_storebi1 */, -{ "Rdd8 = combine ( #2 , #U2 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "011111-0-II10dddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS1_storeb_io */, -{ "Rdd8 = combine ( #2 , #U2 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "011111-0-II10dddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS2_stored_sp */, -{ "Rdd8 = combine ( #2 , #U2 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "011111-0-II10dddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS2_storeh_io */, -{ "Rdd8 = combine ( #2 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #0" , "011111-0-II10dddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS2_storewi0 */, -{ "Rdd8 = combine ( #2 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #1" , "011111-0-II10dddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS2_storewi1 */, -{ "Rdd8 = combine ( #2 , #U2 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "011111-0-II10dddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS1_storew_io */, -{ "Rdd8 = combine ( #2 , #U2 ) ; memw ( Sp + #u5:2 ) = Rt16" , "011111-0-II10dddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SS2_storew_sp */, -{ "Rdd8 = combine ( #2 , #u2 ) ; dealloc_return" , "010111-0-ii10dddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_return */, -{ "Rdd8 = combine ( #2 , #u2 ) ; deallocframe" , "010111-0-ii10dddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_deallocframe */, -{ "Rdd8 = combine ( #2 , #u2 ) ; if ( ! p0 ) dealloc_return" , "010111-0-ii10dddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_return_f */, -{ "Rdd8 = combine ( #2 , #u2 ) ; if ( ! p0 ) jumpr Lr" , "010111-0-ii10dddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_jumpr31_f */, -{ "Rdd8 = combine ( #2 , #u2 ) ; if ( ! p0 .new ) dealloc_return:nt" , "010111-0-ii10dddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_return_fnew */, -{ "Rdd8 = combine ( #2 , #u2 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "010111-0-ii10dddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_jumpr31_fnew */, -{ "Rdd8 = combine ( #2 , #u2 ) ; if ( p0 ) dealloc_return" , "010111-0-ii10dddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_return_t */, -{ "Rdd8 = combine ( #2 , #u2 ) ; if ( p0 ) jumpr Lr" , "010111-0-ii10dddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_jumpr31_t */, -{ "Rdd8 = combine ( #2 , #u2 ) ; if ( p0 .new ) dealloc_return:nt" , "010111-0-ii10dddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_return_tnew */, -{ "Rdd8 = combine ( #2 , #u2 ) ; if ( p0 .new ) jumpr:nt Lr" , "010111-0-ii10dddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_jumpr31_tnew */, -{ "Rdd8 = combine ( #2 , #u2 ) ; jumpr Lr" , "010111-0-ii10dddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_jumpr31 */, -{ "Rdd8 = combine ( #3 , #U2 ) ; allocframe ( #u5:3 )" , "011111-0-II11dddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS2_allocframe */, -{ "Rdd8 = combine ( #3 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #0" , "011111-0-II11dddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS2_storebi0 */, -{ "Rdd8 = combine ( #3 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #1" , "011111-0-II11dddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS2_storebi1 */, -{ "Rdd8 = combine ( #3 , #U2 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "011111-0-II11dddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS1_storeb_io */, -{ "Rdd8 = combine ( #3 , #U2 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "011111-0-II11dddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS2_stored_sp */, -{ "Rdd8 = combine ( #3 , #U2 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "011111-0-II11dddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS2_storeh_io */, -{ "Rdd8 = combine ( #3 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #0" , "011111-0-II11dddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS2_storewi0 */, -{ "Rdd8 = combine ( #3 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #1" , "011111-0-II11dddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS2_storewi1 */, -{ "Rdd8 = combine ( #3 , #U2 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "011111-0-II11dddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS1_storew_io */, -{ "Rdd8 = combine ( #3 , #U2 ) ; memw ( Sp + #u5:2 ) = Rt16" , "011111-0-II11dddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SS2_storew_sp */, -{ "Rdd8 = combine ( #3 , #u2 ) ; dealloc_return" , "010111-0-ii11dddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_return */, -{ "Rdd8 = combine ( #3 , #u2 ) ; deallocframe" , "010111-0-ii11dddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_deallocframe */, -{ "Rdd8 = combine ( #3 , #u2 ) ; if ( ! p0 ) dealloc_return" , "010111-0-ii11dddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_return_f */, -{ "Rdd8 = combine ( #3 , #u2 ) ; if ( ! p0 ) jumpr Lr" , "010111-0-ii11dddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_jumpr31_f */, -{ "Rdd8 = combine ( #3 , #u2 ) ; if ( ! p0 .new ) dealloc_return:nt" , "010111-0-ii11dddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_return_fnew */, -{ "Rdd8 = combine ( #3 , #u2 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "010111-0-ii11dddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_jumpr31_fnew */, -{ "Rdd8 = combine ( #3 , #u2 ) ; if ( p0 ) dealloc_return" , "010111-0-ii11dddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_return_t */, -{ "Rdd8 = combine ( #3 , #u2 ) ; if ( p0 ) jumpr Lr" , "010111-0-ii11dddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_jumpr31_t */, -{ "Rdd8 = combine ( #3 , #u2 ) ; if ( p0 .new ) dealloc_return:nt" , "010111-0-ii11dddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_return_tnew */, -{ "Rdd8 = combine ( #3 , #u2 ) ; if ( p0 .new ) jumpr:nt Lr" , "010111-0-ii11dddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_jumpr31_tnew */, -{ "Rdd8 = combine ( #3 , #u2 ) ; jumpr Lr" , "010111-0-ii11dddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_jumpr31 */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; allocframe ( #u5:3 )" , "011111-1ssss1dddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS2_allocframe */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; dealloc_return" , "010111-1ssss1dddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_return */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; deallocframe" , "010111-1ssss1dddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_deallocframe */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; if ( ! p0 ) dealloc_return" , "010111-1ssss1dddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_return_f */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; if ( ! p0 ) jumpr Lr" , "010111-1ssss1dddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_jumpr31_f */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; if ( ! p0 .new ) dealloc_return:nt" , "010111-1ssss1dddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_return_fnew */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "010111-1ssss1dddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_jumpr31_fnew */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; if ( p0 ) dealloc_return" , "010111-1ssss1dddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_return_t */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; if ( p0 ) jumpr Lr" , "010111-1ssss1dddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_jumpr31_t */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; if ( p0 .new ) dealloc_return:nt" , "010111-1ssss1dddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_return_tnew */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; if ( p0 .new ) jumpr:nt Lr" , "010111-1ssss1dddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_jumpr31_tnew */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; jumpr Lr" , "010111-1ssss1dddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_jumpr31 */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "011111-1ssss1dddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS2_stored_sp */, -{ "Rdd8 = combine ( Rs16 , #0 ) ; memw ( Sp + #u5:2 ) = Rt16" , "011111-1ssss1dddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS2_storew_sp */, -{ "Rdd8 = combine ( Ru16 , #0 ) ; memb ( Rs16 + #u4:0 ) = #0" , "011111-1uuuu1dddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS2_storebi0 */, -{ "Rdd8 = combine ( Ru16 , #0 ) ; memb ( Rs16 + #u4:0 ) = #1" , "011111-1uuuu1dddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS2_storebi1 */, -{ "Rdd8 = combine ( Ru16 , #0 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "011111-1uuuu1dddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS1_storeb_io */, -{ "Rdd8 = combine ( Ru16 , #0 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "011111-1uuuu1dddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS2_storeh_io */, -{ "Rdd8 = combine ( Ru16 , #0 ) ; memw ( Rs16 + #u4:2 ) = #0" , "011111-1uuuu1dddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS2_storewi0 */, -{ "Rdd8 = combine ( Ru16 , #0 ) ; memw ( Rs16 + #u4:2 ) = #1" , "011111-1uuuu1dddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS2_storewi1 */, -{ "Rdd8 = combine ( Ru16 , #0 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "011111-1uuuu1dddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SS1_storew_io */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; allocframe ( #u5:3 )" , "11011110IIIIIdddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS2_allocframe */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; memb ( Rs16 + #u4:0 ) = #0" , "11011110IIIIIdddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS2_storebi0 */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; memb ( Rs16 + #u4:0 ) = #1" , "11011110IIIIIdddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS2_storebi1 */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "10011110IIIIIdddEE11iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS1_storeb_io */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "11011110IIIIIdddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS2_stored_sp */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "11011110IIIIIdddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS2_storeh_io */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; memw ( Rs16 + #u4:2 ) = #0" , "11011110IIIIIdddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS2_storewi0 */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; memw ( Rs16 + #u4:2 ) = #1" , "11011110IIIIIdddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS2_storewi1 */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "10011110IIIIIdddEE10iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS1_storew_io */, -{ "Rdd8 = memd ( Sp + #U5:3 ) ; memw ( Sp + #u5:2 ) = Rt16" , "11011110IIIIIdddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SS2_storew_sp */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; dealloc_return" , "00111110iiiiidddEE01111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_return */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; deallocframe" , "00111110iiiiidddEE01111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_deallocframe */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; if ( ! p0 ) dealloc_return" , "00111110iiiiidddEE01111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_return_f */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; if ( ! p0 ) jumpr Lr" , "00111110iiiiidddEE01111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_jumpr31_f */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; if ( ! p0 .new ) dealloc_return:nt" , "00111110iiiiidddEE01111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_return_fnew */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "00111110iiiiidddEE01111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_jumpr31_fnew */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; if ( p0 ) dealloc_return" , "00111110iiiiidddEE01111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_return_t */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; if ( p0 ) jumpr Lr" , "00111110iiiiidddEE01111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_jumpr31_t */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; if ( p0 .new ) dealloc_return:nt" , "00111110iiiiidddEE01111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_return_tnew */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; if ( p0 .new ) jumpr:nt Lr" , "00111110iiiiidddEE01111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_jumpr31_tnew */, -{ "Rdd8 = memd ( Sp + #u5:3 ) ; jumpr Lr" , "00111110iiiiidddEE01111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_jumpr31 */, -{ "Re16 = #-1 ; Rd16 = #-1" , "0011101--0--eeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_setin1 */, -{ "Re16 = #-1 ; Rd16 = memb ( Rs16 + #u3:0 )" , "0101101--0--eeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_loadrb_io */, -{ "Re16 = #-1 ; Rd16 = memh ( Rs16 + #u3:1 )" , "0101101--0--eeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_loadrh_io */, -{ "Re16 = #-1 ; Rd16 = memub ( Rs16 + #u4:0 )" , "0101101--0--eeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL1_loadrub_io */, -{ "Re16 = #-1 ; Rd16 = memuh ( Rs16 + #u3:1 )" , "0101101--0--eeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_loadruh_io */, -{ "Re16 = #-1 ; Rd16 = memw ( Rs16 + #u4:2 )" , "0101101--0--eeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL1_loadri_io */, -{ "Re16 = #-1 ; Rd16 = memw ( Sp + #u5:2 )" , "0101101--0--eeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_loadri_sp */, -{ "Re16 = #-1 ; Rdd8 = combine ( #0 , #u2 )" , "0011101--0--eeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_combine0i */, -{ "Re16 = #-1 ; Rdd8 = combine ( #0 , Rs16 )" , "0011101--0--eeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_combinezr */, -{ "Re16 = #-1 ; Rdd8 = combine ( #1 , #u2 )" , "0011101--0--eeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_combine1i */, -{ "Re16 = #-1 ; Rdd8 = combine ( #2 , #u2 )" , "0011101--0--eeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_combine2i */, -{ "Re16 = #-1 ; Rdd8 = combine ( #3 , #u2 )" , "0011101--0--eeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_combine3i */, -{ "Re16 = #-1 ; Rdd8 = combine ( Rs16 , #0 )" , "0011101--0--eeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_combinerz */, -{ "Re16 = #-1 ; Rdd8 = memd ( Sp + #u5:3 )" , "0101101--0--eeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SL2_loadrd_sp */, -{ "Re16 = #-1 ; if ( ! p0 ) Rd16 = #0" , "0011101--0--eeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_clrf */, -{ "Re16 = #-1 ; if ( ! p0 .new ) Rd16 = #0" , "0011101--0--eeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_clrfnew */, -{ "Re16 = #-1 ; if ( p0 ) Rd16 = #0" , "0011101--0--eeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_clrt */, -{ "Re16 = #-1 ; if ( p0 .new ) Rd16 = #0" , "0011101--0--eeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_setin1_SA1_clrtnew */, -{ "Re16 = #U6 ; Rd16 = #-1" , "001010IIIIIIeeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_setin1 */, -{ "Re16 = #U6 ; Rd16 = #u6" , "001010IIIIIIeeeeEE1010iiiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_seti */, -{ "Re16 = #U6 ; Rd16 = add ( Rs16 , #-1 )" , "001010IIIIIIeeeeEE110011ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_dec */, -{ "Re16 = #U6 ; Rd16 = add ( Rs16 , #1 )" , "001010IIIIIIeeeeEE110001ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_inc */, -{ "Re16 = #U6 ; Rd16 = add ( Sp , #u6:2 )" , "001010IIIIIIeeeeEE1011iiiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_addsp */, -{ "Re16 = #U6 ; Rd16 = and ( Rs16 , #1 )" , "001010IIIIIIeeeeEE110010ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_and1 */, -{ "Re16 = #U6 ; Rd16 = and ( Rs16 , #255 )" , "001010IIIIIIeeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_zxtb */, -{ "Re16 = #U6 ; Rd16 = memb ( Rs16 + #u3:0 )" , "010010IIIIIIeeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_loadrb_io */, -{ "Re16 = #U6 ; Rd16 = memh ( Rs16 + #u3:1 )" , "010010IIIIIIeeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_loadrh_io */, -{ "Re16 = #U6 ; Rd16 = memub ( Rs16 + #u4:0 )" , "010010IIIIIIeeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL1_loadrub_io */, -{ "Re16 = #U6 ; Rd16 = memuh ( Rs16 + #u3:1 )" , "010010IIIIIIeeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_loadruh_io */, -{ "Re16 = #U6 ; Rd16 = memw ( Rs16 + #u4:2 )" , "010010IIIIIIeeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL1_loadri_io */, -{ "Re16 = #U6 ; Rd16 = memw ( Sp + #u5:2 )" , "010010IIIIIIeeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_loadri_sp */, -{ "Re16 = #U6 ; Rdd8 = combine ( #0 , #u2 )" , "001010IIIIIIeeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_combine0i */, -{ "Re16 = #U6 ; Rdd8 = combine ( #0 , Rs16 )" , "001010IIIIIIeeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_combinezr */, -{ "Re16 = #U6 ; Rdd8 = combine ( #1 , #u2 )" , "001010IIIIIIeeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_combine1i */, -{ "Re16 = #U6 ; Rdd8 = combine ( #2 , #u2 )" , "001010IIIIIIeeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_combine2i */, -{ "Re16 = #U6 ; Rdd8 = combine ( #3 , #u2 )" , "001010IIIIIIeeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_combine3i */, -{ "Re16 = #U6 ; Rdd8 = combine ( Rs16 , #0 )" , "001010IIIIIIeeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_combinerz */, -{ "Re16 = #U6 ; Rdd8 = memd ( Sp + #u5:3 )" , "010010IIIIIIeeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SL2_loadrd_sp */, -{ "Re16 = #U6 ; if ( ! p0 ) Rd16 = #0" , "001010IIIIIIeeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_clrf */, -{ "Re16 = #U6 ; if ( ! p0 .new ) Rd16 = #0" , "001010IIIIIIeeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_clrfnew */, -{ "Re16 = #U6 ; if ( p0 ) Rd16 = #0" , "001010IIIIIIeeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_clrt */, -{ "Re16 = #U6 ; if ( p0 .new ) Rd16 = #0" , "001010IIIIIIeeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_clrtnew */, -{ "Re16 = #u6 ; Rd16 = Rs16" , "001010iiiiiieeeeEE110000ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_tfr */, -{ "Re16 = #u6 ; Rd16 = sxtb ( Rs16 )" , "001010iiiiiieeeeEE110101ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_sxtb */, -{ "Re16 = #u6 ; Rd16 = sxth ( Rs16 )" , "001010iiiiiieeeeEE110100ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_sxth */, -{ "Re16 = #u6 ; Rd16 = zxth ( Rs16 )" , "001010iiiiiieeeeEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_seti_SA1_zxth */, -{ "Re16 = Rs16 ; Rd16 = #-1" , "00110000sssseeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_setin1 */, -{ "Re16 = Rs16 ; Rd16 = memw ( Sp + #u5:2 )" , "01010000sssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_loadri_sp */, -{ "Re16 = Rs16 ; Rdd8 = combine ( #0 , #u2 )" , "00110000sssseeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_combine0i */, -{ "Re16 = Rs16 ; Rdd8 = combine ( #1 , #u2 )" , "00110000sssseeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_combine1i */, -{ "Re16 = Rs16 ; Rdd8 = combine ( #2 , #u2 )" , "00110000sssseeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_combine2i */, -{ "Re16 = Rs16 ; Rdd8 = combine ( #3 , #u2 )" , "00110000sssseeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_combine3i */, -{ "Re16 = Rs16 ; Rdd8 = memd ( Sp + #u5:3 )" , "01010000sssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_loadrd_sp */, -{ "Re16 = Rs16 ; if ( ! p0 ) Rd16 = #0" , "00110000sssseeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_clrf */, -{ "Re16 = Rs16 ; if ( ! p0 .new ) Rd16 = #0" , "00110000sssseeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_clrfnew */, -{ "Re16 = Rs16 ; if ( p0 ) Rd16 = #0" , "00110000sssseeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_clrt */, -{ "Re16 = Rs16 ; if ( p0 .new ) Rd16 = #0" , "00110000sssseeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_clrtnew */, -{ "Re16 = Ru16 ; Rd16 = Rs16" , "00110000uuuueeeeEE110000ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_tfr */, -{ "Re16 = Ru16 ; Rd16 = add ( Rs16 , #-1 )" , "00110000uuuueeeeEE110011ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_dec */, -{ "Re16 = Ru16 ; Rd16 = add ( Rs16 , #1 )" , "00110000uuuueeeeEE110001ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_inc */, -{ "Re16 = Ru16 ; Rd16 = and ( Rs16 , #1 )" , "00110000uuuueeeeEE110010ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_and1 */, -{ "Re16 = Ru16 ; Rd16 = and ( Rs16 , #255 )" , "00110000uuuueeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_zxtb */, -{ "Re16 = Ru16 ; Rd16 = memb ( Rs16 + #u3:0 )" , "01010000uuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_loadrb_io */, -{ "Re16 = Ru16 ; Rd16 = memh ( Rs16 + #u3:1 )" , "01010000uuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_loadrh_io */, -{ "Re16 = Ru16 ; Rd16 = memub ( Rs16 + #u4:0 )" , "01010000uuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL1_loadrub_io */, -{ "Re16 = Ru16 ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01010000uuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL2_loadruh_io */, -{ "Re16 = Ru16 ; Rd16 = memw ( Rs16 + #u4:2 )" , "01010000uuuueeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SL1_loadri_io */, -{ "Re16 = Ru16 ; Rd16 = sxtb ( Rs16 )" , "00110000uuuueeeeEE110101ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_sxtb */, -{ "Re16 = Ru16 ; Rd16 = sxth ( Rs16 )" , "00110000uuuueeeeEE110100ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_sxth */, -{ "Re16 = Ru16 ; Rd16 = zxth ( Rs16 )" , "00110000uuuueeeeEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_zxth */, -{ "Re16 = Ru16 ; Rdd8 = combine ( #0 , Rs16 )" , "00110000uuuueeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_combinezr */, -{ "Re16 = Ru16 ; Rdd8 = combine ( Rs16 , #0 )" , "00110000uuuueeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_tfr_SA1_combinerz */, -{ "Re16 = add ( Rs16 , #-1 ) ; Rd16 = #-1" , "00110011sssseeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_setin1 */, -{ "Re16 = add ( Rs16 , #-1 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01010011sssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_loadri_sp */, -{ "Re16 = add ( Rs16 , #-1 ) ; Rdd8 = combine ( #0 , #u2 )" , "00110011sssseeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_combine0i */, -{ "Re16 = add ( Rs16 , #-1 ) ; Rdd8 = combine ( #1 , #u2 )" , "00110011sssseeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_combine1i */, -{ "Re16 = add ( Rs16 , #-1 ) ; Rdd8 = combine ( #2 , #u2 )" , "00110011sssseeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_combine2i */, -{ "Re16 = add ( Rs16 , #-1 ) ; Rdd8 = combine ( #3 , #u2 )" , "00110011sssseeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_combine3i */, -{ "Re16 = add ( Rs16 , #-1 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01010011sssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_loadrd_sp */, -{ "Re16 = add ( Rs16 , #-1 ) ; if ( ! p0 ) Rd16 = #0" , "00110011sssseeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_clrf */, -{ "Re16 = add ( Rs16 , #-1 ) ; if ( ! p0 .new ) Rd16 = #0" , "00110011sssseeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_clrfnew */, -{ "Re16 = add ( Rs16 , #-1 ) ; if ( p0 ) Rd16 = #0" , "00110011sssseeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_clrt */, -{ "Re16 = add ( Rs16 , #-1 ) ; if ( p0 .new ) Rd16 = #0" , "00110011sssseeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_clrtnew */, -{ "Re16 = add ( Rs16 , #1 ) ; Rd16 = #-1" , "00110001sssseeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_setin1 */, -{ "Re16 = add ( Rs16 , #1 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01010001sssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_loadri_sp */, -{ "Re16 = add ( Rs16 , #1 ) ; Rdd8 = combine ( #0 , #u2 )" , "00110001sssseeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_combine0i */, -{ "Re16 = add ( Rs16 , #1 ) ; Rdd8 = combine ( #1 , #u2 )" , "00110001sssseeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_combine1i */, -{ "Re16 = add ( Rs16 , #1 ) ; Rdd8 = combine ( #2 , #u2 )" , "00110001sssseeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_combine2i */, -{ "Re16 = add ( Rs16 , #1 ) ; Rdd8 = combine ( #3 , #u2 )" , "00110001sssseeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_combine3i */, -{ "Re16 = add ( Rs16 , #1 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01010001sssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_loadrd_sp */, -{ "Re16 = add ( Rs16 , #1 ) ; if ( ! p0 ) Rd16 = #0" , "00110001sssseeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_clrf */, -{ "Re16 = add ( Rs16 , #1 ) ; if ( ! p0 .new ) Rd16 = #0" , "00110001sssseeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_clrfnew */, -{ "Re16 = add ( Rs16 , #1 ) ; if ( p0 ) Rd16 = #0" , "00110001sssseeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_clrt */, -{ "Re16 = add ( Rs16 , #1 ) ; if ( p0 .new ) Rd16 = #0" , "00110001sssseeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_clrtnew */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = add ( Rs16 , #-1 )" , "00110011uuuueeeeEE110011ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_dec */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = and ( Rs16 , #255 )" , "00110011uuuueeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_zxtb */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01010011uuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_loadrb_io */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01010011uuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_loadrh_io */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01010011uuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL1_loadrub_io */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01010011uuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL2_loadruh_io */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01010011uuuueeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SL1_loadri_io */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = sxtb ( Rs16 )" , "00110011uuuueeeeEE110101ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_sxtb */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = sxth ( Rs16 )" , "00110011uuuueeeeEE110100ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_sxth */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rd16 = zxth ( Rs16 )" , "00110011uuuueeeeEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_zxth */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00110011uuuueeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_combinezr */, -{ "Re16 = add ( Ru16 , #-1 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00110011uuuueeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_dec_SA1_combinerz */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = add ( Rs16 , #-1 )" , "00110001uuuueeeeEE110011ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_dec */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = add ( Rs16 , #1 )" , "00110001uuuueeeeEE110001ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_inc */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = and ( Rs16 , #1 )" , "00110001uuuueeeeEE110010ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_and1 */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = and ( Rs16 , #255 )" , "00110001uuuueeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_zxtb */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01010001uuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_loadrb_io */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01010001uuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_loadrh_io */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01010001uuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL1_loadrub_io */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01010001uuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL2_loadruh_io */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01010001uuuueeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SL1_loadri_io */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = sxtb ( Rs16 )" , "00110001uuuueeeeEE110101ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_sxtb */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = sxth ( Rs16 )" , "00110001uuuueeeeEE110100ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_sxth */, -{ "Re16 = add ( Ru16 , #1 ) ; Rd16 = zxth ( Rs16 )" , "00110001uuuueeeeEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_zxth */, -{ "Re16 = add ( Ru16 , #1 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00110001uuuueeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_combinezr */, -{ "Re16 = add ( Ru16 , #1 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00110001uuuueeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_inc_SA1_combinerz */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = #-1" , "001011IIIIIIeeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_setin1 */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = add ( Rs16 , #-1 )" , "001011IIIIIIeeeeEE110011ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_dec */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = add ( Rs16 , #1 )" , "001011IIIIIIeeeeEE110001ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_inc */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = add ( Sp , #u6:2 )" , "001011IIIIIIeeeeEE1011iiiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_addsp */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = and ( Rs16 , #1 )" , "001011IIIIIIeeeeEE110010ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_and1 */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = and ( Rs16 , #255 )" , "001011IIIIIIeeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_zxtb */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "010011IIIIIIeeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_loadrb_io */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "010011IIIIIIeeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_loadrh_io */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "010011IIIIIIeeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL1_loadrub_io */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "010011IIIIIIeeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_loadruh_io */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "010011IIIIIIeeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL1_loadri_io */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rd16 = memw ( Sp + #u5:2 )" , "010011IIIIIIeeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_loadri_sp */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rdd8 = combine ( #0 , #u2 )" , "001011IIIIIIeeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_combine0i */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rdd8 = combine ( #0 , Rs16 )" , "001011IIIIIIeeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_combinezr */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rdd8 = combine ( #1 , #u2 )" , "001011IIIIIIeeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_combine1i */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rdd8 = combine ( #2 , #u2 )" , "001011IIIIIIeeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_combine2i */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rdd8 = combine ( #3 , #u2 )" , "001011IIIIIIeeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_combine3i */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rdd8 = combine ( Rs16 , #0 )" , "001011IIIIIIeeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_combinerz */, -{ "Re16 = add ( Sp , #U6:2 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "010011IIIIIIeeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SL2_loadrd_sp */, -{ "Re16 = add ( Sp , #U6:2 ) ; if ( ! p0 ) Rd16 = #0" , "001011IIIIIIeeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_clrf */, -{ "Re16 = add ( Sp , #U6:2 ) ; if ( ! p0 .new ) Rd16 = #0" , "001011IIIIIIeeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_clrfnew */, -{ "Re16 = add ( Sp , #U6:2 ) ; if ( p0 ) Rd16 = #0" , "001011IIIIIIeeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_clrt */, -{ "Re16 = add ( Sp , #U6:2 ) ; if ( p0 .new ) Rd16 = #0" , "001011IIIIIIeeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_clrtnew */, -{ "Re16 = add ( Sp , #u6:2 ) ; Rd16 = Rs16" , "001011iiiiiieeeeEE110000ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_tfr */, -{ "Re16 = add ( Sp , #u6:2 ) ; Rd16 = sxtb ( Rs16 )" , "001011iiiiiieeeeEE110101ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_sxtb */, -{ "Re16 = add ( Sp , #u6:2 ) ; Rd16 = sxth ( Rs16 )" , "001011iiiiiieeeeEE110100ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_sxth */, -{ "Re16 = add ( Sp , #u6:2 ) ; Rd16 = zxth ( Rs16 )" , "001011iiiiiieeeeEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addsp_SA1_zxth */, -{ "Re16 = and ( Rs16 , #1 ) ; Rd16 = #-1" , "00110010sssseeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_setin1 */, -{ "Re16 = and ( Rs16 , #1 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01010010sssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_loadri_sp */, -{ "Re16 = and ( Rs16 , #1 ) ; Rdd8 = combine ( #0 , #u2 )" , "00110010sssseeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_combine0i */, -{ "Re16 = and ( Rs16 , #1 ) ; Rdd8 = combine ( #1 , #u2 )" , "00110010sssseeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_combine1i */, -{ "Re16 = and ( Rs16 , #1 ) ; Rdd8 = combine ( #2 , #u2 )" , "00110010sssseeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_combine2i */, -{ "Re16 = and ( Rs16 , #1 ) ; Rdd8 = combine ( #3 , #u2 )" , "00110010sssseeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_combine3i */, -{ "Re16 = and ( Rs16 , #1 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01010010sssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_loadrd_sp */, -{ "Re16 = and ( Rs16 , #1 ) ; if ( ! p0 ) Rd16 = #0" , "00110010sssseeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_clrf */, -{ "Re16 = and ( Rs16 , #1 ) ; if ( ! p0 .new ) Rd16 = #0" , "00110010sssseeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_clrfnew */, -{ "Re16 = and ( Rs16 , #1 ) ; if ( p0 ) Rd16 = #0" , "00110010sssseeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_clrt */, -{ "Re16 = and ( Rs16 , #1 ) ; if ( p0 .new ) Rd16 = #0" , "00110010sssseeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_clrtnew */, -{ "Re16 = and ( Rs16 , #255 ) ; Rd16 = #-1" , "00110111sssseeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_setin1 */, -{ "Re16 = and ( Rs16 , #255 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01010111sssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_loadri_sp */, -{ "Re16 = and ( Rs16 , #255 ) ; Rdd8 = combine ( #0 , #u2 )" , "00110111sssseeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_combine0i */, -{ "Re16 = and ( Rs16 , #255 ) ; Rdd8 = combine ( #1 , #u2 )" , "00110111sssseeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_combine1i */, -{ "Re16 = and ( Rs16 , #255 ) ; Rdd8 = combine ( #2 , #u2 )" , "00110111sssseeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_combine2i */, -{ "Re16 = and ( Rs16 , #255 ) ; Rdd8 = combine ( #3 , #u2 )" , "00110111sssseeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_combine3i */, -{ "Re16 = and ( Rs16 , #255 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01010111sssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_loadrd_sp */, -{ "Re16 = and ( Rs16 , #255 ) ; if ( ! p0 ) Rd16 = #0" , "00110111sssseeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_clrf */, -{ "Re16 = and ( Rs16 , #255 ) ; if ( ! p0 .new ) Rd16 = #0" , "00110111sssseeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_clrfnew */, -{ "Re16 = and ( Rs16 , #255 ) ; if ( p0 ) Rd16 = #0" , "00110111sssseeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_clrt */, -{ "Re16 = and ( Rs16 , #255 ) ; if ( p0 .new ) Rd16 = #0" , "00110111sssseeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_clrtnew */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = add ( Rs16 , #-1 )" , "00110010uuuueeeeEE110011ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_dec */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = and ( Rs16 , #1 )" , "00110010uuuueeeeEE110010ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_and1 */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = and ( Rs16 , #255 )" , "00110010uuuueeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_zxtb */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01010010uuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_loadrb_io */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01010010uuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_loadrh_io */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01010010uuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL1_loadrub_io */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01010010uuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL2_loadruh_io */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01010010uuuueeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SL1_loadri_io */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = sxtb ( Rs16 )" , "00110010uuuueeeeEE110101ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_sxtb */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = sxth ( Rs16 )" , "00110010uuuueeeeEE110100ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_sxth */, -{ "Re16 = and ( Ru16 , #1 ) ; Rd16 = zxth ( Rs16 )" , "00110010uuuueeeeEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_zxth */, -{ "Re16 = and ( Ru16 , #1 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00110010uuuueeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_combinezr */, -{ "Re16 = and ( Ru16 , #1 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00110010uuuueeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_and1_SA1_combinerz */, -{ "Re16 = and ( Ru16 , #255 ) ; Rd16 = and ( Rs16 , #255 )" , "00110111uuuueeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_zxtb */, -{ "Re16 = and ( Ru16 , #255 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01010111uuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_loadrb_io */, -{ "Re16 = and ( Ru16 , #255 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01010111uuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_loadrh_io */, -{ "Re16 = and ( Ru16 , #255 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01010111uuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL1_loadrub_io */, -{ "Re16 = and ( Ru16 , #255 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01010111uuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL2_loadruh_io */, -{ "Re16 = and ( Ru16 , #255 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01010111uuuueeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SL1_loadri_io */, -{ "Re16 = and ( Ru16 , #255 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00110111uuuueeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_combinezr */, -{ "Re16 = and ( Ru16 , #255 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00110111uuuueeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxtb_SA1_combinerz */, -{ "Re16 = memb ( Rs16 + #U3:0 ) ; Rd16 = memw ( Sp + #u5:2 )" , "00110IIIsssseeeeEE01110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_loadri_sp */, -{ "Re16 = memb ( Rs16 + #U3:0 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "00110IIIsssseeeeEE011110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_loadrd_sp */, -{ "Re16 = memb ( Ru16 + #U3:0 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "00110IIIuuuueeeeEE010iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrb_io_SL2_loadrb_io */, -{ "Re16 = memh ( Rs16 + #U3:1 ) ; Rd16 = memw ( Sp + #u5:2 )" , "00100IIIsssseeeeEE01110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_loadri_sp */, -{ "Re16 = memh ( Rs16 + #U3:1 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "00100IIIsssseeeeEE011110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_loadrd_sp */, -{ "Re16 = memh ( Ru16 + #U3:1 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "00100IIIuuuueeeeEE010iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_loadrb_io */, -{ "Re16 = memh ( Ru16 + #U3:1 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "00100IIIuuuueeeeEE000iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_loadrh_io */, -{ "Re16 = memh ( Ru16 + #U3:1 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "00100IIIuuuueeeeEE001iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrh_io_SL2_loadruh_io */, -{ "Re16 = memub ( Rs16 + #U4:0 ) ; Rd16 = memw ( Sp + #u5:2 )" , "0001IIIIsssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_loadri_sp */, -{ "Re16 = memub ( Rs16 + #U4:0 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "0001IIIIsssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_loadrd_sp */, -{ "Re16 = memub ( Ru16 + #U4:0 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "0001IIIIuuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_loadrb_io */, -{ "Re16 = memub ( Ru16 + #U4:0 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "0001IIIIuuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_loadrh_io */, -{ "Re16 = memub ( Ru16 + #U4:0 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "0001IIIIuuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL1_loadrub_io */, -{ "Re16 = memub ( Ru16 + #U4:0 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "0001IIIIuuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadrub_io_SL2_loadruh_io */, -{ "Re16 = memuh ( Rs16 + #U3:1 ) ; Rd16 = memw ( Sp + #u5:2 )" , "00101IIIsssseeeeEE01110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_loadri_sp */, -{ "Re16 = memuh ( Rs16 + #U3:1 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "00101IIIsssseeeeEE011110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_loadrd_sp */, -{ "Re16 = memuh ( Ru16 + #U3:1 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "00101IIIuuuueeeeEE010iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_loadrb_io */, -{ "Re16 = memuh ( Ru16 + #U3:1 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "00101IIIuuuueeeeEE001iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadruh_io_SL2_loadruh_io */, -{ "Re16 = memw ( Rs16 + #U4:2 ) ; Rd16 = memw ( Sp + #u5:2 )" , "0000IIIIsssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_loadri_sp */, -{ "Re16 = memw ( Rs16 + #U4:2 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "0000IIIIsssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_loadrd_sp */, -{ "Re16 = memw ( Ru16 + #U4:2 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "0000IIIIuuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_loadrb_io */, -{ "Re16 = memw ( Ru16 + #U4:2 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "0000IIIIuuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_loadrh_io */, -{ "Re16 = memw ( Ru16 + #U4:2 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "0000IIIIuuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL1_loadrub_io */, -{ "Re16 = memw ( Ru16 + #U4:2 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "0000IIIIuuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL2_loadruh_io */, -{ "Re16 = memw ( Ru16 + #U4:2 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "0000IIIIuuuueeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL1_loadri_io_SL1_loadri_io */, -{ "Re16 = memw ( Sp + #U5:2 ) ; Rd16 = memw ( Sp + #u5:2 )" , "0011110IIIIIeeeeEE01110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_loadri_sp */, -{ "Re16 = memw ( Sp + #U5:2 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "0011110IIIIIeeeeEE011110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadri_sp_SL2_loadrd_sp */, -{ "Re16 = sxtb ( Rs16 ) ; Rd16 = #-1" , "00110101sssseeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_setin1 */, -{ "Re16 = sxtb ( Rs16 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01010101sssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_loadri_sp */, -{ "Re16 = sxtb ( Rs16 ) ; Rdd8 = combine ( #0 , #u2 )" , "00110101sssseeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_combine0i */, -{ "Re16 = sxtb ( Rs16 ) ; Rdd8 = combine ( #1 , #u2 )" , "00110101sssseeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_combine1i */, -{ "Re16 = sxtb ( Rs16 ) ; Rdd8 = combine ( #2 , #u2 )" , "00110101sssseeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_combine2i */, -{ "Re16 = sxtb ( Rs16 ) ; Rdd8 = combine ( #3 , #u2 )" , "00110101sssseeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_combine3i */, -{ "Re16 = sxtb ( Rs16 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01010101sssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_loadrd_sp */, -{ "Re16 = sxtb ( Rs16 ) ; if ( ! p0 ) Rd16 = #0" , "00110101sssseeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_clrf */, -{ "Re16 = sxtb ( Rs16 ) ; if ( ! p0 .new ) Rd16 = #0" , "00110101sssseeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_clrfnew */, -{ "Re16 = sxtb ( Rs16 ) ; if ( p0 ) Rd16 = #0" , "00110101sssseeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_clrt */, -{ "Re16 = sxtb ( Rs16 ) ; if ( p0 .new ) Rd16 = #0" , "00110101sssseeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_clrtnew */, -{ "Re16 = sxtb ( Ru16 ) ; Rd16 = and ( Rs16 , #255 )" , "00110101uuuueeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_zxtb */, -{ "Re16 = sxtb ( Ru16 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01010101uuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_loadrb_io */, -{ "Re16 = sxtb ( Ru16 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01010101uuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_loadrh_io */, -{ "Re16 = sxtb ( Ru16 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01010101uuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL1_loadrub_io */, -{ "Re16 = sxtb ( Ru16 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01010101uuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL2_loadruh_io */, -{ "Re16 = sxtb ( Ru16 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01010101uuuueeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SL1_loadri_io */, -{ "Re16 = sxtb ( Ru16 ) ; Rd16 = sxtb ( Rs16 )" , "00110101uuuueeeeEE110101ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_sxtb */, -{ "Re16 = sxtb ( Ru16 ) ; Rd16 = zxth ( Rs16 )" , "00110101uuuueeeeEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_zxth */, -{ "Re16 = sxtb ( Ru16 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00110101uuuueeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_combinezr */, -{ "Re16 = sxtb ( Ru16 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00110101uuuueeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxtb_SA1_combinerz */, -{ "Re16 = sxth ( Rs16 ) ; Rd16 = #-1" , "00110100sssseeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_setin1 */, -{ "Re16 = sxth ( Rs16 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01010100sssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_loadri_sp */, -{ "Re16 = sxth ( Rs16 ) ; Rdd8 = combine ( #0 , #u2 )" , "00110100sssseeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_combine0i */, -{ "Re16 = sxth ( Rs16 ) ; Rdd8 = combine ( #1 , #u2 )" , "00110100sssseeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_combine1i */, -{ "Re16 = sxth ( Rs16 ) ; Rdd8 = combine ( #2 , #u2 )" , "00110100sssseeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_combine2i */, -{ "Re16 = sxth ( Rs16 ) ; Rdd8 = combine ( #3 , #u2 )" , "00110100sssseeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_combine3i */, -{ "Re16 = sxth ( Rs16 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01010100sssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_loadrd_sp */, -{ "Re16 = sxth ( Rs16 ) ; if ( ! p0 ) Rd16 = #0" , "00110100sssseeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_clrf */, -{ "Re16 = sxth ( Rs16 ) ; if ( ! p0 .new ) Rd16 = #0" , "00110100sssseeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_clrfnew */, -{ "Re16 = sxth ( Rs16 ) ; if ( p0 ) Rd16 = #0" , "00110100sssseeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_clrt */, -{ "Re16 = sxth ( Rs16 ) ; if ( p0 .new ) Rd16 = #0" , "00110100sssseeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_clrtnew */, -{ "Re16 = sxth ( Ru16 ) ; Rd16 = and ( Rs16 , #255 )" , "00110100uuuueeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_zxtb */, -{ "Re16 = sxth ( Ru16 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01010100uuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_loadrb_io */, -{ "Re16 = sxth ( Ru16 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01010100uuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_loadrh_io */, -{ "Re16 = sxth ( Ru16 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01010100uuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL1_loadrub_io */, -{ "Re16 = sxth ( Ru16 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01010100uuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL2_loadruh_io */, -{ "Re16 = sxth ( Ru16 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01010100uuuueeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SL1_loadri_io */, -{ "Re16 = sxth ( Ru16 ) ; Rd16 = sxtb ( Rs16 )" , "00110100uuuueeeeEE110101ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_sxtb */, -{ "Re16 = sxth ( Ru16 ) ; Rd16 = sxth ( Rs16 )" , "00110100uuuueeeeEE110100ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_sxth */, -{ "Re16 = sxth ( Ru16 ) ; Rd16 = zxth ( Rs16 )" , "00110100uuuueeeeEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_zxth */, -{ "Re16 = sxth ( Ru16 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00110100uuuueeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_combinezr */, -{ "Re16 = sxth ( Ru16 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00110100uuuueeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_sxth_SA1_combinerz */, -{ "Re16 = zxth ( Rs16 ) ; Rd16 = #-1" , "00110110sssseeeeEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_setin1 */, -{ "Re16 = zxth ( Rs16 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01010110sssseeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_loadri_sp */, -{ "Re16 = zxth ( Rs16 ) ; Rdd8 = combine ( #0 , #u2 )" , "00110110sssseeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_combine0i */, -{ "Re16 = zxth ( Rs16 ) ; Rdd8 = combine ( #1 , #u2 )" , "00110110sssseeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_combine1i */, -{ "Re16 = zxth ( Rs16 ) ; Rdd8 = combine ( #2 , #u2 )" , "00110110sssseeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_combine2i */, -{ "Re16 = zxth ( Rs16 ) ; Rdd8 = combine ( #3 , #u2 )" , "00110110sssseeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_combine3i */, -{ "Re16 = zxth ( Rs16 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01010110sssseeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_loadrd_sp */, -{ "Re16 = zxth ( Rs16 ) ; if ( ! p0 ) Rd16 = #0" , "00110110sssseeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_clrf */, -{ "Re16 = zxth ( Rs16 ) ; if ( ! p0 .new ) Rd16 = #0" , "00110110sssseeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_clrfnew */, -{ "Re16 = zxth ( Rs16 ) ; if ( p0 ) Rd16 = #0" , "00110110sssseeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_clrt */, -{ "Re16 = zxth ( Rs16 ) ; if ( p0 .new ) Rd16 = #0" , "00110110sssseeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_clrtnew */, -{ "Re16 = zxth ( Ru16 ) ; Rd16 = and ( Rs16 , #255 )" , "00110110uuuueeeeEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_zxtb */, -{ "Re16 = zxth ( Ru16 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01010110uuuueeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_loadrb_io */, -{ "Re16 = zxth ( Ru16 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01010110uuuueeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_loadrh_io */, -{ "Re16 = zxth ( Ru16 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01010110uuuueeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL1_loadrub_io */, -{ "Re16 = zxth ( Ru16 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01010110uuuueeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL2_loadruh_io */, -{ "Re16 = zxth ( Ru16 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01010110uuuueeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SL1_loadri_io */, -{ "Re16 = zxth ( Ru16 ) ; Rd16 = zxth ( Rs16 )" , "00110110uuuueeeeEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_zxth */, -{ "Re16 = zxth ( Ru16 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00110110uuuueeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_combinezr */, -{ "Re16 = zxth ( Ru16 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00110110uuuueeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_zxth_SA1_combinerz */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "010111-0-II00eeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_loadrb_io */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "010111-0-II00eeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_loadrh_io */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "010111-0-II00eeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL1_loadrub_io */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "010111-0-II00eeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_loadruh_io */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "010111-0-II00eeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL1_loadri_io */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rd16 = memw ( Sp + #u5:2 )" , "010111-0-II00eeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_loadri_sp */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rdd8 = combine ( #0 , #u2 )" , "001111-0-II00eeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SA1_combine0i */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rdd8 = combine ( #0 , Rs16 )" , "001111-0-II00eeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SA1_combinezr */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rdd8 = combine ( #1 , #u2 )" , "001111-0-II00eeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SA1_combine1i */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rdd8 = combine ( #2 , #u2 )" , "001111-0-II00eeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SA1_combine2i */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rdd8 = combine ( #3 , #u2 )" , "001111-0-II00eeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SA1_combine3i */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rdd8 = combine ( Rs16 , #0 )" , "001111-0-II00eeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SA1_combinerz */, -{ "Ree8 = combine ( #0 , #U2 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "010111-0-II00eeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine0i_SL2_loadrd_sp */, -{ "Ree8 = combine ( #0 , Rs16 ) ; Rd16 = memw ( Sp + #u5:2 )" , "010111-1ssss0eeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_loadri_sp */, -{ "Ree8 = combine ( #0 , Rs16 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "010111-1ssss0eeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_loadrd_sp */, -{ "Ree8 = combine ( #0 , Ru16 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "010111-1uuuu0eeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_loadrb_io */, -{ "Ree8 = combine ( #0 , Ru16 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "010111-1uuuu0eeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_loadrh_io */, -{ "Ree8 = combine ( #0 , Ru16 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "010111-1uuuu0eeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL1_loadrub_io */, -{ "Ree8 = combine ( #0 , Ru16 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "010111-1uuuu0eeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL2_loadruh_io */, -{ "Ree8 = combine ( #0 , Ru16 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "010111-1uuuu0eeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SL1_loadri_io */, -{ "Ree8 = combine ( #0 , Ru16 ) ; Rdd8 = combine ( #0 , Rs16 )" , "001111-1uuuu0eeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SA1_combinezr */, -{ "Ree8 = combine ( #0 , Ru16 ) ; Rdd8 = combine ( Rs16 , #0 )" , "001111-1uuuu0eeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinezr_SA1_combinerz */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "010111-0-II01eeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_loadrb_io */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "010111-0-II01eeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_loadrh_io */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "010111-0-II01eeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL1_loadrub_io */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "010111-0-II01eeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_loadruh_io */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "010111-0-II01eeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL1_loadri_io */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rd16 = memw ( Sp + #u5:2 )" , "010111-0-II01eeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_loadri_sp */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rdd8 = combine ( #0 , Rs16 )" , "001111-0-II01eeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SA1_combinezr */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rdd8 = combine ( #1 , #u2 )" , "001111-0-II01eeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SA1_combine1i */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rdd8 = combine ( #2 , #u2 )" , "001111-0-II01eeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SA1_combine2i */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rdd8 = combine ( #3 , #u2 )" , "001111-0-II01eeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SA1_combine3i */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rdd8 = combine ( Rs16 , #0 )" , "001111-0-II01eeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SA1_combinerz */, -{ "Ree8 = combine ( #1 , #U2 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "010111-0-II01eeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine1i_SL2_loadrd_sp */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "010111-0-II10eeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_loadrb_io */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "010111-0-II10eeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_loadrh_io */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "010111-0-II10eeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL1_loadrub_io */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "010111-0-II10eeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_loadruh_io */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "010111-0-II10eeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL1_loadri_io */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rd16 = memw ( Sp + #u5:2 )" , "010111-0-II10eeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_loadri_sp */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rdd8 = combine ( #0 , Rs16 )" , "001111-0-II10eeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SA1_combinezr */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rdd8 = combine ( #2 , #u2 )" , "001111-0-II10eeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SA1_combine2i */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rdd8 = combine ( #3 , #u2 )" , "001111-0-II10eeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SA1_combine3i */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rdd8 = combine ( Rs16 , #0 )" , "001111-0-II10eeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SA1_combinerz */, -{ "Ree8 = combine ( #2 , #U2 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "010111-0-II10eeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine2i_SL2_loadrd_sp */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "010111-0-II11eeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_loadrb_io */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "010111-0-II11eeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_loadrh_io */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "010111-0-II11eeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL1_loadrub_io */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "010111-0-II11eeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_loadruh_io */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "010111-0-II11eeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL1_loadri_io */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rd16 = memw ( Sp + #u5:2 )" , "010111-0-II11eeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_loadri_sp */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rdd8 = combine ( #0 , Rs16 )" , "001111-0-II11eeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SA1_combinezr */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rdd8 = combine ( #3 , #u2 )" , "001111-0-II11eeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SA1_combine3i */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rdd8 = combine ( Rs16 , #0 )" , "001111-0-II11eeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SA1_combinerz */, -{ "Ree8 = combine ( #3 , #U2 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "010111-0-II11eeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combine3i_SL2_loadrd_sp */, -{ "Ree8 = combine ( Rs16 , #0 ) ; Rd16 = memw ( Sp + #u5:2 )" , "010111-1ssss1eeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_loadri_sp */, -{ "Ree8 = combine ( Rs16 , #0 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "010111-1ssss1eeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_loadrd_sp */, -{ "Ree8 = combine ( Ru16 , #0 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "010111-1uuuu1eeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_loadrb_io */, -{ "Ree8 = combine ( Ru16 , #0 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "010111-1uuuu1eeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_loadrh_io */, -{ "Ree8 = combine ( Ru16 , #0 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "010111-1uuuu1eeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL1_loadrub_io */, -{ "Ree8 = combine ( Ru16 , #0 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "010111-1uuuu1eeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL2_loadruh_io */, -{ "Ree8 = combine ( Ru16 , #0 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "010111-1uuuu1eeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SL1_loadri_io */, -{ "Ree8 = combine ( Ru16 , #0 ) ; Rdd8 = combine ( Rs16 , #0 )" , "001111-1uuuu1eeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ROPS_2|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_combinerz_SA1_combinerz */, -{ "Ree8 = memd ( Sp + #U5:3 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "00111110IIIIIeeeEE011110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_loadrd_sp_SL2_loadrd_sp */, -{ "Rx32.h = #u16" , "0111 0010 ii1xxxxx PPiiiiii iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_tfrih */, -{ "Rx32.l = #u16" , "0111 0001 ii1xxxxx PPiiiiii iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, NULL} /* A2_tfril */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; Rd16 = #-1" , "00111000ssssxxxxEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_setin1 */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01011000ssssxxxxEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_loadri_sp */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; Rdd8 = combine ( #0 , #u2 )" , "00111000ssssxxxxEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_combine0i */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; Rdd8 = combine ( #1 , #u2 )" , "00111000ssssxxxxEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_combine1i */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; Rdd8 = combine ( #2 , #u2 )" , "00111000ssssxxxxEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_combine2i */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; Rdd8 = combine ( #3 , #u2 )" , "00111000ssssxxxxEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_combine3i */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01011000ssssxxxxEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_loadrd_sp */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; allocframe ( #u5:3 )" , "01111000ssssxxxxEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_COMMUTES|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS2_allocframe */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; dealloc_return" , "01011000ssssxxxxEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_return */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; deallocframe" , "01011000ssssxxxxEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_COMMUTES|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_deallocframe */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( ! p0 ) Rd16 = #0" , "00111000ssssxxxxEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_clrf */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( ! p0 ) dealloc_return" , "01011000ssssxxxxEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_return_f */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( ! p0 ) jumpr Lr" , "01011000ssssxxxxEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_jumpr31_f */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( ! p0 .new ) Rd16 = #0" , "00111000ssssxxxxEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_clrfnew */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01011000ssssxxxxEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_return_fnew */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01011000ssssxxxxEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_jumpr31_fnew */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( p0 ) Rd16 = #0" , "00111000ssssxxxxEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_clrt */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( p0 ) dealloc_return" , "01011000ssssxxxxEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_return_t */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( p0 ) jumpr Lr" , "01011000ssssxxxxEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_jumpr31_t */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( p0 .new ) Rd16 = #0" , "00111000ssssxxxxEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_clrtnew */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( p0 .new ) dealloc_return:nt" , "01011000ssssxxxxEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_return_tnew */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; if ( p0 .new ) jumpr:nt Lr" , "01011000ssssxxxxEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_jumpr31_tnew */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; jumpr Lr" , "01011000ssssxxxxEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_jumpr31 */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01111000ssssxxxxEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS2_stored_sp */, -{ "Rx16 = add ( Rs16 , Rx16 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01111000ssssxxxxEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS2_storew_sp */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01011000uuuuxxxxEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_loadrb_io */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01011000uuuuxxxxEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_loadrh_io */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01011000uuuuxxxxEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL1_loadrub_io */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01011000uuuuxxxxEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL2_loadruh_io */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01011000uuuuxxxxEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SL1_loadri_io */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00111000uuuuxxxxEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_combinezr */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00111000uuuuxxxxEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_combinerz */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01111000uuuuxxxxEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS2_storebi0 */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01111000uuuuxxxxEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS2_storebi1 */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01111000uuuuxxxxEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS1_storeb_io */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01111000uuuuxxxxEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS2_storeh_io */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01111000uuuuxxxxEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS2_storewi0 */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01111000uuuuxxxxEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS2_storewi1 */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01111000uuuuxxxxEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SS1_storew_io */, -{ "Rx16 = add ( Ru16 , Rx16 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00111000uuuuxxxxEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_COMMUTES|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_cmpeqi */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = #-1" , "00100IIIIIIIxxxxEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_setin1 */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = #u6" , "00100IIIIIIIxxxxEE1010iiiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_seti */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = add ( Rs16 , #-1 )" , "00100IIIIIIIxxxxEE110011ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_dec */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = add ( Rs16 , #1 )" , "00100IIIIIIIxxxxEE110001ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_inc */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = add ( Sp , #u6:2 )" , "00100IIIIIIIxxxxEE1011iiiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_addsp */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = and ( Rs16 , #1 )" , "00100IIIIIIIxxxxEE110010ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_and1 */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = and ( Rs16 , #255 )" , "00100IIIIIIIxxxxEE110111ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_zxtb */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01000IIIIIIIxxxxEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_loadrb_io */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01000IIIIIIIxxxxEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_loadrh_io */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01000IIIIIIIxxxxEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL1_loadrub_io */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01000IIIIIIIxxxxEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_loadruh_io */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01000IIIIIIIxxxxEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL1_loadri_io */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01000IIIIIIIxxxxEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_loadri_sp */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rdd8 = combine ( #0 , #u2 )" , "00100IIIIIIIxxxxEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_combine0i */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00100IIIIIIIxxxxEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_combinezr */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rdd8 = combine ( #1 , #u2 )" , "00100IIIIIIIxxxxEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_combine1i */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rdd8 = combine ( #2 , #u2 )" , "00100IIIIIIIxxxxEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_combine2i */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rdd8 = combine ( #3 , #u2 )" , "00100IIIIIIIxxxxEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_combine3i */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00100IIIIIIIxxxxEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_ROPS_2|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_combinerz */, -{ "Rx16 = add ( Rx16 , #S7 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01000IIIIIIIxxxxEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_loadrd_sp */, -{ "Rx16 = add ( Rx16 , #S7 ) ; allocframe ( #u5:3 )" , "01100IIIIIIIxxxxEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS2_allocframe */, -{ "Rx16 = add ( Rx16 , #S7 ) ; if ( ! p0 ) Rd16 = #0" , "00100IIIIIIIxxxxEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_clrf */, -{ "Rx16 = add ( Rx16 , #S7 ) ; if ( ! p0 .new ) Rd16 = #0" , "00100IIIIIIIxxxxEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_clrfnew */, -{ "Rx16 = add ( Rx16 , #S7 ) ; if ( p0 ) Rd16 = #0" , "00100IIIIIIIxxxxEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_clrt */, -{ "Rx16 = add ( Rx16 , #S7 ) ; if ( p0 .new ) Rd16 = #0" , "00100IIIIIIIxxxxEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_clrtnew */, -{ "Rx16 = add ( Rx16 , #S7 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01100IIIIIIIxxxxEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS2_storebi0 */, -{ "Rx16 = add ( Rx16 , #S7 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01100IIIIIIIxxxxEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS2_storebi1 */, -{ "Rx16 = add ( Rx16 , #S7 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01100IIIIIIIxxxxEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS1_storeb_io */, -{ "Rx16 = add ( Rx16 , #S7 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01100IIIIIIIxxxxEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS2_stored_sp */, -{ "Rx16 = add ( Rx16 , #S7 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01100IIIIIIIxxxxEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS2_storeh_io */, -{ "Rx16 = add ( Rx16 , #S7 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01100IIIIIIIxxxxEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS2_storewi0 */, -{ "Rx16 = add ( Rx16 , #S7 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01100IIIIIIIxxxxEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS2_storewi1 */, -{ "Rx16 = add ( Rx16 , #S7 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01100IIIIIIIxxxxEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS1_storew_io */, -{ "Rx16 = add ( Rx16 , #S7 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01100IIIIIIIxxxxEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SS2_storew_sp */, -{ "Rx16 = add ( Rx16 , #S7 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00100IIIIIIIxxxxEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_IMPLICIT_WRITES_P0|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_cmpeqi */, -{ "Rx16 = add ( Rx16 , #s7 ) ; Rd16 = Rs16" , "00100iiiiiiixxxxEE110000ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_tfr */, -{ "Rx16 = add ( Rx16 , #s7 ) ; Rd16 = sxtb ( Rs16 )" , "00100iiiiiiixxxxEE110101ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_sxtb */, -{ "Rx16 = add ( Rx16 , #s7 ) ; Rd16 = sxth ( Rs16 )" , "00100iiiiiiixxxxEE110100ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_sxth */, -{ "Rx16 = add ( Rx16 , #s7 ) ; Rd16 = zxth ( Rs16 )" , "00100iiiiiiixxxxEE110110ssssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_zxth */, -{ "Rx16 = add ( Rx16 , #s7 ) ; dealloc_return" , "01000iiiiiiixxxxEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_return */, -{ "Rx16 = add ( Rx16 , #s7 ) ; deallocframe" , "01000iiiiiiixxxxEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_deallocframe */, -{ "Rx16 = add ( Rx16 , #s7 ) ; if ( ! p0 ) dealloc_return" , "01000iiiiiiixxxxEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_return_f */, -{ "Rx16 = add ( Rx16 , #s7 ) ; if ( ! p0 ) jumpr Lr" , "01000iiiiiiixxxxEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_jumpr31_f */, -{ "Rx16 = add ( Rx16 , #s7 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01000iiiiiiixxxxEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_return_fnew */, -{ "Rx16 = add ( Rx16 , #s7 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01000iiiiiiixxxxEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_jumpr31_fnew */, -{ "Rx16 = add ( Rx16 , #s7 ) ; if ( p0 ) dealloc_return" , "01000iiiiiiixxxxEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_return_t */, -{ "Rx16 = add ( Rx16 , #s7 ) ; if ( p0 ) jumpr Lr" , "01000iiiiiiixxxxEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_jumpr31_t */, -{ "Rx16 = add ( Rx16 , #s7 ) ; if ( p0 .new ) dealloc_return:nt" , "01000iiiiiiixxxxEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_return_tnew */, -{ "Rx16 = add ( Rx16 , #s7 ) ; if ( p0 .new ) jumpr:nt Lr" , "01000iiiiiiixxxxEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_jumpr31_tnew */, -{ "Rx16 = add ( Rx16 , #s7 ) ; jumpr Lr" , "01000iiiiiiixxxxEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SL2_jumpr31 */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; Rd16 = #-1" , "00111000ssssxxxxEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_setin1 */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01011000ssssxxxxEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_loadri_sp */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; Rdd8 = combine ( #0 , #u2 )" , "00111000ssssxxxxEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_combine0i */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; Rdd8 = combine ( #1 , #u2 )" , "00111000ssssxxxxEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_combine1i */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; Rdd8 = combine ( #2 , #u2 )" , "00111000ssssxxxxEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_combine2i */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; Rdd8 = combine ( #3 , #u2 )" , "00111000ssssxxxxEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_combine3i */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01011000ssssxxxxEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_loadrd_sp */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; allocframe ( #u5:3 )" , "01111000ssssxxxxEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_COMMUTES|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS2_allocframe */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; dealloc_return" , "01011000ssssxxxxEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_return */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; deallocframe" , "01011000ssssxxxxEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_COMMUTES|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_deallocframe */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( ! p0 ) Rd16 = #0" , "00111000ssssxxxxEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_clrf */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( ! p0 ) dealloc_return" , "01011000ssssxxxxEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_return_f */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( ! p0 ) jumpr Lr" , "01011000ssssxxxxEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_jumpr31_f */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( ! p0 .new ) Rd16 = #0" , "00111000ssssxxxxEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_clrfnew */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01011000ssssxxxxEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_return_fnew */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01011000ssssxxxxEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_jumpr31_fnew */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( p0 ) Rd16 = #0" , "00111000ssssxxxxEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_clrt */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( p0 ) dealloc_return" , "01011000ssssxxxxEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_return_t */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( p0 ) jumpr Lr" , "01011000ssssxxxxEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_jumpr31_t */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( p0 .new ) Rd16 = #0" , "00111000ssssxxxxEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_clrtnew */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( p0 .new ) dealloc_return:nt" , "01011000ssssxxxxEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_return_tnew */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; if ( p0 .new ) jumpr:nt Lr" , "01011000ssssxxxxEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_jumpr31_tnew */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; jumpr Lr" , "01011000ssssxxxxEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_COMMUTES|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_jumpr31 */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01111000ssssxxxxEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS2_stored_sp */, -{ "Rx16 = add ( Rx16 , Rs16 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01111000ssssxxxxEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS2_storew_sp */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01011000uuuuxxxxEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_loadrb_io */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01011000uuuuxxxxEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_loadrh_io */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01011000uuuuxxxxEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL1_loadrub_io */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01011000uuuuxxxxEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL2_loadruh_io */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01011000uuuuxxxxEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SL1_loadri_io */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00111000uuuuxxxxEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_combinezr */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00111000uuuuxxxxEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_combinerz */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01111000uuuuxxxxEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS2_storebi0 */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01111000uuuuxxxxEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS2_storebi1 */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01111000uuuuxxxxEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS1_storeb_io */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01111000uuuuxxxxEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS2_storeh_io */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01111000uuuuxxxxEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS2_storewi0 */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01111000uuuuxxxxEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS2_storewi1 */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01111000uuuuxxxxEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SS1_storew_io */, -{ "Rx16 = add ( Rx16 , Ru16 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00111000uuuuxxxxEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_COMMUTES|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_cmpeqi */, -{ "Rx32 &= and ( Rs32 , Rt32 )" , "11101111010sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_and_and */, -{ "Rx32 &= and ( Rs32 , ~ Rt32 )" , "11101111001sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_and_andn */, -{ "Rx32 &= asl ( Rs32 , #u5 )" , "1000 1110 01-sssss PP0iiiii 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asl_i_r_and */, -{ "Rx32 &= asl ( Rs32 , Rt32 )" , "1100 1100 01-sssss PP-ttttt 10-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_asl_r_r_and */, -{ "Rx32 &= asr ( Rs32 , #u5 )" , "1000 1110 01-sssss PP0iiiii 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asr_i_r_and */, -{ "Rx32 &= asr ( Rs32 , Rt32 )" , "1100 1100 01-sssss PP-ttttt 00-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_r_and */, -{ "Rx32 &= lsl ( Rs32 , Rt32 )" , "1100 1100 01-sssss PP-ttttt 11-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_r_and */, -{ "Rx32 &= lsr ( Rs32 , #u5 )" , "1000 1110 01-sssss PP0iiiii 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_lsr_i_r_and */, -{ "Rx32 &= lsr ( Rs32 , Rt32 )" , "1100 1100 01-sssss PP-ttttt 01-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_r_and */, -{ "Rx32 &= or ( Rs32 , Rt32 )" , "11101111010sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_and_or */, -{ "Rx32 &= xor ( Rs32 , Rt32 )" , "11101111010sssss PP0ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_and_xor */, -{ "Rx32 += add ( Rs32 , #s8 )" , "111000100--sssss PP0iiiii iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* M2_accii */, -{ "Rx32 += add ( Rs32 , Rt32 )" , "11101111000sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_ARCHV2, NULL} /* M2_acci */, -{ "Rx32 += asl ( Rs32 , #u5 )" , "1000 1110 00-sssss PP0iiiii 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asl_i_r_acc */, -{ "Rx32 += asl ( Rs32 , Rt32 )" , "1100 1100 11-sssss PP-ttttt 10-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_asl_r_r_acc */, -{ "Rx32 += asr ( Rs32 , #u5 )" , "1000 1110 00-sssss PP0iiiii 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asr_i_r_acc */, -{ "Rx32 += asr ( Rs32 , Rt32 )" , "1100 1100 11-sssss PP-ttttt 00-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_r_acc */, -{ "Rx32 += lsl ( Rs32 , Rt32 )" , "1100 1100 11-sssss PP-ttttt 11-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_r_acc */, -{ "Rx32 += lsr ( Rs32 , #u5 )" , "1000 1110 00-sssss PP0iiiii 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_lsr_i_r_acc */, -{ "Rx32 += lsr ( Rs32 , Rt32 )" , "1100 1100 11-sssss PP-ttttt 01-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_r_acc */, -{ "Rx32 += mpy ( Rs32.h , Rt32.h ) :<<1 :sat" , "11101110100sssss PP-ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_acc_sat_hh_s1 */, -{ "Rx32 += mpy ( Rs32.h , Rt32.h ) :<<1" , "11101110100sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_acc_hh_s1 */, -{ "Rx32 += mpy ( Rs32.h , Rt32.h ) :sat" , "11101110000sssss PP-ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_acc_sat_hh_s0 */, -{ "Rx32 += mpy ( Rs32.h , Rt32.h )" , "11101110000sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_acc_hh_s0 */, -{ "Rx32 += mpy ( Rs32.h , Rt32.l ) :<<1 :sat" , "11101110100sssss PP-ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_acc_sat_hl_s1 */, -{ "Rx32 += mpy ( Rs32.h , Rt32.l ) :<<1" , "11101110100sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_acc_hl_s1 */, -{ "Rx32 += mpy ( Rs32.h , Rt32.l ) :sat" , "11101110000sssss PP-ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_acc_sat_hl_s0 */, -{ "Rx32 += mpy ( Rs32.h , Rt32.l )" , "11101110000sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_acc_hl_s0 */, -{ "Rx32 += mpy ( Rs32.l , Rt32.h ) :<<1 :sat" , "11101110100sssss PP-ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_acc_sat_lh_s1 */, -{ "Rx32 += mpy ( Rs32.l , Rt32.h ) :<<1" , "11101110100sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_acc_lh_s1 */, -{ "Rx32 += mpy ( Rs32.l , Rt32.h ) :sat" , "11101110000sssss PP-ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_acc_sat_lh_s0 */, -{ "Rx32 += mpy ( Rs32.l , Rt32.h )" , "11101110000sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_acc_lh_s0 */, -{ "Rx32 += mpy ( Rs32.l , Rt32.l ) :<<1 :sat" , "11101110100sssss PP-ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_acc_sat_ll_s1 */, -{ "Rx32 += mpy ( Rs32.l , Rt32.l ) :<<1" , "11101110100sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_acc_ll_s1 */, -{ "Rx32 += mpy ( Rs32.l , Rt32.l ) :sat" , "11101110000sssss PP-ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_acc_sat_ll_s0 */, -{ "Rx32 += mpy ( Rs32.l , Rt32.l )" , "11101110000sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_acc_ll_s0 */, -{ "Rx32 += mpy ( Rs32 , Rt32 ) :<<1 :sat" , "11101111011sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_IT_MPY|A_IT_MPY_32|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M4_mac_up_s1_sat */, -{ "Rx32 += mpyi ( Rs32 , #u8 )" , "111000010--sssss PP0iiiii iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_ROPS_2|A_MPY|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* M2_macsip */, -{ "Rx32 += mpyi ( Rs32 , Rt32 )" , "11101111000sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32|A_ARCHV2|A_ROPS_2|A_MPY, NULL} /* M2_maci */, -{ "Rx32 += mpyu ( Rs32.h , Rt32.h ) :<<1" , "11101110110sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_acc_hh_s1 */, -{ "Rx32 += mpyu ( Rs32.h , Rt32.h )" , "11101110010sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_acc_hh_s0 */, -{ "Rx32 += mpyu ( Rs32.h , Rt32.l ) :<<1" , "11101110110sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_acc_hl_s1 */, -{ "Rx32 += mpyu ( Rs32.h , Rt32.l )" , "11101110010sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_acc_hl_s0 */, -{ "Rx32 += mpyu ( Rs32.l , Rt32.h ) :<<1" , "11101110110sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_acc_lh_s1 */, -{ "Rx32 += mpyu ( Rs32.l , Rt32.h )" , "11101110010sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_acc_lh_s0 */, -{ "Rx32 += mpyu ( Rs32.l , Rt32.l ) :<<1" , "11101110110sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_acc_ll_s1 */, -{ "Rx32 += mpyu ( Rs32.l , Rt32.l )" , "11101110010sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_acc_ll_s0 */, -{ "Rx32 += sfmpy ( Rs32 , Rt32 ) :lib" , "11101111000sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE|A_CONDEXEC, NULL} /* F2_sffma_lib */, -{ "Rx32 += sfmpy ( Rs32 , Rt32 )" , "11101111000sssss PP0ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sffma */, -{ "Rx32 += sfmpy ( Rs32 , Rt32 , Pu4 ) :scale" , "11101111011sssss PP0ttttt 1uuxxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sffma_sc */, -{ "Rx32 += sub ( Rt32 , Rs32 )" , "11101111000sssss PP0ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_ARCHV2, NULL} /* M2_subacc */, -{ "Rx32 -= add ( Rs32 , #s8 )" , "111000101--sssss PP0iiiii iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* M2_naccii */, -{ "Rx32 -= add ( Rs32 , Rt32 )" , "11101111100sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_ARCHV2, NULL} /* M2_nacci */, -{ "Rx32 -= asl ( Rs32 , #u5 )" , "1000 1110 00-sssss PP0iiiii 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asl_i_r_nac */, -{ "Rx32 -= asl ( Rs32 , Rt32 )" , "1100 1100 10-sssss PP-ttttt 10-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_asl_r_r_nac */, -{ "Rx32 -= asr ( Rs32 , #u5 )" , "1000 1110 00-sssss PP0iiiii 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asr_i_r_nac */, -{ "Rx32 -= asr ( Rs32 , Rt32 )" , "1100 1100 10-sssss PP-ttttt 00-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_r_nac */, -{ "Rx32 -= lsl ( Rs32 , Rt32 )" , "1100 1100 10-sssss PP-ttttt 11-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_r_nac */, -{ "Rx32 -= lsr ( Rs32 , #u5 )" , "1000 1110 00-sssss PP0iiiii 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_lsr_i_r_nac */, -{ "Rx32 -= lsr ( Rs32 , Rt32 )" , "1100 1100 10-sssss PP-ttttt 01-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_r_nac */, -{ "Rx32 -= mpy ( Rs32.h , Rt32.h ) :<<1 :sat" , "11101110101sssss PP-ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_nac_sat_hh_s1 */, -{ "Rx32 -= mpy ( Rs32.h , Rt32.h ) :<<1" , "11101110101sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_nac_hh_s1 */, -{ "Rx32 -= mpy ( Rs32.h , Rt32.h ) :sat" , "11101110001sssss PP-ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_nac_sat_hh_s0 */, -{ "Rx32 -= mpy ( Rs32.h , Rt32.h )" , "11101110001sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_nac_hh_s0 */, -{ "Rx32 -= mpy ( Rs32.h , Rt32.l ) :<<1 :sat" , "11101110101sssss PP-ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_nac_sat_hl_s1 */, -{ "Rx32 -= mpy ( Rs32.h , Rt32.l ) :<<1" , "11101110101sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_nac_hl_s1 */, -{ "Rx32 -= mpy ( Rs32.h , Rt32.l ) :sat" , "11101110001sssss PP-ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_nac_sat_hl_s0 */, -{ "Rx32 -= mpy ( Rs32.h , Rt32.l )" , "11101110001sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_nac_hl_s0 */, -{ "Rx32 -= mpy ( Rs32.l , Rt32.h ) :<<1 :sat" , "11101110101sssss PP-ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_nac_sat_lh_s1 */, -{ "Rx32 -= mpy ( Rs32.l , Rt32.h ) :<<1" , "11101110101sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_nac_lh_s1 */, -{ "Rx32 -= mpy ( Rs32.l , Rt32.h ) :sat" , "11101110001sssss PP-ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_nac_sat_lh_s0 */, -{ "Rx32 -= mpy ( Rs32.l , Rt32.h )" , "11101110001sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_nac_lh_s0 */, -{ "Rx32 -= mpy ( Rs32.l , Rt32.l ) :<<1 :sat" , "11101110101sssss PP-ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_nac_sat_ll_s1 */, -{ "Rx32 -= mpy ( Rs32.l , Rt32.l ) :<<1" , "11101110101sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_nac_ll_s1 */, -{ "Rx32 -= mpy ( Rs32.l , Rt32.l ) :sat" , "11101110001sssss PP-ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mpy_nac_sat_ll_s0 */, -{ "Rx32 -= mpy ( Rs32.l , Rt32.l )" , "11101110001sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpy_nac_ll_s0 */, -{ "Rx32 -= mpy ( Rs32 , Rt32 ) :<<1 :sat" , "11101111011sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_IT_MPY|A_IT_MPY_32|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M4_nac_up_s1_sat */, -{ "Rx32 -= mpyi ( Rs32 , #u8 )" , "111000011--sssss PP0iiiii iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_ROPS_2|A_MPY|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* M2_macsin */, -{ "Rx32 -= mpyu ( Rs32.h , Rt32.h ) :<<1" , "11101110111sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_nac_hh_s1 */, -{ "Rx32 -= mpyu ( Rs32.h , Rt32.h )" , "11101110011sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_nac_hh_s0 */, -{ "Rx32 -= mpyu ( Rs32.h , Rt32.l ) :<<1" , "11101110111sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_nac_hl_s1 */, -{ "Rx32 -= mpyu ( Rs32.h , Rt32.l )" , "11101110011sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_nac_hl_s0 */, -{ "Rx32 -= mpyu ( Rs32.l , Rt32.h ) :<<1" , "11101110111sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_nac_lh_s1 */, -{ "Rx32 -= mpyu ( Rs32.l , Rt32.h )" , "11101110011sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_nac_lh_s0 */, -{ "Rx32 -= mpyu ( Rs32.l , Rt32.l ) :<<1" , "11101110111sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_nac_ll_s1 */, -{ "Rx32 -= mpyu ( Rs32.l , Rt32.l )" , "11101110011sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyu_nac_ll_s0 */, -{ "Rx32 -= sfmpy ( Rs32 , Rt32 ) :lib" , "11101111000sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE|A_CONDEXEC, NULL} /* F2_sffms_lib */, -{ "Rx32 -= sfmpy ( Rs32 , Rt32 )" , "11101111000sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPSINGLE, NULL} /* F2_sffms */, -{ "Rx32 = add ( #u8 , asl ( Rx32 , #U5 ) )" , "1101 1110 iiixxxxx PPiIIIII iii0i10-" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_addi_asl_ri */, -{ "Rx32 = add ( #u8 , lsr ( Rx32 , #U5 ) )" , "1101 1110 iiixxxxx PPiIIIII iii1i10-" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_addi_lsr_ri */, -{ "Rx32 = add ( Ru32 , mpyi ( Rx32 , Rs32 ) )" , "1110 0011 000sssss PP-xxxxx ---uuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_MPY, NULL} /* M4_mpyrr_addr */, -{ "Rx32 = and ( #u8 , asl ( Rx32 , #U5 ) )" , "1101 1110 iiixxxxx PPiIIIII iii0i00-" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_andi_asl_ri */, -{ "Rx32 = and ( #u8 , lsr ( Rx32 , #U5 ) )" , "1101 1110 iiixxxxx PPiIIIII iii1i00-" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_andi_lsr_ri */, -{ "Rx32 = insert ( Rs32 , #u5 , #U5 )" , "1000 1111 0IIsssss PP0iiiii IIIxxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_insert */, -{ "Rx32 = insert ( Rs32 , Rtt32 )" , "1100 1000 ---sssss PP-ttttt ---xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_insert_rp */, -{ "Rx32 = or ( #u8 , asl ( Rx32 , #U5 ) )" , "1101 1110 iiixxxxx PPiIIIII iii0i01-" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_ori_asl_ri */, -{ "Rx32 = or ( #u8 , lsr ( Rx32 , #U5 ) )" , "1101 1110 iiixxxxx PPiIIIII iii1i01-" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_ori_lsr_ri */, -{ "Rx32 = or ( Ru32 , and ( Rx32 , #s10 ) )" , "1101 1010 01i xxxxx PPiiiiii iiiuuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_or_andix */, -{ "Rx32 = sub ( #u8 , asl ( Rx32 , #U5 ) )" , "1101 1110 iiixxxxx PPiIIIII iii0i11-" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_subi_asl_ri */, -{ "Rx32 = sub ( #u8 , lsr ( Rx32 , #U5 ) )" , "1101 1110 iiixxxxx PPiIIIII iii1i11-" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_subi_lsr_ri */, -{ "Rx32 = tableidxb ( Rs32 , #u4 , #S6 ) :raw" , "1000 0111 00isssss PPIIIIII iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_BIDIRSHIFTR, NULL} /* S2_tableidxb */, -{ "Rx32 = tableidxb ( Rs32 , #u4 , #U5 )" , "0000IIIIIxxxxxsssssiiii000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_tableidxb_goodsyntax)}, /* mapped to Rx32=tableidxb(Rs32,#u4,#U5):raw */ -{ "Rx32 = tableidxd ( Rs32 , #u4 , #S6 ) :raw" , "1000 0111 11isssss PPIIIIII iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_BIDIRSHIFTR, NULL} /* S2_tableidxd */, -{ "Rx32 = tableidxd ( Rs32 , #u4 , #U5 )" , "0000IIIIIxxxxxsssssiiii000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_tableidxd_goodsyntax)}, /* mapped to Rx32=tableidxd(Rs32,#u4,#U5-3):raw */ -{ "Rx32 = tableidxh ( Rs32 , #u4 , #S6 ) :raw" , "1000 0111 01isssss PPIIIIII iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_BIDIRSHIFTR, NULL} /* S2_tableidxh */, -{ "Rx32 = tableidxh ( Rs32 , #u4 , #U5 )" , "0000IIIIIxxxxxsssssiiii000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_tableidxh_goodsyntax)}, /* mapped to Rx32=tableidxh(Rs32,#u4,#U5-1):raw */ -{ "Rx32 = tableidxw ( Rs32 , #u4 , #S6 ) :raw" , "1000 0111 10isssss PPIIIIII iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2|A_BIDIRSHIFTR, NULL} /* S2_tableidxw */, -{ "Rx32 = tableidxw ( Rs32 , #u4 , #U5 )" , "0000IIIIIxxxxxsssssiiii000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_tableidxw_goodsyntax)}, /* mapped to Rx32=tableidxw(Rs32,#u4,#U5-2):raw */ -{ "Rx32 ^= and ( Rs32 , Rt32 )" , "11101111110sssss PP0ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_xor_and */, -{ "Rx32 ^= and ( Rs32 , ~ Rt32 )" , "11101111001sssss PP0ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_xor_andn */, -{ "Rx32 ^= asl ( Rs32 , #u5 )" , "1000 1110 10-sssss PP0iiiii 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asl_i_r_xacc */, -{ "Rx32 ^= lsr ( Rs32 , #u5 )" , "1000 1110 10-sssss PP0iiiii 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_lsr_i_r_xacc */, -{ "Rx32 ^= or ( Rs32 , Rt32 )" , "11101111110sssss PP0ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_xor_or */, -{ "Rx32 ^= xor ( Rs32 , Rt32 )" , "11101111100sssss PP0ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* M2_xor_xacc */, -{ "Rx32 |= and ( Rs32 , #s10 )" , "1101 1010 00i sssss PPiiiiii iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_or_andi */, -{ "Rx32 |= and ( Rs32 , Rt32 )" , "11101111010sssss PP0ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_or_and */, -{ "Rx32 |= and ( Rs32 , ~ Rt32 )" , "11101111001sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_or_andn */, -{ "Rx32 |= asl ( Rs32 , #u5 )" , "1000 1110 01-sssss PP0iiiii 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asl_i_r_or */, -{ "Rx32 |= asl ( Rs32 , Rt32 )" , "1100 1100 00-sssss PP-ttttt 10-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_asl_r_r_or */, -{ "Rx32 |= asr ( Rs32 , #u5 )" , "1000 1110 01-sssss PP0iiiii 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asr_i_r_or */, -{ "Rx32 |= asr ( Rs32 , Rt32 )" , "1100 1100 00-sssss PP-ttttt 00-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_r_or */, -{ "Rx32 |= lsl ( Rs32 , Rt32 )" , "1100 1100 00-sssss PP-ttttt 11-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_r_or */, -{ "Rx32 |= lsr ( Rs32 , #u5 )" , "1000 1110 01-sssss PP0iiiii 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_lsr_i_r_or */, -{ "Rx32 |= lsr ( Rs32 , Rt32 )" , "1100 1100 00-sssss PP-ttttt 01-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_r_or */, -{ "Rx32 |= or ( Rs32 , #s10 )" , "1101 1010 10i sssss PPiiiiii iiixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_EXT_LOWER_IMMED|A_EXTENDABLE|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_or_ori */, -{ "Rx32 |= or ( Rs32 , Rt32 )" , "11101111110sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_or_or */, -{ "Rx32 |= xor ( Rs32 , Rt32 )" , "11101111110sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* M4_or_xor */, -{ "Rxx32 &= asl ( Rss32 , #u6 )" , "1000 0010 01-sssss PPiiiiii 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asl_i_p_and */, -{ "Rxx32 &= asl ( Rss32 , Rt32 )" , "1100 1011 010sssss PP-ttttt 10-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_asl_r_p_and */, -{ "Rxx32 &= asr ( Rss32 , #u6 )" , "1000 0010 01-sssss PPiiiiii 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asr_i_p_and */, -{ "Rxx32 &= asr ( Rss32 , Rt32 )" , "1100 1011 010sssss PP-ttttt 00-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_p_and */, -{ "Rxx32 &= lsl ( Rss32 , Rt32 )" , "1100 1011 010sssss PP-ttttt 11-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_p_and */, -{ "Rxx32 &= lsr ( Rss32 , #u6 )" , "1000 0010 01-sssss PPiiiiii 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_lsr_i_p_and */, -{ "Rxx32 &= lsr ( Rss32 , Rt32 )" , "1100 1011 010sssss PP-ttttt 01-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_p_and */, -{ "Rxx32 += asl ( Rss32 , #u6 )" , "1000 0010 00-sssss PPiiiiii 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asl_i_p_acc */, -{ "Rxx32 += asl ( Rss32 , Rt32 )" , "1100 1011 110sssss PP-ttttt 10-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_asl_r_p_acc */, -{ "Rxx32 += asr ( Rss32 , #u6 )" , "1000 0010 00-sssss PPiiiiii 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asr_i_p_acc */, -{ "Rxx32 += asr ( Rss32 , Rt32 )" , "1100 1011 110sssss PP-ttttt 00-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_p_acc */, -{ "Rxx32 += cmpy ( Rs32 , Rt32 ) :<<1 :sat" , "11100111100sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmacs_s1 */, -{ "Rxx32 += cmpy ( Rs32 , Rt32 ) :sat" , "11100111000sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmacs_s0 */, -{ "Rxx32 += cmpy ( Rs32 , Rt32 * ) :<<1 :sat" , "11100111110sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmacsc_s1 */, -{ "Rxx32 += cmpy ( Rs32 , Rt32 * ) :sat" , "11100111010sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cmacsc_s0 */, -{ "Rxx32 += cmpyi ( Rs32 , Rt32 )" , "11100111000sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_cmaci_s0 */, -{ "Rxx32 += cmpyr ( Rs32 , Rt32 )" , "11100111000sssss PP0ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_cmacr_s0 */, -{ "Rxx32 += dfmpy ( Rss32 , Rtt32 ) :lib" , "11101010010sssss PP0ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE|A_CONDEXEC, NULL} /* F2_dffma_lib */, -{ "Rxx32 += dfmpy ( Rss32 , Rtt32 )" , "11101010000sssss PP0ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dffma */, -{ "Rxx32 += dfmpy ( Rss32 , Rtt32 , Pu4 ) :scale" , "11101010111sssss PP0ttttt 0uuxxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dffma_sc */, -{ "Rxx32 += lsl ( Rss32 , Rt32 )" , "1100 1011 110sssss PP-ttttt 11-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_p_acc */, -{ "Rxx32 += lsr ( Rss32 , #u6 )" , "1000 0010 00-sssss PPiiiiii 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_lsr_i_p_acc */, -{ "Rxx32 += lsr ( Rss32 , Rt32 )" , "1100 1011 110sssss PP-ttttt 01-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_p_acc */, -{ "Rxx32 += mpy ( Rs32.h , Rt32.h ) :<<1" , "11100110100sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_acc_hh_s1 */, -{ "Rxx32 += mpy ( Rs32.h , Rt32.h )" , "11100110000sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_acc_hh_s0 */, -{ "Rxx32 += mpy ( Rs32.h , Rt32.l ) :<<1" , "11100110100sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_acc_hl_s1 */, -{ "Rxx32 += mpy ( Rs32.h , Rt32.l )" , "11100110000sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_acc_hl_s0 */, -{ "Rxx32 += mpy ( Rs32.l , Rt32.h ) :<<1" , "11100110100sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_acc_lh_s1 */, -{ "Rxx32 += mpy ( Rs32.l , Rt32.h )" , "11100110000sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_acc_lh_s0 */, -{ "Rxx32 += mpy ( Rs32.l , Rt32.l ) :<<1" , "11100110100sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_acc_ll_s1 */, -{ "Rxx32 += mpy ( Rs32.l , Rt32.l )" , "11100110000sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_acc_ll_s0 */, -{ "Rxx32 += mpy ( Rs32 , Rt32 )" , "11100111000sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32|A_ROPS_2, NULL} /* M2_dpmpyss_acc_s0 */, -{ "Rxx32 += mpyu ( Rs32.h , Rt32.h ) :<<1" , "11100110110sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_acc_hh_s1 */, -{ "Rxx32 += mpyu ( Rs32.h , Rt32.h )" , "11100110010sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_acc_hh_s0 */, -{ "Rxx32 += mpyu ( Rs32.h , Rt32.l ) :<<1" , "11100110110sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_acc_hl_s1 */, -{ "Rxx32 += mpyu ( Rs32.h , Rt32.l )" , "11100110010sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_acc_hl_s0 */, -{ "Rxx32 += mpyu ( Rs32.l , Rt32.h ) :<<1" , "11100110110sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_acc_lh_s1 */, -{ "Rxx32 += mpyu ( Rs32.l , Rt32.h )" , "11100110010sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_acc_lh_s0 */, -{ "Rxx32 += mpyu ( Rs32.l , Rt32.l ) :<<1" , "11100110110sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_acc_ll_s1 */, -{ "Rxx32 += mpyu ( Rs32.l , Rt32.l )" , "11100110010sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_acc_ll_s0 */, -{ "Rxx32 += mpyu ( Rs32 , Rt32 )" , "11100111010sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32|A_ROPS_2, NULL} /* M2_dpmpyuu_acc_s0 */, -{ "Rxx32 += vcmpyi ( Rss32 , Rtt32 ) :sat" , "11101010010sssss PP0ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vcmac_s0_sat_i */, -{ "Rxx32 += vcmpyr ( Rss32 , Rtt32 ) :sat" , "11101010001sssss PP0ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vcmac_s0_sat_r */, -{ "Rxx32 += vdmpy ( Rss32 , Rtt32 ) :<<1 :sat" , "11101010100sssss PP0ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vdmacs_s1 */, -{ "Rxx32 += vdmpy ( Rss32 , Rtt32 ) :sat" , "11101010000sssss PP0ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vdmacs_s0 */, -{ "Rxx32 += vdmpybsu ( Rss32 , Rtt32 ) :sat" , "11101010001sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M5_vdmacbsu */, -{ "Rxx32 += vmpybsu ( Rs32 , Rt32 )" , "11100111110sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M5_vmacbsu */, -{ "Rxx32 += vmpybu ( Rs32 , Rt32 )" , "11100111100sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M5_vmacbuu */, -{ "Rxx32 += vmpyeh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101010100sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmac2es_s1 */, -{ "Rxx32 += vmpyeh ( Rss32 , Rtt32 ) :sat" , "11101010000sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmac2es_s0 */, -{ "Rxx32 += vmpyeh ( Rss32 , Rtt32 )" , "11101010001sssss PP0ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* M2_vmac2es */, -{ "Rxx32 += vmpyh ( Rs32 , Rt32 ) :<<1 :sat" , "11100111100sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmac2s_s1 */, -{ "Rxx32 += vmpyh ( Rs32 , Rt32 ) :sat" , "11100111000sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmac2s_s0 */, -{ "Rxx32 += vmpyh ( Rs32 , Rt32 )" , "11100111001sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* M2_vmac2 */, -{ "Rxx32 += vmpyhsu ( Rs32 , Rt32 ) :<<1 :sat" , "11100111111sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmac2su_s1 */, -{ "Rxx32 += vmpyhsu ( Rs32 , Rt32 ) :sat" , "11100111011sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vmac2su_s0 */, -{ "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" , "11101010101sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmacls_rs1 */, -{ "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101010100sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmacls_s1 */, -{ "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :rnd :sat" , "11101010001sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmacls_rs0 */, -{ "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :sat" , "11101010000sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmacls_s0 */, -{ "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" , "11101010111sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmaculs_rs1 */, -{ "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101010110sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmaculs_s1 */, -{ "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :rnd :sat" , "11101010011sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmaculs_rs0 */, -{ "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :sat" , "11101010010sssss PP0ttttt 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmaculs_s0 */, -{ "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" , "11101010101sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmachs_rs1 */, -{ "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101010100sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmachs_s1 */, -{ "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :rnd :sat" , "11101010001sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmachs_rs0 */, -{ "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :sat" , "11101010000sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmachs_s0 */, -{ "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" , "11101010111sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmacuhs_rs1 */, -{ "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :<<1 :sat" , "11101010110sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmacuhs_s1 */, -{ "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :rnd :sat" , "11101010011sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmacuhs_rs0 */, -{ "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :sat" , "11101010010sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_mmacuhs_s0 */, -{ "Rxx32 += vraddub ( Rss32 , Rtt32 )" , "11101010010sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vraddub_acc */, -{ "Rxx32 += vrcmpyi ( Rss32 , Rtt32 )" , "11101010000sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_vrcmaci_s0 */, -{ "Rxx32 += vrcmpyi ( Rss32 , Rtt32 * )" , "11101010010sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* M2_vrcmaci_s0c */, -{ "Rxx32 += vrcmpyr ( Rss32 , Rtt32 )" , "11101010000sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_vrcmacr_s0 */, -{ "Rxx32 += vrcmpyr ( Rss32 , Rtt32 * )" , "11101010011sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ARCHV2, NULL} /* M2_vrcmacr_s0c */, -{ "Rxx32 += vrcmpys ( Rss32 , Rt32 ) :<<1 :sat" , "0000xxxxxsssssttttt0000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(M2_vrcmpys_acc_s1)}, /* mapped to Rxx32+=vrcmpys(Rss32,Rtt32):<<1:sat:raw:hi or Rxx32+=vrcmpys(Rss32,Rtt32):<<1:sat:raw:lo */ -{ "Rxx32 += vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :hi" , "11101010101sssss PP0ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV3|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vrcmpys_acc_s1_h */, -{ "Rxx32 += vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :lo" , "11101010111sssss PP0ttttt 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV3|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_vrcmpys_acc_s1_l */, -{ "Rxx32 += vrcnegh ( Rss32 , Rt32 )" , "1100 1011 001sssss PP1ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_vrcnegh */, -{ "Rxx32 += vrcrotate ( Rss32 , Rt32 , #u2 )" , "1100 1011 101sssss PPittttt --ixxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S4_vrcrotate_acc */, -{ "Rxx32 += vrmpybsu ( Rss32 , Rtt32 )" , "11101010110sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M5_vrmacbsu */, -{ "Rxx32 += vrmpybu ( Rss32 , Rtt32 )" , "11101010100sssss PP0ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M5_vrmacbuu */, -{ "Rxx32 += vrmpyh ( Rss32 , Rtt32 )" , "11101010000sssss PP0ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_vrmac_s0 */, -{ "Rxx32 += vrmpyweh ( Rss32 , Rtt32 ) :<<1" , "11101010101sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vrmpyeh_acc_s1 */, -{ "Rxx32 += vrmpyweh ( Rss32 , Rtt32 )" , "11101010001sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vrmpyeh_acc_s0 */, -{ "Rxx32 += vrmpywoh ( Rss32 , Rtt32 ) :<<1" , "11101010111sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vrmpyoh_acc_s1 */, -{ "Rxx32 += vrmpywoh ( Rss32 , Rtt32 )" , "11101010011sssss PP0ttttt 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vrmpyoh_acc_s0 */, -{ "Rxx32 += vrsadub ( Rss32 , Rtt32 )" , "11101010010sssss PP0ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A2_vrsadub_acc */, -{ "Rxx32 -= asl ( Rss32 , #u6 )" , "1000 0010 00-sssss PPiiiiii 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asl_i_p_nac */, -{ "Rxx32 -= asl ( Rss32 , Rt32 )" , "1100 1011 100sssss PP-ttttt 10-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_asl_r_p_nac */, -{ "Rxx32 -= asr ( Rss32 , #u6 )" , "1000 0010 00-sssss PPiiiiii 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asr_i_p_nac */, -{ "Rxx32 -= asr ( Rss32 , Rt32 )" , "1100 1011 100sssss PP-ttttt 00-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_p_nac */, -{ "Rxx32 -= cmpy ( Rs32 , Rt32 ) :<<1 :sat" , "11100111100sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cnacs_s1 */, -{ "Rxx32 -= cmpy ( Rs32 , Rt32 ) :sat" , "11100111000sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cnacs_s0 */, -{ "Rxx32 -= cmpy ( Rs32 , Rt32 * ) :<<1 :sat" , "11100111110sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cnacsc_s1 */, -{ "Rxx32 -= cmpy ( Rs32 , Rt32 * ) :sat" , "11100111010sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_SR_OVF, 0|A_ARCHV2|A_SATURATE|A_IMPLICIT_WRITES_SRBIT|A_NOTE_SR_OVF_WHEN_SATURATING|A_RESTRICT_NOSRMOVE, NULL} /* M2_cnacsc_s0 */, -{ "Rxx32 -= dfmpy ( Rss32 , Rtt32 ) :lib" , "11101010110sssss PP0ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE|A_CONDEXEC, NULL} /* F2_dffms_lib */, -{ "Rxx32 -= dfmpy ( Rss32 , Rtt32 )" , "11101010100sssss PP0ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_FPOP|A_FPDOUBLE, NULL} /* F2_dffms */, -{ "Rxx32 -= lsl ( Rss32 , Rt32 )" , "1100 1011 100sssss PP-ttttt 11-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_p_nac */, -{ "Rxx32 -= lsr ( Rss32 , #u6 )" , "1000 0010 00-sssss PPiiiiii 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_lsr_i_p_nac */, -{ "Rxx32 -= lsr ( Rss32 , Rt32 )" , "1100 1011 100sssss PP-ttttt 01-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_p_nac */, -{ "Rxx32 -= mpy ( Rs32.h , Rt32.h ) :<<1" , "11100110101sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_nac_hh_s1 */, -{ "Rxx32 -= mpy ( Rs32.h , Rt32.h )" , "11100110001sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_nac_hh_s0 */, -{ "Rxx32 -= mpy ( Rs32.h , Rt32.l ) :<<1" , "11100110101sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_nac_hl_s1 */, -{ "Rxx32 -= mpy ( Rs32.h , Rt32.l )" , "11100110001sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_nac_hl_s0 */, -{ "Rxx32 -= mpy ( Rs32.l , Rt32.h ) :<<1" , "11100110101sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_nac_lh_s1 */, -{ "Rxx32 -= mpy ( Rs32.l , Rt32.h )" , "11100110001sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_nac_lh_s0 */, -{ "Rxx32 -= mpy ( Rs32.l , Rt32.l ) :<<1" , "11100110101sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_nac_ll_s1 */, -{ "Rxx32 -= mpy ( Rs32.l , Rt32.l )" , "11100110001sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyd_nac_ll_s0 */, -{ "Rxx32 -= mpy ( Rs32 , Rt32 )" , "11100111001sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32|A_ROPS_2, NULL} /* M2_dpmpyss_nac_s0 */, -{ "Rxx32 -= mpyu ( Rs32.h , Rt32.h ) :<<1" , "11100110111sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_nac_hh_s1 */, -{ "Rxx32 -= mpyu ( Rs32.h , Rt32.h )" , "11100110011sssss PP-ttttt 011xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_nac_hh_s0 */, -{ "Rxx32 -= mpyu ( Rs32.h , Rt32.l ) :<<1" , "11100110111sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_nac_hl_s1 */, -{ "Rxx32 -= mpyu ( Rs32.h , Rt32.l )" , "11100110011sssss PP-ttttt 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_nac_hl_s0 */, -{ "Rxx32 -= mpyu ( Rs32.l , Rt32.h ) :<<1" , "11100110111sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_nac_lh_s1 */, -{ "Rxx32 -= mpyu ( Rs32.l , Rt32.h )" , "11100110011sssss PP-ttttt 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_nac_lh_s0 */, -{ "Rxx32 -= mpyu ( Rs32.l , Rt32.l ) :<<1" , "11100110111sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_nac_ll_s1 */, -{ "Rxx32 -= mpyu ( Rs32.l , Rt32.l )" , "11100110011sssss PP-ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M2_mpyud_nac_ll_s0 */, -{ "Rxx32 -= mpyu ( Rs32 , Rt32 )" , "11100111011sssss PP0ttttt 000xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_IT_MPY|A_IT_MPY_32|A_ROPS_2, NULL} /* M2_dpmpyuu_nac_s0 */, -{ "Rxx32 = insert ( Rss32 , #u6 , #U6 )" , "1000 0011 IIIsssss PPiiiiii IIIxxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_insertp */, -{ "Rxx32 = insert ( Rss32 , Rtt32 )" , "1100 1010 0--sssss PP0ttttt ---xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_insertp_rp */, -{ "Rxx32 = vrmaxh ( Rss32 , Ru32 )" , "1100 1011 001sssss PP0xxxxx 001uuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vrmaxh */, -{ "Rxx32 = vrmaxuh ( Rss32 , Ru32 )" , "1100 1011 001sssss PP1xxxxx 001uuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vrmaxuh */, -{ "Rxx32 = vrmaxuw ( Rss32 , Ru32 )" , "1100 1011 001sssss PP1xxxxx 010uuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vrmaxuw */, -{ "Rxx32 = vrmaxw ( Rss32 , Ru32 )" , "1100 1011 001sssss PP0xxxxx 010uuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vrmaxw */, -{ "Rxx32 = vrminh ( Rss32 , Ru32 )" , "1100 1011 001sssss PP0xxxxx 101uuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vrminh */, -{ "Rxx32 = vrminuh ( Rss32 , Ru32 )" , "1100 1011 001sssss PP1xxxxx 101uuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vrminuh */, -{ "Rxx32 = vrminuw ( Rss32 , Ru32 )" , "1100 1011 001sssss PP1xxxxx 110uuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vrminuw */, -{ "Rxx32 = vrminw ( Rss32 , Ru32 )" , "1100 1011 001sssss PP0xxxxx 110uuuuu" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* A4_vrminw */, -{ "Rxx32 ^= asl ( Rss32 , #u6 )" , "1000 0010 10-sssss PPiiiiii 010xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_asl_i_p_xacc */, -{ "Rxx32 ^= asl ( Rss32 , Rt32 )" , "1100 1011 011sssss PP-ttttt 10-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_asl_r_p_xor */, -{ "Rxx32 ^= asr ( Rss32 , Rt32 )" , "1100 1011 011sssss PP-ttttt 00-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_p_xor */, -{ "Rxx32 ^= lsl ( Rss32 , Rt32 )" , "1100 1011 011sssss PP-ttttt 11-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_p_xor */, -{ "Rxx32 ^= lsr ( Rss32 , #u6 )" , "1000 0010 10-sssss PPiiiiii 001xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* S2_lsr_i_p_xacc */, -{ "Rxx32 ^= lsr ( Rss32 , Rt32 )" , "1100 1011 011sssss PP-ttttt 01-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_p_xor */, -{ "Rxx32 ^= pmpyw ( Rs32 , Rt32 )" , "11100111001sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_pmpyw_acc */, -{ "Rxx32 ^= vpmpyh ( Rs32 , Rt32 )" , "11100111101sssss PP0ttttt 111xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_vpmpyh_acc */, -{ "Rxx32 ^= xor ( Rss32 , Rtt32 )" , "1100 1010 1--sssss PP0ttttt ---xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0, NULL} /* M4_xor_xacc */, -{ "Rxx32 |= asl ( Rss32 , #u6 )" , "1000 0010 01-sssss PPiiiiii 110xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asl_i_p_or */, -{ "Rxx32 |= asl ( Rss32 , Rt32 )" , "1100 1011 000sssss PP-ttttt 10-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_asl_r_p_or */, -{ "Rxx32 |= asr ( Rss32 , #u6 )" , "1000 0010 01-sssss PPiiiiii 100xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_asr_i_p_or */, -{ "Rxx32 |= asr ( Rss32 , Rt32 )" , "1100 1011 000sssss PP-ttttt 00-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_asr_r_p_or */, -{ "Rxx32 |= lsl ( Rss32 , Rt32 )" , "1100 1011 000sssss PP-ttttt 11-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTL, NULL} /* S2_lsl_r_p_or */, -{ "Rxx32 |= lsr ( Rss32 , #u6 )" , "1000 0010 01-sssss PPiiiiii 101xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2, NULL} /* S2_lsr_i_p_or */, -{ "Rxx32 |= lsr ( Rss32 , Rt32 )" , "1100 1011 000sssss PP-ttttt 01-xxxxx" , HEXAGON_MACH, NULL, NULL, 0xc, 0, 0|A_ROPS_2|A_BIDIRSHIFTR, NULL} /* S2_lsr_r_p_or */, -{ "Ry16 = add ( Ru16 , Ry16 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00111000uuuuyyyyEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_addrx_commuted */, -{ "Ry16 = add ( Ru16 , Ry16 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00111000uuuuyyyyEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_commuted_SA1_addrx */, -{ "Ry16 = add ( Ry16 , #S7 ) ; Rx16 = add ( Rx16 , #s7 )" , "00100IIIIIIIyyyyEE100iiiiiiixxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_UPPER_IMMED|A_EXTENDABLE|PACKED|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_addi */, -{ "Ry16 = add ( Ry16 , #s7 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00100iiiiiiiyyyyEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_COMMUTES|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_addrx_commuted */, -{ "Ry16 = add ( Ry16 , #s7 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00100iiiiiiiyyyyEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_COMMUTES|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* X2_AUTOJOIN_SA1_addi_SA1_addrx */, -{ "Ry16 = add ( Ry16 , Ru16 ) ; Rx16 = add ( Rs16 , Rx16 )" , "00111000uuuuyyyyEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_addrx_commuted */, -{ "Ry16 = add ( Ry16 , Ru16 ) ; Rx16 = add ( Rx16 , Rs16 )" , "00111000uuuuyyyyEE111000ssssxxxx" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_COMMUTES|A_COMMUTES|PACKED, NULL} /* X2_AUTOJOIN_SA1_addrx_SA1_addrx */, -{ "Ryy32 = memb_fifo ( Rf32 = #U6 )" , "1001 1 01 0 100 fffff PP01IIII -IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignb_ap */, -{ "Ryy32 = memb_fifo ( Rs32 )" , "0000yyyyysssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadalignb_zomap)}, /* mapped to Ryy32=memb_fifo(Rs32+#0) */ -{ "Ryy32 = memb_fifo ( Rs32 + #s11:0 )" , "1001 0 ii 0 100 sssss PPiiiiii iiiyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadalignb_io */, -{ "Ryy32 = memb_fifo ( Rt32 << #0 + #U6 )" , "1001 1 10 0 100 ttttt PP01IIII 0IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignb_ur_expand_shamt_0 */, -{ "Ryy32 = memb_fifo ( Rt32 << #1 + #U6 )" , "1001 1 10 0 100 ttttt PP01IIII 1IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignb_ur_expand_shamt_1 */, -{ "Ryy32 = memb_fifo ( Rt32 << #2 + #U6 )" , "1001 1 10 0 100 ttttt PP11IIII 0IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignb_ur_expand_shamt_2 */, -{ "Ryy32 = memb_fifo ( Rt32 << #3 + #U6 )" , "1001 1 10 0 100 ttttt PP11IIII 1IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignb_ur_expand_shamt_3 */, -{ "Ryy32 = memb_fifo ( Rz32 ++ #s4:0 )" , "1001 1 01 0 100 zzzzz PP00---i iiiyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadalignb_pi */, -{ "Ryy32 = memb_fifo ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" , "1001 1 00 0 100 zzzzz PPu0--0i iiiyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadalignb_pci */, -{ "Ryy32 = memb_fifo ( Rz32 ++ Mu2 )" , "1001 1 10 0 100 zzzzz PPu0---- 0--yyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadalignb_pr */, -{ "Ryy32 = memb_fifo ( Rz32 ++ Mu2 :brev )" , "1001 1 11 0 100 zzzzz PPu0---- 0--yyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadalignb_pbr */, -{ "Ryy32 = memb_fifo ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 0 100 zzzzz PPu0--1- 0--yyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadalignb_pcr */, -{ "Ryy32 = memh_fifo ( Rf32 = #U6 )" , "1001 1 01 0 010 fffff PP01IIII -IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignh_ap */, -{ "Ryy32 = memh_fifo ( Rs32 )" , "0000yyyyysssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_loadalignh_zomap)}, /* mapped to Ryy32=memh_fifo(Rs32+#0) */ -{ "Ryy32 = memh_fifo ( Rs32 + #s11:1 )" , "1001 0 ii 0 010 sssss PPiiiiii iiiyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_loadalignh_io */, -{ "Ryy32 = memh_fifo ( Rt32 << #0 + #U6 )" , "1001 1 10 0 010 ttttt PP01IIII 0IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignh_ur_expand_shamt_0 */, -{ "Ryy32 = memh_fifo ( Rt32 << #1 + #U6 )" , "1001 1 10 0 010 ttttt PP01IIII 1IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignh_ur_expand_shamt_1 */, -{ "Ryy32 = memh_fifo ( Rt32 << #2 + #U6 )" , "1001 1 10 0 010 ttttt PP11IIII 0IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignh_ur_expand_shamt_2 */, -{ "Ryy32 = memh_fifo ( Rt32 << #3 + #U6 )" , "1001 1 10 0 010 ttttt PP11IIII 1IIyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_loadalignh_ur_expand_shamt_3 */, -{ "Ryy32 = memh_fifo ( Rz32 ++ #s4:1 )" , "1001 1 01 0 010 zzzzz PP00---i iiiyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadalignh_pi */, -{ "Ryy32 = memh_fifo ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" , "1001 1 00 0 010 zzzzz PPu0--0i iiiyyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadalignh_pci */, -{ "Ryy32 = memh_fifo ( Rz32 ++ Mu2 )" , "1001 1 10 0 010 zzzzz PPu0---- 0--yyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadalignh_pr */, -{ "Ryy32 = memh_fifo ( Rz32 ++ Mu2 :brev )" , "1001 1 11 0 010 zzzzz PPu0---- 0--yyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* L2_loadalignh_pbr */, -{ "Ryy32 = memh_fifo ( Rz32 ++I :circ ( Mu2 ) )" , "1001 1 00 0 010 zzzzz PPu0--1- 0--yyyyy" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* L2_loadalignh_pcr */, -{ "Sd64 = Rs32" , "0110 0111 00-sssss PP------ --dddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_RESTRICT_PACKET_AXOK|A_RESTRICT_PACKET_SOMEREGS_OK|A_NOTE_SPECIALGROUPING, NULL} /* Y2_tfrsrcr */, -{ "Sdd64 = Rss32" , "0110 1101 0--sssss PP------ --dddddd" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_RESTRICT_PACKET_AXOK|A_RESTRICT_PACKET_SOMEREGS_OK|A_NOTE_SPECIALGROUPING, NULL} /* Y4_tfrspcp */, -{ "allocframe ( #u11:3 )" , "1010 000 01 0011101 PP000iii iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP, NULL} /* S2_allocframe */, -{ "barrier" , "1010 100 00 00----- PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_RESTRICT_SLOT0ONLY|A_RESTRICT_PACKET_AXOK, NULL} /* Y2_barrier */, -{ "brkpt" , "0110 1100 001----- PP------ 000-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_break */, -{ "call #r22:2" , "0101 101i iiiiiiii PPiiiiii iiiiiii0" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_DIRECT|A_NOTE_PACKET_PC|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_call */, -{ "callr Rs32" , "0101 0000 101sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR, NULL} /* J2_callr */, -{ "ciad ( Rs32 )" , "0110 0100 000sssss PP------ 011-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK|A_EXCEPTION_SWI, NULL} /* Y2_ciad */, -{ "crswap ( Rx32 , sgp )" , "0000xxxxx00000000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(Y2_crswap_old)}, /* mapped to crswap(Rx32,sgp0) */ -{ "crswap ( Rx32 , sgp0 )" , "0110 0101 000xxxxx PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV, NULL} /* Y2_crswap0 */, -{ "crswap ( Rx32 , sgp1 )" , "0110 0101 001xxxxx PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV, NULL} /* Y4_crswap1 */, -{ "crswap ( Rxx32 , sgp1:0 )" , "0110 1101 1--xxxxx PP------ ---00000" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV, NULL} /* Y4_crswap10 */, -{ "cswi ( Rs32 )" , "0110 0100 000sssss PP------ 001-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK, NULL} /* Y2_cswi */, -{ "dccleana ( Rs32 )" , "1010 000 00 00sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_RESTRICT_SLOT1_AOK|A_NOTE_SLOT1_AOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y2_dccleana */, -{ "dccleanidx ( Rs32 )" , "1010 001 00 01sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y2_dccleanidx */, -{ "dccleaninva ( Rs32 )" , "1010 000 00 10sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_RESTRICT_SLOT1_AOK|A_NOTE_SLOT1_AOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y2_dccleaninva */, -{ "dccleaninvidx ( Rs32 )" , "1010 001 00 11sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y2_dccleaninvidx */, -{ "dcfetch ( Rs32 )" , "0000sssss00000000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(Y2_dcfetch)}, /* mapped to dcfetch(Rs32+#0) */ -{ "dcfetch ( Rs32 + #u11:3 )" , "1001 010 0 000 sssss PP0--iii iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_RESTRICT_PREFERSLOT0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y2_dcfetchbo */, -{ "dcinva ( Rs32 )" , "1010 000 00 01sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_RESTRICT_SLOT1_AOK|A_NOTE_SLOT1_AOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y2_dcinva */, -{ "dcinvidx ( Rs32 )" , "1010 001 00 10sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y2_dcinvidx */, -{ "dckill" , "1010 001 00 00----- PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y2_dckill */, -{ "dctagw ( Rs32 , Rt32 )" , "1010 010 00 00sssss PP-ttttt --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_RESTRICT_SLOT0ONLY|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y2_dctagw */, -{ "dczeroa ( Rs32 )" , "1010 000 01 10sssss PP0----- --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_STORE|A_RESTRICT_SLOT1_AOK|A_NOTE_SLOT1_AOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y2_dczeroa */, -{ "dealloc_return" , "1001 011 0 000 11110 PP0000-- ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_NOTE_DEALLOCRET|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP, NULL} /* L4_return */, -{ "deallocframe ; if ( ! p0 ) jumpr Lr" , "0011111100---0--EE01111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SL2_jumpr31_f */, -{ "deallocframe ; if ( ! p0 .new ) jumpr:nt Lr" , "0011111100---0--EE01111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SL2_jumpr31_fnew */, -{ "deallocframe ; if ( p0 ) jumpr Lr" , "0011111100---0--EE01111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SL2_jumpr31_t */, -{ "deallocframe ; if ( p0 .new ) jumpr:nt Lr" , "0011111100---0--EE01111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SL2_jumpr31_tnew */, -{ "deallocframe ; jumpr Lr" , "0011111100---0--EE01111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SL2_jumpr31 */, -{ "deallocframe ; memb ( Rs16 + #u4:0 ) = #0" , "1101111100---0--EE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SS2_storebi0 */, -{ "deallocframe ; memb ( Rs16 + #u4:0 ) = #1" , "1101111100---0--EE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SS2_storebi1 */, -{ "deallocframe ; memb ( Rs16 + #u4:0 ) = Rt16" , "1001111100---0--EE11iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SS1_storeb_io */, -{ "deallocframe ; memd ( Sp + #s6:3 ) = Rtt8" , "1101111100---0--EE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SS2_stored_sp */, -{ "deallocframe ; memh ( Rs16 + #u3:1 ) = Rt16" , "1101111100---0--EE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SS2_storeh_io */, -{ "deallocframe ; memw ( Rs16 + #u4:2 ) = #0" , "1101111100---0--EE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SS2_storewi0 */, -{ "deallocframe ; memw ( Rs16 + #u4:2 ) = #1" , "1101111100---0--EE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SS2_storewi1 */, -{ "deallocframe ; memw ( Rs16 + #u4:2 ) = Rt16" , "1001111100---0--EE10iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SS1_storew_io */, -{ "deallocframe ; memw ( Sp + #u5:2 ) = Rt16" , "1101111100---0--EE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SL2_deallocframe_SS2_storew_sp */, -{ "deallocframe" , "1001 000 0 000 11110 PP0----- ---11110" , HEXAGON_MACH, NULL, NULL, 0x3, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP, NULL} /* L2_deallocframe */, -{ "hintjr ( Rs32 )" , "0101 0010 101sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_HINTJR, NULL} /* J4_hintjumpr */, -{ "iassignw ( Rs32 )" , "0110 0100 000sssss PP------ 010-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK, NULL} /* Y2_iassignw */, -{ "icinva ( Rs32 )" , "0101 0110 110sssss PP000--- --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_ICOP|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y2_icinva */, -{ "icinvidx ( Rs32 )" , "0101 0110 110sssss PP001--- --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_ICOP|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y2_icinvidx */, -{ "ickill" , "0101 0110 110----- PP010--- --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_ICOP|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y2_ickill */, -{ "ictagw ( Rs32 , Rt32 )" , "0101 0101 110sssss PP-ttttt --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_ICOP|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y2_ictagw */, -{ "if ! Ps4 .new dealloc_return:nt" , "1001 011 0 000 11110 PP1010ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_12|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_return_fnew_pnt_alt */, -{ "if ! Ps4 .new dealloc_return:t" , "1001 011 0 000 11110 PP1110ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_12|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_return_fnew_pt_alt */, -{ "if ! Ps4 dealloc_return" , "1001 011 0 000 11110 PP1100ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_7|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_return_f_alt */, -{ "if ! Pt4 .new Rd32 = memb ( #u6 )" , "1001 1 11 1 000 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrbfnew_abs_alt */, -{ "if ! Pt4 .new Rd32 = memb ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrbfnew_zomap_alt)}, /* mapped to if (!Pt4.new) Rd32=memb(Rs32+#0) */ -{ "if ! Pt4 .new Rd32 = memb ( Rs32 + #u6:0 )" , "0100 0111 000 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrbfnew_io_alt */, -{ "if ! Pt4 .new Rd32 = memb ( Rz32 ++ #s4:0 )" , "1001 1 01 1 000 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrbfnew_pi_alt */, -{ "if ! Pt4 .new Rd32 = memh ( #u6 )" , "1001 1 11 1 010 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrhfnew_abs_alt */, -{ "if ! Pt4 .new Rd32 = memh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrhfnew_zomap_alt)}, /* mapped to if (!Pt4.new) Rd32=memh(Rs32+#0) */ -{ "if ! Pt4 .new Rd32 = memh ( Rs32 + #u6:1 )" , "0100 0111 010 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrhfnew_io_alt */, -{ "if ! Pt4 .new Rd32 = memh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 010 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrhfnew_pi_alt */, -{ "if ! Pt4 .new Rd32 = memub ( #u6 )" , "1001 1 11 1 001 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrubfnew_abs_alt */, -{ "if ! Pt4 .new Rd32 = memub ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrubfnew_zomap_alt)}, /* mapped to if (!Pt4.new) Rd32=memub(Rs32+#0) */ -{ "if ! Pt4 .new Rd32 = memub ( Rs32 + #u6:0 )" , "0100 0111 001 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrubfnew_io_alt */, -{ "if ! Pt4 .new Rd32 = memub ( Rz32 ++ #s4:0 )" , "1001 1 01 1 001 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrubfnew_pi_alt */, -{ "if ! Pt4 .new Rd32 = memuh ( #u6 )" , "1001 1 11 1 011 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadruhfnew_abs_alt */, -{ "if ! Pt4 .new Rd32 = memuh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadruhfnew_zomap_alt)}, /* mapped to if (!Pt4.new) Rd32=memuh(Rs32+#0) */ -{ "if ! Pt4 .new Rd32 = memuh ( Rs32 + #u6:1 )" , "0100 0111 011 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadruhfnew_io_alt */, -{ "if ! Pt4 .new Rd32 = memuh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 011 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadruhfnew_pi_alt */, -{ "if ! Pt4 .new Rd32 = memw ( #u6 )" , "1001 1 11 1 100 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrifnew_abs_alt */, -{ "if ! Pt4 .new Rd32 = memw ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrifnew_zomap_alt)}, /* mapped to if (!Pt4.new) Rd32=memw(Rs32+#0) */ -{ "if ! Pt4 .new Rd32 = memw ( Rs32 + #u6:2 )" , "0100 0111 100 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrifnew_io_alt */, -{ "if ! Pt4 .new Rd32 = memw ( Rz32 ++ #s4:2 )" , "1001 1 01 1 100 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrifnew_pi_alt */, -{ "if ! Pt4 .new Rdd32 = memd ( #u6 )" , "1001 1 11 1 110 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrdfnew_abs_alt */, -{ "if ! Pt4 .new Rdd32 = memd ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrdfnew_zomap_alt)}, /* mapped to if (!Pt4.new) Rdd32=memd(Rs32+#0) */ -{ "if ! Pt4 .new Rdd32 = memd ( Rs32 + #u6:3 )" , "0100 0111 110 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrdfnew_io_alt */, -{ "if ! Pt4 .new Rdd32 = memd ( Rz32 ++ #s4:3 )" , "1001 1 01 1 110 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrdfnew_pi_alt */, -{ "if ! Pt4 Rd32 = memb ( #u6 )" , "1001 1 11 1 000 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrbf_abs_alt */, -{ "if ! Pt4 Rd32 = memb ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrbf_zomap_alt)}, /* mapped to if (!Pt4) Rd32=memb(Rs32+#0) */ -{ "if ! Pt4 Rd32 = memb ( Rs32 + #u6:0 )" , "0100 0101 000 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrbf_io_alt */, -{ "if ! Pt4 Rd32 = memb ( Rz32 ++ #s4:0 )" , "1001 1 01 1 000 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrbf_pi_alt */, -{ "if ! Pt4 Rd32 = memh ( #u6 )" , "1001 1 11 1 010 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrhf_abs_alt */, -{ "if ! Pt4 Rd32 = memh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrhf_zomap_alt)}, /* mapped to if (!Pt4) Rd32=memh(Rs32+#0) */ -{ "if ! Pt4 Rd32 = memh ( Rs32 + #u6:1 )" , "0100 0101 010 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrhf_io_alt */, -{ "if ! Pt4 Rd32 = memh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 010 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrhf_pi_alt */, -{ "if ! Pt4 Rd32 = memub ( #u6 )" , "1001 1 11 1 001 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrubf_abs_alt */, -{ "if ! Pt4 Rd32 = memub ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrubf_zomap_alt)}, /* mapped to if (!Pt4) Rd32=memub(Rs32+#0) */ -{ "if ! Pt4 Rd32 = memub ( Rs32 + #u6:0 )" , "0100 0101 001 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrubf_io_alt */, -{ "if ! Pt4 Rd32 = memub ( Rz32 ++ #s4:0 )" , "1001 1 01 1 001 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrubf_pi_alt */, -{ "if ! Pt4 Rd32 = memuh ( #u6 )" , "1001 1 11 1 011 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadruhf_abs_alt */, -{ "if ! Pt4 Rd32 = memuh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadruhf_zomap_alt)}, /* mapped to if (!Pt4) Rd32=memuh(Rs32+#0) */ -{ "if ! Pt4 Rd32 = memuh ( Rs32 + #u6:1 )" , "0100 0101 011 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadruhf_io_alt */, -{ "if ! Pt4 Rd32 = memuh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 011 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadruhf_pi_alt */, -{ "if ! Pt4 Rd32 = memw ( #u6 )" , "1001 1 11 1 100 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrif_abs_alt */, -{ "if ! Pt4 Rd32 = memw ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrif_zomap_alt)}, /* mapped to if (!Pt4) Rd32=memw(Rs32+#0) */ -{ "if ! Pt4 Rd32 = memw ( Rs32 + #u6:2 )" , "0100 0101 100 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrif_io_alt */, -{ "if ! Pt4 Rd32 = memw ( Rz32 ++ #s4:2 )" , "1001 1 01 1 100 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrif_pi_alt */, -{ "if ! Pt4 Rdd32 = memd ( #u6 )" , "1001 1 11 1 110 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrdf_abs_alt */, -{ "if ! Pt4 Rdd32 = memd ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrdf_zomap_alt)}, /* mapped to if (!Pt4) Rdd32=memd(Rs32+#0) */ -{ "if ! Pt4 Rdd32 = memd ( Rs32 + #u6:3 )" , "0100 0101 110 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrdf_io_alt */, -{ "if ! Pt4 Rdd32 = memd ( Rz32 ++ #s4:3 )" , "1001 1 01 1 110 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrdf_pi_alt */, -{ "if ! Pu4 .new Rd32 = #s12" , "0111 1110 1uu0iiii PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmovenewif_alt */, -{ "if ! Pu4 .new Rd32 = Rs32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrfnew_alt)}, /* mapped to if (!Pu4.new) Rd32=add(Rs32,#0) */ -{ "if ! Pu4 .new Rd32 = add ( Rs32 , #s8 )" , "0111 0100 1uusssss PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_paddifnew_alt */, -{ "if ! Pu4 .new Rd32 = add ( Rs32 , Rt32 )" , "1111 1011 0-0sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_paddfnew_alt */, -{ "if ! Pu4 .new Rd32 = and ( Rs32 , Rt32 )" , "1111 1001 -00sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_pandfnew_alt */, -{ "if ! Pu4 .new Rd32 = aslh ( Rs32 )" , "0111 0000 000sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_paslhfnew_alt */, -{ "if ! Pu4 .new Rd32 = asrh ( Rs32 )" , "0111 0000 001sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_pasrhfnew_alt */, -{ "if ! Pu4 .new Rd32 = or ( Rs32 , Rt32 )" , "1111 1001 -01sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_porfnew_alt */, -{ "if ! Pu4 .new Rd32 = sub ( Rt32 , Rs32 )" , "1111 1011 0-1sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_psubfnew_alt */, -{ "if ! Pu4 .new Rd32 = sxtb ( Rs32 )" , "0111 0000 101sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_psxtbfnew_alt */, -{ "if ! Pu4 .new Rd32 = sxth ( Rs32 )" , "0111 0000 111sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_psxthfnew_alt */, -{ "if ! Pu4 .new Rd32 = xor ( Rs32 , Rt32 )" , "1111 1001 -11sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_pxorfnew_alt */, -{ "if ! Pu4 .new Rd32 = zxtb ( Rs32 )" , "0111 0000 100sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_pzxtbfnew_alt */, -{ "if ! Pu4 .new Rd32 = zxth ( Rs32 )" , "0111 0000 110sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_pzxthfnew_alt */, -{ "if ! Pu4 .new Rdd32 = Rss32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrpfnew_alt)}, /* mapped to if (!Pu4.new) Rdd32=combine(Rss.H32,Rss.L32) */ -{ "if ! Pu4 .new Rdd32 = combine ( Rs32 , Rt32 )" , "1111 1101 ---sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_ROPS_2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* C2_ccombinewnewf_alt */, -{ "if ! Pu4 .new jump:nt #r15:2" , "0101 1100 ii1iiiii PPi01-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_NOTE_CONDITIONAL|A_ARCHV2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumpfnew_alt */, -{ "if ! Pu4 .new jump:t #r15:2" , "0101 1100 ii1iiiii PPi11-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_NOTE_CONDITIONAL|A_ARCHV2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumpfnewpt_alt */, -{ "if ! Pu4 .new jumpr:nt Rs32" , "0101 0011 011sssss PP-01-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_ARCHV3|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* J2_jumprfnew_alt */, -{ "if ! Pu4 .new jumpr:t Rs32" , "0101 0011 011sssss PP-11-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_ARCHV3|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* J2_jumprfnewpt_alt */, -{ "if ! Pu4 Rd32 = #s12" , "0111 1110 1uu0iiii PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmoveif_alt */, -{ "if ! Pu4 Rd32 = Rs32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrf_alt)}, /* mapped to if (!Pu4) Rd32=add(Rs32,#0) */ -{ "if ! Pu4 Rd32 = add ( Rs32 , #s8 )" , "0111 0100 1uusssss PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_paddif_alt */, -{ "if ! Pu4 Rd32 = add ( Rs32 , Rt32 )" , "1111 1011 0-0sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_paddf_alt */, -{ "if ! Pu4 Rd32 = and ( Rs32 , Rt32 )" , "1111 1001 -00sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_pandf_alt */, -{ "if ! Pu4 Rd32 = aslh ( Rs32 )" , "0111 0000 000sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_paslhf_alt */, -{ "if ! Pu4 Rd32 = asrh ( Rs32 )" , "0111 0000 001sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_pasrhf_alt */, -{ "if ! Pu4 Rd32 = or ( Rs32 , Rt32 )" , "1111 1001 -01sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_porf_alt */, -{ "if ! Pu4 Rd32 = sub ( Rt32 , Rs32 )" , "1111 1011 0-1sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_psubf_alt */, -{ "if ! Pu4 Rd32 = sxtb ( Rs32 )" , "0111 0000 101sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_psxtbf_alt */, -{ "if ! Pu4 Rd32 = sxth ( Rs32 )" , "0111 0000 111sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_psxthf_alt */, -{ "if ! Pu4 Rd32 = xor ( Rs32 , Rt32 )" , "1111 1001 -11sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_pxorf_alt */, -{ "if ! Pu4 Rd32 = zxtb ( Rs32 )" , "0111 0000 100sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_pzxtbf_alt */, -{ "if ! Pu4 Rd32 = zxth ( Rs32 )" , "0111 0000 110sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_pzxthf_alt */, -{ "if ! Pu4 Rdd32 = Rss32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrpf_alt)}, /* mapped to if (!Pu4) Rdd32=combine(Rss.H32,Rss.L32) */ -{ "if ! Pu4 Rdd32 = combine ( Rs32 , Rt32 )" , "1111 1101 ---sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_ROPS_2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* C2_ccombinewf_alt */, -{ "if ! Pu4 call #r15:2" , "0101 1101 ii1iiiii PPi-0-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_DIRECT|A_NOTE_PACKET_PC|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_NOTE_CONDITIONAL|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_PC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_callf_alt */, -{ "if ! Pu4 callr Rs32" , "0101 0001 001sssss PP----uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* J2_callrf_alt */, -{ "if ! Pu4 jump #r15:2" , "0101 1100 ii1iiiii PPi-0-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumpf_alt */, -{ "if ! Pu4 jumpr Rs32" , "0101 0011 011sssss PP--0-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* J2_jumprf_alt */, -{ "if ! Pv4 .new Rd32 = memb ( Rs32 + Rt32 << #0 )" , "0011 00 11 000 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrbfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new Rd32 = memb ( Rs32 + Rt32 << #1 )" , "0011 00 11 000 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrbfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new Rd32 = memb ( Rs32 + Rt32 << #2 )" , "0011 00 11 000 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrbfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new Rd32 = memb ( Rs32 + Rt32 << #3 )" , "0011 00 11 000 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrbfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new Rd32 = memh ( Rs32 + Rt32 << #0 )" , "0011 00 11 010 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrhfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new Rd32 = memh ( Rs32 + Rt32 << #1 )" , "0011 00 11 010 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrhfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new Rd32 = memh ( Rs32 + Rt32 << #2 )" , "0011 00 11 010 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrhfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new Rd32 = memh ( Rs32 + Rt32 << #3 )" , "0011 00 11 010 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrhfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new Rd32 = memub ( Rs32 + Rt32 << #0 )" , "0011 00 11 001 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrubfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new Rd32 = memub ( Rs32 + Rt32 << #1 )" , "0011 00 11 001 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrubfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new Rd32 = memub ( Rs32 + Rt32 << #2 )" , "0011 00 11 001 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrubfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new Rd32 = memub ( Rs32 + Rt32 << #3 )" , "0011 00 11 001 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrubfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new Rd32 = memuh ( Rs32 + Rt32 << #0 )" , "0011 00 11 011 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadruhfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new Rd32 = memuh ( Rs32 + Rt32 << #1 )" , "0011 00 11 011 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadruhfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new Rd32 = memuh ( Rs32 + Rt32 << #2 )" , "0011 00 11 011 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadruhfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new Rd32 = memuh ( Rs32 + Rt32 << #3 )" , "0011 00 11 011 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadruhfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new Rd32 = memw ( Rs32 + Rt32 << #0 )" , "0011 00 11 100 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrifnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new Rd32 = memw ( Rs32 + Rt32 << #1 )" , "0011 00 11 100 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrifnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new Rd32 = memw ( Rs32 + Rt32 << #2 )" , "0011 00 11 100 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrifnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new Rd32 = memw ( Rs32 + Rt32 << #3 )" , "0011 00 11 100 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrifnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new Rdd32 = memd ( Rs32 + Rt32 << #0 )" , "0011 00 11 110 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrdfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new Rdd32 = memd ( Rs32 + Rt32 << #1 )" , "0011 00 11 110 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrdfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new Rdd32 = memd ( Rs32 + Rt32 << #2 )" , "0011 00 11 110 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrdfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new Rdd32 = memd ( Rs32 + Rt32 << #3 )" , "0011 00 11 110 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrdfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new memb ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP100ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbnewfnew_abs_alt */, -{ "if ! Pv4 .new memb ( #u6 ) = Rt32" , "1010 1 11 1 000 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbfnew_abs_alt */, -{ "if ! Pv4 .new memb ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirbfnew_zomap_alt)}, /* mapped to if (!Pv4.new) memb(Rs32+#0)=#S6 */ -{ "if ! Pv4 .new memb ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerbnewfnew_zomap_alt)}, /* mapped to if (!Pv4.new) memb(Rs32+#0)=Nt8.new */ -{ "if ! Pv4 .new memb ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerbfnew_zomap_alt)}, /* mapped to if (!Pv4.new) memb(Rs32+#0)=Rt32 */ -{ "if ! Pv4 .new memb ( Rs32 + #u6:0 ) = #S6" , "0011 100 11 00 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirbfnew_io_alt */, -{ "if ! Pv4 .new memb ( Rs32 + #u6:0 ) = Nt8 .new" , "0100 0110 101 sssss PPi00ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerbnewfnew_io_alt */, -{ "if ! Pv4 .new memb ( Rs32 + #u6:0 ) = Rt32" , "0100 0110 000 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerbfnew_io_alt */, -{ "if ! Pv4 .new memb ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbnewfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new memb ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 11 000 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new memb ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbnewfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new memb ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 11 000 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new memb ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbnewfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new memb ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 11 000 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new memb ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbnewfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new memb ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 11 000 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new memb ( Rz32 ++ #s4:0 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP100ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerbnewfnew_pi_alt */, -{ "if ! Pv4 .new memb ( Rz32 ++ #s4:0 ) = Rt32" , "1010 1 01 1 000 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerbfnew_pi_alt */, -{ "if ! Pv4 .new memd ( #u6 ) = Rtt32" , "1010 1 11 1 110 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerdfnew_abs_alt */, -{ "if ! Pv4 .new memd ( Rs32 ) = Rtt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerdfnew_zomap_alt)}, /* mapped to if (!Pv4.new) memd(Rs32+#0)=Rtt32 */ -{ "if ! Pv4 .new memd ( Rs32 + #u6:3 ) = Rtt32" , "0100 0110 110 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerdfnew_io_alt */, -{ "if ! Pv4 .new memd ( Rs32 + Ru32 << #0 ) = Rtt32" , "0011 01 11 110 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerdfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new memd ( Rs32 + Ru32 << #1 ) = Rtt32" , "0011 01 11 110 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerdfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new memd ( Rs32 + Ru32 << #2 ) = Rtt32" , "0011 01 11 110 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerdfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new memd ( Rs32 + Ru32 << #3 ) = Rtt32" , "0011 01 11 110 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerdfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new memd ( Rz32 ++ #s4:3 ) = Rtt32" , "1010 1 01 1 110 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerdfnew_pi_alt */, -{ "if ! Pv4 .new memh ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP101ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhnewfnew_abs_alt */, -{ "if ! Pv4 .new memh ( #u6 ) = Rt32.h" , "1010 1 11 1 011 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerffnew_abs_alt */, -{ "if ! Pv4 .new memh ( #u6 ) = Rt32" , "1010 1 11 1 010 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhfnew_abs_alt */, -{ "if ! Pv4 .new memh ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirhfnew_zomap_alt)}, /* mapped to if (!Pv4.new) memh(Rs32+#0)=#S6 */ -{ "if ! Pv4 .new memh ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerhnewfnew_zomap_alt)}, /* mapped to if (!Pv4.new) memh(Rs32+#0)=Nt8.new */ -{ "if ! Pv4 .new memh ( Rs32 ) = Rt32.h" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerffnew_zomap_alt)}, /* mapped to if (!Pv4.new) memh(Rs32+#0)=Rt32.h */ -{ "if ! Pv4 .new memh ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerhfnew_zomap_alt)}, /* mapped to if (!Pv4.new) memh(Rs32+#0)=Rt32 */ -{ "if ! Pv4 .new memh ( Rs32 + #u6:1 ) = #S6" , "0011 100 11 01 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirhfnew_io_alt */, -{ "if ! Pv4 .new memh ( Rs32 + #u6:1 ) = Nt8 .new" , "0100 0110 101 sssss PPi01ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerhnewfnew_io_alt */, -{ "if ! Pv4 .new memh ( Rs32 + #u6:1 ) = Rt32.h" , "0100 0110 011 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerffnew_io_alt */, -{ "if ! Pv4 .new memh ( Rs32 + #u6:1 ) = Rt32" , "0100 0110 010 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerhfnew_io_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhnewfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #0 ) = Rt32.h" , "0011 01 11 011 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerffnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 11 010 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhnewfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #1 ) = Rt32.h" , "0011 01 11 011 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerffnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 11 010 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhnewfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #2 ) = Rt32.h" , "0011 01 11 011 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerffnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 11 010 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhnewfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #3 ) = Rt32.h" , "0011 01 11 011 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerffnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new memh ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 11 010 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new memh ( Rz32 ++ #s4:1 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP101ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerhnewfnew_pi_alt */, -{ "if ! Pv4 .new memh ( Rz32 ++ #s4:1 ) = Rt32.h" , "1010 1 01 1 011 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerffnew_pi_alt */, -{ "if ! Pv4 .new memh ( Rz32 ++ #s4:1 ) = Rt32" , "1010 1 01 1 010 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerhfnew_pi_alt */, -{ "if ! Pv4 .new memw ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP110ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerinewfnew_abs_alt */, -{ "if ! Pv4 .new memw ( #u6 ) = Rt32" , "1010 1 11 1 100 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerifnew_abs_alt */, -{ "if ! Pv4 .new memw ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirifnew_zomap_alt)}, /* mapped to if (!Pv4.new) memw(Rs32+#0)=#S6 */ -{ "if ! Pv4 .new memw ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerinewfnew_zomap_alt)}, /* mapped to if (!Pv4.new) memw(Rs32+#0)=Nt8.new */ -{ "if ! Pv4 .new memw ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerifnew_zomap_alt)}, /* mapped to if (!Pv4.new) memw(Rs32+#0)=Rt32 */ -{ "if ! Pv4 .new memw ( Rs32 + #u6:2 ) = #S6" , "0011 100 11 10 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirifnew_io_alt */, -{ "if ! Pv4 .new memw ( Rs32 + #u6:2 ) = Nt8 .new" , "0100 0110 101 sssss PPi10ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerinewfnew_io_alt */, -{ "if ! Pv4 .new memw ( Rs32 + #u6:2 ) = Rt32" , "0100 0110 100 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerifnew_io_alt */, -{ "if ! Pv4 .new memw ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerinewfnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new memw ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 11 100 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerifnew_rr_expand_shamt_0_alt */, -{ "if ! Pv4 .new memw ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerinewfnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new memw ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 11 100 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerifnew_rr_expand_shamt_1_alt */, -{ "if ! Pv4 .new memw ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerinewfnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new memw ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 11 100 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerifnew_rr_expand_shamt_2_alt */, -{ "if ! Pv4 .new memw ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerinewfnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new memw ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 11 100 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerifnew_rr_expand_shamt_3_alt */, -{ "if ! Pv4 .new memw ( Rz32 ++ #s4:2 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP110ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerinewfnew_pi_alt */, -{ "if ! Pv4 .new memw ( Rz32 ++ #s4:2 ) = Rt32" , "1010 1 01 1 100 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerifnew_pi_alt */, -{ "if ! Pv4 Rd32 = memb ( Rs32 + Rt32 << #0 )" , "0011 00 01 000 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrbf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 Rd32 = memb ( Rs32 + Rt32 << #1 )" , "0011 00 01 000 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrbf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 Rd32 = memb ( Rs32 + Rt32 << #2 )" , "0011 00 01 000 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrbf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 Rd32 = memb ( Rs32 + Rt32 << #3 )" , "0011 00 01 000 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrbf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 Rd32 = memh ( Rs32 + Rt32 << #0 )" , "0011 00 01 010 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrhf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 Rd32 = memh ( Rs32 + Rt32 << #1 )" , "0011 00 01 010 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrhf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 Rd32 = memh ( Rs32 + Rt32 << #2 )" , "0011 00 01 010 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrhf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 Rd32 = memh ( Rs32 + Rt32 << #3 )" , "0011 00 01 010 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrhf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 Rd32 = memub ( Rs32 + Rt32 << #0 )" , "0011 00 01 001 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrubf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 Rd32 = memub ( Rs32 + Rt32 << #1 )" , "0011 00 01 001 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrubf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 Rd32 = memub ( Rs32 + Rt32 << #2 )" , "0011 00 01 001 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrubf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 Rd32 = memub ( Rs32 + Rt32 << #3 )" , "0011 00 01 001 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrubf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 Rd32 = memuh ( Rs32 + Rt32 << #0 )" , "0011 00 01 011 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadruhf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 Rd32 = memuh ( Rs32 + Rt32 << #1 )" , "0011 00 01 011 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadruhf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 Rd32 = memuh ( Rs32 + Rt32 << #2 )" , "0011 00 01 011 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadruhf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 Rd32 = memuh ( Rs32 + Rt32 << #3 )" , "0011 00 01 011 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadruhf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 Rd32 = memw ( Rs32 + Rt32 << #0 )" , "0011 00 01 100 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrif_rr_expand_shamt_0_alt */, -{ "if ! Pv4 Rd32 = memw ( Rs32 + Rt32 << #1 )" , "0011 00 01 100 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrif_rr_expand_shamt_1_alt */, -{ "if ! Pv4 Rd32 = memw ( Rs32 + Rt32 << #2 )" , "0011 00 01 100 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrif_rr_expand_shamt_2_alt */, -{ "if ! Pv4 Rd32 = memw ( Rs32 + Rt32 << #3 )" , "0011 00 01 100 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrif_rr_expand_shamt_3_alt */, -{ "if ! Pv4 Rdd32 = memd ( Rs32 + Rt32 << #0 )" , "0011 00 01 110 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrdf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 Rdd32 = memd ( Rs32 + Rt32 << #1 )" , "0011 00 01 110 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrdf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 Rdd32 = memd ( Rs32 + Rt32 << #2 )" , "0011 00 01 110 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrdf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 Rdd32 = memd ( Rs32 + Rt32 << #3 )" , "0011 00 01 110 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrdf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 memb ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP000ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbnewf_abs_alt */, -{ "if ! Pv4 memb ( #u6 ) = Rt32" , "1010 1 11 1 000 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbf_abs_alt */, -{ "if ! Pv4 memb ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirbf_zomap_alt)}, /* mapped to if (!Pv4) memb(Rs32+#0)=#S6 */ -{ "if ! Pv4 memb ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerbnewf_zomap_alt)}, /* mapped to if (!Pv4) memb(Rs32+#0)=Nt8.new */ -{ "if ! Pv4 memb ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerbf_zomap_alt)}, /* mapped to if (!Pv4) memb(Rs32+#0)=Rt32 */ -{ "if ! Pv4 memb ( Rs32 + #u6:0 ) = #S6" , "0011 100 01 00 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirbf_io_alt */, -{ "if ! Pv4 memb ( Rs32 + #u6:0 ) = Nt8 .new" , "0100 0100 101 sssss PPi00ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerbnewf_io_alt */, -{ "if ! Pv4 memb ( Rs32 + #u6:0 ) = Rt32" , "0100 0100 000 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerbf_io_alt */, -{ "if ! Pv4 memb ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbnewf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 memb ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 01 000 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 memb ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbnewf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 memb ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 01 000 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 memb ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbnewf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 memb ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 01 000 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 memb ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbnewf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 memb ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 01 000 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 memb ( Rz32 ++ #s4:0 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP100ttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerbnewf_pi_alt */, -{ "if ! Pv4 memb ( Rz32 ++ #s4:0 ) = Rt32" , "1010 1 01 1 000 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerbf_pi_alt */, -{ "if ! Pv4 memd ( #u6 ) = Rtt32" , "1010 1 11 1 110 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerdf_abs_alt */, -{ "if ! Pv4 memd ( Rs32 ) = Rtt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerdf_zomap_alt)}, /* mapped to if (!Pv4) memd(Rs32+#0)=Rtt32 */ -{ "if ! Pv4 memd ( Rs32 + #u6:3 ) = Rtt32" , "0100 0100 110 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerdf_io_alt */, -{ "if ! Pv4 memd ( Rs32 + Ru32 << #0 ) = Rtt32" , "0011 01 01 110 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerdf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 memd ( Rs32 + Ru32 << #1 ) = Rtt32" , "0011 01 01 110 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerdf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 memd ( Rs32 + Ru32 << #2 ) = Rtt32" , "0011 01 01 110 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerdf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 memd ( Rs32 + Ru32 << #3 ) = Rtt32" , "0011 01 01 110 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerdf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 memd ( Rz32 ++ #s4:3 ) = Rtt32" , "1010 1 01 1 110 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerdf_pi_alt */, -{ "if ! Pv4 memh ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP001ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhnewf_abs_alt */, -{ "if ! Pv4 memh ( #u6 ) = Rt32.h" , "1010 1 11 1 011 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerff_abs_alt */, -{ "if ! Pv4 memh ( #u6 ) = Rt32" , "1010 1 11 1 010 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhf_abs_alt */, -{ "if ! Pv4 memh ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirhf_zomap_alt)}, /* mapped to if (!Pv4) memh(Rs32+#0)=#S6 */ -{ "if ! Pv4 memh ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerhnewf_zomap_alt)}, /* mapped to if (!Pv4) memh(Rs32+#0)=Nt8.new */ -{ "if ! Pv4 memh ( Rs32 ) = Rt32.h" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerff_zomap_alt)}, /* mapped to if (!Pv4) memh(Rs32+#0)=Rt32.h */ -{ "if ! Pv4 memh ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerhf_zomap_alt)}, /* mapped to if (!Pv4) memh(Rs32+#0)=Rt32 */ -{ "if ! Pv4 memh ( Rs32 + #u6:1 ) = #S6" , "0011 100 01 01 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirhf_io_alt */, -{ "if ! Pv4 memh ( Rs32 + #u6:1 ) = Nt8 .new" , "0100 0100 101 sssss PPi01ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerhnewf_io_alt */, -{ "if ! Pv4 memh ( Rs32 + #u6:1 ) = Rt32.h" , "0100 0100 011 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerff_io_alt */, -{ "if ! Pv4 memh ( Rs32 + #u6:1 ) = Rt32" , "0100 0100 010 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerhf_io_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhnewf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #0 ) = Rt32.h" , "0011 01 01 011 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerff_rr_expand_shamt_0_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 01 010 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhnewf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #1 ) = Rt32.h" , "0011 01 01 011 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerff_rr_expand_shamt_1_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 01 010 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhnewf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #2 ) = Rt32.h" , "0011 01 01 011 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerff_rr_expand_shamt_2_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 01 010 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhnewf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #3 ) = Rt32.h" , "0011 01 01 011 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerff_rr_expand_shamt_3_alt */, -{ "if ! Pv4 memh ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 01 010 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 memh ( Rz32 ++ #s4:1 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP101ttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerhnewf_pi_alt */, -{ "if ! Pv4 memh ( Rz32 ++ #s4:1 ) = Rt32.h" , "1010 1 01 1 011 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerff_pi_alt */, -{ "if ! Pv4 memh ( Rz32 ++ #s4:1 ) = Rt32" , "1010 1 01 1 010 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerhf_pi_alt */, -{ "if ! Pv4 memw ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP010ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerinewf_abs_alt */, -{ "if ! Pv4 memw ( #u6 ) = Rt32" , "1010 1 11 1 100 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerif_abs_alt */, -{ "if ! Pv4 memw ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirif_zomap_alt)}, /* mapped to if (!Pv4) memw(Rs32+#0)=#S6 */ -{ "if ! Pv4 memw ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerinewf_zomap_alt)}, /* mapped to if (!Pv4) memw(Rs32+#0)=Nt8.new */ -{ "if ! Pv4 memw ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerif_zomap_alt)}, /* mapped to if (!Pv4) memw(Rs32+#0)=Rt32 */ -{ "if ! Pv4 memw ( Rs32 + #u6:2 ) = #S6" , "0011 100 01 10 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirif_io_alt */, -{ "if ! Pv4 memw ( Rs32 + #u6:2 ) = Nt8 .new" , "0100 0100 101 sssss PPi10ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerinewf_io_alt */, -{ "if ! Pv4 memw ( Rs32 + #u6:2 ) = Rt32" , "0100 0100 100 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerif_io_alt */, -{ "if ! Pv4 memw ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerinewf_rr_expand_shamt_0_alt */, -{ "if ! Pv4 memw ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 01 100 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerif_rr_expand_shamt_0_alt */, -{ "if ! Pv4 memw ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerinewf_rr_expand_shamt_1_alt */, -{ "if ! Pv4 memw ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 01 100 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerif_rr_expand_shamt_1_alt */, -{ "if ! Pv4 memw ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerinewf_rr_expand_shamt_2_alt */, -{ "if ! Pv4 memw ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 01 100 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerif_rr_expand_shamt_2_alt */, -{ "if ! Pv4 memw ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerinewf_rr_expand_shamt_3_alt */, -{ "if ! Pv4 memw ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 01 100 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerif_rr_expand_shamt_3_alt */, -{ "if ! Pv4 memw ( Rz32 ++ #s4:2 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP110ttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerinewf_pi_alt */, -{ "if ! Pv4 memw ( Rz32 ++ #s4:2 ) = Rt32" , "1010 1 01 1 100 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerif_pi_alt */, -{ "if ( ! Ps4 ) dealloc_return" , "1001 011 0 000 11110 PP1100ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_7|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_return_f */, -{ "if ( ! Ps4 .new ) dealloc_return:nt" , "1001 011 0 000 11110 PP1010ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_12|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_return_fnew_pnt */, -{ "if ( ! Ps4 .new ) dealloc_return:t" , "1001 011 0 000 11110 PP1110ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_12|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_return_fnew_pt */, -{ "if ( ! Pt4 ) Rd32 = memb ( #u6 )" , "1001 1 11 1 000 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrbf_abs */, -{ "if ( ! Pt4 ) Rd32 = memb ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrbf_zomap)}, /* mapped to if (!Pt4) Rd32=memb(Rs32+#0) */ -{ "if ( ! Pt4 ) Rd32 = memb ( Rs32 + #u6:0 )" , "0100 0101 000 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrbf_io */, -{ "if ( ! Pt4 ) Rd32 = memb ( Rz32 ++ #s4:0 )" , "1001 1 01 1 000 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrbf_pi */, -{ "if ( ! Pt4 ) Rd32 = memh ( #u6 )" , "1001 1 11 1 010 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrhf_abs */, -{ "if ( ! Pt4 ) Rd32 = memh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrhf_zomap)}, /* mapped to if (!Pt4) Rd32=memh(Rs32+#0) */ -{ "if ( ! Pt4 ) Rd32 = memh ( Rs32 + #u6:1 )" , "0100 0101 010 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrhf_io */, -{ "if ( ! Pt4 ) Rd32 = memh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 010 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrhf_pi */, -{ "if ( ! Pt4 ) Rd32 = memub ( #u6 )" , "1001 1 11 1 001 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrubf_abs */, -{ "if ( ! Pt4 ) Rd32 = memub ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrubf_zomap)}, /* mapped to if (!Pt4) Rd32=memub(Rs32+#0) */ -{ "if ( ! Pt4 ) Rd32 = memub ( Rs32 + #u6:0 )" , "0100 0101 001 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrubf_io */, -{ "if ( ! Pt4 ) Rd32 = memub ( Rz32 ++ #s4:0 )" , "1001 1 01 1 001 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrubf_pi */, -{ "if ( ! Pt4 ) Rd32 = memuh ( #u6 )" , "1001 1 11 1 011 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadruhf_abs */, -{ "if ( ! Pt4 ) Rd32 = memuh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadruhf_zomap)}, /* mapped to if (!Pt4) Rd32=memuh(Rs32+#0) */ -{ "if ( ! Pt4 ) Rd32 = memuh ( Rs32 + #u6:1 )" , "0100 0101 011 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadruhf_io */, -{ "if ( ! Pt4 ) Rd32 = memuh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 011 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadruhf_pi */, -{ "if ( ! Pt4 ) Rd32 = memw ( #u6 )" , "1001 1 11 1 100 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrif_abs */, -{ "if ( ! Pt4 ) Rd32 = memw ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrif_zomap)}, /* mapped to if (!Pt4) Rd32=memw(Rs32+#0) */ -{ "if ( ! Pt4 ) Rd32 = memw ( Rs32 + #u6:2 )" , "0100 0101 100 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrif_io */, -{ "if ( ! Pt4 ) Rd32 = memw ( Rz32 ++ #s4:2 )" , "1001 1 01 1 100 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrif_pi */, -{ "if ( ! Pt4 ) Rdd32 = memd ( #u6 )" , "1001 1 11 1 110 iiiii PP101tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrdf_abs */, -{ "if ( ! Pt4 ) Rdd32 = memd ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrdf_zomap)}, /* mapped to if (!Pt4) Rdd32=memd(Rs32+#0) */ -{ "if ( ! Pt4 ) Rdd32 = memd ( Rs32 + #u6:3 )" , "0100 0101 110 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrdf_io */, -{ "if ( ! Pt4 ) Rdd32 = memd ( Rz32 ++ #s4:3 )" , "1001 1 01 1 110 zzzzz PP101tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L2_ploadrdf_pi */, -{ "if ( ! Pt4 .new ) Rd32 = memb ( #u6 )" , "1001 1 11 1 000 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrbfnew_abs */, -{ "if ( ! Pt4 .new ) Rd32 = memb ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrbfnew_zomap)}, /* mapped to if (!Pt4.new) Rd32=memb(Rs32+#0) */ -{ "if ( ! Pt4 .new ) Rd32 = memb ( Rs32 + #u6:0 )" , "0100 0111 000 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrbfnew_io */, -{ "if ( ! Pt4 .new ) Rd32 = memb ( Rz32 ++ #s4:0 )" , "1001 1 01 1 000 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrbfnew_pi */, -{ "if ( ! Pt4 .new ) Rd32 = memh ( #u6 )" , "1001 1 11 1 010 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrhfnew_abs */, -{ "if ( ! Pt4 .new ) Rd32 = memh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrhfnew_zomap)}, /* mapped to if (!Pt4.new) Rd32=memh(Rs32+#0) */ -{ "if ( ! Pt4 .new ) Rd32 = memh ( Rs32 + #u6:1 )" , "0100 0111 010 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrhfnew_io */, -{ "if ( ! Pt4 .new ) Rd32 = memh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 010 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrhfnew_pi */, -{ "if ( ! Pt4 .new ) Rd32 = memub ( #u6 )" , "1001 1 11 1 001 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrubfnew_abs */, -{ "if ( ! Pt4 .new ) Rd32 = memub ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrubfnew_zomap)}, /* mapped to if (!Pt4.new) Rd32=memub(Rs32+#0) */ -{ "if ( ! Pt4 .new ) Rd32 = memub ( Rs32 + #u6:0 )" , "0100 0111 001 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrubfnew_io */, -{ "if ( ! Pt4 .new ) Rd32 = memub ( Rz32 ++ #s4:0 )" , "1001 1 01 1 001 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrubfnew_pi */, -{ "if ( ! Pt4 .new ) Rd32 = memuh ( #u6 )" , "1001 1 11 1 011 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadruhfnew_abs */, -{ "if ( ! Pt4 .new ) Rd32 = memuh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadruhfnew_zomap)}, /* mapped to if (!Pt4.new) Rd32=memuh(Rs32+#0) */ -{ "if ( ! Pt4 .new ) Rd32 = memuh ( Rs32 + #u6:1 )" , "0100 0111 011 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadruhfnew_io */, -{ "if ( ! Pt4 .new ) Rd32 = memuh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 011 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadruhfnew_pi */, -{ "if ( ! Pt4 .new ) Rd32 = memw ( #u6 )" , "1001 1 11 1 100 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrifnew_abs */, -{ "if ( ! Pt4 .new ) Rd32 = memw ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrifnew_zomap)}, /* mapped to if (!Pt4.new) Rd32=memw(Rs32+#0) */ -{ "if ( ! Pt4 .new ) Rd32 = memw ( Rs32 + #u6:2 )" , "0100 0111 100 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrifnew_io */, -{ "if ( ! Pt4 .new ) Rd32 = memw ( Rz32 ++ #s4:2 )" , "1001 1 01 1 100 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrifnew_pi */, -{ "if ( ! Pt4 .new ) Rdd32 = memd ( #u6 )" , "1001 1 11 1 110 iiiii PP111tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrdfnew_abs */, -{ "if ( ! Pt4 .new ) Rdd32 = memd ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrdfnew_zomap)}, /* mapped to if (!Pt4.new) Rdd32=memd(Rs32+#0) */ -{ "if ( ! Pt4 .new ) Rdd32 = memd ( Rs32 + #u6:3 )" , "0100 0111 110 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrdfnew_io */, -{ "if ( ! Pt4 .new ) Rdd32 = memd ( Rz32 ++ #s4:3 )" , "1001 1 01 1 110 zzzzz PP111tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L2_ploadrdfnew_pi */, -{ "if ( ! Pu4 ) Rd32 = #s12" , "0111 1110 1uu0iiii PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmoveif */, -{ "if ( ! Pu4 ) Rd32 = Rs32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrf)}, /* mapped to if (!Pu4) Rd32=add(Rs32,#0) */ -{ "if ( ! Pu4 ) Rd32 = add ( Rs32 , #s8 )" , "0111 0100 1uusssss PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_paddif */, -{ "if ( ! Pu4 ) Rd32 = add ( Rs32 , Rt32 )" , "1111 1011 0-0sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_paddf */, -{ "if ( ! Pu4 ) Rd32 = and ( Rs32 , Rt32 )" , "1111 1001 -00sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_pandf */, -{ "if ( ! Pu4 ) Rd32 = aslh ( Rs32 )" , "0111 0000 000sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_paslhf */, -{ "if ( ! Pu4 ) Rd32 = asrh ( Rs32 )" , "0111 0000 001sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_pasrhf */, -{ "if ( ! Pu4 ) Rd32 = or ( Rs32 , Rt32 )" , "1111 1001 -01sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_porf */, -{ "if ( ! Pu4 ) Rd32 = sub ( Rt32 , Rs32 )" , "1111 1011 0-1sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_psubf */, -{ "if ( ! Pu4 ) Rd32 = sxtb ( Rs32 )" , "0111 0000 101sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_psxtbf */, -{ "if ( ! Pu4 ) Rd32 = sxth ( Rs32 )" , "0111 0000 111sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_psxthf */, -{ "if ( ! Pu4 ) Rd32 = xor ( Rs32 , Rt32 )" , "1111 1001 -11sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A2_pxorf */, -{ "if ( ! Pu4 ) Rd32 = zxtb ( Rs32 )" , "0111 0000 100sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_pzxtbf */, -{ "if ( ! Pu4 ) Rd32 = zxth ( Rs32 )" , "0111 0000 110sssss PP1-10uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* A4_pzxthf */, -{ "if ( ! Pu4 ) Rdd32 = Rss32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrpf)}, /* mapped to if (!Pu4) Rdd32=combine(Rss.H32,Rss.L32) */ -{ "if ( ! Pu4 ) Rdd32 = combine ( Rs32 , Rt32 )" , "1111 1101 ---sssss PP0ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_ROPS_2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* C2_ccombinewf */, -{ "if ( ! Pu4 ) call #r15:2" , "0101 1101 ii1iiiii PPi-0-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_DIRECT|A_NOTE_PACKET_PC|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_NOTE_CONDITIONAL|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_PC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_callf */, -{ "if ( ! Pu4 ) callr Rs32" , "0101 0001 001sssss PP----uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* J2_callrf */, -{ "if ( ! Pu4 ) jump #r15:2" , "0101 1100 ii1iiiii PPi-0-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumpf */, -{ "if ( ! Pu4 ) jumpr Rs32" , "0101 0011 011sssss PP--0-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* J2_jumprf */, -{ "if ( ! Pu4 .new ) Rd32 = #s12" , "0111 1110 1uu0iiii PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmovenewif */, -{ "if ( ! Pu4 .new ) Rd32 = Rs32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrfnew)}, /* mapped to if (!Pu4.new) Rd32=add(Rs32,#0) */ -{ "if ( ! Pu4 .new ) Rd32 = add ( Rs32 , #s8 )" , "0111 0100 1uusssss PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_paddifnew */, -{ "if ( ! Pu4 .new ) Rd32 = add ( Rs32 , Rt32 )" , "1111 1011 0-0sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_paddfnew */, -{ "if ( ! Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )" , "1111 1001 -00sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_pandfnew */, -{ "if ( ! Pu4 .new ) Rd32 = aslh ( Rs32 )" , "0111 0000 000sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_paslhfnew */, -{ "if ( ! Pu4 .new ) Rd32 = asrh ( Rs32 )" , "0111 0000 001sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_pasrhfnew */, -{ "if ( ! Pu4 .new ) Rd32 = or ( Rs32 , Rt32 )" , "1111 1001 -01sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_porfnew */, -{ "if ( ! Pu4 .new ) Rd32 = sub ( Rt32 , Rs32 )" , "1111 1011 0-1sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_psubfnew */, -{ "if ( ! Pu4 .new ) Rd32 = sxtb ( Rs32 )" , "0111 0000 101sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_psxtbfnew */, -{ "if ( ! Pu4 .new ) Rd32 = sxth ( Rs32 )" , "0111 0000 111sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_psxthfnew */, -{ "if ( ! Pu4 .new ) Rd32 = xor ( Rs32 , Rt32 )" , "1111 1001 -11sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A2_pxorfnew */, -{ "if ( ! Pu4 .new ) Rd32 = zxtb ( Rs32 )" , "0111 0000 100sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_pzxtbfnew */, -{ "if ( ! Pu4 .new ) Rd32 = zxth ( Rs32 )" , "0111 0000 110sssss PP1-11uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* A4_pzxthfnew */, -{ "if ( ! Pu4 .new ) Rdd32 = Rss32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrpfnew)}, /* mapped to if (!Pu4.new) Rdd32=combine(Rss.H32,Rss.L32) */ -{ "if ( ! Pu4 .new ) Rdd32 = combine ( Rs32 , Rt32 )" , "1111 1101 ---sssss PP1ttttt 1uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_ROPS_2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* C2_ccombinewnewf */, -{ "if ( ! Pu4 .new ) jump:nt #r15:2" , "0101 1100 ii1iiiii PPi01-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_NOTE_CONDITIONAL|A_ARCHV2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumpfnew */, -{ "if ( ! Pu4 .new ) jump:t #r15:2" , "0101 1100 ii1iiiii PPi11-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_NOTE_CONDITIONAL|A_ARCHV2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumpfnewpt */, -{ "if ( ! Pu4 .new ) jumpr:nt Rs32" , "0101 0011 011sssss PP-01-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_ARCHV3|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* J2_jumprfnew */, -{ "if ( ! Pu4 .new ) jumpr:t Rs32" , "0101 0011 011sssss PP-11-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_ARCHV3|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* J2_jumprfnewpt */, -{ "if ( ! Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #0 )" , "0011 00 01 000 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrbf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #1 )" , "0011 00 01 000 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrbf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #2 )" , "0011 00 01 000 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrbf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #3 )" , "0011 00 01 000 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrbf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #0 )" , "0011 00 01 010 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrhf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #1 )" , "0011 00 01 010 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrhf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #2 )" , "0011 00 01 010 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrhf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #3 )" , "0011 00 01 010 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrhf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #0 )" , "0011 00 01 001 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrubf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #1 )" , "0011 00 01 001 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrubf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #2 )" , "0011 00 01 001 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrubf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #3 )" , "0011 00 01 001 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrubf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #0 )" , "0011 00 01 011 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadruhf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #1 )" , "0011 00 01 011 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadruhf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #2 )" , "0011 00 01 011 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadruhf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #3 )" , "0011 00 01 011 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadruhf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #0 )" , "0011 00 01 100 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrif_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #1 )" , "0011 00 01 100 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrif_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #2 )" , "0011 00 01 100 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrif_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #3 )" , "0011 00 01 100 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrif_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #0 )" , "0011 00 01 110 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrdf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #1 )" , "0011 00 01 110 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrdf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #2 )" , "0011 00 01 110 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrdf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #3 )" , "0011 00 01 110 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* L4_ploadrdf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) memb ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP000ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbnewf_abs */, -{ "if ( ! Pv4 ) memb ( #u6 ) = Rt32" , "1010 1 11 1 000 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbf_abs */, -{ "if ( ! Pv4 ) memb ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirbf_zomap)}, /* mapped to if (!Pv4) memb(Rs32+#0)=#S6 */ -{ "if ( ! Pv4 ) memb ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerbnewf_zomap)}, /* mapped to if (!Pv4) memb(Rs32+#0)=Nt8.new */ -{ "if ( ! Pv4 ) memb ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerbf_zomap)}, /* mapped to if (!Pv4) memb(Rs32+#0)=Rt32 */ -{ "if ( ! Pv4 ) memb ( Rs32 + #u6:0 ) = #S6" , "0011 100 01 00 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirbf_io */, -{ "if ( ! Pv4 ) memb ( Rs32 + #u6:0 ) = Nt8 .new" , "0100 0100 101 sssss PPi00ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerbnewf_io */, -{ "if ( ! Pv4 ) memb ( Rs32 + #u6:0 ) = Rt32" , "0100 0100 000 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerbf_io */, -{ "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbnewf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 01 000 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbnewf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 01 000 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbnewf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 01 000 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbnewf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 01 000 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerbf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP100ttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerbnewf_pi */, -{ "if ( ! Pv4 ) memb ( Rz32 ++ #s4:0 ) = Rt32" , "1010 1 01 1 000 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerbf_pi */, -{ "if ( ! Pv4 ) memd ( #u6 ) = Rtt32" , "1010 1 11 1 110 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerdf_abs */, -{ "if ( ! Pv4 ) memd ( Rs32 ) = Rtt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerdf_zomap)}, /* mapped to if (!Pv4) memd(Rs32+#0)=Rtt32 */ -{ "if ( ! Pv4 ) memd ( Rs32 + #u6:3 ) = Rtt32" , "0100 0100 110 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerdf_io */, -{ "if ( ! Pv4 ) memd ( Rs32 + Ru32 << #0 ) = Rtt32" , "0011 01 01 110 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerdf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) memd ( Rs32 + Ru32 << #1 ) = Rtt32" , "0011 01 01 110 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerdf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) memd ( Rs32 + Ru32 << #2 ) = Rtt32" , "0011 01 01 110 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerdf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) memd ( Rs32 + Ru32 << #3 ) = Rtt32" , "0011 01 01 110 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerdf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) memd ( Rz32 ++ #s4:3 ) = Rtt32" , "1010 1 01 1 110 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerdf_pi */, -{ "if ( ! Pv4 ) memh ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP001ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhnewf_abs */, -{ "if ( ! Pv4 ) memh ( #u6 ) = Rt32.h" , "1010 1 11 1 011 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerff_abs */, -{ "if ( ! Pv4 ) memh ( #u6 ) = Rt32" , "1010 1 11 1 010 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhf_abs */, -{ "if ( ! Pv4 ) memh ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirhf_zomap)}, /* mapped to if (!Pv4) memh(Rs32+#0)=#S6 */ -{ "if ( ! Pv4 ) memh ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerhnewf_zomap)}, /* mapped to if (!Pv4) memh(Rs32+#0)=Nt8.new */ -{ "if ( ! Pv4 ) memh ( Rs32 ) = Rt32.h" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerff_zomap)}, /* mapped to if (!Pv4) memh(Rs32+#0)=Rt32.h */ -{ "if ( ! Pv4 ) memh ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerhf_zomap)}, /* mapped to if (!Pv4) memh(Rs32+#0)=Rt32 */ -{ "if ( ! Pv4 ) memh ( Rs32 + #u6:1 ) = #S6" , "0011 100 01 01 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirhf_io */, -{ "if ( ! Pv4 ) memh ( Rs32 + #u6:1 ) = Nt8 .new" , "0100 0100 101 sssss PPi01ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerhnewf_io */, -{ "if ( ! Pv4 ) memh ( Rs32 + #u6:1 ) = Rt32.h" , "0100 0100 011 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerff_io */, -{ "if ( ! Pv4 ) memh ( Rs32 + #u6:1 ) = Rt32" , "0100 0100 010 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerhf_io */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhnewf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #0 ) = Rt32.h" , "0011 01 01 011 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerff_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 01 010 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhnewf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #1 ) = Rt32.h" , "0011 01 01 011 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerff_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 01 010 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhnewf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #2 ) = Rt32.h" , "0011 01 01 011 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerff_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 01 010 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhnewf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #3 ) = Rt32.h" , "0011 01 01 011 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerff_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 01 010 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerhf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP101ttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerhnewf_pi */, -{ "if ( ! Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" , "1010 1 01 1 011 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerff_pi */, -{ "if ( ! Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32" , "1010 1 01 1 010 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerhf_pi */, -{ "if ( ! Pv4 ) memw ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP010ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerinewf_abs */, -{ "if ( ! Pv4 ) memw ( #u6 ) = Rt32" , "1010 1 11 1 100 ---ii PP0ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerif_abs */, -{ "if ( ! Pv4 ) memw ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirif_zomap)}, /* mapped to if (!Pv4) memw(Rs32+#0)=#S6 */ -{ "if ( ! Pv4 ) memw ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerinewf_zomap)}, /* mapped to if (!Pv4) memw(Rs32+#0)=Nt8.new */ -{ "if ( ! Pv4 ) memw ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerif_zomap)}, /* mapped to if (!Pv4) memw(Rs32+#0)=Rt32 */ -{ "if ( ! Pv4 ) memw ( Rs32 + #u6:2 ) = #S6" , "0011 100 01 10 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirif_io */, -{ "if ( ! Pv4 ) memw ( Rs32 + #u6:2 ) = Nt8 .new" , "0100 0100 101 sssss PPi10ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerinewf_io */, -{ "if ( ! Pv4 ) memw ( Rs32 + #u6:2 ) = Rt32" , "0100 0100 100 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerif_io */, -{ "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerinewf_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 01 100 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerif_rr_expand_shamt_0 */, -{ "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 01 101 sssss PP0uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerinewf_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 01 100 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerif_rr_expand_shamt_1 */, -{ "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerinewf_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 01 100 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerif_rr_expand_shamt_2 */, -{ "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 01 101 sssss PP1uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerinewf_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 01 100 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S4_pstorerif_rr_expand_shamt_3 */, -{ "if ( ! Pv4 ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP110ttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerinewf_pi */, -{ "if ( ! Pv4 ) memw ( Rz32 ++ #s4:2 ) = Rt32" , "1010 1 01 1 100 zzzzz PP1ttttt 0iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED , NULL} /* S2_pstorerif_pi */, -{ "if ( ! Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #0 )" , "0011 00 11 000 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrbfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #1 )" , "0011 00 11 000 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrbfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #2 )" , "0011 00 11 000 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrbfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #3 )" , "0011 00 11 000 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrbfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #0 )" , "0011 00 11 010 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrhfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #1 )" , "0011 00 11 010 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrhfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #2 )" , "0011 00 11 010 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrhfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #3 )" , "0011 00 11 010 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrhfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #0 )" , "0011 00 11 001 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrubfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #1 )" , "0011 00 11 001 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrubfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #2 )" , "0011 00 11 001 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrubfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #3 )" , "0011 00 11 001 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrubfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #0 )" , "0011 00 11 011 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadruhfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #1 )" , "0011 00 11 011 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadruhfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #2 )" , "0011 00 11 011 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadruhfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #3 )" , "0011 00 11 011 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadruhfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #0 )" , "0011 00 11 100 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrifnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #1 )" , "0011 00 11 100 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrifnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #2 )" , "0011 00 11 100 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrifnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #3 )" , "0011 00 11 100 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrifnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #0 )" , "0011 00 11 110 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrdfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #1 )" , "0011 00 11 110 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrdfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #2 )" , "0011 00 11 110 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrdfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #3 )" , "0011 00 11 110 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* L4_ploadrdfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) memb ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP100ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbnewfnew_abs */, -{ "if ( ! Pv4 .new ) memb ( #u6 ) = Rt32" , "1010 1 11 1 000 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbfnew_abs */, -{ "if ( ! Pv4 .new ) memb ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirbfnew_zomap)}, /* mapped to if (!Pv4.new) memb(Rs32+#0)=#S6 */ -{ "if ( ! Pv4 .new ) memb ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerbnewfnew_zomap)}, /* mapped to if (!Pv4.new) memb(Rs32+#0)=Nt8.new */ -{ "if ( ! Pv4 .new ) memb ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerbfnew_zomap)}, /* mapped to if (!Pv4.new) memb(Rs32+#0)=Rt32 */ -{ "if ( ! Pv4 .new ) memb ( Rs32 + #u6:0 ) = #S6" , "0011 100 11 00 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirbfnew_io */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + #u6:0 ) = Nt8 .new" , "0100 0110 101 sssss PPi00ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerbnewfnew_io */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + #u6:0 ) = Rt32" , "0100 0110 000 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerbfnew_io */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbnewfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 11 000 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbnewfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 11 000 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbnewfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 11 000 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbnewfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 11 000 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerbfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP100ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerbnewfnew_pi */, -{ "if ( ! Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Rt32" , "1010 1 01 1 000 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerbfnew_pi */, -{ "if ( ! Pv4 .new ) memd ( #u6 ) = Rtt32" , "1010 1 11 1 110 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerdfnew_abs */, -{ "if ( ! Pv4 .new ) memd ( Rs32 ) = Rtt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerdfnew_zomap)}, /* mapped to if (!Pv4.new) memd(Rs32+#0)=Rtt32 */ -{ "if ( ! Pv4 .new ) memd ( Rs32 + #u6:3 ) = Rtt32" , "0100 0110 110 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerdfnew_io */, -{ "if ( ! Pv4 .new ) memd ( Rs32 + Ru32 << #0 ) = Rtt32" , "0011 01 11 110 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerdfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) memd ( Rs32 + Ru32 << #1 ) = Rtt32" , "0011 01 11 110 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerdfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) memd ( Rs32 + Ru32 << #2 ) = Rtt32" , "0011 01 11 110 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerdfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) memd ( Rs32 + Ru32 << #3 ) = Rtt32" , "0011 01 11 110 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerdfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) memd ( Rz32 ++ #s4:3 ) = Rtt32" , "1010 1 01 1 110 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerdfnew_pi */, -{ "if ( ! Pv4 .new ) memh ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP101ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhnewfnew_abs */, -{ "if ( ! Pv4 .new ) memh ( #u6 ) = Rt32.h" , "1010 1 11 1 011 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerffnew_abs */, -{ "if ( ! Pv4 .new ) memh ( #u6 ) = Rt32" , "1010 1 11 1 010 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhfnew_abs */, -{ "if ( ! Pv4 .new ) memh ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirhfnew_zomap)}, /* mapped to if (!Pv4.new) memh(Rs32+#0)=#S6 */ -{ "if ( ! Pv4 .new ) memh ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerhnewfnew_zomap)}, /* mapped to if (!Pv4.new) memh(Rs32+#0)=Nt8.new */ -{ "if ( ! Pv4 .new ) memh ( Rs32 ) = Rt32.h" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerffnew_zomap)}, /* mapped to if (!Pv4.new) memh(Rs32+#0)=Rt32.h */ -{ "if ( ! Pv4 .new ) memh ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerhfnew_zomap)}, /* mapped to if (!Pv4.new) memh(Rs32+#0)=Rt32 */ -{ "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1 ) = #S6" , "0011 100 11 01 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirhfnew_io */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1 ) = Nt8 .new" , "0100 0110 101 sssss PPi01ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerhnewfnew_io */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1 ) = Rt32.h" , "0100 0110 011 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerffnew_io */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1 ) = Rt32" , "0100 0110 010 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerhfnew_io */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhnewfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #0 ) = Rt32.h" , "0011 01 11 011 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerffnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 11 010 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhnewfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #1 ) = Rt32.h" , "0011 01 11 011 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerffnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 11 010 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhnewfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #2 ) = Rt32.h" , "0011 01 11 011 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerffnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 11 010 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhnewfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #3 ) = Rt32.h" , "0011 01 11 011 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerffnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 11 010 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerhfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP101ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerhnewfnew_pi */, -{ "if ( ! Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" , "1010 1 01 1 011 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerffnew_pi */, -{ "if ( ! Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32" , "1010 1 01 1 010 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerhfnew_pi */, -{ "if ( ! Pv4 .new ) memw ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP110ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerinewfnew_abs */, -{ "if ( ! Pv4 .new ) memw ( #u6 ) = Rt32" , "1010 1 11 1 100 ---ii PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerifnew_abs */, -{ "if ( ! Pv4 .new ) memw ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirifnew_zomap)}, /* mapped to if (!Pv4.new) memw(Rs32+#0)=#S6 */ -{ "if ( ! Pv4 .new ) memw ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerinewfnew_zomap)}, /* mapped to if (!Pv4.new) memw(Rs32+#0)=Nt8.new */ -{ "if ( ! Pv4 .new ) memw ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerifnew_zomap)}, /* mapped to if (!Pv4.new) memw(Rs32+#0)=Rt32 */ -{ "if ( ! Pv4 .new ) memw ( Rs32 + #u6:2 ) = #S6" , "0011 100 11 10 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirifnew_io */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + #u6:2 ) = Nt8 .new" , "0100 0110 101 sssss PPi10ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerinewfnew_io */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + #u6:2 ) = Rt32" , "0100 0110 100 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerifnew_io */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerinewfnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 11 100 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerifnew_rr_expand_shamt_0 */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 11 101 sssss PP0uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerinewfnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 11 100 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerifnew_rr_expand_shamt_1 */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerinewfnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 11 100 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerifnew_rr_expand_shamt_2 */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 11 101 sssss PP1uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerinewfnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 11 100 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S4_pstorerifnew_rr_expand_shamt_3 */, -{ "if ( ! Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP110ttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerinewfnew_pi */, -{ "if ( ! Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Rt32" , "1010 1 01 1 100 zzzzz PP1ttttt 1iiii1vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW, NULL} /* S2_pstorerifnew_pi */, -{ "if ( ! cmp.eq ( Ns8 .new , #-1 ) ) jump:nt #r9:2" , "0010 -1 100 1ii-sss PP0----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_f_jumpnv_nt */, -{ "if ( ! cmp.eq ( Ns8 .new , #-1 ) ) jump:t #r9:2" , "0010 -1 100 1ii-sss PP1----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_f_jumpnv_t */, -{ "if ( ! cmp.eq ( Ns8 .new , #U5 ) ) jump:nt #r9:2" , "0010 -1 000 1ii-sss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_f_jumpnv_nt */, -{ "if ( ! cmp.eq ( Ns8 .new , #U5 ) ) jump:t #r9:2" , "0010 -1 000 1ii-sss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_f_jumpnv_t */, -{ "if ( ! cmp.eq ( Ns8 .new , Rt32 ) ) jump:nt #r9:2" , "0010 -0 000 1ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_f_jumpnv_nt */, -{ "if ( ! cmp.eq ( Ns8 .new , Rt32 ) ) jump:t #r9:2" , "0010 -0 000 1ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_f_jumpnv_t */, -{ "if ( ! cmp.gt ( Ns8 .new , #-1 ) ) jump:nt #r9:2" , "0010 -1 101 1ii-sss PP0----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_f_jumpnv_nt */, -{ "if ( ! cmp.gt ( Ns8 .new , #-1 ) ) jump:t #r9:2" , "0010 -1 101 1ii-sss PP1----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_f_jumpnv_t */, -{ "if ( ! cmp.gt ( Ns8 .new , #U5 ) ) jump:nt #r9:2" , "0010 -1 001 1ii-sss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_f_jumpnv_nt */, -{ "if ( ! cmp.gt ( Ns8 .new , #U5 ) ) jump:t #r9:2" , "0010 -1 001 1ii-sss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_f_jumpnv_t */, -{ "if ( ! cmp.gt ( Ns8 .new , Rt32 ) ) jump:nt #r9:2" , "0010 -0 001 1ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_f_jumpnv_nt */, -{ "if ( ! cmp.gt ( Ns8 .new , Rt32 ) ) jump:t #r9:2" , "0010 -0 001 1ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_f_jumpnv_t */, -{ "if ( ! cmp.gt ( Rt32 , Ns8 .new ) ) jump:nt #r9:2" , "0010 -0 011 1ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmplt_f_jumpnv_nt */, -{ "if ( ! cmp.gt ( Rt32 , Ns8 .new ) ) jump:t #r9:2" , "0010 -0 011 1ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmplt_f_jumpnv_t */, -{ "if ( ! cmp.gtu ( Ns8 .new , #U5 ) ) jump:nt #r9:2" , "0010 -1 010 1ii-sss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_f_jumpnv_nt */, -{ "if ( ! cmp.gtu ( Ns8 .new , #U5 ) ) jump:t #r9:2" , "0010 -1 010 1ii-sss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_f_jumpnv_t */, -{ "if ( ! cmp.gtu ( Ns8 .new , Rt32 ) ) jump:nt #r9:2" , "0010 -0 010 1ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_f_jumpnv_nt */, -{ "if ( ! cmp.gtu ( Ns8 .new , Rt32 ) ) jump:t #r9:2" , "0010 -0 010 1ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_f_jumpnv_t */, -{ "if ( ! cmp.gtu ( Rt32 , Ns8 .new ) ) jump:nt #r9:2" , "0010 -0 100 1ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpltu_f_jumpnv_nt */, -{ "if ( ! cmp.gtu ( Rt32 , Ns8 .new ) ) jump:t #r9:2" , "0010 -0 100 1ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpltu_f_jumpnv_t */, -{ "if ( ! p0 ) Rd16 = #0 ; allocframe ( #u5:3 )" , "0111101--111ddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS2_allocframe */, -{ "if ( ! p0 ) Rd16 = #0 ; dealloc_return" , "0101101--111ddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_return */, -{ "if ( ! p0 ) Rd16 = #0 ; deallocframe" , "0101101--111ddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_deallocframe */, -{ "if ( ! p0 ) Rd16 = #0 ; if ( ! p0 ) dealloc_return" , "0101101--111ddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_return_f */, -{ "if ( ! p0 ) Rd16 = #0 ; if ( ! p0 ) jumpr Lr" , "0101101--111ddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_jumpr31_f */, -{ "if ( ! p0 ) Rd16 = #0 ; if ( ! p0 .new ) dealloc_return:nt" , "0101101--111ddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_return_fnew */, -{ "if ( ! p0 ) Rd16 = #0 ; if ( ! p0 .new ) jumpr:nt Lr" , "0101101--111ddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_jumpr31_fnew */, -{ "if ( ! p0 ) Rd16 = #0 ; if ( p0 ) dealloc_return" , "0101101--111ddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_return_t */, -{ "if ( ! p0 ) Rd16 = #0 ; if ( p0 ) jumpr Lr" , "0101101--111ddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_jumpr31_t */, -{ "if ( ! p0 ) Rd16 = #0 ; if ( p0 .new ) dealloc_return:nt" , "0101101--111ddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_return_tnew */, -{ "if ( ! p0 ) Rd16 = #0 ; if ( p0 .new ) jumpr:nt Lr" , "0101101--111ddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_jumpr31_tnew */, -{ "if ( ! p0 ) Rd16 = #0 ; jumpr Lr" , "0101101--111ddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_jumpr31 */, -{ "if ( ! p0 ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = #0" , "0111101--111ddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS2_storebi0 */, -{ "if ( ! p0 ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = #1" , "0111101--111ddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS2_storebi1 */, -{ "if ( ! p0 ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = Rt16" , "0111101--111ddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS1_storeb_io */, -{ "if ( ! p0 ) Rd16 = #0 ; memd ( Sp + #s6:3 ) = Rtt8" , "0111101--111ddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS2_stored_sp */, -{ "if ( ! p0 ) Rd16 = #0 ; memh ( Rs16 + #u3:1 ) = Rt16" , "0111101--111ddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS2_storeh_io */, -{ "if ( ! p0 ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = #0" , "0111101--111ddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS2_storewi0 */, -{ "if ( ! p0 ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = #1" , "0111101--111ddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS2_storewi1 */, -{ "if ( ! p0 ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = Rt16" , "0111101--111ddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS1_storew_io */, -{ "if ( ! p0 ) Rd16 = #0 ; memw ( Sp + #u5:2 ) = Rt16" , "0111101--111ddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SS2_storew_sp */, -{ "if ( ! p0 ) Re16 = #0 ; Rd16 = memb ( Rs16 + #u3:0 )" , "0101101--111eeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_loadrb_io */, -{ "if ( ! p0 ) Re16 = #0 ; Rd16 = memh ( Rs16 + #u3:1 )" , "0101101--111eeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_loadrh_io */, -{ "if ( ! p0 ) Re16 = #0 ; Rd16 = memub ( Rs16 + #u4:0 )" , "0101101--111eeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL1_loadrub_io */, -{ "if ( ! p0 ) Re16 = #0 ; Rd16 = memuh ( Rs16 + #u3:1 )" , "0101101--111eeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_loadruh_io */, -{ "if ( ! p0 ) Re16 = #0 ; Rd16 = memw ( Rs16 + #u4:2 )" , "0101101--111eeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL1_loadri_io */, -{ "if ( ! p0 ) Re16 = #0 ; Rd16 = memw ( Sp + #u5:2 )" , "0101101--111eeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_loadri_sp */, -{ "if ( ! p0 ) Re16 = #0 ; Rdd8 = combine ( #0 , #u2 )" , "0011101--111eeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SA1_combine0i */, -{ "if ( ! p0 ) Re16 = #0 ; Rdd8 = combine ( #0 , Rs16 )" , "0011101--111eeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SA1_combinezr */, -{ "if ( ! p0 ) Re16 = #0 ; Rdd8 = combine ( #1 , #u2 )" , "0011101--111eeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SA1_combine1i */, -{ "if ( ! p0 ) Re16 = #0 ; Rdd8 = combine ( #2 , #u2 )" , "0011101--111eeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SA1_combine2i */, -{ "if ( ! p0 ) Re16 = #0 ; Rdd8 = combine ( #3 , #u2 )" , "0011101--111eeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SA1_combine3i */, -{ "if ( ! p0 ) Re16 = #0 ; Rdd8 = combine ( Rs16 , #0 )" , "0011101--111eeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SA1_combinerz */, -{ "if ( ! p0 ) Re16 = #0 ; Rdd8 = memd ( Sp + #u5:3 )" , "0101101--111eeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SL2_loadrd_sp */, -{ "if ( ! p0 ) Re16 = #0 ; if ( ! p0 ) Rd16 = #0" , "0011101--111eeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrf_SA1_clrf */, -{ "if ( ! p0 .new ) Rd16 = #0 ; allocframe ( #u5:3 )" , "0111101--101ddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS2_allocframe */, -{ "if ( ! p0 .new ) Rd16 = #0 ; dealloc_return" , "0101101--101ddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_return */, -{ "if ( ! p0 .new ) Rd16 = #0 ; deallocframe" , "0101101--101ddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_deallocframe */, -{ "if ( ! p0 .new ) Rd16 = #0 ; if ( ! p0 ) dealloc_return" , "0101101--101ddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_return_f */, -{ "if ( ! p0 .new ) Rd16 = #0 ; if ( ! p0 ) jumpr Lr" , "0101101--101ddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_jumpr31_f */, -{ "if ( ! p0 .new ) Rd16 = #0 ; if ( ! p0 .new ) dealloc_return:nt" , "0101101--101ddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_return_fnew */, -{ "if ( ! p0 .new ) Rd16 = #0 ; if ( ! p0 .new ) jumpr:nt Lr" , "0101101--101ddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_jumpr31_fnew */, -{ "if ( ! p0 .new ) Rd16 = #0 ; if ( p0 ) dealloc_return" , "0101101--101ddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_return_t */, -{ "if ( ! p0 .new ) Rd16 = #0 ; if ( p0 ) jumpr Lr" , "0101101--101ddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_jumpr31_t */, -{ "if ( ! p0 .new ) Rd16 = #0 ; if ( p0 .new ) dealloc_return:nt" , "0101101--101ddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_return_tnew */, -{ "if ( ! p0 .new ) Rd16 = #0 ; if ( p0 .new ) jumpr:nt Lr" , "0101101--101ddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_jumpr31_tnew */, -{ "if ( ! p0 .new ) Rd16 = #0 ; jumpr Lr" , "0101101--101ddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_jumpr31 */, -{ "if ( ! p0 .new ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = #0" , "0111101--101ddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS2_storebi0 */, -{ "if ( ! p0 .new ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = #1" , "0111101--101ddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS2_storebi1 */, -{ "if ( ! p0 .new ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = Rt16" , "0111101--101ddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS1_storeb_io */, -{ "if ( ! p0 .new ) Rd16 = #0 ; memd ( Sp + #s6:3 ) = Rtt8" , "0111101--101ddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS2_stored_sp */, -{ "if ( ! p0 .new ) Rd16 = #0 ; memh ( Rs16 + #u3:1 ) = Rt16" , "0111101--101ddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS2_storeh_io */, -{ "if ( ! p0 .new ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = #0" , "0111101--101ddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS2_storewi0 */, -{ "if ( ! p0 .new ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = #1" , "0111101--101ddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS2_storewi1 */, -{ "if ( ! p0 .new ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = Rt16" , "0111101--101ddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS1_storew_io */, -{ "if ( ! p0 .new ) Rd16 = #0 ; memw ( Sp + #u5:2 ) = Rt16" , "0111101--101ddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SS2_storew_sp */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rd16 = memb ( Rs16 + #u3:0 )" , "0101101--101eeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_loadrb_io */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rd16 = memh ( Rs16 + #u3:1 )" , "0101101--101eeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_loadrh_io */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rd16 = memub ( Rs16 + #u4:0 )" , "0101101--101eeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL1_loadrub_io */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rd16 = memuh ( Rs16 + #u3:1 )" , "0101101--101eeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_loadruh_io */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rd16 = memw ( Rs16 + #u4:2 )" , "0101101--101eeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL1_loadri_io */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rd16 = memw ( Sp + #u5:2 )" , "0101101--101eeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_loadri_sp */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rdd8 = combine ( #0 , #u2 )" , "0011101--101eeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SA1_combine0i */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rdd8 = combine ( #0 , Rs16 )" , "0011101--101eeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SA1_combinezr */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rdd8 = combine ( #1 , #u2 )" , "0011101--101eeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SA1_combine1i */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rdd8 = combine ( #2 , #u2 )" , "0011101--101eeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SA1_combine2i */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rdd8 = combine ( #3 , #u2 )" , "0011101--101eeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SA1_combine3i */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rdd8 = combine ( Rs16 , #0 )" , "0011101--101eeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SA1_combinerz */, -{ "if ( ! p0 .new ) Re16 = #0 ; Rdd8 = memd ( Sp + #u5:3 )" , "0101101--101eeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SL2_loadrd_sp */, -{ "if ( ! p0 .new ) Re16 = #0 ; if ( ! p0 ) Rd16 = #0" , "0011101--101eeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SA1_clrf */, -{ "if ( ! p0 .new ) Re16 = #0 ; if ( ! p0 .new ) Rd16 = #0" , "0011101--101eeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SA1_clrfnew */, -{ "if ( ! p0 .new ) Re16 = #0 ; if ( p0 ) Rd16 = #0" , "0011101--101eeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrfnew_SA1_clrt */, -{ "if ( ! tstbit ( Ns8 .new , #0 ) ) jump:nt #r9:2" , "0010 -1 011 1ii-sss PP0----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_f_jumpnv_nt */, -{ "if ( ! tstbit ( Ns8 .new , #0 ) ) jump:t #r9:2" , "0010 -1 011 1ii-sss PP1----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_f_jumpnv_t */, -{ "if ( Ps4 ) dealloc_return" , "1001 011 0 000 11110 PP0100ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_7|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_return_t */, -{ "if ( Ps4 .new ) dealloc_return:nt" , "1001 011 0 000 11110 PP0010ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_12|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_return_tnew_pnt */, -{ "if ( Ps4 .new ) dealloc_return:t" , "1001 011 0 000 11110 PP0110ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_12|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_return_tnew_pt */, -{ "if ( Pt4 ) Rd32 = memb ( #u6 )" , "1001 1 11 1 000 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrbt_abs */, -{ "if ( Pt4 ) Rd32 = memb ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrbt_zomap)}, /* mapped to if (Pt4) Rd32=memb(Rs32+#0) */ -{ "if ( Pt4 ) Rd32 = memb ( Rs32 + #u6:0 )" , "0100 0001 000 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrbt_io */, -{ "if ( Pt4 ) Rd32 = memb ( Rz32 ++ #s4:0 )" , "1001 1 01 1 000 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrbt_pi */, -{ "if ( Pt4 ) Rd32 = memh ( #u6 )" , "1001 1 11 1 010 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrht_abs */, -{ "if ( Pt4 ) Rd32 = memh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrht_zomap)}, /* mapped to if (Pt4) Rd32=memh(Rs32+#0) */ -{ "if ( Pt4 ) Rd32 = memh ( Rs32 + #u6:1 )" , "0100 0001 010 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrht_io */, -{ "if ( Pt4 ) Rd32 = memh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 010 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrht_pi */, -{ "if ( Pt4 ) Rd32 = memub ( #u6 )" , "1001 1 11 1 001 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrubt_abs */, -{ "if ( Pt4 ) Rd32 = memub ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrubt_zomap)}, /* mapped to if (Pt4) Rd32=memub(Rs32+#0) */ -{ "if ( Pt4 ) Rd32 = memub ( Rs32 + #u6:0 )" , "0100 0001 001 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrubt_io */, -{ "if ( Pt4 ) Rd32 = memub ( Rz32 ++ #s4:0 )" , "1001 1 01 1 001 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrubt_pi */, -{ "if ( Pt4 ) Rd32 = memuh ( #u6 )" , "1001 1 11 1 011 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadruht_abs */, -{ "if ( Pt4 ) Rd32 = memuh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadruht_zomap)}, /* mapped to if (Pt4) Rd32=memuh(Rs32+#0) */ -{ "if ( Pt4 ) Rd32 = memuh ( Rs32 + #u6:1 )" , "0100 0001 011 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadruht_io */, -{ "if ( Pt4 ) Rd32 = memuh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 011 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadruht_pi */, -{ "if ( Pt4 ) Rd32 = memw ( #u6 )" , "1001 1 11 1 100 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrit_abs */, -{ "if ( Pt4 ) Rd32 = memw ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrit_zomap)}, /* mapped to if (Pt4) Rd32=memw(Rs32+#0) */ -{ "if ( Pt4 ) Rd32 = memw ( Rs32 + #u6:2 )" , "0100 0001 100 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrit_io */, -{ "if ( Pt4 ) Rd32 = memw ( Rz32 ++ #s4:2 )" , "1001 1 01 1 100 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrit_pi */, -{ "if ( Pt4 ) Rdd32 = memd ( #u6 )" , "1001 1 11 1 110 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrdt_abs */, -{ "if ( Pt4 ) Rdd32 = memd ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrdt_zomap)}, /* mapped to if (Pt4) Rdd32=memd(Rs32+#0) */ -{ "if ( Pt4 ) Rdd32 = memd ( Rs32 + #u6:3 )" , "0100 0001 110 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrdt_io */, -{ "if ( Pt4 ) Rdd32 = memd ( Rz32 ++ #s4:3 )" , "1001 1 01 1 110 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrdt_pi */, -{ "if ( Pt4 .new ) Rd32 = memb ( #u6 )" , "1001 1 11 1 000 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrbtnew_abs */, -{ "if ( Pt4 .new ) Rd32 = memb ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrbtnew_zomap)}, /* mapped to if (Pt4.new) Rd32=memb(Rs32+#0) */ -{ "if ( Pt4 .new ) Rd32 = memb ( Rs32 + #u6:0 )" , "0100 0011 000 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrbtnew_io */, -{ "if ( Pt4 .new ) Rd32 = memb ( Rz32 ++ #s4:0 )" , "1001 1 01 1 000 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadrbtnew_pi */, -{ "if ( Pt4 .new ) Rd32 = memh ( #u6 )" , "1001 1 11 1 010 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrhtnew_abs */, -{ "if ( Pt4 .new ) Rd32 = memh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrhtnew_zomap)}, /* mapped to if (Pt4.new) Rd32=memh(Rs32+#0) */ -{ "if ( Pt4 .new ) Rd32 = memh ( Rs32 + #u6:1 )" , "0100 0011 010 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrhtnew_io */, -{ "if ( Pt4 .new ) Rd32 = memh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 010 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadrhtnew_pi */, -{ "if ( Pt4 .new ) Rd32 = memub ( #u6 )" , "1001 1 11 1 001 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrubtnew_abs */, -{ "if ( Pt4 .new ) Rd32 = memub ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrubtnew_zomap)}, /* mapped to if (Pt4.new) Rd32=memub(Rs32+#0) */ -{ "if ( Pt4 .new ) Rd32 = memub ( Rs32 + #u6:0 )" , "0100 0011 001 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrubtnew_io */, -{ "if ( Pt4 .new ) Rd32 = memub ( Rz32 ++ #s4:0 )" , "1001 1 01 1 001 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadrubtnew_pi */, -{ "if ( Pt4 .new ) Rd32 = memuh ( #u6 )" , "1001 1 11 1 011 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadruhtnew_abs */, -{ "if ( Pt4 .new ) Rd32 = memuh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadruhtnew_zomap)}, /* mapped to if (Pt4.new) Rd32=memuh(Rs32+#0) */ -{ "if ( Pt4 .new ) Rd32 = memuh ( Rs32 + #u6:1 )" , "0100 0011 011 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadruhtnew_io */, -{ "if ( Pt4 .new ) Rd32 = memuh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 011 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadruhtnew_pi */, -{ "if ( Pt4 .new ) Rd32 = memw ( #u6 )" , "1001 1 11 1 100 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadritnew_abs */, -{ "if ( Pt4 .new ) Rd32 = memw ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadritnew_zomap)}, /* mapped to if (Pt4.new) Rd32=memw(Rs32+#0) */ -{ "if ( Pt4 .new ) Rd32 = memw ( Rs32 + #u6:2 )" , "0100 0011 100 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadritnew_io */, -{ "if ( Pt4 .new ) Rd32 = memw ( Rz32 ++ #s4:2 )" , "1001 1 01 1 100 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadritnew_pi */, -{ "if ( Pt4 .new ) Rdd32 = memd ( #u6 )" , "1001 1 11 1 110 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrdtnew_abs */, -{ "if ( Pt4 .new ) Rdd32 = memd ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrdtnew_zomap)}, /* mapped to if (Pt4.new) Rdd32=memd(Rs32+#0) */ -{ "if ( Pt4 .new ) Rdd32 = memd ( Rs32 + #u6:3 )" , "0100 0011 110 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrdtnew_io */, -{ "if ( Pt4 .new ) Rdd32 = memd ( Rz32 ++ #s4:3 )" , "1001 1 01 1 110 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadrdtnew_pi */, -{ "if ( Pu4 ) Rd32 = #s12" , "0111 1110 0uu0iiii PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmoveit */, -{ "if ( Pu4 ) Rd32 = Rs32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrt)}, /* mapped to if (Pu4) Rd32=add(Rs32,#0) */ -{ "if ( Pu4 ) Rd32 = add ( Rs32 , #s8 )" , "0111 0100 0uusssss PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_paddit */, -{ "if ( Pu4 ) Rd32 = add ( Rs32 , Rt32 )" , "1111 1011 0-0sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_paddt */, -{ "if ( Pu4 ) Rd32 = and ( Rs32 , Rt32 )" , "1111 1001 -00sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_pandt */, -{ "if ( Pu4 ) Rd32 = aslh ( Rs32 )" , "0111 0000 000sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_paslht */, -{ "if ( Pu4 ) Rd32 = asrh ( Rs32 )" , "0111 0000 001sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_pasrht */, -{ "if ( Pu4 ) Rd32 = or ( Rs32 , Rt32 )" , "1111 1001 -01sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_port */, -{ "if ( Pu4 ) Rd32 = sub ( Rt32 , Rs32 )" , "1111 1011 0-1sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_psubt */, -{ "if ( Pu4 ) Rd32 = sxtb ( Rs32 )" , "0111 0000 101sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_psxtbt */, -{ "if ( Pu4 ) Rd32 = sxth ( Rs32 )" , "0111 0000 111sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_psxtht */, -{ "if ( Pu4 ) Rd32 = xor ( Rs32 , Rt32 )" , "1111 1001 -11sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_pxort */, -{ "if ( Pu4 ) Rd32 = zxtb ( Rs32 )" , "0111 0000 100sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_pzxtbt */, -{ "if ( Pu4 ) Rd32 = zxth ( Rs32 )" , "0111 0000 110sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_pzxtht */, -{ "if ( Pu4 ) Rdd32 = Rss32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrpt)}, /* mapped to if (Pu4) Rdd32=combine(Rss.H32,Rss.L32) */ -{ "if ( Pu4 ) Rdd32 = combine ( Rs32 , Rt32 )" , "1111 1101 ---sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_ROPS_2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* C2_ccombinewt */, -{ "if ( Pu4 ) call #r15:2" , "0101 1101 ii0iiiii PPi-0-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_DIRECT|A_NOTE_PACKET_PC|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_NOTE_CONDITIONAL|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_PC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_callt */, -{ "if ( Pu4 ) callr Rs32" , "0101 0001 000sssss PP----uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* J2_callrt */, -{ "if ( Pu4 ) jump #r15:2" , "0101 1100 ii0iiiii PPi-0-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumpt */, -{ "if ( Pu4 ) jumpr Rs32" , "0101 0011 010sssss PP--0-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprt */, -{ "if ( Pu4 .new ) Rd32 = #s12" , "0111 1110 0uu0iiii PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmovenewit */, -{ "if ( Pu4 .new ) Rd32 = Rs32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrtnew)}, /* mapped to if (Pu4.new) Rd32=add(Rs32,#0) */ -{ "if ( Pu4 .new ) Rd32 = add ( Rs32 , #s8 )" , "0111 0100 0uusssss PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_padditnew */, -{ "if ( Pu4 .new ) Rd32 = add ( Rs32 , Rt32 )" , "1111 1011 0-0sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_paddtnew */, -{ "if ( Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )" , "1111 1001 -00sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_pandtnew */, -{ "if ( Pu4 .new ) Rd32 = aslh ( Rs32 )" , "0111 0000 000sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_paslhtnew */, -{ "if ( Pu4 .new ) Rd32 = asrh ( Rs32 )" , "0111 0000 001sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_pasrhtnew */, -{ "if ( Pu4 .new ) Rd32 = or ( Rs32 , Rt32 )" , "1111 1001 -01sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_portnew */, -{ "if ( Pu4 .new ) Rd32 = sub ( Rt32 , Rs32 )" , "1111 1011 0-1sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_psubtnew */, -{ "if ( Pu4 .new ) Rd32 = sxtb ( Rs32 )" , "0111 0000 101sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_psxtbtnew */, -{ "if ( Pu4 .new ) Rd32 = sxth ( Rs32 )" , "0111 0000 111sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_psxthtnew */, -{ "if ( Pu4 .new ) Rd32 = xor ( Rs32 , Rt32 )" , "1111 1001 -11sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_pxortnew */, -{ "if ( Pu4 .new ) Rd32 = zxtb ( Rs32 )" , "0111 0000 100sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_pzxtbtnew */, -{ "if ( Pu4 .new ) Rd32 = zxth ( Rs32 )" , "0111 0000 110sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_pzxthtnew */, -{ "if ( Pu4 .new ) Rdd32 = Rss32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrptnew)}, /* mapped to if (Pu4.new) Rdd32=combine(Rss.H32,Rss.L32) */ -{ "if ( Pu4 .new ) Rdd32 = combine ( Rs32 , Rt32 )" , "1111 1101 ---sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ROPS_2|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* C2_ccombinewnewt */, -{ "if ( Pu4 .new ) jump:nt #r15:2" , "0101 1100 ii0iiiii PPi01-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_NOTE_CONDITIONAL|A_ARCHV2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumptnew */, -{ "if ( Pu4 .new ) jump:t #r15:2" , "0101 1100 ii0iiiii PPi11-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_NOTE_CONDITIONAL|A_ARCHV2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumptnewpt */, -{ "if ( Pu4 .new ) jumpr:nt Rs32" , "0101 0011 010sssss PP-01-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_ARCHV3|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* J2_jumprtnew */, -{ "if ( Pu4 .new ) jumpr:t Rs32" , "0101 0011 010sssss PP-11-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_ARCHV3|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* J2_jumprtnewpt */, -{ "if ( Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #0 )" , "0011 00 00 000 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrbt_rr_expand_shamt_0 */, -{ "if ( Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #1 )" , "0011 00 00 000 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrbt_rr_expand_shamt_1 */, -{ "if ( Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #2 )" , "0011 00 00 000 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrbt_rr_expand_shamt_2 */, -{ "if ( Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #3 )" , "0011 00 00 000 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrbt_rr_expand_shamt_3 */, -{ "if ( Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #0 )" , "0011 00 00 010 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrht_rr_expand_shamt_0 */, -{ "if ( Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #1 )" , "0011 00 00 010 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrht_rr_expand_shamt_1 */, -{ "if ( Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #2 )" , "0011 00 00 010 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrht_rr_expand_shamt_2 */, -{ "if ( Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #3 )" , "0011 00 00 010 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrht_rr_expand_shamt_3 */, -{ "if ( Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #0 )" , "0011 00 00 001 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrubt_rr_expand_shamt_0 */, -{ "if ( Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #1 )" , "0011 00 00 001 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrubt_rr_expand_shamt_1 */, -{ "if ( Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #2 )" , "0011 00 00 001 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrubt_rr_expand_shamt_2 */, -{ "if ( Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #3 )" , "0011 00 00 001 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrubt_rr_expand_shamt_3 */, -{ "if ( Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #0 )" , "0011 00 00 011 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadruht_rr_expand_shamt_0 */, -{ "if ( Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #1 )" , "0011 00 00 011 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadruht_rr_expand_shamt_1 */, -{ "if ( Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #2 )" , "0011 00 00 011 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadruht_rr_expand_shamt_2 */, -{ "if ( Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #3 )" , "0011 00 00 011 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadruht_rr_expand_shamt_3 */, -{ "if ( Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #0 )" , "0011 00 00 100 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrit_rr_expand_shamt_0 */, -{ "if ( Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #1 )" , "0011 00 00 100 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrit_rr_expand_shamt_1 */, -{ "if ( Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #2 )" , "0011 00 00 100 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrit_rr_expand_shamt_2 */, -{ "if ( Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #3 )" , "0011 00 00 100 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrit_rr_expand_shamt_3 */, -{ "if ( Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #0 )" , "0011 00 00 110 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrdt_rr_expand_shamt_0 */, -{ "if ( Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #1 )" , "0011 00 00 110 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrdt_rr_expand_shamt_1 */, -{ "if ( Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #2 )" , "0011 00 00 110 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrdt_rr_expand_shamt_2 */, -{ "if ( Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #3 )" , "0011 00 00 110 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrdt_rr_expand_shamt_3 */, -{ "if ( Pv4 ) memb ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP000ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbnewt_abs */, -{ "if ( Pv4 ) memb ( #u6 ) = Rt32" , "1010 1 11 1 000 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbt_abs */, -{ "if ( Pv4 ) memb ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirbt_zomap)}, /* mapped to if (Pv4) memb(Rs32+#0)=#S6 */ -{ "if ( Pv4 ) memb ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerbnewt_zomap)}, /* mapped to if (Pv4) memb(Rs32+#0)=Nt8.new */ -{ "if ( Pv4 ) memb ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerbt_zomap)}, /* mapped to if (Pv4) memb(Rs32+#0)=Rt32 */ -{ "if ( Pv4 ) memb ( Rs32 + #u6:0 ) = #S6" , "0011 100 00 00 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirbt_io */, -{ "if ( Pv4 ) memb ( Rs32 + #u6:0 ) = Nt8 .new" , "0100 0000 101 sssss PPi00ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerbnewt_io */, -{ "if ( Pv4 ) memb ( Rs32 + #u6:0 ) = Rt32" , "0100 0000 000 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerbt_io */, -{ "if ( Pv4 ) memb ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerbnewt_rr_expand_shamt_0 */, -{ "if ( Pv4 ) memb ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 00 000 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerbt_rr_expand_shamt_0 */, -{ "if ( Pv4 ) memb ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerbnewt_rr_expand_shamt_1 */, -{ "if ( Pv4 ) memb ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 00 000 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerbt_rr_expand_shamt_1 */, -{ "if ( Pv4 ) memb ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerbnewt_rr_expand_shamt_2 */, -{ "if ( Pv4 ) memb ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 00 000 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerbt_rr_expand_shamt_2 */, -{ "if ( Pv4 ) memb ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerbnewt_rr_expand_shamt_3 */, -{ "if ( Pv4 ) memb ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 00 000 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerbt_rr_expand_shamt_3 */, -{ "if ( Pv4 ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP100ttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S2_pstorerbnewt_pi */, -{ "if ( Pv4 ) memb ( Rz32 ++ #s4:0 ) = Rt32" , "1010 1 01 1 000 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerbt_pi */, -{ "if ( Pv4 ) memd ( #u6 ) = Rtt32" , "1010 1 11 1 110 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerdt_abs */, -{ "if ( Pv4 ) memd ( Rs32 ) = Rtt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerdt_zomap)}, /* mapped to if (Pv4) memd(Rs32+#0)=Rtt32 */ -{ "if ( Pv4 ) memd ( Rs32 + #u6:3 ) = Rtt32" , "0100 0000 110 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerdt_io */, -{ "if ( Pv4 ) memd ( Rs32 + Ru32 << #0 ) = Rtt32" , "0011 01 00 110 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerdt_rr_expand_shamt_0 */, -{ "if ( Pv4 ) memd ( Rs32 + Ru32 << #1 ) = Rtt32" , "0011 01 00 110 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerdt_rr_expand_shamt_1 */, -{ "if ( Pv4 ) memd ( Rs32 + Ru32 << #2 ) = Rtt32" , "0011 01 00 110 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerdt_rr_expand_shamt_2 */, -{ "if ( Pv4 ) memd ( Rs32 + Ru32 << #3 ) = Rtt32" , "0011 01 00 110 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerdt_rr_expand_shamt_3 */, -{ "if ( Pv4 ) memd ( Rz32 ++ #s4:3 ) = Rtt32" , "1010 1 01 1 110 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerdt_pi */, -{ "if ( Pv4 ) memh ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP001ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhnewt_abs */, -{ "if ( Pv4 ) memh ( #u6 ) = Rt32.h" , "1010 1 11 1 011 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerft_abs */, -{ "if ( Pv4 ) memh ( #u6 ) = Rt32" , "1010 1 11 1 010 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerht_abs */, -{ "if ( Pv4 ) memh ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirht_zomap)}, /* mapped to if (Pv4) memh(Rs32+#0)=#S6 */ -{ "if ( Pv4 ) memh ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerhnewt_zomap)}, /* mapped to if (Pv4) memh(Rs32+#0)=Nt8.new */ -{ "if ( Pv4 ) memh ( Rs32 ) = Rt32.h" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerft_zomap)}, /* mapped to if (Pv4) memh(Rs32+#0)=Rt32.h */ -{ "if ( Pv4 ) memh ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerht_zomap)}, /* mapped to if (Pv4) memh(Rs32+#0)=Rt32 */ -{ "if ( Pv4 ) memh ( Rs32 + #u6:1 ) = #S6" , "0011 100 00 01 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirht_io */, -{ "if ( Pv4 ) memh ( Rs32 + #u6:1 ) = Nt8 .new" , "0100 0000 101 sssss PPi01ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerhnewt_io */, -{ "if ( Pv4 ) memh ( Rs32 + #u6:1 ) = Rt32.h" , "0100 0000 011 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerft_io */, -{ "if ( Pv4 ) memh ( Rs32 + #u6:1 ) = Rt32" , "0100 0000 010 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerht_io */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerhnewt_rr_expand_shamt_0 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #0 ) = Rt32.h" , "0011 01 00 011 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerft_rr_expand_shamt_0 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 00 010 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerht_rr_expand_shamt_0 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerhnewt_rr_expand_shamt_1 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #1 ) = Rt32.h" , "0011 01 00 011 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerft_rr_expand_shamt_1 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 00 010 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerht_rr_expand_shamt_1 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerhnewt_rr_expand_shamt_2 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #2 ) = Rt32.h" , "0011 01 00 011 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerft_rr_expand_shamt_2 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 00 010 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerht_rr_expand_shamt_2 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerhnewt_rr_expand_shamt_3 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #3 ) = Rt32.h" , "0011 01 00 011 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerft_rr_expand_shamt_3 */, -{ "if ( Pv4 ) memh ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 00 010 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerht_rr_expand_shamt_3 */, -{ "if ( Pv4 ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP101ttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S2_pstorerhnewt_pi */, -{ "if ( Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" , "1010 1 01 1 011 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerft_pi */, -{ "if ( Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32" , "1010 1 01 1 010 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerht_pi */, -{ "if ( Pv4 ) memw ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP010ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerinewt_abs */, -{ "if ( Pv4 ) memw ( #u6 ) = Rt32" , "1010 1 11 1 100 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerit_abs */, -{ "if ( Pv4 ) memw ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirit_zomap)}, /* mapped to if (Pv4) memw(Rs32+#0)=#S6 */ -{ "if ( Pv4 ) memw ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerinewt_zomap)}, /* mapped to if (Pv4) memw(Rs32+#0)=Nt8.new */ -{ "if ( Pv4 ) memw ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerit_zomap)}, /* mapped to if (Pv4) memw(Rs32+#0)=Rt32 */ -{ "if ( Pv4 ) memw ( Rs32 + #u6:2 ) = #S6" , "0011 100 00 10 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirit_io */, -{ "if ( Pv4 ) memw ( Rs32 + #u6:2 ) = Nt8 .new" , "0100 0000 101 sssss PPi10ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerinewt_io */, -{ "if ( Pv4 ) memw ( Rs32 + #u6:2 ) = Rt32" , "0100 0000 100 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerit_io */, -{ "if ( Pv4 ) memw ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerinewt_rr_expand_shamt_0 */, -{ "if ( Pv4 ) memw ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 00 100 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerit_rr_expand_shamt_0 */, -{ "if ( Pv4 ) memw ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerinewt_rr_expand_shamt_1 */, -{ "if ( Pv4 ) memw ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 00 100 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerit_rr_expand_shamt_1 */, -{ "if ( Pv4 ) memw ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerinewt_rr_expand_shamt_2 */, -{ "if ( Pv4 ) memw ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 00 100 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerit_rr_expand_shamt_2 */, -{ "if ( Pv4 ) memw ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerinewt_rr_expand_shamt_3 */, -{ "if ( Pv4 ) memw ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 00 100 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerit_rr_expand_shamt_3 */, -{ "if ( Pv4 ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP110ttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S2_pstorerinewt_pi */, -{ "if ( Pv4 ) memw ( Rz32 ++ #s4:2 ) = Rt32" , "1010 1 01 1 100 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerit_pi */, -{ "if ( Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #0 )" , "0011 00 10 000 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrbtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #1 )" , "0011 00 10 000 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrbtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #2 )" , "0011 00 10 000 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrbtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #3 )" , "0011 00 10 000 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrbtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #0 )" , "0011 00 10 010 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrhtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #1 )" , "0011 00 10 010 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrhtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #2 )" , "0011 00 10 010 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrhtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #3 )" , "0011 00 10 010 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrhtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #0 )" , "0011 00 10 001 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrubtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #1 )" , "0011 00 10 001 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrubtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #2 )" , "0011 00 10 001 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrubtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #3 )" , "0011 00 10 001 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrubtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #0 )" , "0011 00 10 011 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadruhtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #1 )" , "0011 00 10 011 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadruhtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #2 )" , "0011 00 10 011 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadruhtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #3 )" , "0011 00 10 011 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadruhtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #0 )" , "0011 00 10 100 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadritnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #1 )" , "0011 00 10 100 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadritnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #2 )" , "0011 00 10 100 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadritnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #3 )" , "0011 00 10 100 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadritnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #0 )" , "0011 00 10 110 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrdtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #1 )" , "0011 00 10 110 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrdtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #2 )" , "0011 00 10 110 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrdtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #3 )" , "0011 00 10 110 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrdtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) memb ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP100ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbnewtnew_abs */, -{ "if ( Pv4 .new ) memb ( #u6 ) = Rt32" , "1010 1 11 1 000 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbtnew_abs */, -{ "if ( Pv4 .new ) memb ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirbtnew_zomap)}, /* mapped to if (Pv4.new) memb(Rs32+#0)=#S6 */ -{ "if ( Pv4 .new ) memb ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerbnewtnew_zomap)}, /* mapped to if (Pv4.new) memb(Rs32+#0)=Nt8.new */ -{ "if ( Pv4 .new ) memb ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerbtnew_zomap)}, /* mapped to if (Pv4.new) memb(Rs32+#0)=Rt32 */ -{ "if ( Pv4 .new ) memb ( Rs32 + #u6:0 ) = #S6" , "0011 100 10 00 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirbtnew_io */, -{ "if ( Pv4 .new ) memb ( Rs32 + #u6:0 ) = Nt8 .new" , "0100 0010 101 sssss PPi00ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerbnewtnew_io */, -{ "if ( Pv4 .new ) memb ( Rs32 + #u6:0 ) = Rt32" , "0100 0010 000 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerbtnew_io */, -{ "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbnewtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 10 000 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbnewtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 10 000 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbnewtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 10 000 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbnewtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 10 000 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP100ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerbnewtnew_pi */, -{ "if ( Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Rt32" , "1010 1 01 1 000 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerbtnew_pi */, -{ "if ( Pv4 .new ) memd ( #u6 ) = Rtt32" , "1010 1 11 1 110 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerdtnew_abs */, -{ "if ( Pv4 .new ) memd ( Rs32 ) = Rtt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerdtnew_zomap)}, /* mapped to if (Pv4.new) memd(Rs32+#0)=Rtt32 */ -{ "if ( Pv4 .new ) memd ( Rs32 + #u6:3 ) = Rtt32" , "0100 0010 110 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerdtnew_io */, -{ "if ( Pv4 .new ) memd ( Rs32 + Ru32 << #0 ) = Rtt32" , "0011 01 10 110 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerdtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) memd ( Rs32 + Ru32 << #1 ) = Rtt32" , "0011 01 10 110 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerdtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) memd ( Rs32 + Ru32 << #2 ) = Rtt32" , "0011 01 10 110 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerdtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) memd ( Rs32 + Ru32 << #3 ) = Rtt32" , "0011 01 10 110 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerdtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) memd ( Rz32 ++ #s4:3 ) = Rtt32" , "1010 1 01 1 110 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerdtnew_pi */, -{ "if ( Pv4 .new ) memh ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP101ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhnewtnew_abs */, -{ "if ( Pv4 .new ) memh ( #u6 ) = Rt32.h" , "1010 1 11 1 011 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerftnew_abs */, -{ "if ( Pv4 .new ) memh ( #u6 ) = Rt32" , "1010 1 11 1 010 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhtnew_abs */, -{ "if ( Pv4 .new ) memh ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirhtnew_zomap)}, /* mapped to if (Pv4.new) memh(Rs32+#0)=#S6 */ -{ "if ( Pv4 .new ) memh ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerhnewtnew_zomap)}, /* mapped to if (Pv4.new) memh(Rs32+#0)=Nt8.new */ -{ "if ( Pv4 .new ) memh ( Rs32 ) = Rt32.h" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerftnew_zomap)}, /* mapped to if (Pv4.new) memh(Rs32+#0)=Rt32.h */ -{ "if ( Pv4 .new ) memh ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerhtnew_zomap)}, /* mapped to if (Pv4.new) memh(Rs32+#0)=Rt32 */ -{ "if ( Pv4 .new ) memh ( Rs32 + #u6:1 ) = #S6" , "0011 100 10 01 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirhtnew_io */, -{ "if ( Pv4 .new ) memh ( Rs32 + #u6:1 ) = Nt8 .new" , "0100 0010 101 sssss PPi01ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerhnewtnew_io */, -{ "if ( Pv4 .new ) memh ( Rs32 + #u6:1 ) = Rt32.h" , "0100 0010 011 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerftnew_io */, -{ "if ( Pv4 .new ) memh ( Rs32 + #u6:1 ) = Rt32" , "0100 0010 010 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerhtnew_io */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhnewtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #0 ) = Rt32.h" , "0011 01 10 011 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerftnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 10 010 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhnewtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #1 ) = Rt32.h" , "0011 01 10 011 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerftnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 10 010 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhnewtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #2 ) = Rt32.h" , "0011 01 10 011 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerftnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 10 010 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhnewtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #3 ) = Rt32.h" , "0011 01 10 011 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerftnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 10 010 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP101ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerhnewtnew_pi */, -{ "if ( Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" , "1010 1 01 1 011 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerftnew_pi */, -{ "if ( Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32" , "1010 1 01 1 010 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerhtnew_pi */, -{ "if ( Pv4 .new ) memw ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP110ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerinewtnew_abs */, -{ "if ( Pv4 .new ) memw ( #u6 ) = Rt32" , "1010 1 11 1 100 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstoreritnew_abs */, -{ "if ( Pv4 .new ) memw ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeiritnew_zomap)}, /* mapped to if (Pv4.new) memw(Rs32+#0)=#S6 */ -{ "if ( Pv4 .new ) memw ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerinewtnew_zomap)}, /* mapped to if (Pv4.new) memw(Rs32+#0)=Nt8.new */ -{ "if ( Pv4 .new ) memw ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstoreritnew_zomap)}, /* mapped to if (Pv4.new) memw(Rs32+#0)=Rt32 */ -{ "if ( Pv4 .new ) memw ( Rs32 + #u6:2 ) = #S6" , "0011 100 10 10 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeiritnew_io */, -{ "if ( Pv4 .new ) memw ( Rs32 + #u6:2 ) = Nt8 .new" , "0100 0010 101 sssss PPi10ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerinewtnew_io */, -{ "if ( Pv4 .new ) memw ( Rs32 + #u6:2 ) = Rt32" , "0100 0010 100 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstoreritnew_io */, -{ "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerinewtnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 10 100 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstoreritnew_rr_expand_shamt_0 */, -{ "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerinewtnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 10 100 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstoreritnew_rr_expand_shamt_1 */, -{ "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerinewtnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 10 100 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstoreritnew_rr_expand_shamt_2 */, -{ "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerinewtnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 10 100 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstoreritnew_rr_expand_shamt_3 */, -{ "if ( Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP110ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerinewtnew_pi */, -{ "if ( Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Rt32" , "1010 1 01 1 100 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstoreritnew_pi */, -{ "if ( Rs32 != #0 ) jump:nt #r13:2" , "0110 0001 00isssss PPi0iiii iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_PC, 0|A_NOTE_DEPRECATED|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_ARCHV3|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprz */, -{ "if ( Rs32 != #0 ) jump:t #r13:2" , "0110 0001 00isssss PPi1iiii iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_PC, 0|A_NOTE_DEPRECATED|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_ARCHV3|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprzpt */, -{ "if ( Rs32 <= #0 ) jump:nt #r13:2" , "0110 0001 11isssss PPi0iiii iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_PC, 0|A_NOTE_DEPRECATED|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_ARCHV3|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprltez */, -{ "if ( Rs32 <= #0 ) jump:t #r13:2" , "0110 0001 11isssss PPi1iiii iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_PC, 0|A_NOTE_DEPRECATED|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_ARCHV3|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprltezpt */, -{ "if ( Rs32 == #0 ) jump:nt #r13:2" , "0110 0001 10isssss PPi0iiii iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_PC, 0|A_NOTE_DEPRECATED|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_ARCHV3|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprnz */, -{ "if ( Rs32 == #0 ) jump:t #r13:2" , "0110 0001 10isssss PPi1iiii iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_PC, 0|A_NOTE_DEPRECATED|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_ARCHV3|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprnzpt */, -{ "if ( Rs32 >= #0 ) jump:nt #r13:2" , "0110 0001 01isssss PPi0iiii iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_PC, 0|A_NOTE_DEPRECATED|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_ARCHV3|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprgtez */, -{ "if ( Rs32 >= #0 ) jump:t #r13:2" , "0110 0001 01isssss PPi1iiii iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_PC, 0|A_NOTE_DEPRECATED|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_ARCHV3|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprgtezpt */, -{ "if ( cmp.eq ( Ns8 .new , #-1 ) ) jump:nt #r9:2" , "0010 -1 100 0ii-sss PP0----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_t_jumpnv_nt */, -{ "if ( cmp.eq ( Ns8 .new , #-1 ) ) jump:t #r9:2" , "0010 -1 100 0ii-sss PP1----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_t_jumpnv_t */, -{ "if ( cmp.eq ( Ns8 .new , #U5 ) ) jump:nt #r9:2" , "0010 -1 000 0ii-sss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_t_jumpnv_nt */, -{ "if ( cmp.eq ( Ns8 .new , #U5 ) ) jump:t #r9:2" , "0010 -1 000 0ii-sss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_t_jumpnv_t */, -{ "if ( cmp.eq ( Ns8 .new , Rt32 ) ) jump:nt #r9:2" , "0010 -0 000 0ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_t_jumpnv_nt */, -{ "if ( cmp.eq ( Ns8 .new , Rt32 ) ) jump:t #r9:2" , "0010 -0 000 0ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_t_jumpnv_t */, -{ "if ( cmp.gt ( Ns8 .new , #-1 ) ) jump:nt #r9:2" , "0010 -1 101 0ii-sss PP0----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_t_jumpnv_nt */, -{ "if ( cmp.gt ( Ns8 .new , #-1 ) ) jump:t #r9:2" , "0010 -1 101 0ii-sss PP1----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_t_jumpnv_t */, -{ "if ( cmp.gt ( Ns8 .new , #U5 ) ) jump:nt #r9:2" , "0010 -1 001 0ii-sss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_t_jumpnv_nt */, -{ "if ( cmp.gt ( Ns8 .new , #U5 ) ) jump:t #r9:2" , "0010 -1 001 0ii-sss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_t_jumpnv_t */, -{ "if ( cmp.gt ( Ns8 .new , Rt32 ) ) jump:nt #r9:2" , "0010 -0 001 0ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_t_jumpnv_nt */, -{ "if ( cmp.gt ( Ns8 .new , Rt32 ) ) jump:t #r9:2" , "0010 -0 001 0ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_t_jumpnv_t */, -{ "if ( cmp.gt ( Rt32 , Ns8 .new ) ) jump:nt #r9:2" , "0010 -0 011 0ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmplt_t_jumpnv_nt */, -{ "if ( cmp.gt ( Rt32 , Ns8 .new ) ) jump:t #r9:2" , "0010 -0 011 0ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmplt_t_jumpnv_t */, -{ "if ( cmp.gtu ( Ns8 .new , #U5 ) ) jump:nt #r9:2" , "0010 -1 010 0ii-sss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_t_jumpnv_nt */, -{ "if ( cmp.gtu ( Ns8 .new , #U5 ) ) jump:t #r9:2" , "0010 -1 010 0ii-sss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_t_jumpnv_t */, -{ "if ( cmp.gtu ( Ns8 .new , Rt32 ) ) jump:nt #r9:2" , "0010 -0 010 0ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_t_jumpnv_nt */, -{ "if ( cmp.gtu ( Ns8 .new , Rt32 ) ) jump:t #r9:2" , "0010 -0 010 0ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_t_jumpnv_t */, -{ "if ( cmp.gtu ( Rt32 , Ns8 .new ) ) jump:nt #r9:2" , "0010 -0 100 0ii-sss PP0ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpltu_t_jumpnv_nt */, -{ "if ( cmp.gtu ( Rt32 , Ns8 .new ) ) jump:t #r9:2" , "0010 -0 100 0ii-sss PP1ttttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpltu_t_jumpnv_t */, -{ "if ( p0 ) Rd16 = #0 ; allocframe ( #u5:3 )" , "0111101--110ddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS2_allocframe */, -{ "if ( p0 ) Rd16 = #0 ; dealloc_return" , "0101101--110ddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_return */, -{ "if ( p0 ) Rd16 = #0 ; deallocframe" , "0101101--110ddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_deallocframe */, -{ "if ( p0 ) Rd16 = #0 ; if ( ! p0 ) dealloc_return" , "0101101--110ddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_return_f */, -{ "if ( p0 ) Rd16 = #0 ; if ( ! p0 ) jumpr Lr" , "0101101--110ddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_jumpr31_f */, -{ "if ( p0 ) Rd16 = #0 ; if ( ! p0 .new ) dealloc_return:nt" , "0101101--110ddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_return_fnew */, -{ "if ( p0 ) Rd16 = #0 ; if ( ! p0 .new ) jumpr:nt Lr" , "0101101--110ddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_jumpr31_fnew */, -{ "if ( p0 ) Rd16 = #0 ; if ( p0 ) dealloc_return" , "0101101--110ddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_return_t */, -{ "if ( p0 ) Rd16 = #0 ; if ( p0 ) jumpr Lr" , "0101101--110ddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_jumpr31_t */, -{ "if ( p0 ) Rd16 = #0 ; if ( p0 .new ) dealloc_return:nt" , "0101101--110ddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_return_tnew */, -{ "if ( p0 ) Rd16 = #0 ; if ( p0 .new ) jumpr:nt Lr" , "0101101--110ddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_jumpr31_tnew */, -{ "if ( p0 ) Rd16 = #0 ; jumpr Lr" , "0101101--110ddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_jumpr31 */, -{ "if ( p0 ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = #0" , "0111101--110ddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS2_storebi0 */, -{ "if ( p0 ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = #1" , "0111101--110ddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS2_storebi1 */, -{ "if ( p0 ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = Rt16" , "0111101--110ddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS1_storeb_io */, -{ "if ( p0 ) Rd16 = #0 ; memd ( Sp + #s6:3 ) = Rtt8" , "0111101--110ddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS2_stored_sp */, -{ "if ( p0 ) Rd16 = #0 ; memh ( Rs16 + #u3:1 ) = Rt16" , "0111101--110ddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS2_storeh_io */, -{ "if ( p0 ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = #0" , "0111101--110ddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS2_storewi0 */, -{ "if ( p0 ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = #1" , "0111101--110ddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS2_storewi1 */, -{ "if ( p0 ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = Rt16" , "0111101--110ddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS1_storew_io */, -{ "if ( p0 ) Rd16 = #0 ; memw ( Sp + #u5:2 ) = Rt16" , "0111101--110ddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SS2_storew_sp */, -{ "if ( p0 ) Re16 = #0 ; Rd16 = memb ( Rs16 + #u3:0 )" , "0101101--110eeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_loadrb_io */, -{ "if ( p0 ) Re16 = #0 ; Rd16 = memh ( Rs16 + #u3:1 )" , "0101101--110eeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_loadrh_io */, -{ "if ( p0 ) Re16 = #0 ; Rd16 = memub ( Rs16 + #u4:0 )" , "0101101--110eeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL1_loadrub_io */, -{ "if ( p0 ) Re16 = #0 ; Rd16 = memuh ( Rs16 + #u3:1 )" , "0101101--110eeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_loadruh_io */, -{ "if ( p0 ) Re16 = #0 ; Rd16 = memw ( Rs16 + #u4:2 )" , "0101101--110eeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL1_loadri_io */, -{ "if ( p0 ) Re16 = #0 ; Rd16 = memw ( Sp + #u5:2 )" , "0101101--110eeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_loadri_sp */, -{ "if ( p0 ) Re16 = #0 ; Rdd8 = combine ( #0 , #u2 )" , "0011101--110eeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SA1_combine0i */, -{ "if ( p0 ) Re16 = #0 ; Rdd8 = combine ( #0 , Rs16 )" , "0011101--110eeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SA1_combinezr */, -{ "if ( p0 ) Re16 = #0 ; Rdd8 = combine ( #1 , #u2 )" , "0011101--110eeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SA1_combine1i */, -{ "if ( p0 ) Re16 = #0 ; Rdd8 = combine ( #2 , #u2 )" , "0011101--110eeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SA1_combine2i */, -{ "if ( p0 ) Re16 = #0 ; Rdd8 = combine ( #3 , #u2 )" , "0011101--110eeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SA1_combine3i */, -{ "if ( p0 ) Re16 = #0 ; Rdd8 = combine ( Rs16 , #0 )" , "0011101--110eeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SA1_combinerz */, -{ "if ( p0 ) Re16 = #0 ; Rdd8 = memd ( Sp + #u5:3 )" , "0101101--110eeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SL2_loadrd_sp */, -{ "if ( p0 ) Re16 = #0 ; if ( ! p0 ) Rd16 = #0" , "0011101--110eeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SA1_clrf */, -{ "if ( p0 ) Re16 = #0 ; if ( p0 ) Rd16 = #0" , "0011101--110eeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrt_SA1_clrt */, -{ "if ( p0 .new ) Rd16 = #0 ; allocframe ( #u5:3 )" , "0111101--100ddddEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS2_allocframe */, -{ "if ( p0 .new ) Rd16 = #0 ; dealloc_return" , "0101101--100ddddEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_return */, -{ "if ( p0 .new ) Rd16 = #0 ; deallocframe" , "0101101--100ddddEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_deallocframe */, -{ "if ( p0 .new ) Rd16 = #0 ; if ( ! p0 ) dealloc_return" , "0101101--100ddddEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_return_f */, -{ "if ( p0 .new ) Rd16 = #0 ; if ( ! p0 ) jumpr Lr" , "0101101--100ddddEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_jumpr31_f */, -{ "if ( p0 .new ) Rd16 = #0 ; if ( ! p0 .new ) dealloc_return:nt" , "0101101--100ddddEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_return_fnew */, -{ "if ( p0 .new ) Rd16 = #0 ; if ( ! p0 .new ) jumpr:nt Lr" , "0101101--100ddddEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_jumpr31_fnew */, -{ "if ( p0 .new ) Rd16 = #0 ; if ( p0 ) dealloc_return" , "0101101--100ddddEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_return_t */, -{ "if ( p0 .new ) Rd16 = #0 ; if ( p0 ) jumpr Lr" , "0101101--100ddddEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_jumpr31_t */, -{ "if ( p0 .new ) Rd16 = #0 ; if ( p0 .new ) dealloc_return:nt" , "0101101--100ddddEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_return_tnew */, -{ "if ( p0 .new ) Rd16 = #0 ; if ( p0 .new ) jumpr:nt Lr" , "0101101--100ddddEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_jumpr31_tnew */, -{ "if ( p0 .new ) Rd16 = #0 ; jumpr Lr" , "0101101--100ddddEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_jumpr31 */, -{ "if ( p0 .new ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = #0" , "0111101--100ddddEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS2_storebi0 */, -{ "if ( p0 .new ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = #1" , "0111101--100ddddEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS2_storebi1 */, -{ "if ( p0 .new ) Rd16 = #0 ; memb ( Rs16 + #u4:0 ) = Rt16" , "0111101--100ddddEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS1_storeb_io */, -{ "if ( p0 .new ) Rd16 = #0 ; memd ( Sp + #s6:3 ) = Rtt8" , "0111101--100ddddEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS2_stored_sp */, -{ "if ( p0 .new ) Rd16 = #0 ; memh ( Rs16 + #u3:1 ) = Rt16" , "0111101--100ddddEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS2_storeh_io */, -{ "if ( p0 .new ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = #0" , "0111101--100ddddEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS2_storewi0 */, -{ "if ( p0 .new ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = #1" , "0111101--100ddddEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS2_storewi1 */, -{ "if ( p0 .new ) Rd16 = #0 ; memw ( Rs16 + #u4:2 ) = Rt16" , "0111101--100ddddEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS1_storew_io */, -{ "if ( p0 .new ) Rd16 = #0 ; memw ( Sp + #u5:2 ) = Rt16" , "0111101--100ddddEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SS2_storew_sp */, -{ "if ( p0 .new ) Re16 = #0 ; Rd16 = memb ( Rs16 + #u3:0 )" , "0101101--100eeeeEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_loadrb_io */, -{ "if ( p0 .new ) Re16 = #0 ; Rd16 = memh ( Rs16 + #u3:1 )" , "0101101--100eeeeEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_loadrh_io */, -{ "if ( p0 .new ) Re16 = #0 ; Rd16 = memub ( Rs16 + #u4:0 )" , "0101101--100eeeeEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL1_loadrub_io */, -{ "if ( p0 .new ) Re16 = #0 ; Rd16 = memuh ( Rs16 + #u3:1 )" , "0101101--100eeeeEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_loadruh_io */, -{ "if ( p0 .new ) Re16 = #0 ; Rd16 = memw ( Rs16 + #u4:2 )" , "0101101--100eeeeEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL1_loadri_io */, -{ "if ( p0 .new ) Re16 = #0 ; Rd16 = memw ( Sp + #u5:2 )" , "0101101--100eeeeEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_loadri_sp */, -{ "if ( p0 .new ) Re16 = #0 ; Rdd8 = combine ( #0 , #u2 )" , "0011101--100eeeeEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_combine0i */, -{ "if ( p0 .new ) Re16 = #0 ; Rdd8 = combine ( #0 , Rs16 )" , "0011101--100eeeeEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_combinezr */, -{ "if ( p0 .new ) Re16 = #0 ; Rdd8 = combine ( #1 , #u2 )" , "0011101--100eeeeEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_combine1i */, -{ "if ( p0 .new ) Re16 = #0 ; Rdd8 = combine ( #2 , #u2 )" , "0011101--100eeeeEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_combine2i */, -{ "if ( p0 .new ) Re16 = #0 ; Rdd8 = combine ( #3 , #u2 )" , "0011101--100eeeeEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_combine3i */, -{ "if ( p0 .new ) Re16 = #0 ; Rdd8 = combine ( Rs16 , #0 )" , "0011101--100eeeeEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_ROPS_2|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_combinerz */, -{ "if ( p0 .new ) Re16 = #0 ; Rdd8 = memd ( Sp + #u5:3 )" , "0101101--100eeeeEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SL2_loadrd_sp */, -{ "if ( p0 .new ) Re16 = #0 ; if ( ! p0 ) Rd16 = #0" , "0011101--100eeeeEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_clrf */, -{ "if ( p0 .new ) Re16 = #0 ; if ( ! p0 .new ) Rd16 = #0" , "0011101--100eeeeEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_clrfnew */, -{ "if ( p0 .new ) Re16 = #0 ; if ( p0 ) Rd16 = #0" , "0011101--100eeeeEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_clrt */, -{ "if ( p0 .new ) Re16 = #0 ; if ( p0 .new ) Rd16 = #0" , "0011101--100eeeeEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_clrtnew_SA1_clrtnew */, -{ "if ( tstbit ( Ns8 .new , #0 ) ) jump:nt #r9:2" , "0010 -1 011 0ii-sss PP0----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_t_jumpnv_nt */, -{ "if ( tstbit ( Ns8 .new , #0 ) ) jump:t #r9:2" , "0010 -1 011 0ii-sss PP1----- iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_DOTNEWVALUE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_ROPS_2|A_RESTRICT_NOSLOT1_STORE|A_RESTRICT_SLOT0ONLY|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_t_jumpnv_t */, -{ "if Ps4 .new dealloc_return:nt" , "1001 011 0 000 11110 PP0010ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_12|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_return_tnew_pnt_alt */, -{ "if Ps4 .new dealloc_return:t" , "1001 011 0 000 11110 PP0110ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_12|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_return_tnew_pt_alt */, -{ "if Ps4 dealloc_return" , "1001 011 0 000 11110 PP0100ss ---11110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_ROPS_2|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_PRED_BIT_7|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_return_t_alt */, -{ "if Pt4 .new Rd32 = memb ( #u6 )" , "1001 1 11 1 000 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrbtnew_abs_alt */, -{ "if Pt4 .new Rd32 = memb ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrbtnew_zomap_alt)}, /* mapped to if (Pt4.new) Rd32=memb(Rs32+#0) */ -{ "if Pt4 .new Rd32 = memb ( Rs32 + #u6:0 )" , "0100 0011 000 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrbtnew_io_alt */, -{ "if Pt4 .new Rd32 = memb ( Rz32 ++ #s4:0 )" , "1001 1 01 1 000 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadrbtnew_pi_alt */, -{ "if Pt4 .new Rd32 = memh ( #u6 )" , "1001 1 11 1 010 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrhtnew_abs_alt */, -{ "if Pt4 .new Rd32 = memh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrhtnew_zomap_alt)}, /* mapped to if (Pt4.new) Rd32=memh(Rs32+#0) */ -{ "if Pt4 .new Rd32 = memh ( Rs32 + #u6:1 )" , "0100 0011 010 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrhtnew_io_alt */, -{ "if Pt4 .new Rd32 = memh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 010 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadrhtnew_pi_alt */, -{ "if Pt4 .new Rd32 = memub ( #u6 )" , "1001 1 11 1 001 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrubtnew_abs_alt */, -{ "if Pt4 .new Rd32 = memub ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrubtnew_zomap_alt)}, /* mapped to if (Pt4.new) Rd32=memub(Rs32+#0) */ -{ "if Pt4 .new Rd32 = memub ( Rs32 + #u6:0 )" , "0100 0011 001 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrubtnew_io_alt */, -{ "if Pt4 .new Rd32 = memub ( Rz32 ++ #s4:0 )" , "1001 1 01 1 001 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadrubtnew_pi_alt */, -{ "if Pt4 .new Rd32 = memuh ( #u6 )" , "1001 1 11 1 011 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadruhtnew_abs_alt */, -{ "if Pt4 .new Rd32 = memuh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadruhtnew_zomap_alt)}, /* mapped to if (Pt4.new) Rd32=memuh(Rs32+#0) */ -{ "if Pt4 .new Rd32 = memuh ( Rs32 + #u6:1 )" , "0100 0011 011 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadruhtnew_io_alt */, -{ "if Pt4 .new Rd32 = memuh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 011 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadruhtnew_pi_alt */, -{ "if Pt4 .new Rd32 = memw ( #u6 )" , "1001 1 11 1 100 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadritnew_abs_alt */, -{ "if Pt4 .new Rd32 = memw ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadritnew_zomap_alt)}, /* mapped to if (Pt4.new) Rd32=memw(Rs32+#0) */ -{ "if Pt4 .new Rd32 = memw ( Rs32 + #u6:2 )" , "0100 0011 100 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadritnew_io_alt */, -{ "if Pt4 .new Rd32 = memw ( Rz32 ++ #s4:2 )" , "1001 1 01 1 100 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadritnew_pi_alt */, -{ "if Pt4 .new Rdd32 = memd ( #u6 )" , "1001 1 11 1 110 iiiii PP110tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrdtnew_abs_alt */, -{ "if Pt4 .new Rdd32 = memd ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrdtnew_zomap_alt)}, /* mapped to if (Pt4.new) Rdd32=memd(Rs32+#0) */ -{ "if Pt4 .new Rdd32 = memd ( Rs32 + #u6:3 )" , "0100 0011 110 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrdtnew_io_alt */, -{ "if Pt4 .new Rdd32 = memd ( Rz32 ++ #s4:3 )" , "1001 1 01 1 110 zzzzz PP110tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L2_ploadrdtnew_pi_alt */, -{ "if Pt4 Rd32 = memb ( #u6 )" , "1001 1 11 1 000 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrbt_abs_alt */, -{ "if Pt4 Rd32 = memb ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrbt_zomap_alt)}, /* mapped to if (Pt4) Rd32=memb(Rs32+#0) */ -{ "if Pt4 Rd32 = memb ( Rs32 + #u6:0 )" , "0100 0001 000 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrbt_io_alt */, -{ "if Pt4 Rd32 = memb ( Rz32 ++ #s4:0 )" , "1001 1 01 1 000 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrbt_pi_alt */, -{ "if Pt4 Rd32 = memh ( #u6 )" , "1001 1 11 1 010 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrht_abs_alt */, -{ "if Pt4 Rd32 = memh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrht_zomap_alt)}, /* mapped to if (Pt4) Rd32=memh(Rs32+#0) */ -{ "if Pt4 Rd32 = memh ( Rs32 + #u6:1 )" , "0100 0001 010 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrht_io_alt */, -{ "if Pt4 Rd32 = memh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 010 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrht_pi_alt */, -{ "if Pt4 Rd32 = memub ( #u6 )" , "1001 1 11 1 001 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrubt_abs_alt */, -{ "if Pt4 Rd32 = memub ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrubt_zomap_alt)}, /* mapped to if (Pt4) Rd32=memub(Rs32+#0) */ -{ "if Pt4 Rd32 = memub ( Rs32 + #u6:0 )" , "0100 0001 001 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrubt_io_alt */, -{ "if Pt4 Rd32 = memub ( Rz32 ++ #s4:0 )" , "1001 1 01 1 001 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrubt_pi_alt */, -{ "if Pt4 Rd32 = memuh ( #u6 )" , "1001 1 11 1 011 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadruht_abs_alt */, -{ "if Pt4 Rd32 = memuh ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadruht_zomap_alt)}, /* mapped to if (Pt4) Rd32=memuh(Rs32+#0) */ -{ "if Pt4 Rd32 = memuh ( Rs32 + #u6:1 )" , "0100 0001 011 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadruht_io_alt */, -{ "if Pt4 Rd32 = memuh ( Rz32 ++ #s4:1 )" , "1001 1 01 1 011 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadruht_pi_alt */, -{ "if Pt4 Rd32 = memw ( #u6 )" , "1001 1 11 1 100 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrit_abs_alt */, -{ "if Pt4 Rd32 = memw ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrit_zomap_alt)}, /* mapped to if (Pt4) Rd32=memw(Rs32+#0) */ -{ "if Pt4 Rd32 = memw ( Rs32 + #u6:2 )" , "0100 0001 100 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrit_io_alt */, -{ "if Pt4 Rd32 = memw ( Rz32 ++ #s4:2 )" , "1001 1 01 1 100 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrit_pi_alt */, -{ "if Pt4 Rdd32 = memd ( #u6 )" , "1001 1 11 1 110 iiiii PP100tti 1--ddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* L4_ploadrdt_abs_alt */, -{ "if Pt4 Rdd32 = memd ( Rs32 )" , "0000ttdddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L2_ploadrdt_zomap_alt)}, /* mapped to if (Pt4) Rdd32=memd(Rs32+#0) */ -{ "if Pt4 Rdd32 = memd ( Rs32 + #u6:3 )" , "0100 0001 110 sssss PP0ttiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L2_ploadrdt_io_alt */, -{ "if Pt4 Rdd32 = memd ( Rz32 ++ #s4:3 )" , "1001 1 01 1 110 zzzzz PP100tti iiiddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L2_ploadrdt_pi_alt */, -{ "if Pu4 .new Rd32 = #s12" , "0111 1110 0uu0iiii PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmovenewit_alt */, -{ "if Pu4 .new Rd32 = Rs32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrtnew_alt)}, /* mapped to if (Pu4.new) Rd32=add(Rs32,#0) */ -{ "if Pu4 .new Rd32 = add ( Rs32 , #s8 )" , "0111 0100 0uusssss PP1iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_padditnew_alt */, -{ "if Pu4 .new Rd32 = add ( Rs32 , Rt32 )" , "1111 1011 0-0sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_paddtnew_alt */, -{ "if Pu4 .new Rd32 = and ( Rs32 , Rt32 )" , "1111 1001 -00sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_pandtnew_alt */, -{ "if Pu4 .new Rd32 = aslh ( Rs32 )" , "0111 0000 000sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_paslhtnew_alt */, -{ "if Pu4 .new Rd32 = asrh ( Rs32 )" , "0111 0000 001sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_pasrhtnew_alt */, -{ "if Pu4 .new Rd32 = or ( Rs32 , Rt32 )" , "1111 1001 -01sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_portnew_alt */, -{ "if Pu4 .new Rd32 = sub ( Rt32 , Rs32 )" , "1111 1011 0-1sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_psubtnew_alt */, -{ "if Pu4 .new Rd32 = sxtb ( Rs32 )" , "0111 0000 101sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_psxtbtnew_alt */, -{ "if Pu4 .new Rd32 = sxth ( Rs32 )" , "0111 0000 111sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_psxthtnew_alt */, -{ "if Pu4 .new Rd32 = xor ( Rs32 , Rt32 )" , "1111 1001 -11sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A2_pxortnew_alt */, -{ "if Pu4 .new Rd32 = zxtb ( Rs32 )" , "0111 0000 100sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_pzxtbtnew_alt */, -{ "if Pu4 .new Rd32 = zxth ( Rs32 )" , "0111 0000 110sssss PP1-01uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* A4_pzxthtnew_alt */, -{ "if Pu4 .new Rdd32 = Rss32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrptnew_alt)}, /* mapped to if (Pu4.new) Rdd32=combine(Rss.H32,Rss.L32) */ -{ "if Pu4 .new Rdd32 = combine ( Rs32 , Rt32 )" , "1111 1101 ---sssss PP1ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ROPS_2|A_ARCHV2|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* C2_ccombinewnewt_alt */, -{ "if Pu4 .new jump:nt #r15:2" , "0101 1100 ii0iiiii PPi01-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_NOTE_CONDITIONAL|A_ARCHV2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumptnew_alt */, -{ "if Pu4 .new jump:t #r15:2" , "0101 1100 ii0iiiii PPi11-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_NOTE_CONDITIONAL|A_ARCHV2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumptnewpt_alt */, -{ "if Pu4 .new jumpr:nt Rs32" , "0101 0011 010sssss PP-01-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_ARCHV3|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* J2_jumprtnew_alt */, -{ "if Pu4 .new jumpr:t Rs32" , "0101 0011 010sssss PP-11-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_ARCHV3|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* J2_jumprtnewpt_alt */, -{ "if Pu4 Rd32 = #s12" , "0111 1110 0uu0iiii PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* C2_cmoveit_alt */, -{ "if Pu4 Rd32 = Rs32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrt_alt)}, /* mapped to if (Pu4) Rd32=add(Rs32,#0) */ -{ "if Pu4 Rd32 = add ( Rs32 , #s8 )" , "0111 0100 0uusssss PP0iiiii iiiddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* A2_paddit_alt */, -{ "if Pu4 Rd32 = add ( Rs32 , Rt32 )" , "1111 1011 0-0sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_paddt_alt */, -{ "if Pu4 Rd32 = and ( Rs32 , Rt32 )" , "1111 1001 -00sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_pandt_alt */, -{ "if Pu4 Rd32 = aslh ( Rs32 )" , "0111 0000 000sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_paslht_alt */, -{ "if Pu4 Rd32 = asrh ( Rs32 )" , "0111 0000 001sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_pasrht_alt */, -{ "if Pu4 Rd32 = or ( Rs32 , Rt32 )" , "1111 1001 -01sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_port_alt */, -{ "if Pu4 Rd32 = sub ( Rt32 , Rs32 )" , "1111 1011 0-1sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_psubt_alt */, -{ "if Pu4 Rd32 = sxtb ( Rs32 )" , "0111 0000 101sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_psxtbt_alt */, -{ "if Pu4 Rd32 = sxth ( Rs32 )" , "0111 0000 111sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_psxtht_alt */, -{ "if Pu4 Rd32 = xor ( Rs32 , Rt32 )" , "1111 1001 -11sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A2_pxort_alt */, -{ "if Pu4 Rd32 = zxtb ( Rs32 )" , "0111 0000 100sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_pzxtbt_alt */, -{ "if Pu4 Rd32 = zxth ( Rs32 )" , "0111 0000 110sssss PP1-00uu ---ddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* A4_pzxtht_alt */, -{ "if Pu4 Rdd32 = Rss32" , "0000uudddddsssss0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(A2_tfrpt_alt)}, /* mapped to if (Pu4) Rdd32=combine(Rss.H32,Rss.L32) */ -{ "if Pu4 Rdd32 = combine ( Rs32 , Rt32 )" , "1111 1101 ---sssss PP0ttttt 0uuddddd" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_ARCHV2|A_ROPS_2|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* C2_ccombinewt_alt */, -{ "if Pu4 call #r15:2" , "0101 1101 ii0iiiii PPi-0-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_DIRECT|A_NOTE_PACKET_PC|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_NOTE_CONDITIONAL|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_PC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_callt_alt */, -{ "if Pu4 callr Rs32" , "0101 0001 000sssss PP----uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC|IMPLICIT_LR, 0|A_CALL|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_LR|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* J2_callrt_alt */, -{ "if Pu4 jump #r15:2" , "0101 1100 ii0iiiii PPi-0-uu iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_PRED_BIT_12|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jumpt_alt */, -{ "if Pu4 jumpr Rs32" , "0101 0011 010sssss PP--0-uu --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_PRED_BIT_12|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC, NULL} /* J2_jumprt_alt */, -{ "if Pv4 .new Rd32 = memb ( Rs32 + Rt32 << #0 )" , "0011 00 10 000 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrbtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new Rd32 = memb ( Rs32 + Rt32 << #1 )" , "0011 00 10 000 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrbtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new Rd32 = memb ( Rs32 + Rt32 << #2 )" , "0011 00 10 000 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrbtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new Rd32 = memb ( Rs32 + Rt32 << #3 )" , "0011 00 10 000 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrbtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new Rd32 = memh ( Rs32 + Rt32 << #0 )" , "0011 00 10 010 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrhtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new Rd32 = memh ( Rs32 + Rt32 << #1 )" , "0011 00 10 010 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrhtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new Rd32 = memh ( Rs32 + Rt32 << #2 )" , "0011 00 10 010 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrhtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new Rd32 = memh ( Rs32 + Rt32 << #3 )" , "0011 00 10 010 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrhtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new Rd32 = memub ( Rs32 + Rt32 << #0 )" , "0011 00 10 001 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrubtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new Rd32 = memub ( Rs32 + Rt32 << #1 )" , "0011 00 10 001 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrubtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new Rd32 = memub ( Rs32 + Rt32 << #2 )" , "0011 00 10 001 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrubtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new Rd32 = memub ( Rs32 + Rt32 << #3 )" , "0011 00 10 001 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrubtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new Rd32 = memuh ( Rs32 + Rt32 << #0 )" , "0011 00 10 011 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadruhtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new Rd32 = memuh ( Rs32 + Rt32 << #1 )" , "0011 00 10 011 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadruhtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new Rd32 = memuh ( Rs32 + Rt32 << #2 )" , "0011 00 10 011 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadruhtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new Rd32 = memuh ( Rs32 + Rt32 << #3 )" , "0011 00 10 011 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadruhtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new Rd32 = memw ( Rs32 + Rt32 << #0 )" , "0011 00 10 100 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadritnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new Rd32 = memw ( Rs32 + Rt32 << #1 )" , "0011 00 10 100 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadritnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new Rd32 = memw ( Rs32 + Rt32 << #2 )" , "0011 00 10 100 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadritnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new Rd32 = memw ( Rs32 + Rt32 << #3 )" , "0011 00 10 100 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadritnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new Rdd32 = memd ( Rs32 + Rt32 << #0 )" , "0011 00 10 110 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrdtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new Rdd32 = memd ( Rs32 + Rt32 << #1 )" , "0011 00 10 110 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrdtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new Rdd32 = memd ( Rs32 + Rt32 << #2 )" , "0011 00 10 110 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrdtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new Rdd32 = memd ( Rs32 + Rt32 << #3 )" , "0011 00 10 110 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_DOTNEW|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* L4_ploadrdtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new memb ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP100ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbnewtnew_abs_alt */, -{ "if Pv4 .new memb ( #u6 ) = Rt32" , "1010 1 11 1 000 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbtnew_abs_alt */, -{ "if Pv4 .new memb ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirbtnew_zomap_alt)}, /* mapped to if (Pv4.new) memb(Rs32+#0)=#S6 */ -{ "if Pv4 .new memb ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerbnewtnew_zomap_alt)}, /* mapped to if (Pv4.new) memb(Rs32+#0)=Nt8.new */ -{ "if Pv4 .new memb ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerbtnew_zomap_alt)}, /* mapped to if (Pv4.new) memb(Rs32+#0)=Rt32 */ -{ "if Pv4 .new memb ( Rs32 + #u6:0 ) = #S6" , "0011 100 10 00 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirbtnew_io_alt */, -{ "if Pv4 .new memb ( Rs32 + #u6:0 ) = Nt8 .new" , "0100 0010 101 sssss PPi00ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerbnewtnew_io_alt */, -{ "if Pv4 .new memb ( Rs32 + #u6:0 ) = Rt32" , "0100 0010 000 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerbtnew_io_alt */, -{ "if Pv4 .new memb ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbnewtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new memb ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 10 000 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new memb ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbnewtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new memb ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 10 000 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new memb ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbnewtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new memb ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 10 000 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new memb ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbnewtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new memb ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 10 000 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerbtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new memb ( Rz32 ++ #s4:0 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP100ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerbnewtnew_pi_alt */, -{ "if Pv4 .new memb ( Rz32 ++ #s4:0 ) = Rt32" , "1010 1 01 1 000 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerbtnew_pi_alt */, -{ "if Pv4 .new memd ( #u6 ) = Rtt32" , "1010 1 11 1 110 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerdtnew_abs_alt */, -{ "if Pv4 .new memd ( Rs32 ) = Rtt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerdtnew_zomap_alt)}, /* mapped to if (Pv4.new) memd(Rs32+#0)=Rtt32 */ -{ "if Pv4 .new memd ( Rs32 + #u6:3 ) = Rtt32" , "0100 0010 110 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerdtnew_io_alt */, -{ "if Pv4 .new memd ( Rs32 + Ru32 << #0 ) = Rtt32" , "0011 01 10 110 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerdtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new memd ( Rs32 + Ru32 << #1 ) = Rtt32" , "0011 01 10 110 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerdtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new memd ( Rs32 + Ru32 << #2 ) = Rtt32" , "0011 01 10 110 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerdtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new memd ( Rs32 + Ru32 << #3 ) = Rtt32" , "0011 01 10 110 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerdtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new memd ( Rz32 ++ #s4:3 ) = Rtt32" , "1010 1 01 1 110 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerdtnew_pi_alt */, -{ "if Pv4 .new memh ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP101ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhnewtnew_abs_alt */, -{ "if Pv4 .new memh ( #u6 ) = Rt32.h" , "1010 1 11 1 011 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerftnew_abs_alt */, -{ "if Pv4 .new memh ( #u6 ) = Rt32" , "1010 1 11 1 010 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhtnew_abs_alt */, -{ "if Pv4 .new memh ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirhtnew_zomap_alt)}, /* mapped to if (Pv4.new) memh(Rs32+#0)=#S6 */ -{ "if Pv4 .new memh ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerhnewtnew_zomap_alt)}, /* mapped to if (Pv4.new) memh(Rs32+#0)=Nt8.new */ -{ "if Pv4 .new memh ( Rs32 ) = Rt32.h" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerftnew_zomap_alt)}, /* mapped to if (Pv4.new) memh(Rs32+#0)=Rt32.h */ -{ "if Pv4 .new memh ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerhtnew_zomap_alt)}, /* mapped to if (Pv4.new) memh(Rs32+#0)=Rt32 */ -{ "if Pv4 .new memh ( Rs32 + #u6:1 ) = #S6" , "0011 100 10 01 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirhtnew_io_alt */, -{ "if Pv4 .new memh ( Rs32 + #u6:1 ) = Nt8 .new" , "0100 0010 101 sssss PPi01ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerhnewtnew_io_alt */, -{ "if Pv4 .new memh ( Rs32 + #u6:1 ) = Rt32.h" , "0100 0010 011 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerftnew_io_alt */, -{ "if Pv4 .new memh ( Rs32 + #u6:1 ) = Rt32" , "0100 0010 010 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerhtnew_io_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhnewtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #0 ) = Rt32.h" , "0011 01 10 011 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerftnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 10 010 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhnewtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #1 ) = Rt32.h" , "0011 01 10 011 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerftnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 10 010 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhnewtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #2 ) = Rt32.h" , "0011 01 10 011 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerftnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 10 010 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhnewtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #3 ) = Rt32.h" , "0011 01 10 011 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerftnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new memh ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 10 010 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerhtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new memh ( Rz32 ++ #s4:1 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP101ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerhnewtnew_pi_alt */, -{ "if Pv4 .new memh ( Rz32 ++ #s4:1 ) = Rt32.h" , "1010 1 01 1 011 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerftnew_pi_alt */, -{ "if Pv4 .new memh ( Rz32 ++ #s4:1 ) = Rt32" , "1010 1 01 1 010 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerhtnew_pi_alt */, -{ "if Pv4 .new memw ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP110ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerinewtnew_abs_alt */, -{ "if Pv4 .new memw ( #u6 ) = Rt32" , "1010 1 11 1 100 ---ii PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstoreritnew_abs_alt */, -{ "if Pv4 .new memw ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeiritnew_zomap_alt)}, /* mapped to if (Pv4.new) memw(Rs32+#0)=#S6 */ -{ "if Pv4 .new memw ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstorerinewtnew_zomap_alt)}, /* mapped to if (Pv4.new) memw(Rs32+#0)=Nt8.new */ -{ "if Pv4 .new memw ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_pstoreritnew_zomap_alt)}, /* mapped to if (Pv4.new) memw(Rs32+#0)=Rt32 */ -{ "if Pv4 .new memw ( Rs32 + #u6:2 ) = #S6" , "0011 100 10 10 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeiritnew_io_alt */, -{ "if Pv4 .new memw ( Rs32 + #u6:2 ) = Nt8 .new" , "0100 0010 101 sssss PPi10ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstorerinewtnew_io_alt */, -{ "if Pv4 .new memw ( Rs32 + #u6:2 ) = Rt32" , "0100 0010 100 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S4_pstoreritnew_io_alt */, -{ "if Pv4 .new memw ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerinewtnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new memw ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 10 100 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstoreritnew_rr_expand_shamt_0_alt */, -{ "if Pv4 .new memw ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 10 101 sssss PP0uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerinewtnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new memw ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 10 100 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstoreritnew_rr_expand_shamt_1_alt */, -{ "if Pv4 .new memw ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerinewtnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new memw ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 10 100 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstoreritnew_rr_expand_shamt_2_alt */, -{ "if Pv4 .new memw ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 10 101 sssss PP1uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstorerinewtnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new memw ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 10 100 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S4_pstoreritnew_rr_expand_shamt_3_alt */, -{ "if Pv4 .new memw ( Rz32 ++ #s4:2 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP110ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstorerinewtnew_pi_alt */, -{ "if Pv4 .new memw ( Rz32 ++ #s4:2 ) = Rt32" , "1010 1 01 1 100 zzzzz PP1ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEW|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW, NULL} /* S2_pstoreritnew_pi_alt */, -{ "if Pv4 Rd32 = memb ( Rs32 + Rt32 << #0 )" , "0011 00 00 000 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrbt_rr_expand_shamt_0_alt */, -{ "if Pv4 Rd32 = memb ( Rs32 + Rt32 << #1 )" , "0011 00 00 000 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrbt_rr_expand_shamt_1_alt */, -{ "if Pv4 Rd32 = memb ( Rs32 + Rt32 << #2 )" , "0011 00 00 000 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrbt_rr_expand_shamt_2_alt */, -{ "if Pv4 Rd32 = memb ( Rs32 + Rt32 << #3 )" , "0011 00 00 000 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrbt_rr_expand_shamt_3_alt */, -{ "if Pv4 Rd32 = memh ( Rs32 + Rt32 << #0 )" , "0011 00 00 010 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrht_rr_expand_shamt_0_alt */, -{ "if Pv4 Rd32 = memh ( Rs32 + Rt32 << #1 )" , "0011 00 00 010 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrht_rr_expand_shamt_1_alt */, -{ "if Pv4 Rd32 = memh ( Rs32 + Rt32 << #2 )" , "0011 00 00 010 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrht_rr_expand_shamt_2_alt */, -{ "if Pv4 Rd32 = memh ( Rs32 + Rt32 << #3 )" , "0011 00 00 010 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrht_rr_expand_shamt_3_alt */, -{ "if Pv4 Rd32 = memub ( Rs32 + Rt32 << #0 )" , "0011 00 00 001 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrubt_rr_expand_shamt_0_alt */, -{ "if Pv4 Rd32 = memub ( Rs32 + Rt32 << #1 )" , "0011 00 00 001 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrubt_rr_expand_shamt_1_alt */, -{ "if Pv4 Rd32 = memub ( Rs32 + Rt32 << #2 )" , "0011 00 00 001 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrubt_rr_expand_shamt_2_alt */, -{ "if Pv4 Rd32 = memub ( Rs32 + Rt32 << #3 )" , "0011 00 00 001 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrubt_rr_expand_shamt_3_alt */, -{ "if Pv4 Rd32 = memuh ( Rs32 + Rt32 << #0 )" , "0011 00 00 011 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadruht_rr_expand_shamt_0_alt */, -{ "if Pv4 Rd32 = memuh ( Rs32 + Rt32 << #1 )" , "0011 00 00 011 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadruht_rr_expand_shamt_1_alt */, -{ "if Pv4 Rd32 = memuh ( Rs32 + Rt32 << #2 )" , "0011 00 00 011 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadruht_rr_expand_shamt_2_alt */, -{ "if Pv4 Rd32 = memuh ( Rs32 + Rt32 << #3 )" , "0011 00 00 011 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadruht_rr_expand_shamt_3_alt */, -{ "if Pv4 Rd32 = memw ( Rs32 + Rt32 << #0 )" , "0011 00 00 100 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrit_rr_expand_shamt_0_alt */, -{ "if Pv4 Rd32 = memw ( Rs32 + Rt32 << #1 )" , "0011 00 00 100 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrit_rr_expand_shamt_1_alt */, -{ "if Pv4 Rd32 = memw ( Rs32 + Rt32 << #2 )" , "0011 00 00 100 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrit_rr_expand_shamt_2_alt */, -{ "if Pv4 Rd32 = memw ( Rs32 + Rt32 << #3 )" , "0011 00 00 100 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrit_rr_expand_shamt_3_alt */, -{ "if Pv4 Rdd32 = memd ( Rs32 + Rt32 << #0 )" , "0011 00 00 110 sssss PP0ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrdt_rr_expand_shamt_0_alt */, -{ "if Pv4 Rdd32 = memd ( Rs32 + Rt32 << #1 )" , "0011 00 00 110 sssss PP0ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrdt_rr_expand_shamt_1_alt */, -{ "if Pv4 Rdd32 = memd ( Rs32 + Rt32 << #2 )" , "0011 00 00 110 sssss PP1ttttt 0vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrdt_rr_expand_shamt_2_alt */, -{ "if Pv4 Rdd32 = memd ( Rs32 + Rt32 << #3 )" , "0011 00 00 110 sssss PP1ttttt 1vvddddd" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* L4_ploadrdt_rr_expand_shamt_3_alt */, -{ "if Pv4 memb ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP000ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbnewt_abs_alt */, -{ "if Pv4 memb ( #u6 ) = Rt32" , "1010 1 11 1 000 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerbt_abs_alt */, -{ "if Pv4 memb ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirbt_zomap_alt)}, /* mapped to if (Pv4) memb(Rs32+#0)=#S6 */ -{ "if Pv4 memb ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerbnewt_zomap_alt)}, /* mapped to if (Pv4) memb(Rs32+#0)=Nt8.new */ -{ "if Pv4 memb ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerbt_zomap_alt)}, /* mapped to if (Pv4) memb(Rs32+#0)=Rt32 */ -{ "if Pv4 memb ( Rs32 + #u6:0 ) = #S6" , "0011 100 00 00 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirbt_io_alt */, -{ "if Pv4 memb ( Rs32 + #u6:0 ) = Nt8 .new" , "0100 0000 101 sssss PPi00ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerbnewt_io_alt */, -{ "if Pv4 memb ( Rs32 + #u6:0 ) = Rt32" , "0100 0000 000 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerbt_io_alt */, -{ "if Pv4 memb ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerbnewt_rr_expand_shamt_0_alt */, -{ "if Pv4 memb ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 00 000 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerbt_rr_expand_shamt_0_alt */, -{ "if Pv4 memb ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerbnewt_rr_expand_shamt_1_alt */, -{ "if Pv4 memb ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 00 000 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerbt_rr_expand_shamt_1_alt */, -{ "if Pv4 memb ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 0vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerbnewt_rr_expand_shamt_2_alt */, -{ "if Pv4 memb ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 00 000 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerbt_rr_expand_shamt_2_alt */, -{ "if Pv4 memb ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 1vv00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerbnewt_rr_expand_shamt_3_alt */, -{ "if Pv4 memb ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 00 000 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerbt_rr_expand_shamt_3_alt */, -{ "if Pv4 memb ( Rz32 ++ #s4:0 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP100ttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S2_pstorerbnewt_pi_alt */, -{ "if Pv4 memb ( Rz32 ++ #s4:0 ) = Rt32" , "1010 1 01 1 000 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerbt_pi_alt */, -{ "if Pv4 memd ( #u6 ) = Rtt32" , "1010 1 11 1 110 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerdt_abs_alt */, -{ "if Pv4 memd ( Rs32 ) = Rtt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerdt_zomap_alt)}, /* mapped to if (Pv4) memd(Rs32+#0)=Rtt32 */ -{ "if Pv4 memd ( Rs32 + #u6:3 ) = Rtt32" , "0100 0000 110 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerdt_io_alt */, -{ "if Pv4 memd ( Rs32 + Ru32 << #0 ) = Rtt32" , "0011 01 00 110 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerdt_rr_expand_shamt_0_alt */, -{ "if Pv4 memd ( Rs32 + Ru32 << #1 ) = Rtt32" , "0011 01 00 110 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerdt_rr_expand_shamt_1_alt */, -{ "if Pv4 memd ( Rs32 + Ru32 << #2 ) = Rtt32" , "0011 01 00 110 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerdt_rr_expand_shamt_2_alt */, -{ "if Pv4 memd ( Rs32 + Ru32 << #3 ) = Rtt32" , "0011 01 00 110 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerdt_rr_expand_shamt_3_alt */, -{ "if Pv4 memd ( Rz32 ++ #s4:3 ) = Rtt32" , "1010 1 01 1 110 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerdt_pi_alt */, -{ "if Pv4 memh ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP001ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerhnewt_abs_alt */, -{ "if Pv4 memh ( #u6 ) = Rt32.h" , "1010 1 11 1 011 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerft_abs_alt */, -{ "if Pv4 memh ( #u6 ) = Rt32" , "1010 1 11 1 010 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerht_abs_alt */, -{ "if Pv4 memh ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirht_zomap_alt)}, /* mapped to if (Pv4) memh(Rs32+#0)=#S6 */ -{ "if Pv4 memh ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerhnewt_zomap_alt)}, /* mapped to if (Pv4) memh(Rs32+#0)=Nt8.new */ -{ "if Pv4 memh ( Rs32 ) = Rt32.h" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerft_zomap_alt)}, /* mapped to if (Pv4) memh(Rs32+#0)=Rt32.h */ -{ "if Pv4 memh ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerht_zomap_alt)}, /* mapped to if (Pv4) memh(Rs32+#0)=Rt32 */ -{ "if Pv4 memh ( Rs32 + #u6:1 ) = #S6" , "0011 100 00 01 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirht_io_alt */, -{ "if Pv4 memh ( Rs32 + #u6:1 ) = Nt8 .new" , "0100 0000 101 sssss PPi01ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerhnewt_io_alt */, -{ "if Pv4 memh ( Rs32 + #u6:1 ) = Rt32.h" , "0100 0000 011 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerft_io_alt */, -{ "if Pv4 memh ( Rs32 + #u6:1 ) = Rt32" , "0100 0000 010 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerht_io_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerhnewt_rr_expand_shamt_0_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #0 ) = Rt32.h" , "0011 01 00 011 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerft_rr_expand_shamt_0_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 00 010 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerht_rr_expand_shamt_0_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerhnewt_rr_expand_shamt_1_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #1 ) = Rt32.h" , "0011 01 00 011 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerft_rr_expand_shamt_1_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 00 010 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerht_rr_expand_shamt_1_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 0vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerhnewt_rr_expand_shamt_2_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #2 ) = Rt32.h" , "0011 01 00 011 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerft_rr_expand_shamt_2_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 00 010 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerht_rr_expand_shamt_2_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 1vv01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerhnewt_rr_expand_shamt_3_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #3 ) = Rt32.h" , "0011 01 00 011 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerft_rr_expand_shamt_3_alt */, -{ "if Pv4 memh ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 00 010 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerht_rr_expand_shamt_3_alt */, -{ "if Pv4 memh ( Rz32 ++ #s4:1 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP101ttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S2_pstorerhnewt_pi_alt */, -{ "if Pv4 memh ( Rz32 ++ #s4:1 ) = Rt32.h" , "1010 1 01 1 011 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerft_pi_alt */, -{ "if Pv4 memh ( Rz32 ++ #s4:1 ) = Rt32" , "1010 1 01 1 010 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerht_pi_alt */, -{ "if Pv4 memw ( #u6 ) = Nt8 .new" , "1010 1 11 1 101 ---ii PP010ttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerinewt_abs_alt */, -{ "if Pv4 memw ( #u6 ) = Rt32" , "1010 1 11 1 100 ---ii PP0ttttt 1iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_pstorerit_abs_alt */, -{ "if Pv4 memw ( Rs32 ) = #S6" , "0000IIIIIIvvsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirit_zomap_alt)}, /* mapped to if (Pv4) memw(Rs32+#0)=#S6 */ -{ "if Pv4 memw ( Rs32 ) = Nt8 .new" , "0000tttvvsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerinewt_zomap_alt)}, /* mapped to if (Pv4) memw(Rs32+#0)=Nt8.new */ -{ "if Pv4 memw ( Rs32 ) = Rt32" , "0000vvsssssttttt0000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_pstorerit_zomap_alt)}, /* mapped to if (Pv4) memw(Rs32+#0)=Rt32 */ -{ "if Pv4 memw ( Rs32 + #u6:2 ) = #S6" , "0011 100 00 10 sssss PPIiiiii ivvIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirit_io_alt */, -{ "if Pv4 memw ( Rs32 + #u6:2 ) = Nt8 .new" , "0100 0000 101 sssss PPi10ttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerinewt_io_alt */, -{ "if Pv4 memw ( Rs32 + #u6:2 ) = Rt32" , "0100 0000 100 sssss PPittttt iiiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_pstorerit_io_alt */, -{ "if Pv4 memw ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerinewt_rr_expand_shamt_0_alt */, -{ "if Pv4 memw ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 01 00 100 sssss PP0uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerit_rr_expand_shamt_0_alt */, -{ "if Pv4 memw ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 01 00 101 sssss PP0uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerinewt_rr_expand_shamt_1_alt */, -{ "if Pv4 memw ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 01 00 100 sssss PP0uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerit_rr_expand_shamt_1_alt */, -{ "if Pv4 memw ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 0vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerinewt_rr_expand_shamt_2_alt */, -{ "if Pv4 memw ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 01 00 100 sssss PP1uuuuu 0vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerit_rr_expand_shamt_2_alt */, -{ "if Pv4 memw ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 01 00 101 sssss PP1uuuuu 1vv10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S4_pstorerinewt_rr_expand_shamt_3_alt */, -{ "if Pv4 memw ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 01 00 100 sssss PP1uuuuu 1vvttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S4_pstorerit_rr_expand_shamt_3_alt */, -{ "if Pv4 memw ( Rz32 ++ #s4:2 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP110ttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_DOTOLD|CONDITIONAL_EXEC, NULL} /* S2_pstorerinewt_pi_alt */, -{ "if Pv4 memw ( Rz32 ++ #s4:2 ) = Rt32" , "1010 1 01 1 100 zzzzz PP1ttttt 0iiii0vv" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC, NULL} /* S2_pstorerit_pi_alt */, -{ "immext ( #u26:6 )" , "0000iiii iiiiiiii PPiiiiii iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_IT_EXTENDER, NULL} /* A4_ext */, -{ "isync" , "0101 0111 11000000 PP0---00 00000010" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_isync */, -{ "jump #r22:2" , "0101 100i iiiiiiii PPiiiiii iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC, 0|A_JUMP|A_DIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_jump */, -{ "jumpr Rs32" , "0101 0010 100sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_IMPLICIT_WRITES_PC|A_COF, NULL} /* J2_jumpr */, -{ "k0lock" , "0110 1100 001----- PP------ 011-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_k0lock */, -{ "k0unlock" , "0110 1100 001----- PP------ 100-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_k0unlock */, -{ "l2cleanidx ( Rs32 )" , "1010 011 00 01sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y5_l2cleanidx */, -{ "l2cleaninvidx ( Rs32 )" , "1010 100 00 11sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y2_l2cleaninvidx */, -{ "l2fetch ( Rs32 , Rt32 )" , "1010 011 00 00sssss PP-ttttt --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_RESTRICT_SLOT0ONLY|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y4_l2fetch */, -{ "l2fetch ( Rs32 , Rtt32 )" , "1010 011 01 00sssss PP-ttttt --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_RESTRICT_SLOT0ONLY|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y5_l2fetch */, -{ "l2invidx ( Rs32 )" , "1010 011 00 10sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK|A_RESTRICT_SLOT0ONLY|A_CACHEOP|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* Y5_l2invidx */, -{ "l2kill" , "1010 100 00 01----- PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y2_l2kill */, -{ "l2tagw ( Rs32 , Rt32 )" , "1010 010 00 10sssss PP0ttttt --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_PRIV|A_NOTE_PRIV|A_RESTRICT_SLOT0ONLY|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_CACHEOP, NULL} /* Y4_l2tagw */, -{ "loop0 ( #r7:2 , #U10 )" , "0110 1001 000IIIII PP-iiiii IIIii-II" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC0|IMPLICIT_SA0|IMPLICIT_SR_OVF, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_HWLOOP0_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC0|A_IMPLICIT_WRITES_SA0|A_IMPLICIT_WRITES_SRBIT|A_RESTRICT_NOSRMOVE|A_EXTENDABLE|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_loop0i */, -{ "loop0 ( #r7:2 , Rs32 )" , "0110 0000 000sssss PP-iiiii ---ii---" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC0|IMPLICIT_SA0|IMPLICIT_SR_OVF, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_HWLOOP0_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC0|A_IMPLICIT_WRITES_SA0|A_IMPLICIT_WRITES_SRBIT|A_RESTRICT_NOSRMOVE|A_EXTENDABLE|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_loop0r */, -{ "loop1 ( #r7:2 , #U10 )" , "0110 1001 001IIIII PP-iiiii IIIii-II" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC1|IMPLICIT_SA1, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_HWLOOP1_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC1|A_IMPLICIT_WRITES_SA1|A_EXTENDABLE|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_loop1i */, -{ "loop1 ( #r7:2 , Rs32 )" , "0110 0000 001sssss PP-iiiii ---ii---" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC1|IMPLICIT_SA1, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_HWLOOP1_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC1|A_IMPLICIT_WRITES_SA1|A_EXTENDABLE|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_loop1r */, -{ "memb ( gp + #u16:0 ) = Nt8 .new" , "0100 1ii0 101 iiiii PPi00ttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerbnewgp */, -{ "memb ( gp + #u16:0 ) = Rt32" , "0100 1ii0 000 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerbgp */, -{ "memb ( #g16:0 ) = Nt8 .new" , "0100 1ii0 101 iiiii PPi00ttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerbnewgp */, -{ "memb ( #g16:0 ) = Rt32" , "0100 1ii0 000 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerbgp */, -{ "memb ( Rf32 = #U6 ) = Nt8 .new" , "1010 1 01 1 101 fffff PP000ttt 1-IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerbnew_ap */, -{ "memb ( Rf32 = #U6 ) = Rt32" , "1010 1 01 1 000 fffff PP0ttttt 1-IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerb_ap */, -{ "memb ( Rs16 + #U4:0 ) = #0 ; allocframe ( #u5:3 )" , "11110010ssssIIIIEE01110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi0_SS2_allocframe */, -{ "memb ( Rs16 + #U4:0 ) = #0 ; memd ( Sp + #s6:3 ) = Rtt8" , "11110010ssssIIIIEE00101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi0_SS2_stored_sp */, -{ "memb ( Rs16 + #U4:0 ) = #0 ; memw ( Sp + #u5:2 ) = Rt16" , "11110010ssssIIIIEE00100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi0_SS2_storew_sp */, -{ "memb ( Rs16 + #U4:0 ) = #1 ; allocframe ( #u5:3 )" , "11110011ssssIIIIEE01110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi1_SS2_allocframe */, -{ "memb ( Rs16 + #U4:0 ) = #1 ; memd ( Sp + #s6:3 ) = Rtt8" , "11110011ssssIIIIEE00101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi1_SS2_stored_sp */, -{ "memb ( Rs16 + #U4:0 ) = #1 ; memw ( Sp + #u5:2 ) = Rt16" , "11110011ssssIIIIEE00100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi1_SS2_storew_sp */, -{ "memb ( Rs16 + #U4:0 ) = Rt16 ; allocframe ( #u5:3 )" , "1011IIIIssssttttEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS2_allocframe */, -{ "memb ( Rs16 + #U4:0 ) = Rv16 ; memd ( Sp + #s6:3 ) = Rtt8" , "1011IIIIssssvvvvEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS2_stored_sp */, -{ "memb ( Rs16 + #U4:0 ) = Rv16 ; memw ( Sp + #u5:2 ) = Rt16" , "1011IIIIssssvvvvEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS2_storew_sp */, -{ "memb ( Rs32 ) &= Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_and_memopb_zomap)}, /* mapped to memb(Rs32+#0)&=Rt32 */ -{ "memb ( Rs32 ) += #U5" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_iadd_memopb_zomap)}, /* mapped to memb(Rs32+#0)+=#U5 */ -{ "memb ( Rs32 ) += Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_add_memopb_zomap)}, /* mapped to memb(Rs32+#0)+=Rt32 */ -{ "memb ( Rs32 ) -= #U5" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_isub_memopb_zomap)}, /* mapped to memb(Rs32+#0)-=#U5 */ -{ "memb ( Rs32 ) -= Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_sub_memopb_zomap)}, /* mapped to memb(Rs32+#0)-=Rt32 */ -{ "memb ( Rs32 ) = #S8" , "0000IIIIIIIIsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirb_zomap)}, /* mapped to memb(Rs32+#0)=#S8 */ -{ "memb ( Rs32 ) = Nt8 .new" , "0000tttsssss00000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_storerbnew_zomap)}, /* mapped to memb(Rs32+#0)=Nt8.new */ -{ "memb ( Rs32 ) = Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_storerb_zomap)}, /* mapped to memb(Rs32+#0)=Rt32 */ -{ "memb ( Rs32 ) = clrbit ( #U5 )" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_iand_memopb_zomap)}, /* mapped to memb(Rs32+#0)=clrbit(#U5) */ -{ "memb ( Rs32 ) = setbit ( #U5 )" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_ior_memopb_zomap)}, /* mapped to memb(Rs32+#0)=setbit(#U5) */ -{ "memb ( Rs32 ) |= Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_or_memopb_zomap)}, /* mapped to memb(Rs32+#0)|=Rt32 */ -{ "memb ( Rs32 + #s11:0 ) = Nt8 .new" , "1010 0 ii 1 101 sssss PPi00ttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerbnew_io */, -{ "memb ( Rs32 + #s11:0 ) = Rt32" , "1010 0 ii 1 000 sssss PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerb_io */, -{ "memb ( Rs32 + #u6:0 ) &= Rt32" , "0011 111 0- 00sssss PP0iiiii i10ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_1B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_and_memopb_io */, -{ "memb ( Rs32 + #u6:0 ) += #U5" , "0011 111 1- 00sssss PP0iiiii i00IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_1B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_iadd_memopb_io */, -{ "memb ( Rs32 + #u6:0 ) += Rt32" , "0011 111 0- 00sssss PP0iiiii i00ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_1B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_add_memopb_io */, -{ "memb ( Rs32 + #u6:0 ) -= #U5" , "0011 111 1- 00sssss PP0iiiii i01IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_1B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_isub_memopb_io */, -{ "memb ( Rs32 + #u6:0 ) -= Rt32" , "0011 111 0- 00sssss PP0iiiii i01ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_1B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_sub_memopb_io */, -{ "memb ( Rs32 + #u6:0 ) = #S8" , "0011 110 -- 00 sssss PPIiiiii iIIIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_1B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirb_io */, -{ "memb ( Rs32 + #u6:0 ) = clrbit ( #U5 )" , "0011 111 1- 00sssss PP0iiiii i10IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_1B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_iand_memopb_io */, -{ "memb ( Rs32 + #u6:0 ) = setbit ( #U5 )" , "0011 111 1- 00sssss PP0iiiii i11IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_1B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_ior_memopb_io */, -{ "memb ( Rs32 + #u6:0 ) |= Rt32" , "0011 111 0- 00sssss PP0iiiii i11ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_1B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_or_memopb_io */, -{ "memb ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 1011 101 sssss PP0uuuuu 0--00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerbnew_rr_expand_shamt_0 */, -{ "memb ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 1011 000 sssss PP0uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerb_rr_expand_shamt_0 */, -{ "memb ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 1011 101 sssss PP0uuuuu 1--00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerbnew_rr_expand_shamt_1 */, -{ "memb ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 1011 000 sssss PP0uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerb_rr_expand_shamt_1 */, -{ "memb ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 1011 101 sssss PP1uuuuu 0--00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerbnew_rr_expand_shamt_2 */, -{ "memb ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 1011 000 sssss PP1uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerb_rr_expand_shamt_2 */, -{ "memb ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 1011 101 sssss PP1uuuuu 1--00ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerbnew_rr_expand_shamt_3 */, -{ "memb ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 1011 000 sssss PP1uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerb_rr_expand_shamt_3 */, -{ "memb ( Ru16 + #U4:0 ) = #0 ; memb ( Rs16 + #u4:0 ) = #0" , "11110010uuuuIIIIEE010010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi0_SS2_storebi0 */, -{ "memb ( Ru16 + #U4:0 ) = #0 ; memb ( Rs16 + #u4:0 ) = #1" , "11110010uuuuIIIIEE010011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi0_SS2_storebi1 */, -{ "memb ( Ru16 + #U4:0 ) = #0 ; memh ( Rs16 + #u3:1 ) = Rt16" , "11110010uuuuIIIIEE000iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi0_SS2_storeh_io */, -{ "memb ( Ru16 + #U4:0 ) = #0 ; memw ( Rs16 + #u4:2 ) = #0" , "11110010uuuuIIIIEE010000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi0_SS2_storewi0 */, -{ "memb ( Ru16 + #U4:0 ) = #0 ; memw ( Rs16 + #u4:2 ) = #1" , "11110010uuuuIIIIEE010001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi0_SS2_storewi1 */, -{ "memb ( Ru16 + #U4:0 ) = #1 ; memb ( Rs16 + #u4:0 ) = #0" , "11110011uuuuIIIIEE010010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi1_SS2_storebi0 */, -{ "memb ( Ru16 + #U4:0 ) = #1 ; memb ( Rs16 + #u4:0 ) = #1" , "11110011uuuuIIIIEE010011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi1_SS2_storebi1 */, -{ "memb ( Ru16 + #U4:0 ) = #1 ; memh ( Rs16 + #u3:1 ) = Rt16" , "11110011uuuuIIIIEE000iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi1_SS2_storeh_io */, -{ "memb ( Ru16 + #U4:0 ) = #1 ; memw ( Rs16 + #u4:2 ) = #0" , "11110011uuuuIIIIEE010000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi1_SS2_storewi0 */, -{ "memb ( Ru16 + #U4:0 ) = #1 ; memw ( Rs16 + #u4:2 ) = #1" , "11110011uuuuIIIIEE010001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storebi1_SS2_storewi1 */, -{ "memb ( Ru16 + #U4:0 ) = Rt16 ; memb ( Rs16 + #u4:0 ) = #0" , "1011IIIIuuuuttttEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS2_storebi0 */, -{ "memb ( Ru16 + #U4:0 ) = Rt16 ; memb ( Rs16 + #u4:0 ) = #1" , "1011IIIIuuuuttttEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS2_storebi1 */, -{ "memb ( Ru16 + #U4:0 ) = Rt16 ; memw ( Rs16 + #u4:2 ) = #0" , "1011IIIIuuuuttttEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS2_storewi0 */, -{ "memb ( Ru16 + #U4:0 ) = Rt16 ; memw ( Rs16 + #u4:2 ) = #1" , "1011IIIIuuuuttttEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS2_storewi1 */, -{ "memb ( Ru16 + #U4:0 ) = Rv16 ; memb ( Rs16 + #u4:0 ) = Rt16" , "1011IIIIuuuuvvvvEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS1_storeb_io */, -{ "memb ( Ru16 + #U4:0 ) = Rv16 ; memh ( Rs16 + #u3:1 ) = Rt16" , "1011IIIIuuuuvvvvEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS2_storeh_io */, -{ "memb ( Ru16 + #U4:0 ) = Rv16 ; memw ( Rs16 + #u4:2 ) = Rt16" , "1011IIIIuuuuvvvvEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storeb_io_SS1_storew_io */, -{ "memb ( Ru32 << #0 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP000ttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerbnew_ur_expand_shamt_0 */, -{ "memb ( Ru32 << #0 + #U6 ) = Rt32" , "1010 1 10 1 000 uuuuu PP0ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerb_ur_expand_shamt_0 */, -{ "memb ( Ru32 << #1 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP000ttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerbnew_ur_expand_shamt_1 */, -{ "memb ( Ru32 << #1 + #U6 ) = Rt32" , "1010 1 10 1 000 uuuuu PP0ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerb_ur_expand_shamt_1 */, -{ "memb ( Ru32 << #2 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP100ttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerbnew_ur_expand_shamt_2 */, -{ "memb ( Ru32 << #2 + #U6 ) = Rt32" , "1010 1 10 1 000 uuuuu PP1ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerb_ur_expand_shamt_2 */, -{ "memb ( Ru32 << #3 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP100ttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerbnew_ur_expand_shamt_3 */, -{ "memb ( Ru32 << #3 + #U6 ) = Rt32" , "1010 1 10 1 000 uuuuu PP1ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerb_ur_expand_shamt_3 */, -{ "memb ( Rz32 ++ #s4:0 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP000ttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S2_storerbnew_pi */, -{ "memb ( Rz32 ++ #s4:0 ) = Rt32" , "1010 1 01 1 000 zzzzz PP0ttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerb_pi */, -{ "memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) ) = Nt8 .new" , "1010 1 00 1 101 zzzzz PPu00ttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerbnew_pci */, -{ "memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) ) = Rt32" , "1010 1 00 1 000 zzzzz PPuttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerb_pci */, -{ "memb ( Rz32 ++ Mu2 ) = Nt8 .new" , "1010 1 10 1 101 zzzzz PPu00ttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S2_storerbnew_pr */, -{ "memb ( Rz32 ++ Mu2 ) = Rt32" , "1010 1 10 1 000 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerb_pr */, -{ "memb ( Rz32 ++ Mu2 :brev ) = Nt8 .new" , "1010 1 11 1 101 zzzzz PPu00ttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S2_storerbnew_pbr */, -{ "memb ( Rz32 ++ Mu2 :brev ) = Rt32" , "1010 1 11 1 000 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerb_pbr */, -{ "memb ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" , "1010 1 00 1 101 zzzzz PPu00ttt 0-----1-" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_1B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerbnew_pcr */, -{ "memb ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" , "1010 1 00 1 000 zzzzz PPuttttt 0-----1-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerb_pcr */, -{ "memd ( gp + #u16:3 ) = Rtt32" , "0100 1ii0 110 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerdgp */, -{ "memd ( #g16:3 ) = Rtt32" , "0100 1ii0 110 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerdgp */, -{ "memd ( Rf32 = #U6 ) = Rtt32" , "1010 1 01 1 110 fffff PP0ttttt 1-IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerd_ap */, -{ "memd ( Rs32 ) = Rtt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_storerd_zomap)}, /* mapped to memd(Rs32+#0)=Rtt32 */ -{ "memd ( Rs32 + #s11:3 ) = Rtt32" , "1010 0 ii 1 110 sssss PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerd_io */, -{ "memd ( Rs32 + Ru32 << #0 ) = Rtt32" , "0011 1011 110 sssss PP0uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerd_rr_expand_shamt_0 */, -{ "memd ( Rs32 + Ru32 << #1 ) = Rtt32" , "0011 1011 110 sssss PP0uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerd_rr_expand_shamt_1 */, -{ "memd ( Rs32 + Ru32 << #2 ) = Rtt32" , "0011 1011 110 sssss PP1uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerd_rr_expand_shamt_2 */, -{ "memd ( Rs32 + Ru32 << #3 ) = Rtt32" , "0011 1011 110 sssss PP1uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerd_rr_expand_shamt_3 */, -{ "memd ( Ru32 << #0 + #U6 ) = Rtt32" , "1010 1 10 1 110 uuuuu PP0ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerd_ur_expand_shamt_0 */, -{ "memd ( Ru32 << #1 + #U6 ) = Rtt32" , "1010 1 10 1 110 uuuuu PP0ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerd_ur_expand_shamt_1 */, -{ "memd ( Ru32 << #2 + #U6 ) = Rtt32" , "1010 1 10 1 110 uuuuu PP1ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerd_ur_expand_shamt_2 */, -{ "memd ( Ru32 << #3 + #U6 ) = Rtt32" , "1010 1 10 1 110 uuuuu PP1ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerd_ur_expand_shamt_3 */, -{ "memd ( Rz32 ++ #s4:3 ) = Rtt32" , "1010 1 01 1 110 zzzzz PP0ttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerd_pi */, -{ "memd ( Rz32 ++ #s4:3 :circ ( Mu2 ) ) = Rtt32" , "1010 1 00 1 110 zzzzz PPuttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerd_pci */, -{ "memd ( Rz32 ++ Mu2 ) = Rtt32" , "1010 1 10 1 110 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerd_pr */, -{ "memd ( Rz32 ++ Mu2 :brev ) = Rtt32" , "1010 1 11 1 110 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerd_pbr */, -{ "memd ( Rz32 ++I :circ ( Mu2 ) ) = Rtt32" , "1010 1 00 1 110 zzzzz PPuttttt 0-----1-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerd_pcr */, -{ "memd ( Sp + #S6:3 ) = Rtt8 ; allocframe ( #u5:3 )" , "1110101IIIIIItttEE01110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SS2_stored_sp_SS2_allocframe */, -{ "memd ( Sp + #S6:3 ) = Rtt8 ; memb ( Rs16 + #u4:0 ) = #0" , "1110101IIIIIItttEE010010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_stored_sp_SS2_storebi0 */, -{ "memd ( Sp + #S6:3 ) = Rtt8 ; memb ( Rs16 + #u4:0 ) = #1" , "1110101IIIIIItttEE010011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_stored_sp_SS2_storebi1 */, -{ "memd ( Sp + #S6:3 ) = Rtt8 ; memw ( Rs16 + #u4:2 ) = #0" , "1110101IIIIIItttEE010000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_stored_sp_SS2_storewi0 */, -{ "memd ( Sp + #S6:3 ) = Rtt8 ; memw ( Rs16 + #u4:2 ) = #1" , "1110101IIIIIItttEE010001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_stored_sp_SS2_storewi1 */, -{ "memd ( Sp + #S6:3 ) = Rvv8 ; memd ( Sp + #s6:3 ) = Rtt8" , "1110101IIIIIIvvvEE00101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_stored_sp_SS2_stored_sp */, -{ "memd ( Sp + #S6:3 ) = Rvv8 ; memh ( Rs16 + #u3:1 ) = Rt16" , "1110101IIIIIIvvvEE000iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_stored_sp_SS2_storeh_io */, -{ "memd ( Sp + #S6:3 ) = Rvv8 ; memw ( Sp + #u5:2 ) = Rt16" , "1110101IIIIIIvvvEE00100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_stored_sp_SS2_storew_sp */, -{ "memd_locked ( Rs32 , Pd4 ) = Rtt32" , "1010 000 01 11sssss PP-ttttt ------dd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_stored_locked */, -{ "memh ( gp + #u16:1 ) = Nt8 .new" , "0100 1ii0 101 iiiii PPi01ttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerhnewgp */, -{ "memh ( gp + #u16:1 ) = Rt32.h" , "0100 1ii0 011 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerfgp */, -{ "memh ( gp + #u16:1 ) = Rt32" , "0100 1ii0 010 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerhgp */, -{ "memh ( #g16:1 ) = Nt8 .new" , "0100 1ii0 101 iiiii PPi01ttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerhnewgp */, -{ "memh ( #g16:1 ) = Rt32.h" , "0100 1ii0 011 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerfgp */, -{ "memh ( #g16:1 ) = Rt32" , "0100 1ii0 010 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerhgp */, -{ "memh ( Rf32 = #U6 ) = Nt8 .new" , "1010 1 01 1 101 fffff PP001ttt 1-IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerhnew_ap */, -{ "memh ( Rf32 = #U6 ) = Rt32.h" , "1010 1 01 1 011 fffff PP0ttttt 1-IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerf_ap */, -{ "memh ( Rf32 = #U6 ) = Rt32" , "1010 1 01 1 010 fffff PP0ttttt 1-IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerh_ap */, -{ "memh ( Rs16 + #U3:1 ) = Rt16 ; allocframe ( #u5:3 )" , "11100IIIssssttttEE01110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SS2_storeh_io_SS2_allocframe */, -{ "memh ( Rs16 + #U3:1 ) = Rv16 ; memd ( Sp + #s6:3 ) = Rtt8" , "11100IIIssssvvvvEE00101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storeh_io_SS2_stored_sp */, -{ "memh ( Rs16 + #U3:1 ) = Rv16 ; memw ( Sp + #u5:2 ) = Rt16" , "11100IIIssssvvvvEE00100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storeh_io_SS2_storew_sp */, -{ "memh ( Rs32 ) &= Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_and_memoph_zomap)}, /* mapped to memh(Rs32+#0)&=Rt32 */ -{ "memh ( Rs32 ) += #U5" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_iadd_memoph_zomap)}, /* mapped to memh(Rs32+#0)+=#U5 */ -{ "memh ( Rs32 ) += Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_add_memoph_zomap)}, /* mapped to memh(Rs32+#0)+=Rt32 */ -{ "memh ( Rs32 ) -= #U5" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_isub_memoph_zomap)}, /* mapped to memh(Rs32+#0)-=#U5 */ -{ "memh ( Rs32 ) -= Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_sub_memoph_zomap)}, /* mapped to memh(Rs32+#0)-=Rt32 */ -{ "memh ( Rs32 ) = #S8" , "0000IIIIIIIIsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeirh_zomap)}, /* mapped to memh(Rs32+#0)=#S8 */ -{ "memh ( Rs32 ) = Nt8 .new" , "0000tttsssss00000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_storerhnew_zomap)}, /* mapped to memh(Rs32+#0)=Nt8.new */ -{ "memh ( Rs32 ) = Rt32.h" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_storerf_zomap)}, /* mapped to memh(Rs32+#0)=Rt32.h */ -{ "memh ( Rs32 ) = Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_storerh_zomap)}, /* mapped to memh(Rs32+#0)=Rt32 */ -{ "memh ( Rs32 ) = clrbit ( #U5 )" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_iand_memoph_zomap)}, /* mapped to memh(Rs32+#0)=clrbit(#U5) */ -{ "memh ( Rs32 ) = setbit ( #U5 )" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_ior_memoph_zomap)}, /* mapped to memh(Rs32+#0)=setbit(#U5) */ -{ "memh ( Rs32 ) |= Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_or_memoph_zomap)}, /* mapped to memh(Rs32+#0)|=Rt32 */ -{ "memh ( Rs32 + #s11:1 ) = Nt8 .new" , "1010 0 ii 1 101 sssss PPi01ttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerhnew_io */, -{ "memh ( Rs32 + #s11:1 ) = Rt32.h" , "1010 0 ii 1 011 sssss PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerf_io */, -{ "memh ( Rs32 + #s11:1 ) = Rt32" , "1010 0 ii 1 010 sssss PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerh_io */, -{ "memh ( Rs32 + #u6:1 ) &= Rt32" , "0011 111 0- 01sssss PP0iiiii i10ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_2B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_and_memoph_io */, -{ "memh ( Rs32 + #u6:1 ) += #U5" , "0011 111 1- 01sssss PP0iiiii i00IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_2B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_iadd_memoph_io */, -{ "memh ( Rs32 + #u6:1 ) += Rt32" , "0011 111 0- 01sssss PP0iiiii i00ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_2B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_add_memoph_io */, -{ "memh ( Rs32 + #u6:1 ) -= #U5" , "0011 111 1- 01sssss PP0iiiii i01IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_2B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_isub_memoph_io */, -{ "memh ( Rs32 + #u6:1 ) -= Rt32" , "0011 111 0- 01sssss PP0iiiii i01ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_2B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_sub_memoph_io */, -{ "memh ( Rs32 + #u6:1 ) = #S8" , "0011 110 -- 01 sssss PPIiiiii iIIIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_2B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeirh_io */, -{ "memh ( Rs32 + #u6:1 ) = clrbit ( #U5 )" , "0011 111 1- 01sssss PP0iiiii i10IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_2B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_iand_memoph_io */, -{ "memh ( Rs32 + #u6:1 ) = setbit ( #U5 )" , "0011 111 1- 01sssss PP0iiiii i11IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_2B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_ior_memoph_io */, -{ "memh ( Rs32 + #u6:1 ) |= Rt32" , "0011 111 0- 01sssss PP0iiiii i11ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_2B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_or_memoph_io */, -{ "memh ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 1011 101 sssss PP0uuuuu 0--01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerhnew_rr_expand_shamt_0 */, -{ "memh ( Rs32 + Ru32 << #0 ) = Rt32.h" , "0011 1011 011 sssss PP0uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerf_rr_expand_shamt_0 */, -{ "memh ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 1011 010 sssss PP0uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerh_rr_expand_shamt_0 */, -{ "memh ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 1011 101 sssss PP0uuuuu 1--01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerhnew_rr_expand_shamt_1 */, -{ "memh ( Rs32 + Ru32 << #1 ) = Rt32.h" , "0011 1011 011 sssss PP0uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerf_rr_expand_shamt_1 */, -{ "memh ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 1011 010 sssss PP0uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerh_rr_expand_shamt_1 */, -{ "memh ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 1011 101 sssss PP1uuuuu 0--01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerhnew_rr_expand_shamt_2 */, -{ "memh ( Rs32 + Ru32 << #2 ) = Rt32.h" , "0011 1011 011 sssss PP1uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerf_rr_expand_shamt_2 */, -{ "memh ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 1011 010 sssss PP1uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerh_rr_expand_shamt_2 */, -{ "memh ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 1011 101 sssss PP1uuuuu 1--01ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerhnew_rr_expand_shamt_3 */, -{ "memh ( Rs32 + Ru32 << #3 ) = Rt32.h" , "0011 1011 011 sssss PP1uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerf_rr_expand_shamt_3 */, -{ "memh ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 1011 010 sssss PP1uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storerh_rr_expand_shamt_3 */, -{ "memh ( Ru16 + #U3:1 ) = Rt16 ; memb ( Rs16 + #u4:0 ) = #0" , "11100IIIuuuuttttEE010010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storeh_io_SS2_storebi0 */, -{ "memh ( Ru16 + #U3:1 ) = Rt16 ; memb ( Rs16 + #u4:0 ) = #1" , "11100IIIuuuuttttEE010011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storeh_io_SS2_storebi1 */, -{ "memh ( Ru16 + #U3:1 ) = Rt16 ; memw ( Rs16 + #u4:2 ) = #0" , "11100IIIuuuuttttEE010000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storeh_io_SS2_storewi0 */, -{ "memh ( Ru16 + #U3:1 ) = Rt16 ; memw ( Rs16 + #u4:2 ) = #1" , "11100IIIuuuuttttEE010001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storeh_io_SS2_storewi1 */, -{ "memh ( Ru16 + #U3:1 ) = Rv16 ; memh ( Rs16 + #u3:1 ) = Rt16" , "11100IIIuuuuvvvvEE000iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storeh_io_SS2_storeh_io */, -{ "memh ( Ru32 << #0 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP001ttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerhnew_ur_expand_shamt_0 */, -{ "memh ( Ru32 << #0 + #U6 ) = Rt32.h" , "1010 1 10 1 011 uuuuu PP0ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerf_ur_expand_shamt_0 */, -{ "memh ( Ru32 << #0 + #U6 ) = Rt32" , "1010 1 10 1 010 uuuuu PP0ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerh_ur_expand_shamt_0 */, -{ "memh ( Ru32 << #1 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP001ttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerhnew_ur_expand_shamt_1 */, -{ "memh ( Ru32 << #1 + #U6 ) = Rt32.h" , "1010 1 10 1 011 uuuuu PP0ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerf_ur_expand_shamt_1 */, -{ "memh ( Ru32 << #1 + #U6 ) = Rt32" , "1010 1 10 1 010 uuuuu PP0ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerh_ur_expand_shamt_1 */, -{ "memh ( Ru32 << #2 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP101ttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerhnew_ur_expand_shamt_2 */, -{ "memh ( Ru32 << #2 + #U6 ) = Rt32.h" , "1010 1 10 1 011 uuuuu PP1ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerf_ur_expand_shamt_2 */, -{ "memh ( Ru32 << #2 + #U6 ) = Rt32" , "1010 1 10 1 010 uuuuu PP1ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerh_ur_expand_shamt_2 */, -{ "memh ( Ru32 << #3 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP101ttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerhnew_ur_expand_shamt_3 */, -{ "memh ( Ru32 << #3 + #U6 ) = Rt32.h" , "1010 1 10 1 011 uuuuu PP1ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerf_ur_expand_shamt_3 */, -{ "memh ( Ru32 << #3 + #U6 ) = Rt32" , "1010 1 10 1 010 uuuuu PP1ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerh_ur_expand_shamt_3 */, -{ "memh ( Rz32 ++ #s4:1 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP001ttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S2_storerhnew_pi */, -{ "memh ( Rz32 ++ #s4:1 ) = Rt32.h" , "1010 1 01 1 011 zzzzz PP0ttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerf_pi */, -{ "memh ( Rz32 ++ #s4:1 ) = Rt32" , "1010 1 01 1 010 zzzzz PP0ttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerh_pi */, -{ "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Nt8 .new" , "1010 1 00 1 101 zzzzz PPu01ttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerhnew_pci */, -{ "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Rt32.h" , "1010 1 00 1 011 zzzzz PPuttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerf_pci */, -{ "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Rt32" , "1010 1 00 1 010 zzzzz PPuttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerh_pci */, -{ "memh ( Rz32 ++ Mu2 ) = Nt8 .new" , "1010 1 10 1 101 zzzzz PPu01ttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S2_storerhnew_pr */, -{ "memh ( Rz32 ++ Mu2 ) = Rt32.h" , "1010 1 10 1 011 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerf_pr */, -{ "memh ( Rz32 ++ Mu2 ) = Rt32" , "1010 1 10 1 010 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerh_pr */, -{ "memh ( Rz32 ++ Mu2 :brev ) = Nt8 .new" , "1010 1 11 1 101 zzzzz PPu01ttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S2_storerhnew_pbr */, -{ "memh ( Rz32 ++ Mu2 :brev ) = Rt32.h" , "1010 1 11 1 011 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerf_pbr */, -{ "memh ( Rz32 ++ Mu2 :brev ) = Rt32" , "1010 1 11 1 010 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storerh_pbr */, -{ "memh ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" , "1010 1 00 1 101 zzzzz PPu01ttt 0-----1-" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_2B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerhnew_pcr */, -{ "memh ( Rz32 ++I :circ ( Mu2 ) ) = Rt32.h" , "1010 1 00 1 011 zzzzz PPuttttt 0-----1-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerf_pcr */, -{ "memh ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" , "1010 1 00 1 010 zzzzz PPuttttt 0-----1-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerh_pcr */, -{ "memw ( gp + #u16:2 ) = Nt8 .new" , "0100 1ii0 101 iiiii PPi10ttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerinewgp */, -{ "memw ( gp + #u16:2 ) = Rt32" , "0100 1ii0 100 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerigp */, -{ "memw ( #g16:2 ) = Nt8 .new" , "0100 1ii0 101 iiiii PPi10ttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerinewgp */, -{ "memw ( #g16:2 ) = Rt32" , "0100 1ii0 100 iiiii PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_ARCHV2|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_READS_GP|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerigp */, -{ "memw ( Rf32 = #U6 ) = Nt8 .new" , "1010 1 01 1 101 fffff PP010ttt 1-IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerinew_ap */, -{ "memw ( Rf32 = #U6 ) = Rt32" , "1010 1 01 1 100 fffff PP0ttttt 1-IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storeri_ap */, -{ "memw ( Rs16 + #U4:2 ) = #0 ; allocframe ( #u5:3 )" , "11110000ssssIIIIEE01110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi0_SS2_allocframe */, -{ "memw ( Rs16 + #U4:2 ) = #0 ; memd ( Sp + #s6:3 ) = Rtt8" , "11110000ssssIIIIEE00101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi0_SS2_stored_sp */, -{ "memw ( Rs16 + #U4:2 ) = #0 ; memw ( Sp + #u5:2 ) = Rt16" , "11110000ssssIIIIEE00100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi0_SS2_storew_sp */, -{ "memw ( Rs16 + #U4:2 ) = #1 ; allocframe ( #u5:3 )" , "11110001ssssIIIIEE01110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi1_SS2_allocframe */, -{ "memw ( Rs16 + #U4:2 ) = #1 ; memd ( Sp + #s6:3 ) = Rtt8" , "11110001ssssIIIIEE00101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi1_SS2_stored_sp */, -{ "memw ( Rs16 + #U4:2 ) = #1 ; memw ( Sp + #u5:2 ) = Rt16" , "11110001ssssIIIIEE00100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi1_SS2_storew_sp */, -{ "memw ( Rs16 + #U4:2 ) = Rt16 ; allocframe ( #u5:3 )" , "1010IIIIssssttttEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS2_allocframe */, -{ "memw ( Rs16 + #U4:2 ) = Rv16 ; memd ( Sp + #s6:3 ) = Rtt8" , "1010IIIIssssvvvvEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS2_stored_sp */, -{ "memw ( Rs16 + #U4:2 ) = Rv16 ; memw ( Sp + #u5:2 ) = Rt16" , "1010IIIIssssvvvvEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS2_storew_sp */, -{ "memw ( Rs32 ) &= Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_and_memopw_zomap)}, /* mapped to memw(Rs32+#0)&=Rt32 */ -{ "memw ( Rs32 ) += #U5" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_iadd_memopw_zomap)}, /* mapped to memw(Rs32+#0)+=#U5 */ -{ "memw ( Rs32 ) += Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_add_memopw_zomap)}, /* mapped to memw(Rs32+#0)+=Rt32 */ -{ "memw ( Rs32 ) -= #U5" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_isub_memopw_zomap)}, /* mapped to memw(Rs32+#0)-=#U5 */ -{ "memw ( Rs32 ) -= Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_sub_memopw_zomap)}, /* mapped to memw(Rs32+#0)-=Rt32 */ -{ "memw ( Rs32 ) = #S8" , "0000IIIIIIIIsssss000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S4_storeiri_zomap)}, /* mapped to memw(Rs32+#0)=#S8 */ -{ "memw ( Rs32 ) = Nt8 .new" , "0000tttsssss00000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_storerinew_zomap)}, /* mapped to memw(Rs32+#0)=Nt8.new */ -{ "memw ( Rs32 ) = Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(S2_storeri_zomap)}, /* mapped to memw(Rs32+#0)=Rt32 */ -{ "memw ( Rs32 ) = clrbit ( #U5 )" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_iand_memopw_zomap)}, /* mapped to memw(Rs32+#0)=clrbit(#U5) */ -{ "memw ( Rs32 ) = setbit ( #U5 )" , "0000IIIIIsssss000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_ior_memopw_zomap)}, /* mapped to memw(Rs32+#0)=setbit(#U5) */ -{ "memw ( Rs32 ) |= Rt32" , "0000sssssttttt000000000000000000" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0, HEXAGON_MAP_FNAME(L4_or_memopw_zomap)}, /* mapped to memw(Rs32+#0)|=Rt32 */ -{ "memw ( Rs32 + #s11:2 ) = Nt8 .new" , "1010 0 ii 1 101 sssss PPi10ttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storerinew_io */, -{ "memw ( Rs32 + #s11:2 ) = Rt32" , "1010 0 ii 1 100 sssss PPittttt iiiiiiii" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* S2_storeri_io */, -{ "memw ( Rs32 + #u6:2 ) &= Rt32" , "0011 111 0- 10sssss PP0iiiii i10ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_4B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_and_memopw_io */, -{ "memw ( Rs32 + #u6:2 ) += #U5" , "0011 111 1- 10sssss PP0iiiii i00IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_4B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_iadd_memopw_io */, -{ "memw ( Rs32 + #u6:2 ) += Rt32" , "0011 111 0- 10sssss PP0iiiii i00ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_4B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_add_memopw_io */, -{ "memw ( Rs32 + #u6:2 ) -= #U5" , "0011 111 1- 10sssss PP0iiiii i01IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_4B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_isub_memopw_io */, -{ "memw ( Rs32 + #u6:2 ) -= Rt32" , "0011 111 0- 10sssss PP0iiiii i01ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_4B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_sub_memopw_io */, -{ "memw ( Rs32 + #u6:2 ) = #S8" , "0011 110 -- 10 sssss PPIiiiii iIIIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_ROPS_2|A_MEMSIZE_4B|A_STORE|A_STOREIMMED|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE, NULL} /* S4_storeiri_io */, -{ "memw ( Rs32 + #u6:2 ) = clrbit ( #U5 )" , "0011 111 1- 10sssss PP0iiiii i10IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_4B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_iand_memopw_io */, -{ "memw ( Rs32 + #u6:2 ) = setbit ( #U5 )" , "0011 111 1- 10sssss PP0iiiii i11IIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_4B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_ior_memopw_io */, -{ "memw ( Rs32 + #u6:2 ) |= Rt32" , "0011 111 0- 10sssss PP0iiiii i11ttttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMOP|A_ROPS_3|A_MEMSIZE_4B|A_RESTRICT_SLOT0ONLY|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_LOAD|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* L4_or_memopw_io */, -{ "memw ( Rs32 + Ru32 << #0 ) = Nt8 .new" , "0011 1011 101 sssss PP0uuuuu 0--10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerinew_rr_expand_shamt_0 */, -{ "memw ( Rs32 + Ru32 << #0 ) = Rt32" , "0011 1011 100 sssss PP0uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storeri_rr_expand_shamt_0 */, -{ "memw ( Rs32 + Ru32 << #1 ) = Nt8 .new" , "0011 1011 101 sssss PP0uuuuu 1--10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerinew_rr_expand_shamt_1 */, -{ "memw ( Rs32 + Ru32 << #1 ) = Rt32" , "0011 1011 100 sssss PP0uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storeri_rr_expand_shamt_1 */, -{ "memw ( Rs32 + Ru32 << #2 ) = Nt8 .new" , "0011 1011 101 sssss PP1uuuuu 0--10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerinew_rr_expand_shamt_2 */, -{ "memw ( Rs32 + Ru32 << #2 ) = Rt32" , "0011 1011 100 sssss PP1uuuuu 0--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storeri_rr_expand_shamt_2 */, -{ "memw ( Rs32 + Ru32 << #3 ) = Nt8 .new" , "0011 1011 101 sssss PP1uuuuu 1--10ttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_ARCHV2|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S4_storerinew_rr_expand_shamt_3 */, -{ "memw ( Rs32 + Ru32 << #3 ) = Rt32" , "0011 1011 100 sssss PP1uuuuu 1--ttttt" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_ARCHV2|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S4_storeri_rr_expand_shamt_3 */, -{ "memw ( Ru16 + #U4:2 ) = #0 ; memb ( Rs16 + #u4:0 ) = #0" , "11110000uuuuIIIIEE010010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi0_SS2_storebi0 */, -{ "memw ( Ru16 + #U4:2 ) = #0 ; memb ( Rs16 + #u4:0 ) = #1" , "11110000uuuuIIIIEE010011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi0_SS2_storebi1 */, -{ "memw ( Ru16 + #U4:2 ) = #0 ; memh ( Rs16 + #u3:1 ) = Rt16" , "11110000uuuuIIIIEE000iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi0_SS2_storeh_io */, -{ "memw ( Ru16 + #U4:2 ) = #0 ; memw ( Rs16 + #u4:2 ) = #0" , "11110000uuuuIIIIEE010000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi0_SS2_storewi0 */, -{ "memw ( Ru16 + #U4:2 ) = #0 ; memw ( Rs16 + #u4:2 ) = #1" , "11110000uuuuIIIIEE010001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi0_SS2_storewi1 */, -{ "memw ( Ru16 + #U4:2 ) = #1 ; memb ( Rs16 + #u4:0 ) = #0" , "11110001uuuuIIIIEE010010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi1_SS2_storebi0 */, -{ "memw ( Ru16 + #U4:2 ) = #1 ; memb ( Rs16 + #u4:0 ) = #1" , "11110001uuuuIIIIEE010011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi1_SS2_storebi1 */, -{ "memw ( Ru16 + #U4:2 ) = #1 ; memh ( Rs16 + #u3:1 ) = Rt16" , "11110001uuuuIIIIEE000iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi1_SS2_storeh_io */, -{ "memw ( Ru16 + #U4:2 ) = #1 ; memw ( Rs16 + #u4:2 ) = #0" , "11110001uuuuIIIIEE010000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi1_SS2_storewi0 */, -{ "memw ( Ru16 + #U4:2 ) = #1 ; memw ( Rs16 + #u4:2 ) = #1" , "11110001uuuuIIIIEE010001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storewi1_SS2_storewi1 */, -{ "memw ( Ru16 + #U4:2 ) = Rt16 ; memb ( Rs16 + #u4:0 ) = #0" , "1010IIIIuuuuttttEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS2_storebi0 */, -{ "memw ( Ru16 + #U4:2 ) = Rt16 ; memb ( Rs16 + #u4:0 ) = #1" , "1010IIIIuuuuttttEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS2_storebi1 */, -{ "memw ( Ru16 + #U4:2 ) = Rt16 ; memw ( Rs16 + #u4:2 ) = #0" , "1010IIIIuuuuttttEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS2_storewi0 */, -{ "memw ( Ru16 + #U4:2 ) = Rt16 ; memw ( Rs16 + #u4:2 ) = #1" , "1010IIIIuuuuttttEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS2_storewi1 */, -{ "memw ( Ru16 + #U4:2 ) = Rv16 ; memb ( Rs16 + #u4:0 ) = Rt16" , "1010IIIIuuuuvvvvEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS1_storeb_io */, -{ "memw ( Ru16 + #U4:2 ) = Rv16 ; memh ( Rs16 + #u3:1 ) = Rt16" , "1010IIIIuuuuvvvvEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS2_storeh_io */, -{ "memw ( Ru16 + #U4:2 ) = Rv16 ; memw ( Rs16 + #u4:2 ) = Rt16" , "1010IIIIuuuuvvvvEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS1_storew_io_SS1_storew_io */, -{ "memw ( Ru32 << #0 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP010ttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerinew_ur_expand_shamt_0 */, -{ "memw ( Ru32 << #0 + #U6 ) = Rt32" , "1010 1 10 1 100 uuuuu PP0ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storeri_ur_expand_shamt_0 */, -{ "memw ( Ru32 << #1 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP010ttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerinew_ur_expand_shamt_1 */, -{ "memw ( Ru32 << #1 + #U6 ) = Rt32" , "1010 1 10 1 100 uuuuu PP0ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storeri_ur_expand_shamt_1 */, -{ "memw ( Ru32 << #2 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP110ttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerinew_ur_expand_shamt_2 */, -{ "memw ( Ru32 << #2 + #U6 ) = Rt32" , "1010 1 10 1 100 uuuuu PP1ttttt 10IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storeri_ur_expand_shamt_2 */, -{ "memw ( Ru32 << #3 + #U6 ) = Nt8 .new" , "1010 1 10 1 101 uuuuu PP110ttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storerinew_ur_expand_shamt_3 */, -{ "memw ( Ru32 << #3 + #U6 ) = Rt32" , "1010 1 10 1 100 uuuuu PP1ttttt 11IIIIII" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_EXT_UPPER_IMMED|A_EXTENDABLE|A_MUST_EXTEND|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|EXTENDABLE_UPPER_CASE_IMMEDIATE|MUST_EXTEND, NULL} /* S4_storeri_ur_expand_shamt_3 */, -{ "memw ( Rz32 ++ #s4:2 ) = Nt8 .new" , "1010 1 01 1 101 zzzzz PP010ttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S2_storerinew_pi */, -{ "memw ( Rz32 ++ #s4:2 ) = Rt32" , "1010 1 01 1 100 zzzzz PP0ttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storeri_pi */, -{ "memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) ) = Nt8 .new" , "1010 1 00 1 101 zzzzz PPu10ttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerinew_pci */, -{ "memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) ) = Rt32" , "1010 1 00 1 100 zzzzz PPuttttt 0iiii-0-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storeri_pci */, -{ "memw ( Rz32 ++ Mu2 ) = Nt8 .new" , "1010 1 10 1 101 zzzzz PPu10ttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S2_storerinew_pr */, -{ "memw ( Rz32 ++ Mu2 ) = Rt32" , "1010 1 10 1 100 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storeri_pr */, -{ "memw ( Rz32 ++ Mu2 :brev ) = Nt8 .new" , "1010 1 11 1 101 zzzzz PPu10ttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC, NULL} /* S2_storerinew_pbr */, -{ "memw ( Rz32 ++ Mu2 :brev ) = Rt32" , "1010 1 11 1 100 zzzzz PPuttttt 0-------" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_BREVADDR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storeri_pbr */, -{ "memw ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" , "1010 1 00 1 101 zzzzz PPu10ttt 0-----1-" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NEWVAL_SLOT0|A_NVSTORE|A_NOTE_NVSLOT0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_NOSLOT1_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_DOTNEWVALUE|A_RESTRICT_SLOT0ONLY|A_CONDEXEC|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storerinew_pcr */, -{ "memw ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" , "1010 1 00 1 100 zzzzz PPuttttt 0-----1-" , HEXAGON_MACH, NULL, NULL, 0x3, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_CIRCADDR|A_IMPLICIT_READS_CS, NULL} /* S2_storeri_pcr */, -{ "memw ( Sp + #U5:2 ) = Rt16 ; allocframe ( #u5:3 )" , "1110100IIIIIttttEE01110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_SP|IMPLICIT_FP, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SS2_storew_sp_SS2_allocframe */, -{ "memw ( Sp + #U5:2 ) = Rt16 ; memb ( Rs16 + #u4:0 ) = #0" , "1110100IIIIIttttEE010010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storew_sp_SS2_storebi0 */, -{ "memw ( Sp + #U5:2 ) = Rt16 ; memb ( Rs16 + #u4:0 ) = #1" , "1110100IIIIIttttEE010011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storew_sp_SS2_storebi1 */, -{ "memw ( Sp + #U5:2 ) = Rt16 ; memw ( Rs16 + #u4:2 ) = #0" , "1110100IIIIIttttEE010000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storew_sp_SS2_storewi0 */, -{ "memw ( Sp + #U5:2 ) = Rt16 ; memw ( Rs16 + #u4:2 ) = #1" , "1110100IIIIIttttEE010001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storew_sp_SS2_storewi1 */, -{ "memw ( Sp + #U5:2 ) = Rv16 ; memd ( Sp + #s6:3 ) = Rtt8" , "1110100IIIIIvvvvEE00101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storew_sp_SS2_stored_sp */, -{ "memw ( Sp + #U5:2 ) = Rv16 ; memh ( Rs16 + #u3:1 ) = Rt16" , "1110100IIIIIvvvvEE000iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storew_sp_SS2_storeh_io */, -{ "memw ( Sp + #U5:2 ) = Rv16 ; memw ( Sp + #u5:2 ) = Rt16" , "1110100IIIIIvvvvEE00100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SS2_storew_sp_SS2_storew_sp */, -{ "memw_locked ( Rs32 , Pd4 ) = Rt32" , "1010 000 01 01sssss PP-ttttt ------dd" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_MEMSIZE_4B|A_STORE|A_RESTRICT_SLOT0ONLY|A_RESTRICT_PACKET_AXOK|A_NOTE_AXOK|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST, NULL} /* S2_storew_locked */, -{ "nmi ( Rs32 )" , "0110 0100 011sssss PP------ 010-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y4_nmi */, -{ "nop" , "0111 1111 -------- PP------ --------" , HEXAGON_MACH, NULL, NULL, 0xf, 0, 0|A_IT_NOP, NULL} /* A2_nop */, -{ "p0 = cmp.eq ( Rs16 , #-1 ) ; if ( ! p0 .new ) jump:nt #r9:2" , "0001 -0 0 11 1iissss PP0---00 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_fp0_jump_nt */, -{ "p0 = cmp.eq ( Rs16 , #-1 ) ; if ( ! p0 .new ) jump:t #r9:2" , "0001 -0 0 11 1iissss PP1---00 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_fp0_jump_t */, -{ "p0 = cmp.eq ( Rs16 , #-1 ) ; if ( p0 .new ) jump:nt #r9:2" , "0001 -0 0 11 0iissss PP0---00 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_tp0_jump_nt */, -{ "p0 = cmp.eq ( Rs16 , #-1 ) ; if ( p0 .new ) jump:t #r9:2" , "0001 -0 0 11 0iissss PP1---00 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_tp0_jump_t */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; Rd16 = #-1" , "00111001ssss--IIEE11101--0--dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_setin1 */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; Rd16 = memw ( Sp + #u5:2 )" , "01011001ssss--IIEE11110iiiiidddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_loadri_sp */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; Rdd8 = combine ( #0 , #u2 )" , "00111001ssss--IIEE1111-0-ii00ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_combine0i */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; Rdd8 = combine ( #1 , #u2 )" , "00111001ssss--IIEE1111-0-ii01ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_combine1i */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; Rdd8 = combine ( #2 , #u2 )" , "00111001ssss--IIEE1111-0-ii10ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_combine2i */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; Rdd8 = combine ( #3 , #u2 )" , "00111001ssss--IIEE1111-0-ii11ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_combine3i */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; Rdd8 = memd ( Sp + #u5:3 )" , "01011001ssss--IIEE111110iiiiiddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_8B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_loadrd_sp */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; allocframe ( #u5:3 )" , "01111001ssss--IIEE11110iiiii----" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_8B|A_STORE|A_RESTRICT_SLOT0ONLY|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_READS_SP|A_IMPLICIT_READS_LR|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS2_allocframe */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; if ( ! p0 ) Rd16 = #0" , "00111001ssss--IIEE11101--111dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_clrf */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; if ( ! p0 .new ) Rd16 = #0" , "00111001ssss--IIEE11101--101dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_clrfnew */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; if ( p0 ) Rd16 = #0" , "00111001ssss--IIEE11101--110dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_IMPLICIT_READS_P0|A_DOTOLD|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_clrt */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; if ( p0 .new ) Rd16 = #0" , "00111001ssss--IIEE11101--100dddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_DOTNEW|A_IMPLICIT_READS_P0|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_clrtnew */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; memd ( Sp + #s6:3 ) = Rtt8" , "01111001ssss--IIEE10101iiiiiittt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_8B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS2_stored_sp */, -{ "p0 = cmp.eq ( Rs16 , #U2 ) ; memw ( Sp + #u5:2 ) = Rt16" , "01111001ssss--IIEE10100iiiiitttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS2_storew_sp */, -{ "p0 = cmp.eq ( Rs16 , #U5 ) ; if ( ! p0 .new ) jump:nt #r9:2" , "0001 -0 0 00 1iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_fp0_jump_nt */, -{ "p0 = cmp.eq ( Rs16 , #U5 ) ; if ( ! p0 .new ) jump:t #r9:2" , "0001 -0 0 00 1iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_fp0_jump_t */, -{ "p0 = cmp.eq ( Rs16 , #U5 ) ; if ( p0 .new ) jump:nt #r9:2" , "0001 -0 0 00 0iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_tp0_jump_nt */, -{ "p0 = cmp.eq ( Rs16 , #U5 ) ; if ( p0 .new ) jump:t #r9:2" , "0001 -0 0 00 0iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_tp0_jump_t */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; dealloc_return" , "01011001ssss--iiEE11111101---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_return */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; deallocframe" , "01011001ssss--iiEE11111100---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_8B|A_LOAD|A_IMPLICIT_WRITES_LR|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_deallocframe */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; if ( ! p0 ) dealloc_return" , "01011001ssss--iiEE11111101---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_return_f */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; if ( ! p0 ) jumpr Lr" , "01011001ssss--iiEE11111111---101" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_PC, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_jumpr31_f */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; if ( ! p0 .new ) dealloc_return:nt" , "01011001ssss--iiEE11111101---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_return_fnew */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; if ( ! p0 .new ) jumpr:nt Lr" , "01011001ssss--iiEE11111111---111" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_PC, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_jumpr31_fnew */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; if ( p0 ) dealloc_return" , "01011001ssss--iiEE11111101---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_LR|IMPLICIT_SP|IMPLICIT_FP|IMPLICIT_PC, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_WRITES_LR|A_IMPLICIT_READS_P0|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_return_t */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; if ( p0 ) jumpr Lr" , "01011001ssss--iiEE11111111---100" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_PC, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTOLD|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_jumpr31_t */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; if ( p0 .new ) dealloc_return:nt" , "01011001ssss--iiEE11111101---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_LR|IMPLICIT_PC|IMPLICIT_SP|IMPLICIT_FP, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_ROPS_2|A_MEMSIZE_8B|A_LOAD|A_RESTRICT_COF_MAX1|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOSLOT1_STORE|A_RET_TYPE|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_LR|A_IMPLICIT_WRITES_PC|A_COF|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|A_IMPLICIT_WRITES_SP|A_IMPLICIT_WRITES_FP|A_IMPLICIT_READS_FP|A_CONDEXEC|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_return_tnew */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; if ( p0 .new ) jumpr:nt Lr" , "01011001ssss--iiEE11111111---110" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_PC, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_CJUMP|A_DOTNEW|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_PRED_BIT_4|A_IMPLICIT_READS_P0|A_IMPLICIT_WRITES_PC|A_COF|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_jumpr31_tnew */, -{ "p0 = cmp.eq ( Rs16 , #u2 ) ; jumpr Lr" , "01011001ssss--iiEE11111111---0--" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_PC, 0|A_IMPLICIT_WRITES_P0|A_JUMP|A_INDIRECT|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_NOTE_CONDITIONAL|A_RESTRICT_SLOT0ONLY|A_RET_TYPE|A_IMPLICIT_WRITES_PC|A_COF|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_jumpr31 */, -{ "p0 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! p0 .new ) jump:nt #r9:2" , "0001 -1 0 00 1iissss PP00tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_fp0_jump_nt */, -{ "p0 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! p0 .new ) jump:t #r9:2" , "0001 -1 0 00 1iissss PP10tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_fp0_jump_t */, -{ "p0 = cmp.eq ( Rs16 , Rt16 ) ; if ( p0 .new ) jump:nt #r9:2" , "0001 -1 0 00 0iissss PP00tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_tp0_jump_nt */, -{ "p0 = cmp.eq ( Rs16 , Rt16 ) ; if ( p0 .new ) jump:t #r9:2" , "0001 -1 0 00 0iissss PP10tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_tp0_jump_t */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; Rd16 = memb ( Rs16 + #u3:0 )" , "01011001uuuu--IIEE110iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_loadrb_io */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; Rd16 = memh ( Rs16 + #u3:1 )" , "01011001uuuu--IIEE100iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_loadrh_io */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; Rd16 = memub ( Rs16 + #u4:0 )" , "01011001uuuu--IIEE01iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_1B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL1_loadrub_io */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; Rd16 = memuh ( Rs16 + #u3:1 )" , "01011001uuuu--IIEE101iiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_2B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL2_loadruh_io */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; Rd16 = memw ( Rs16 + #u4:2 )" , "01011001uuuu--IIEE00iiiissssdddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_4B|A_LOAD|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SL1_loadri_io */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; Rdd8 = combine ( #0 , Rs16 )" , "00111001uuuu--IIEE1111-1ssss0ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_combinezr */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; Rdd8 = combine ( Rs16 , #0 )" , "00111001uuuu--IIEE1111-1ssss1ddd" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_ROPS_2|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_combinerz */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #0" , "01111001uuuu--IIEE110010ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS2_storebi0 */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; memb ( Rs16 + #u4:0 ) = #1" , "01111001uuuu--IIEE110011ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_1B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS2_storebi1 */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; memb ( Rs16 + #u4:0 ) = Rt16" , "01111001uuuu--IIEE01iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_1B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS1_storeb_io */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; memh ( Rs16 + #u3:1 ) = Rt16" , "01111001uuuu--IIEE100iiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_2B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS2_storeh_io */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #0" , "01111001uuuu--IIEE110000ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS2_storewi0 */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; memw ( Rs16 + #u4:2 ) = #1" , "01111001uuuu--IIEE110001ssssiiii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_4B|A_STORE|A_ROPS_2|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS2_storewi1 */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; memw ( Rs16 + #u4:2 ) = Rt16" , "01111001uuuu--IIEE00iiiisssstttt" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_MEMSIZE_4B|A_STORE|A_MEMLIKE|A_RESTRICT_SINGLE_MEM_FIRST|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SS1_storew_io */, -{ "p0 = cmp.eq ( Ru16 , #U2 ) ; p0 = cmp.eq ( Rs16 , #u2 )" , "00111001uuuu--IIEE111001ssss--ii" , HEXAGON_MACH, NULL, NULL, 0x1, 0|IMPLICIT_P0|IMPLICIT_P0, 0|A_IMPLICIT_WRITES_P0|A_IMPLICIT_WRITES_P0|PACKED, NULL} /* X2_AUTOJOIN_SA1_cmpeqi_SA1_cmpeqi */, -{ "p0 = cmp.gt ( Rs16 , #-1 ) ; if ( ! p0 .new ) jump:nt #r9:2" , "0001 -0 0 11 1iissss PP0---01 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_fp0_jump_nt */, -{ "p0 = cmp.gt ( Rs16 , #-1 ) ; if ( ! p0 .new ) jump:t #r9:2" , "0001 -0 0 11 1iissss PP1---01 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_fp0_jump_t */, -{ "p0 = cmp.gt ( Rs16 , #-1 ) ; if ( p0 .new ) jump:nt #r9:2" , "0001 -0 0 11 0iissss PP0---01 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_tp0_jump_nt */, -{ "p0 = cmp.gt ( Rs16 , #-1 ) ; if ( p0 .new ) jump:t #r9:2" , "0001 -0 0 11 0iissss PP1---01 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_tp0_jump_t */, -{ "p0 = cmp.gt ( Rs16 , #U5 ) ; if ( ! p0 .new ) jump:nt #r9:2" , "0001 -0 0 01 1iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_fp0_jump_nt */, -{ "p0 = cmp.gt ( Rs16 , #U5 ) ; if ( ! p0 .new ) jump:t #r9:2" , "0001 -0 0 01 1iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_fp0_jump_t */, -{ "p0 = cmp.gt ( Rs16 , #U5 ) ; if ( p0 .new ) jump:nt #r9:2" , "0001 -0 0 01 0iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_tp0_jump_nt */, -{ "p0 = cmp.gt ( Rs16 , #U5 ) ; if ( p0 .new ) jump:t #r9:2" , "0001 -0 0 01 0iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_tp0_jump_t */, -{ "p0 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! p0 .new ) jump:nt #r9:2" , "0001 -1 0 01 1iissss PP00tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_fp0_jump_nt */, -{ "p0 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! p0 .new ) jump:t #r9:2" , "0001 -1 0 01 1iissss PP10tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_fp0_jump_t */, -{ "p0 = cmp.gt ( Rs16 , Rt16 ) ; if ( p0 .new ) jump:nt #r9:2" , "0001 -1 0 01 0iissss PP00tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_tp0_jump_nt */, -{ "p0 = cmp.gt ( Rs16 , Rt16 ) ; if ( p0 .new ) jump:t #r9:2" , "0001 -1 0 01 0iissss PP10tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_tp0_jump_t */, -{ "p0 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! p0 .new ) jump:nt #r9:2" , "0001 -0 0 10 1iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_fp0_jump_nt */, -{ "p0 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! p0 .new ) jump:t #r9:2" , "0001 -0 0 10 1iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_fp0_jump_t */, -{ "p0 = cmp.gtu ( Rs16 , #U5 ) ; if ( p0 .new ) jump:nt #r9:2" , "0001 -0 0 10 0iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_tp0_jump_nt */, -{ "p0 = cmp.gtu ( Rs16 , #U5 ) ; if ( p0 .new ) jump:t #r9:2" , "0001 -0 0 10 0iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_tp0_jump_t */, -{ "p0 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! p0 .new ) jump:nt #r9:2" , "0001 -1 0 10 1iissss PP00tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_fp0_jump_nt */, -{ "p0 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! p0 .new ) jump:t #r9:2" , "0001 -1 0 10 1iissss PP10tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_fp0_jump_t */, -{ "p0 = cmp.gtu ( Rs16 , Rt16 ) ; if ( p0 .new ) jump:nt #r9:2" , "0001 -1 0 10 0iissss PP00tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_tp0_jump_nt */, -{ "p0 = cmp.gtu ( Rs16 , Rt16 ) ; if ( p0 .new ) jump:t #r9:2" , "0001 -1 0 10 0iissss PP10tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_tp0_jump_t */, -{ "p0 = tstbit ( Rs16 , #0 ) ; if ( ! p0 .new ) jump:nt #r9:2" , "0001 -0 0 11 1iissss PP0---11 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_fp0_jump_nt */, -{ "p0 = tstbit ( Rs16 , #0 ) ; if ( ! p0 .new ) jump:t #r9:2" , "0001 -0 0 11 1iissss PP1---11 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_fp0_jump_t */, -{ "p0 = tstbit ( Rs16 , #0 ) ; if ( p0 .new ) jump:nt #r9:2" , "0001 -0 0 11 0iissss PP0---11 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_tp0_jump_nt */, -{ "p0 = tstbit ( Rs16 , #0 ) ; if ( p0 .new ) jump:t #r9:2" , "0001 -0 0 11 0iissss PP1---11 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P0, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_EXT_LOWER_IMMED|A_IMPLICIT_READS_P0|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P0|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_tp0_jump_t */, -{ "p1 = cmp.eq ( Rs16 , #-1 ) ; if ( ! p1 .new ) jump:nt #r9:2" , "0001 -0 1 11 1iissss PP0---00 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_fp1_jump_nt */, -{ "p1 = cmp.eq ( Rs16 , #-1 ) ; if ( ! p1 .new ) jump:t #r9:2" , "0001 -0 1 11 1iissss PP1---00 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_fp1_jump_t */, -{ "p1 = cmp.eq ( Rs16 , #-1 ) ; if ( p1 .new ) jump:nt #r9:2" , "0001 -0 1 11 0iissss PP0---00 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_tp1_jump_nt */, -{ "p1 = cmp.eq ( Rs16 , #-1 ) ; if ( p1 .new ) jump:t #r9:2" , "0001 -0 1 11 0iissss PP1---00 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqn1_tp1_jump_t */, -{ "p1 = cmp.eq ( Rs16 , #U5 ) ; if ( ! p1 .new ) jump:nt #r9:2" , "0001 -0 1 00 1iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_fp1_jump_nt */, -{ "p1 = cmp.eq ( Rs16 , #U5 ) ; if ( ! p1 .new ) jump:t #r9:2" , "0001 -0 1 00 1iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_fp1_jump_t */, -{ "p1 = cmp.eq ( Rs16 , #U5 ) ; if ( p1 .new ) jump:nt #r9:2" , "0001 -0 1 00 0iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_tp1_jump_nt */, -{ "p1 = cmp.eq ( Rs16 , #U5 ) ; if ( p1 .new ) jump:t #r9:2" , "0001 -0 1 00 0iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeqi_tp1_jump_t */, -{ "p1 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! p1 .new ) jump:nt #r9:2" , "0001 -1 0 00 1iissss PP01tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_fp1_jump_nt */, -{ "p1 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! p1 .new ) jump:t #r9:2" , "0001 -1 0 00 1iissss PP11tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_fp1_jump_t */, -{ "p1 = cmp.eq ( Rs16 , Rt16 ) ; if ( p1 .new ) jump:nt #r9:2" , "0001 -1 0 00 0iissss PP01tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_tp1_jump_nt */, -{ "p1 = cmp.eq ( Rs16 , Rt16 ) ; if ( p1 .new ) jump:t #r9:2" , "0001 -1 0 00 0iissss PP11tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpeq_tp1_jump_t */, -{ "p1 = cmp.gt ( Rs16 , #-1 ) ; if ( ! p1 .new ) jump:nt #r9:2" , "0001 -0 1 11 1iissss PP0---01 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_fp1_jump_nt */, -{ "p1 = cmp.gt ( Rs16 , #-1 ) ; if ( ! p1 .new ) jump:t #r9:2" , "0001 -0 1 11 1iissss PP1---01 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_fp1_jump_t */, -{ "p1 = cmp.gt ( Rs16 , #-1 ) ; if ( p1 .new ) jump:nt #r9:2" , "0001 -0 1 11 0iissss PP0---01 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_tp1_jump_nt */, -{ "p1 = cmp.gt ( Rs16 , #-1 ) ; if ( p1 .new ) jump:t #r9:2" , "0001 -0 1 11 0iissss PP1---01 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtn1_tp1_jump_t */, -{ "p1 = cmp.gt ( Rs16 , #U5 ) ; if ( ! p1 .new ) jump:nt #r9:2" , "0001 -0 1 01 1iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_fp1_jump_nt */, -{ "p1 = cmp.gt ( Rs16 , #U5 ) ; if ( ! p1 .new ) jump:t #r9:2" , "0001 -0 1 01 1iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_fp1_jump_t */, -{ "p1 = cmp.gt ( Rs16 , #U5 ) ; if ( p1 .new ) jump:nt #r9:2" , "0001 -0 1 01 0iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_tp1_jump_nt */, -{ "p1 = cmp.gt ( Rs16 , #U5 ) ; if ( p1 .new ) jump:t #r9:2" , "0001 -0 1 01 0iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgti_tp1_jump_t */, -{ "p1 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! p1 .new ) jump:nt #r9:2" , "0001 -1 0 01 1iissss PP01tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_fp1_jump_nt */, -{ "p1 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! p1 .new ) jump:t #r9:2" , "0001 -1 0 01 1iissss PP11tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_fp1_jump_t */, -{ "p1 = cmp.gt ( Rs16 , Rt16 ) ; if ( p1 .new ) jump:nt #r9:2" , "0001 -1 0 01 0iissss PP01tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_tp1_jump_nt */, -{ "p1 = cmp.gt ( Rs16 , Rt16 ) ; if ( p1 .new ) jump:t #r9:2" , "0001 -1 0 01 0iissss PP11tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgt_tp1_jump_t */, -{ "p1 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! p1 .new ) jump:nt #r9:2" , "0001 -0 1 10 1iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_fp1_jump_nt */, -{ "p1 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! p1 .new ) jump:t #r9:2" , "0001 -0 1 10 1iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_fp1_jump_t */, -{ "p1 = cmp.gtu ( Rs16 , #U5 ) ; if ( p1 .new ) jump:nt #r9:2" , "0001 -0 1 10 0iissss PP0IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_tp1_jump_nt */, -{ "p1 = cmp.gtu ( Rs16 , #U5 ) ; if ( p1 .new ) jump:t #r9:2" , "0001 -0 1 10 0iissss PP1IIIII iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtui_tp1_jump_t */, -{ "p1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! p1 .new ) jump:nt #r9:2" , "0001 -1 0 10 1iissss PP01tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_fp1_jump_nt */, -{ "p1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! p1 .new ) jump:t #r9:2" , "0001 -1 0 10 1iissss PP11tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_fp1_jump_t */, -{ "p1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( p1 .new ) jump:nt #r9:2" , "0001 -1 0 10 0iissss PP01tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_tp1_jump_nt */, -{ "p1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( p1 .new ) jump:t #r9:2" , "0001 -1 0 10 0iissss PP11tttt iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_cmpgtu_tp1_jump_t */, -{ "p1 = tstbit ( Rs16 , #0 ) ; if ( ! p1 .new ) jump:nt #r9:2" , "0001 -0 1 11 1iissss PP0---11 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_fp1_jump_nt */, -{ "p1 = tstbit ( Rs16 , #0 ) ; if ( ! p1 .new ) jump:t #r9:2" , "0001 -0 1 11 1iissss PP1---11 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_SENSE_INVERTED |CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_fp1_jump_t */, -{ "p1 = tstbit ( Rs16 , #0 ) ; if ( p1 .new ) jump:nt #r9:2" , "0001 -0 1 11 0iissss PP0---11 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_tp1_jump_nt */, -{ "p1 = tstbit ( Rs16 , #0 ) ; if ( p1 .new ) jump:t #r9:2" , "0001 -0 1 11 0iissss PP1---11 iiiiiii-" , HEXAGON_MACH, NULL, NULL, 0xc, 0|IMPLICIT_PC|IMPLICIT_P1, 0|A_JUMP|A_DIRECT|A_CJUMP|A_RESTRICT_LOOP_LA|A_RESTRICT_COF_MAX1|A_BRANCHADDER|A_DOTNEW|A_ROPS_2|A_RESTRICT_COF_MAX1|A_RELAX_COF_2ND|A_RELAX_COF_1ST|A_NEWCMPJUMP|A_PRED_BIT_13|A_IMPLICIT_READS_P1|A_EXT_LOWER_IMMED|A_EXTENDABLE|A_IMPLICIT_READS_PC|A_IMPLICIT_WRITES_PC|A_COF|A_IMPLICIT_WRITES_P1|CONDITIONAL_EXEC|CONDITION_DOTNEW|PACKED|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J4_tstbit0_tp1_jump_t */, -{ "p3 = sp1loop0 ( #r7:2 , #U10 )" , "0110 1001 101IIIII PP-iiiii IIIii-II" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC0|IMPLICIT_SA0|IMPLICIT_SR_OVF|IMPLICIT_P3, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_ARCHV2|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_HWLOOP0_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC0|A_IMPLICIT_WRITES_SA0|A_IMPLICIT_WRITES_SRBIT|A_RESTRICT_NOSRMOVE|A_EXTENDABLE|A_IMPLICIT_WRITES_P3|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_ploop1si */, -{ "p3 = sp1loop0 ( #r7:2 , Rs32 )" , "0110 0000 101sssss PP-iiiii ---ii---" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC0|IMPLICIT_SA0|IMPLICIT_SR_OVF|IMPLICIT_P3, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_ARCHV2|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_HWLOOP0_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC0|A_IMPLICIT_WRITES_SA0|A_IMPLICIT_WRITES_SRBIT|A_RESTRICT_NOSRMOVE|A_EXTENDABLE|A_IMPLICIT_WRITES_P3|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_ploop1sr */, -{ "p3 = sp2loop0 ( #r7:2 , #U10 )" , "0110 1001 110IIIII PP-iiiii IIIii-II" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC0|IMPLICIT_SA0|IMPLICIT_SR_OVF|IMPLICIT_P3, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_ARCHV2|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_HWLOOP0_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC0|A_IMPLICIT_WRITES_SA0|A_IMPLICIT_WRITES_SRBIT|A_RESTRICT_NOSRMOVE|A_EXTENDABLE|A_IMPLICIT_WRITES_P3|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_ploop2si */, -{ "p3 = sp2loop0 ( #r7:2 , Rs32 )" , "0110 0000 110sssss PP-iiiii ---ii---" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC0|IMPLICIT_SA0|IMPLICIT_SR_OVF|IMPLICIT_P3, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_ARCHV2|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_HWLOOP0_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC0|A_IMPLICIT_WRITES_SA0|A_IMPLICIT_WRITES_SRBIT|A_RESTRICT_NOSRMOVE|A_EXTENDABLE|A_IMPLICIT_WRITES_P3|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_ploop2sr */, -{ "p3 = sp3loop0 ( #r7:2 , #U10 )" , "0110 1001 111IIIII PP-iiiii IIIii-II" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC0|IMPLICIT_SA0|IMPLICIT_SR_OVF|IMPLICIT_P3, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_ARCHV2|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_HWLOOP0_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC0|A_IMPLICIT_WRITES_SA0|A_IMPLICIT_WRITES_SRBIT|A_RESTRICT_NOSRMOVE|A_EXTENDABLE|A_IMPLICIT_WRITES_P3|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_ploop3si */, -{ "p3 = sp3loop0 ( #r7:2 , Rs32 )" , "0110 0000 111sssss PP-iiiii ---ii---" , HEXAGON_MACH, NULL, NULL, 0x8, 0|IMPLICIT_LC0|IMPLICIT_SA0|IMPLICIT_SR_OVF|IMPLICIT_P3, 0|A_NOTE_PACKET_NPC|A_NOTE_RELATIVE_ADDRESS|A_NOTE_PACKET_PC|A_NOTE_LA_RESTRICT|A_RESTRICT_LOOP_LA|A_BRANCHADDER|A_IT_HWLOOP|A_RELAX_COF_1ST|A_RELAX_COF_2ND|A_ARCHV2|A_RESTRICT_LATEPRED|A_NOTE_LATEPRED|A_HWLOOP0_SETUP|A_EXT_LOWER_IMMED|A_IMPLICIT_WRITES_LC0|A_IMPLICIT_WRITES_SA0|A_IMPLICIT_WRITES_SRBIT|A_RESTRICT_NOSRMOVE|A_EXTENDABLE|A_IMPLICIT_WRITES_P3|A_IMPLICIT_READS_PC|EXTENDABLE_LOWER_CASE_IMMEDIATE, NULL} /* J2_ploop3sr */, -{ "pause ( #u8 )" , "0101 0100 01------ PP-iiiii ---iii--" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_COF|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* J2_pause */, -{ "resume ( Rs32 )" , "0110 0100 010sssss PP------ 001-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_resume */, -{ "rteunlock" , "0101 0111 111----- PP01---- 000-----" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_PRIV|A_NOTE_PRIV|A_IMPLICIT_WRITES_PC|A_COF, NULL} /* J2_rteunlock */, -{ "rte" , "0101 0111 111----- PP00---- 000-----" , HEXAGON_MACH, NULL, NULL, 0x4, 0|IMPLICIT_PC, 0|A_PRIV|A_NOTE_PRIV|A_IMPLICIT_WRITES_PC|A_COF, NULL} /* J2_rte */, -{ "setimask ( Pt4 , Rs32 )" , "0110 0100 100sssss PP----tt 000-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK, NULL} /* Y2_setimask */, -{ "siad ( Rs32 )" , "0110 0100 100sssss PP------ 011-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK|A_EXCEPTION_SWI, NULL} /* Y4_siad */, -{ "start ( Rs32 )" , "0110 0100 011sssss PP------ 001-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_start */, -{ "stop ( Rs32 )" , "0110 0100 011sssss PP------ 000-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_stop */, -{ "swi ( Rs32 )" , "0110 0100 000sssss PP------ 000-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK|A_EXCEPTION_SWI, NULL} /* Y2_swi */, -{ "syncht" , "1010 100 00 10----- PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x1, 0, 0|A_NOTE_NOPACKET|A_RESTRICT_SLOT0ONLY|A_RESTRICT_NOPACKET, NULL} /* Y2_syncht */, -{ "tlbinvasid ( Rs32 )" , "0110 1100 101sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y5_tlbasidi */, -{ "tlblock" , "0110 1100 001----- PP------ 001-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_tlblock */, -{ "tlbunlock" , "0110 1100 001----- PP------ 010-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_tlbunlock */, -{ "tlbw ( Rss32 , Rt32 )" , "0110 1100 000sssss PP0ttttt --------" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_tlbw */, -{ "trace ( Rs32 )" , "0110 0010 010sssss PP------ --------" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_NOTE_AXOK|A_RESTRICT_PACKET_AXOK, NULL} /* Y4_trace */, -{ "trap0 ( #u8 )" , "0101 0100 00------ PP-iiiii ---iii--" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_COF|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_EXCEPTION_SWI, NULL} /* J2_trap0 */, -{ "trap1 ( #u8 )" , "0101 0100 10------ PP-iiiii ---iii--" , HEXAGON_MACH, NULL, NULL, 0x4, 0, 0|A_COF|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET|A_EXCEPTION_SWI, NULL} /* J2_trap1 */, -{ "wait ( Rs32 )" , "0110 0100 010sssss PP------ 000-----" , HEXAGON_MACH, NULL, NULL, 0x8, 0, 0|A_PRIV|A_NOTE_PRIV|A_NOTE_NOPACKET|A_RESTRICT_NOPACKET, NULL} /* Y2_wait */, diff --git a/importer.py b/importer.py deleted file mode 100755 index 92988b8b..00000000 --- a/importer.py +++ /dev/null @@ -1,2000 +0,0 @@ -#!/usr/bin/env python3 -# pylint: disable=missing-docstring, invalid-name, line-too-long, too-many-lines, fixme -# pylint: disable=too-few-public-methods - -from __future__ import (absolute_import, division, - print_function, unicode_literals) - -import argparse -import re -import operator -import collections -import sys - -class UnexpectedException(Exception): - def __init__(self, message): - super().__init__(message) - -def standarize_syntax_objdump(syntax): - """Change instruction syntax to match Qualcomm's objdump output. - - Args: - syntax (str): instruction syntax, probably as was obtained from the parsed manual. - - Returns: - str: matching objdump syntax (as close as possible). - - TODO: - * Care should be taken not to modify the syntax patterns used in the decoder - to recognize different attributes of the instruction, e.g., ``Rd`` can - be splitted with a space like ``R d``. - - * Document the most complex regex. - - """ - - # Add spaces to certain chars like '=' and '()' - - both_spaces = ['=', '+', '-', '*', '/', '&', '|', '<<', '^'] - left_space = ['(', '!'] - rigth_space = [')', ','] - for c in both_spaces: - syntax = syntax.replace(c, ' ' + c + ' ') - for c in left_space: - syntax = syntax.replace(c, ' ' + c) - for c in rigth_space: - syntax = syntax.replace(c, c + ' ') - - syntax = re.sub(r'\s{2,}', ' ', syntax) - - # TODO: Special hack for the unary minus. - syntax = re.sub(r'\#\s-\s', '#-', syntax) - - syntax = re.sub(r'\(\s*', '(', syntax) - syntax = re.sub(r'\s*\)', ')', syntax) - - # Compound assingment - syntax = re.sub(r'([\+\-\*\/\&\|\^\!]) =', r'\1=', syntax) - - syntax = syntax.replace(' ,', ',') - syntax = syntax.replace(' .', '.') - - # Remove parenthesis from (!p0.new). just to match objdump, - # but I prefer it with parenthesis. - if ';' not in syntax: - m = re.search(r'\( (\s* ! \s* [pP]\w(.new)? \s*) \)', syntax, re.X) - - if m: - syntax = syntax.replace('(' + m.group(1) + ')', m.group(1)) - # syntax = re.sub(r'\( (\s* ! \s* [pP]\w(.new)? \s*) \)', r'\1', syntax, re.X) - # TODO: The re.sub is not working, don't know why.. - - - syntax = syntax.replace('dfcmp', 'cmp') - syntax = syntax.replace('sfcmp', 'cmp') - - # Special cases: ++, ==, != - syntax = syntax.replace('+ +', '++') - syntax = syntax.replace('= =', '==') - syntax = syntax.replace('! =', '!=') - - # Special cases: <>1 - syntax = syntax.replace(': << N', ':<> 1', ':>>1') - - syntax = syntax.strip() - - return syntax - - -class OperandTemplate(): - # TODO: Document class. - - __slots__ = ['syntax_name'] - # TODO: Change `syntax_name` to ``syntax``. - - def __init__(self, syntax_name): - self.syntax_name = syntax_name - - -class RegisterTemplate(OperandTemplate): - # TODO: Document class. - - __slots__ = ['is_register_pair', 'is_predicate', 'is_control', 'is_system', 'is_newvalue', 'syntax', 'index'] - - def __init__(self, syntax_name): - super(RegisterTemplate, self).__init__(syntax_name) - self.syntax = syntax_name - self.is_register_pair = False - self.is_control = False - self.is_system = False - self.is_predicate = False - self.is_newvalue = False - self.index = 0 - - # Register pair analysis. - - if self.syntax_name[0] == 'R': - # General register. - - if len(self.syntax_name[1:]) == 2: - self.is_register_pair = True - - if self.syntax_name[1] != self.syntax_name[2]: - # the two chars of the register pair do not match - raise UnexpectedException("The two chars of the register pair do not match:" - "'{:s}' and '{:s}'".format(self.syntax_name[1], self.syntax_name[2])) - - if self.syntax_name[0] == 'P': - # Predicate - self.is_predicate = True - - if self.syntax_name[0] == 'C': - # Control register - self.is_control = True - if len(self.syntax_name[1:]) == 2: - self.is_register_pair = True - - if self.syntax_name[1] != self.syntax_name[2]: - # the two chars of the register pair do not match - raise UnexpectedException("The two chars of the register pair do not match:" - "'{:s}' and '{:s}'".format(self.syntax_name[1], self.syntax_name[2])) - - if self.syntax_name[0] == 'S': - # System control register - self.is_system = True - if len(self.syntax_name[1:]) == 2: - self.is_register_pair = True - - if self.syntax_name[1] != self.syntax_name[2]: - # the two chars of the register pair do not match - raise UnexpectedException("The two chars of the register pair do not match:" - "'{:s}' and '{:s}'".format(self.syntax_name[1], self.syntax_name[2])) - - - if self.syntax_name[0] == 'N': - # New value register - self.is_newvalue = True - - - # TODO: Check if the general purpose register is the only that uses reg. pairs. - # (the control reg is also possible as reg. pair but they are usually rreferencedby their alias) - - - -class ImmediateTemplate(OperandTemplate): - # TODO: Document class. Develop the notion of immediate type, e.g., r, m, s, etc. - - __slots__ = ['scaled', 'type', 'syntax', 'signed', 'index'] - # TODO: Change `scaled` to ``scale`` (because it's used as an int, not a bool). - - def __init__(self, syntax_name, scaled=0): - super(ImmediateTemplate, self).__init__(syntax_name) - self.syntax = syntax_name - self.scaled = scaled - self.signed = False - self.index = 0 - - self.type = self.syntax_name[1].lower() - if self.type == 's': - self.signed = True - - if self.type not in ['s', 'u', 'm', 'r', 'g', 'n']: - raise UnexpectedException("Unknown immediate type: {:s}".format(self.type)) - -class OptionalTemplate(OperandTemplate): - __slots__ = ['syntax', 'index', 'syntax_pos'] - - def __init__(self, syntax_name): - super(OptionalTemplate, self).__init__(syntax_name) - self.syntax = syntax_name - self.index = 0 - self.syntax_pos = 0 - -class EncodingField(): - """Hexagon instruction encoding field, as seen in the manual. - - An encoding field can be characterized with only a mask (int) with the 1's set - to indicate the positions of the field chars in the encoding. E.g., in the encoding - (str) ``1011iiiiiiisssssPPiiiiiiiiiddddd``, the field ``s5`` would have a mask - (int) like ``0b00000000000111110000000000000000``. - - This mask is used to later extract the value of the field in the instruction - being disassembled, which would be used to generate either an immediate or - register operand. - - This value extraction (bit by bit) can be time consuming. To improve performance, - and taking advantage of the fact that most encoding fields are unified, (i.e., - all their field chars have consecutive order, like the example above), other - (redundant) attributes are added to the class to reflect this. - If a field is unified (``no_mask_split`` is True), the field value can - be extracted just by applying a logical and operation, if the mask is split, - after the logical and, the extracted bits need to be joined (which is time consumig - for the disassembly process, as seen in the profiling results). - - Attributes: - - mask (int): resulting from setting to 1's the positions in the instruction encoding - where the corresponding field char appears. - mask_len (int): number of times the field char appears on the encoding field (i.e., - number of 1's in the mask). - no_mask_split (bool): indicates whether all the field chars have a consecutive - bit ordering (i.e., if all the 1's in the mask are together). - mask_lower_pos (int): lowest bit index in the encoding where the field char is found - (i.e. position of the first 1 in the mask). - index (int): the number of operand - - TODOs: - * Improve this class explanation, its use is in the disassembler, maybe move - some of the explanation there (to `extract_and_join_mask_bits` function). - - * Clearly differentiate between bit-by-bit processing vs manipulating all - bits together (extract bits). - - * Change `mask_lower_pos` to ``field_lower_pos`` or ``field_start_pos``. - - * Change `no_mask_split` to ``mask_split`` and adjust logic, asking - for ``if not no_mask_split`` is too cumbersome. - - """ - __slots__ = ['mask', 'mask_len', 'no_mask_split', 'mask_lower_pos', 'index'] - - def __init__(self): - self.mask = 0 - self.mask_len = 0 - # Used to determine the sign of immediates. - # TODO: Is mask_len used just for that? - self.index = 0 - - -class TemplateBranch(): - """Hexagon instruction branch. - - Attribute that adds information to the InstructionTemplate, used mainly - in the IDA processor module to perform branch analysis.. - - Attributes: - - type (str): of branch, useful for IDA analysis. - target (OperandTemplate): operand template (register or immediate) in the instruction - that contains the target of the branch. - is_conditional (bool): True if conditional branch (there's an 'if' inside - the syntax); False otherwise. - - TODOs: - - * Define the branch type inside a class or enum or somewhere unified, - not as strings, and not inside the class. - - * Comment on each branch type separately, explaining the difference. - - * Change `all_branches` name to ``branch_syntax(es)``. - - * Change `all_branches` name to ``branch_syntax(es)``. - - * Document a branch as the union of hexagon jumps and calls. - - * The branch syntax is used like a regexp pattern, the spaces (added for readability) - are ignored only if ``re.search`` is called with ``re.X`` argument - (e.g., as `analyze_branch` does), enforce/specify this. - - * Once the branch types are unified give examples. - - """ - __slots__ = ['target', 'is_conditional', 'type'] - - jump_reg_syntax = r'jumpr (?: :t | :nt)?' # ``?:`` don't capture group - jump_imm_syntax = jump_reg_syntax.replace('jumpr', 'jump') - call_reg_syntax = r'callr' - call_imm_syntax = call_reg_syntax.replace('callr', 'call') - dealloc_ret_syntax = r'dealloc_return' - all_branches = [jump_reg_syntax, jump_imm_syntax, call_reg_syntax, call_imm_syntax, dealloc_ret_syntax] - - def __init__(self, type): - self.type = type - self.target = None - self.is_conditional = False - -class TemplateToken(): - """Hexagon instruction template token. - - Used mainly in the IDA processor module, to print some parts of the syntax (tokens) - in a special manner, matching the strings (`s`) with their corresponding operand (`op`). - - Attributes: - - s (str): token string. - op (Optional[OperandTemplate]): operand template (if any) that corresponds to the token. - - TODOs: - * Change `s` name to something more descriptive, maybe also `op`, - using more than 2 letters is allowed... - - """ - __slots__ = ['s', 'op'] - - def __init__(self, s): - self.s = s - self.op = None - - -class InstructionEncoding(): - """Hexagon instruction encoding. - - Attributes: - text (str): encoding chars, without spaces, of len 32, each char represents one bit of the - instruction, e.g., the encoding of ``Rd=add(Rs,#s16)`` is ``1011iiiiiiisssssPPiiiiiiiiiddddd``, - ``text[0]`` corresponds to bit 31 and ``text[31]`` to bit 0 (LSB) of the encoding. - mask (int): resulting from setting to 1's all the instruction defining bits, used in the - disassembly to determine the type of an instruction. - value (int): resulting from extracting only the instruction defining bits, used in conjunction with - the mask to determine the type of an instruction. - fields (Dict[str, EncodingField]): instruction encoding fields, indexed by the field char, - e.g. fields['d'] -> EncodingField(Rd). - - TODOs: - * Change `text` attribute's name, so as not to be confused with an instruction text. - * Fields is a redundant attribute, because the encodings fields are contained - in the operands dict. key (of the instruction template), - but it's clearer this way. Should it be eliminated? - - """ - __slots__ = ['text', 'value', 'mask', 'fields'] - - def __init__(self, text): - - #if len(text) != 32: - # raise UnexpectedException('There has been a problem during the instruction definition import process.') - - # TODO: Check also `text` for spaces. - - # TODO: check that ICLASS bits (31:28 and 31:29,13 for duplex) in `text` are always defined to 0/1. - - self.text = text - - self.fields = {} - - self.generate_mask_and_value() - self.generate_fields() - - def generate_mask_and_value(self): - """Generate the mask and value of the instruction encoding, from its text (str). - - There are no Args nor Return values, everything is done manipulating the - object attributes: the input would be `self.text` and the output `self.mask` - and `self.value`. - - """ - self.mask = 0 - self.value = 0 - - for text_pos in range(32): - - mask_pos = 31 - text_pos - # The orders of mask bits (int) and text bits (str) are reversed. - - if self.text[text_pos] in ['0', '1']: - self.mask |= (1 << mask_pos) - self.value |= int(self.text[text_pos]) << mask_pos - - def generate_fields(self): - """Generate instruction fields of the instruction encoding, from its text (str). - - Parse everything else that's not a instruction defining bit (0/1), like the ICLASS - bits, and generate the corresponding fields from each different spotted char. - The other type of chars ignored (besides 0/1) are '-' (irrelevant bit) - and 'P' (parse bit). - - The fields created (EncodingField) do not differentiate between immediate or register, - they are just a bit field at this stage. - - The generation of each field mask is pretty straight forward, but the process - has been complicated with the fact that the generated mask is checked to see if - bits are consecutive (no_mask_split), for performance reasons. See `EncodingField` - description. - - There are no Args nor Return values, everything is done manipulating the - object attributes: the input would be `self.text` and the output `self.fields`. - - TODOs: - * Rethink this explanation. 'P' is a valid field, but I'm skipping it because it - won't be a valid imm. o reg. operand. So even though this encoding fields - are just bits their ultimate use will be for operands. - - * Use the terms "specific fields" (from "Instruction-specific fields") and - Common fields (defined in section 10.2 of the manual). ICLASS and parse - bits (common fields) are the ones I'm ignoring. - - * The rationale behind the `no_mask_split` is split between here and - `EncodingField`. Unifiy. - - * Avoid skipping any field here, create all the bit fields from the instruction, - and then skip them during reg./imm. ops. creation, to simplify the logic - here (less coupling, this function is doing -or knowing- more than it should). - - """ - field_last_seen_pos = {} # type: Dict[str, int]) - # Used to detect a mask split. - # TODO: Elaborate on this. - - # TODO: XXX: add the index of operand for each field - for text_pos in range(32): - - mask_pos = 31 - text_pos - # The orders of mask bits (int) and text bits (str) are reversed. - - if mask_pos in [14, 15]: # skip 'P', parse bits - continue - # TODO: Remove this check when this function is permitted to parse all fields - # (and discard the P field later when generating the operands). - - c = self.text[text_pos] - - if c not in ['0', '1', '-']: - # TODO: Change to a continue clause, to remove all the following indentation. - - if c not in self.fields: - # Char seen for the first time, create a new field. - - self.fields[c] = EncodingField() - self.fields[c].no_mask_split = True - field_last_seen_pos[c] = (-1) - # (-1): used to indicate that it's a new field, and there's - # no last seen char before this one. - - self.fields[c].mask |= (1 << mask_pos) - self.fields[c].mask_len += 1 - - # Detect a split in the field (and if so, reflect it on the mask). - - if field_last_seen_pos[c] != -1: - if mask_pos != (field_last_seen_pos[c] - 1): # mask_pos iteration is going ackwards - self.fields[c].no_mask_split = False - - field_last_seen_pos[c] = mask_pos - - for c in self.fields: - self.fields[c].mask_lower_pos = field_last_seen_pos[c] - # The last seen position in the text (str) of each field is the - # lowest position in the mask (int), as their orders are reversed. - - -class InstructionDefinition(): - """Definition of an instruction (like the manual): syntax, encoding, and beahvior. - - Instructions obtained by the importer (either from the manual or the objdump - headers). It has the minimal processing, only on the instruction encoding, converted - to `InstructionEncoding` (it has no use as a string), the major work is done in - the `InstructionTemplate` through the decoder. - - The behavior attribute is optional, because the parser still doesn't support many of - the manual's behavior strings. - - Attributes: - syntax (str) - encoding (InstructionEncoding) - behavior (str) - - """ - __slots__ = ['syntax', 'encoding', 'behavior'] - - def __init__(self, syntax, encoding, behavior): - self.syntax = syntax - self.encoding = InstructionEncoding(encoding) - self.behavior = behavior - -# TODO: Handle also TAB characters - -class InstructionTemplate(): - """Definition of the instruction with the maximum processing done before being used for disassembly. - - Created by the decoder from an `InstructionDefinition`. - All the major attributes of the instruction are processed and - stored here, e.g., operands, duplex, branches, tokens, etc. - - Attributes: - encoding (InstructionEncoding): Hexagon instruction encoding, as seen in the manual. - syntax (str): Hexagon instruction syntax, as seen in the manual, e.g. ``Rd=add(Rs,#s16)``. - operands (Dict[str, InstructionOperand]): Operands (registers or immediates) indexed by their - respective field char, e.g., operands['d'] -> InstructionOperand(Rd). - mult_inst (bool): Has more than one atomic instruction, i.e., has a ';' in the syntax. - is_duplex (bool): Indicates if this is a duplex instruction. - imm_ops (List[ImmediateTemplate]): List of the instruction register operand templates. - reg_ops (List[RegisterTemplate]): List of the instruction immediate operand templates. - opt_ops (List[OptionalTemplate]): List of the instruction optional operand templates. - branch (Optional[TemplateBranch]): If not None, has the branch being performed by the - instruction, identified by the encoding analyzing the instruction syntax and not - its behavior (as it should). - behavior (str): Hexagon instruction behavior, as seen in the manual, e.g. ``Rd=Rs+#s;``. - imm_ext_op (Optional[ImmediateTemplate]): "Pointer" to the immediate operand that can - be extended in the instruction. It is just a hint for the disassembler, to let it - know what immediate operand can be the target of a constant extension. "Pointer" - here means that it has one of the imm. ops. in the `imm_ops` list. - tokens (List[TemplateToken]): List of strings representing the tokenized behavior, where - splits are done in the cases where part of the syntax can be linked to an operand, - see `HexagonInstructionDecoder.tokenize_syntax`. - name (str): Name. - - """ - __slots__ = ['encoding', 'syntax', 'operands', 'mult_inst', - 'is_duplex', 'imm_ops', 'reg_ops', 'opt_ops', 'branch', 'behavior', - 'imm_ext_op', 'tokens', 'name'] - - - register_operand_field_chars = ['t', 'd', 'x', 'u', 'e', 'y', 'v', 's'] - # Seen on the manual - - # Added from the objdump headers, but not in the manual - register_operand_field_chars.extend(['f', 'z']) - - immediate_operand_field_chars = ['i', 'I'] - - other_field_chars = ['-', 'P', 'E', 'N'] - # 'E' added from the objdump header encodings (not in the manual) - - field_chars = register_operand_field_chars + \ - immediate_operand_field_chars + \ - other_field_chars - # TODO: move all field char definitions inside `generate_operand` or in `common.py`. - - def __init__(self, inst_def): - - #print(inst_def) - #if not isinstance(inst_def, InstructionTemplate): - # pass - - self.encoding = inst_def.encoding - self.syntax = standarize_syntax_objdump(inst_def.syntax) - self.behavior = inst_def.behavior - # TODO: Create an ``InstructionField`` that groups these 3 attributes. - - self.imm_ops = [] - self.reg_ops = [] - self.opt_ops = [] - - self.operands = {} - # Contains the same info as imm_ops + reg_ops, only used inside - # `generate_instruction_operands`. - # TODO: Remove this attribute. - - self.branch = None - self.imm_ext_op = None - self.tokens = [] - self.name = None - - self.mult_inst = (';' in self.syntax) - - self.is_duplex = (self.encoding.text[16:18] == '00') - # PP (parity bits) set to '00' - #print("is duplex? {0}".format(self.is_duplex)) - - for c in self.encoding.fields: - #print(c) - self.generate_operand(c) - - # Calculate operand indexes - self.operand_calculate_indices() - - # C: char, ie: inst encoding - def generate_operand(self, c): - """Generate an operand from an instruction field. - - Args: - c (str): Field char. - - Returns: - None: the information is added to `reg_ops`/`imm_ops` and `operands` - of the same InstructionTemplate. - - """ - #print("syntax = \"{0}\" char = \"{1}\"".format(self.syntax, c)) - if c not in InstructionTemplate.field_chars: - print("Field char {:s} not recognized.".format(c)) - raise UnexpectedException("Field char {:s} not recognized.".format(c)) - - if c in self.register_operand_field_chars: - reg = self.match_register_in_syntax(self.syntax, c) - if reg: - self.operands[c] = reg - self.reg_ops.append(reg) - return - print("not register operand match in syntax! [{0:s}]".format(c)) - - if c in self.immediate_operand_field_chars: - imm = self.match_immediate_char_in_syntax(self.syntax, c) - if imm: - self.operands[c] = imm - self.imm_ops.append(imm) - - return - print("no immediate operand match in syntax! [{0:s}]".format(c)) - - # There is a pretty similar structure in both processings. - # TODO: Can this be abstracted to a more general function? - if c == 'N': - # 'N' operand, it indicates an optional behavior in the instruction (which doesn't happen often). - m = re.search(r"(\[\s*:\s*<<\s*N\s*\])", self.syntax) - if m: - opt = OptionalTemplate('[:< 0, tokens)) - - # Generate list of TemplateToken and match string tokens to operands. - - for str_token in tokens: - - #template_token = TemplateToken(str_token.lower()) - template_token = TemplateToken(str_token) - # TODO: Is it ok to convert to lowercase here? - # The letter case of the operands text is useful (specially in IDA) to - # identify them quickly in the visual analysis (from the rest of the instruction). - - for op in template.reg_ops + template.imm_ops + template.opt_ops: # type: InstructionOperand - - if str_token == op.syntax_name: - # The string token names the operand, match them. - - template_token.op = op - break - - template.tokens.append(template_token) - - return - - def resolve_constant_extender(self, template): - """In case there are two imm. operands, indicate to which one would apply a constant extension. - - This is done for instructions that can be extended by a constant but have two - immediate operands and it has to be indicated to which one the extension applies. - - The function ``apply_extension()`` in instruction behaviours is used as an indication - that a constant extension can be applied, and the argument of the function specifies - the syntax of which immediate operand it applies to. - - Args: - template (InstructionTemplate): to be processed. - - Returns: - None: the data is applied to the template itself. - - TODOs: - * Add to the function description an example of an instruction where - there are two imm. ops. and the ``apply_extension()`` resolves which one. - - """ - if len(template.imm_ops) < 2: - # There's no need to perform the check, there's (at most) only one - # immediate operand to choose from. - if template.imm_ops: - template.imm_ext_op = template.imm_ops[0] - return - m = re.search(r""" - # Looking for something like: "apply_extension(...);" - - apply_extension - \( - (.*?) # Capture group for the imm. op. name, e.g., ``#s``. - \) - """, template.behavior.replace(' ', ''), re.X) - # The spaces are removed from the behavior string to simplify the regex. - - if m is None: - # No constant extension found in the behavior. - # But it has immediates -> assume imm_ops[0] - template.imm_ext_op = template.imm_ops[0] - return - - imm_op_ext_name = m.group(1) - # Name of the imm. op. that is the argument of ``apply_extension()``. - - for imm_op in template.imm_ops: - if imm_op_ext_name in imm_op.syntax_name: - # An equal comparison is not made in the previous if because - # the op. name in the apply_extension argument is usually a shorter - # version of the name in the syntax (normally because the - # operand's bit size was removed), e.g., ``#s16`` in - # ``Rd=add(Rs,#s16)`` is referenced as ``apply_extension(#s);``. - template.imm_ext_op = imm_op - return - - raise UnexpectedException("Cannot parse constant extender") - # If the regex matched, the operand should have been found in the previous loop. - - def analyze_branch(self, template): - """Find a branch in the instruction syntax and generate the template info. - - Used in (IDA) static analysis. - - Args: - template (InstructionTemplate): to be processed. - - Returns: - None: the data is applied to the template itself. - - TODOs: - * Change function name to something like 'find_branch(es)'. - - * This type of analysis should be done by studying the REIL translation - of the instruction, which truly reflects its behaviour. When the REIL - translation is added this function should be adapted. - - * Multiple branches in one instruction: is it possible? I think not, - at most, two branches in one packet but separate. Check this. - - * The branch string itself is used to represent it, maybe some constants - should be used instead. - - """ - for branch_syntax in TemplateBranch.all_branches: # type: str - # Find any of the possible branch syntaxes in the instruction - # to detect a branch. - m = re.search(branch_syntax, template.syntax, re.X) - if m is None: - continue - - if branch_syntax == TemplateBranch.dealloc_ret_syntax: - # The instruction is a 'dealloc_return', a jump to the - # LR as target. - pass - - template.branch = TemplateBranch(branch_syntax) - - template.branch.is_conditional = ('if' in template.syntax) - # TODO: The if could be applying to another sub-instruction. Improve detection. - - if branch_syntax in [TemplateBranch.jump_reg_syntax, TemplateBranch.call_reg_syntax]: - # Branch type: jump/call register. - - # Find which register is the target of the branch. - - for reg in template.reg_ops: # type: RegisterTemplate - m = re.search(branch_syntax + r'\s*' + reg.syntax_name, template.syntax, re.X) - if m: - template.branch.target = reg - return - - # The target register operand was not found, this shouldn't happen, but - # for now the case of register alias (specially the case of LR) is not - # being handled, so an exception can't be raised, and this case is - # tolerated (retuning instead). - - # raise UnexpectedException() - return - - if branch_syntax in [TemplateBranch.jump_imm_syntax, TemplateBranch.call_imm_syntax]: - # Branch type: jump/call immediate. - - for imm in template.imm_ops: # type: ImmediateTemplate - m = re.search(branch_syntax + r'\s*' + imm.syntax_name.replace('#', r'\#'), template.syntax, re.X) - # The '#' (used in imm. op. names) is escaped, as it is interpreted as - # a comment in verbose regex (re.X), and verbose regex is used because - # the branch syntax is written with spaces (verbose style) to improve - # its readability. - - if m: - template.branch.target = imm - return - - raise UnexpectedException("Cannot find target immediate operand") - # The target immediate operand should have been found. - - return - -class ManualParser: - - def __init__(self, manual_fn): - self.manual = open(manual_fn, 'r', newline=None) # universal newlines, to get rid of '\r' when opening in linux - self.lines = self.manual.read().splitlines() - self.ln = 0 - self.current_line = self.lines[self.ln] - - # TODO: change the name, this are not yet instruction templates until the decoder process them - self.instructions = [] - - self.syntax_behavior_text = [] - - - self.current_inst_name = "" - self.total_encodings = 0 - - def get_next_line(self): - self.ln += 1 - - if self.ln == len(self.lines): - raise self.OutOfLinesException() - - return self.get_current_line() - - def peek_next_line(self): - if self.ln + 1 == len(self.lines): - raise self.OutOfLinesException() - - return self.lines[self.ln + 1] - - def peek_prev_line(self): - if self.ln - 1 == -1: - raise self.OutOfLinesException() - - return self.lines[self.ln - 1] - - def get_current_line(self): - self.current_line = self.lines[self.ln] - return self.current_line - - def get_prev_line(self): - self.ln -= 1 - - if self.ln < 0: - raise self.UnexpectedException() - - return self.get_current_line() - - def go_to_instruction_set_start(self): - - try: - while True: - m = re.search(r"Hexagon V62 Programmer's Reference Manual\s*Instruction Set", self.current_line) - if m: - #print("Found start of Instruction Set at line: " + str(self.ln)) - #print(self.current_line) - break - - self.get_next_line() - - except self.OutOfLinesException: - raise self.UnexpectedException() - - def find_encondings(self): - try: - inside_encoding = False - inside_behavior = False - - last_syntax_found_ln = -1 - last_behavior_found_ln = -1 - while True: - - self.get_next_line() - #print(self.current_line) - - m = re.search(r"\s*Syntax\s*Behavior\s*", self.current_line) - if m: - #print("\nFound start of Syntax/Behavior at line: " + str(self.ln)) - #print(self.current_line) - inside_behavior = True - continue - - m = re.search(r"^\s*Class: .*", self.current_line) - if m: - #print("\nFound start of Class at line: " + str(self.ln)) - #print(self.current_line) - inside_behavior = False - continue - - m = re.search(r"\s*Encoding\s*", self.current_line) - if m: - #print("\nFound start of Encoding at line: " + str(self.ln)) - #print(self.current_line) - inside_encoding = True - inside_behavior = False - continue - - # The end of an econding section is typically signaled by the start of the "Field name" section. - m = re.search(r"Field name\s*Description", self.current_line) - if m: - #print("Found end of Encoding at line: " + str(self.ln) + '\n') - #print(self.current_line) - inside_encoding = False - inside_behavior = False - continue - - ''' - Syntax/Behavior extraction: - Organized in two columns. - ''' - if inside_behavior: - - - # Instructions without a clear separation of syntax and behavior are skipped - complicated_instructions = [ - "Vector", - "Floating", - "Complex add/sub halfwords", - "Multiply", - "Shift by register", - "Set/clear/toggle bit", - "Extract bitfield", - "Test bit", - "CABAC decode bin", - ] - if True in [ci.lower() in self.current_inst_name.lower() for ci in complicated_instructions]: - continue - - - #if self.current_line.strip().decode('utf-8') == '': - if self.current_line.strip() == '': - continue - - # Page header/footer skip - # TODO: maybe this should apply to more parts of the code, no just syntax/behavior - if ("Hexagon V62 Programmer's Reference Manual" in self.current_line or - "MAY CONTAIN U.S. AND INTERNATIONAL EXPORT" in self.current_line or - "80-N2040-36 B" in self.current_line): - continue - - - - - # Try to match the 2 column format, basically tryng to see the separation space between them (the 5 spaces min requirement) - m = re.search(r"^\s*(\S.+?\S)\s{5,}(\S.+)", self.current_line) - if m: - #print("Found pair of syntax/behavior") - #print("Group 1: " + m.group(1)) - #print("Group 2: " + m.group(2)) - behavior_1st_column_pos = m.start(1) - behavior_2nd_column_pos = m.start(2) - -# if self.current_line[0:behavior_2nd_column_pos].strip() != '': -# # Syntax column -# # TODO this if check should be include in the previous regex - - # Continuation syntax (in 2 consecutive lines) - if self.ln - 1 == last_syntax_found_ln: - #print("Cont Syntax: " + m.group(1)) - self.syntax_behavior_text[-1][0] += " " + m.group(1) - else: - #print("New Syntax: " + m.group(1)) - self.syntax_behavior_text.append([m.group(1), '']) - last_syntax_found_ln = self.ln - - #print("Behavior is: " + m.group(2)) - self.syntax_behavior_text[-1][1] += m.group(2) - last_behavior_found_ln = self.ln - - else: - # Can be a behavior continuation line - if self.current_line[behavior_2nd_column_pos:].strip() != '': - if self.ln - 1 == last_behavior_found_ln: - #print("Behavior cont is: " + self.current_line[behavior_2nd_column_pos:].strip()) - self.syntax_behavior_text[-1][1] += self.current_line[behavior_2nd_column_pos:].strip() - last_behavior_found_ln = self.ln - - - ''' - Start of a page of the "Instruction Set" section: if the first non empty line that appears - in the next 3 to 5 lines (usually its 3 blank lines and the title) - has text at the begining of the line, it's likely a new title, and hence a new instruction - name. I'm assuming the title has at least 3 chars. - - TODO: Double line titles - ''' - m = re.search(r"Hexagon V62 Programmer's Reference Manual\s*Instruction Set", self.current_line) - if m: -# print "Found start of Instruction Set page at line: " + str(self.ln) - start_ln = self.ln - title_found = False - for _ in range(5): - self.get_next_line() -# print self.current_line - m = re.search(r"^\w{3}", self.current_line) - if m: - #print("Found title at line: " + str(self.ln)) - #print(self.current_line) - self.current_inst_name = self.current_line.strip() - break - - # Just to be sure I return to where the search for a title began - if not title_found: - self.ln = start_ln - - continue - - # The first four bits (ICLASS) of an encoding are always set (either to 0 or 1), - # and are at the start of the line - m = re.search(r"^([01]\s*){4}", self.current_line) - if m: -# print "Found encoding at line: " + str(self.ln) -# print self.current_line - - # Bits not defined in the encoding are marked as "-", not left blank, - # so there is always 32 non-whites, particulary: 0/1, chars or "-". - m = re.search(r"^(([01a-zA-Z\-]\s*){32})(.*)$", self.current_line) - if m is None: - raise self.UnexpectedException() - - ie = m.group(1).replace(' ', '') - syntax = m.group(3) # My limited regex understanding doesn't get why this is the 3rd group and not the 2nd, but this works. - - # The syntax may be splitted in 2 lines, in this case the second line - # is all white spaces, until the position where the syntax started in the - # previous line, where the sytax string continues. Or can be the contrary, - # the second line of the syntax has the encoding and the first line is blank - next_line = self.peek_next_line() - prev_line = self.peek_prev_line() - - if len(next_line) > m.start(3) and re.search(r"^\s*$", next_line[0 : m.start(3)]): # all spaces up to the syntax string - # TODO: Change name m2. - m2 = re.search(r"^(\S.*)", next_line[m.start(3):]) # here has to be something (I can't specify what exactly besides a non space) - if m2: - #print("Found syntax continuation") - #print(("1st line: {:s}".format(syntax))) - #print(("2nd line: {:s}".format(m2.group(1)))) - - syntax += ' ' + m2.group(1) - - self.get_next_line() # To really pass over this continuation syntax line - - elif len(prev_line) > m.start(3) and re.search(r"^\s*$", prev_line[0 : m.start(3)]): - # TODO: Change name m2. - m2 = re.search(r"^(\S.*)", prev_line[m.start(3):]) # here has to be something (I can't specify what exactly besides a non space) - if m2: - #print("Found syntax continuation in prev line") - #print(("1st line: {:s}".format(m2.group(1)))) - #print(("2nd line: {:s}".format(syntax))) - - syntax = m2.group(1) + ' ' + syntax - - else: - # TODO: Tidy up. - # The same can happen but with a disalignment of the other syntax line (prev or next) by 1 char - if len(next_line) > (m.start(3) - 1) and re.search(r"^\s*$", next_line[0 : (m.start(3) - 1)]): # all spaces up to the syntax string - # TODO: Change name m2. - m2 = re.search(r"^(\S.*)", next_line[(m.start(3) - 1):]) # here has to be something (I can't specify what exactly besides a non space) - if m2: - #print("Found syntax continuation") - #print(("1st line: {:s}".format(syntax))) - #print(("2nd line: {:s}".format(m2.group(1)))) - - syntax += ' ' + m2.group(1) - - self.get_next_line() # To really pass over this continuation syntax line - - elif len(prev_line) > (m.start(3) - 1) and re.search(r"^\s*$", prev_line[0 : (m.start(3) - 1)]): - # TODO: Change name m2. - m2 = re.search(r"^(\S.*)", prev_line[(m.start(3) - 1):]) # here has to be something (I can't specify what exactly besides a non space) - if m2: - #print("Found syntax continuation in prev line") - #print(("1st line: {:s}".format(m2.group(1)))) - #print(("2nd line: {:s}".format(syntax))) - - syntax = m2.group(1) + ' ' + syntax - - - #print("Encoding: " + ie) - #print("syntax:" + syntax) - - # TODO: handle instruction name -# if self.current_inst_name not in self.instructions: -# self.instructions[self.current_inst_name] = [] - - self.instructions.append(InstructionDefinition(syntax, ie, self.syntax_behavior_text[-1][1])) - - self.total_encodings += 1 - - continue - - - except ManualParser.OutOfLinesException: - pass -# print("End of scipt, out of lines") - - pass - - class OutOfLinesException(Exception): - pass - - class UnexpectedException(Exception): - pass - - -class HeaderParser: - def __init__(self, header_fn): - self.header = open(header_fn, 'r') - self.lines = self.header.read().splitlines() - - self.duplex_inst_encodings = [] - self.other_inst_encodings = [] - - def parse(self): - for l in self.lines: - - # TODO: check out HEXAGON_MAPPING - #m = re.search(r'^HEXAGON_OPCODE \s* \( \s* " (.*)? " \s* , \s* " (.*)? "', l, re.X) - m = re.search(r'^{\s* "(.*)?" \s* , \s* "(.*)?"', l, re.X) - if m: - syntax = m.group(1) - encoding = m.group(2).replace(' ', '') - - if len(encoding) != 32: - raise UnexpectedException - - # Split intructions: with subinsructions, marked with - # 'EE' in the 15:14 (from rigth to left) position of their encoding, which - # are going to be added to the database, and the rest, which only in the - # case they were not already added from the manual will be included (this is - # generally undocumented system instructions) - - if encoding[16:18].lower() == 'ee': - # I index the array from left to rigth, and just to be sure I'm converting to lower - encoding = (encoding[:16] + '00' + encoding[18:]) # '00' - duplex type - self.duplex_inst_encodings.append(InstructionDefinition(syntax, encoding, '')) - else: - self.other_inst_encodings.append(InstructionDefinition(syntax, encoding, '')) -# print("syntax: " + syntax) -# print("encoding: " + encoding) - - def standarize_syntax(self, encodings): - # To make it look like the manual - - for i in range(len(encodings)): - syntax = encodings[i].syntax - - # Remove registers size (I'm assuming) from their name: - # Rd16 -> Rd -# print("Before: " + syntax) - syntax = re.sub(r'\b ([RPNMCGS][a-z]{1,2}) \d{0,2} \b', r'\1', syntax, flags=re.X) # TODO: Register all possible register types, s,r,t,e etc. -# print("After: " + syntax) - - encodings[i].syntax = syntax - -# ------------------------------------------------------------------------------------- - -hex_insn_names = [] # For generating the instruction names header - -# TODO: add directions hint -# TODO: Add loop/endloop -# TODO: Support assignments -def generate_name(ins_syntax): - mname = "" - # Zero thing - "bla" - m = re.search(r'^\s*([_a-zA-Z\d]+)\s*$', ins_syntax) - if m: - mname = m.group(1) - # just copy as is - return mname.upper() - - # First thing - "bla bla insn (bla bla)" - # extract "insn"()a - m = re.search(r'([_a-zA-Z\d\.]+)\s*(\(.+\))+\s*.*$', ins_syntax) - if m: - mname = m.group(1) - return mname.upper() - -# HACK: just filter out the special characters and we're good to go -# TODO: Find a better way to generate names -def generate_dirtyname(ins_syntax): - #mname = "".join(e for e in ins_syntax if e.isalnum()) - mname = ins_syntax.replace("!", "_NOT_") - mname = mname.replace("-=", "_MINUS_EQ_") - mname = mname.replace("= -", "_EQ_MINUS_") - mname = mname.replace("+=", "_PLUS_EQ_") - mname = mname.replace("= +", "_EQ_PLUS_") - mname = mname.replace("&=", "_AND_EQ_") - mname = mname.replace("|=", "_OR_EQ_") - mname = mname.replace("< =", "_LT_EQ_") - mname = mname.replace("> =", "_GT_EQ_") - mname = mname.replace("==", "_EQ_") - mname = mname.translate({ord(c): "_" for c in " !@#$%^&*()[]{};:,./<>?\|`~-=+"}) - return mname.upper() - -def generate_insn(ins_tmpl): - iname = "HEX_INS" - if ins_tmpl.is_duplex: - iname += "_DUPLEX" - else: - if ins_tmpl.mult_inst: - iname += "_MULT" - # Split by ";" for multinstructions and duplexes - subs = ins_tmpl.syntax.split(";") - for sub in subs: - # Extract predicate - subname = generate_dirtyname(sub) - iname += "_" + subname - - # There is a weird case when two different instructions have the same syntax - if iname in hex_insn_names: - iname += "_" - - return iname - -# -------------------------------------------------------------------------------- -# Make a new C block (if/case/etc) -# TODO: support more syntax constructs -def make_C_block(lines, begin = None, end = None, ret = None, indent=True): - new = [] - ws = "\t" - if not indent: - ws = "" - if begin: - new += [begin + " {"] - else: - new += ["{"] - for l in lines: - new += [ws + l] - if ret: - new += [ws + ret] - if end: - new += ["} " + end] - else: - new += ["}"] - return new - -# -------------------------------------------------------------------------------- -# Associated bits of an instruction field are scattered over the encoding instruction in a whole. -# Here we assemble them by using the mask of the field. -# -# Simple example: -# Let the input mask of an immediate be: 0b1111111110011111111111110 -# The bits of the actual immediate need to be concatenated ignoring bit 15:14 and bit 0 (the zeros in the mask). -# So this function returns C-code which shifts the bits of the immediate segments and ORs them to represent a valid value. -# -# hi_u32 is the raw instruction from which we want to concatenate bit 24:16 and bit 13:1 (bit 31:25 are ignored here) -# 10th 2 1 -# bit # 432109876 54 3210987654321 0 - -# Mask: 111111111|00|1111111111111|0 -# hi_u32: 100111101|10|1010000010011|0 -# | | -# | | -# +--+ >---------------|-------[shift bit 24:16] -# ____|____ | ((hi_u32 & 0x1ff0000) >> 3) -# 1001111010000000000000 | [shift bit 13:1] -# OR 1010000010011 >-+---------------------------------((hi_u32 & 0x3ffe) >> 1)) -# _______________________ -# imm = 1001111011010000010011 - -# imm = ((hi_u32 & 0x1ff0000) >> 3) | ((hi_u32 & 0x3ffe) >> 1)) - -def make_sparse_mask(num, mask): - switch = False - ncount = 0 # counts how many bits were *not* set. - masks_count = 0 # How many masks we do have - masks = {} - bshift = {} - for i in range(0, 31): - if (mask >> i) & 1: - if not switch: - switch = True - masks_count += 1 - bshift[masks_count] = ncount - if masks_count in masks: - masks[masks_count] |= 1 << i - else: - masks[masks_count] = 1 << i - #bcount -= 1 - else: - switch = False - ncount += 1 - - # print("MASK") # For grep - # print(bin(mask)) - # print(masks) - outstrings = [] - for i in range(masks_count, 0, -1): - outstrings += ["(({0:s} & 0x{1:x}) >> {2:d})".format(num, masks[i], bshift[i])] - # print(outstrings) - outstring = " | ".join(outstrings) - outstring = "({0:s})".format(outstring) - return outstring - -def find_common_bits(masks_list): - combits = 0 - for mask in masks_list: - if combits: - combits &= mask - else: - combits = mask - return combits - -# -------------------------------------------------------------------------------- -# RIZIN SPECIFIC CODE - -preds = { - "if (Pu)" : "HEX_PRED_TRUE", - "if (Pv)" : "HEX_PRED_TRUE", - "if (Pt)" : "HEX_PRED_TRUE", - "if !Pu " : "HEX_PRED_FALSE", - "if !Pv " : "HEX_PRED_FALSE", - "if !Pt " : "HEX_PRED_FALSE", - "if (Pu.new)" : "HEX_PRED_TRUE_NEW", - "if (Pv.new)" : "HEX_PRED_TRUE_NEW", - "if (Pt.new)" : "HEX_PRED_TRUE_NEW", - "if !Pu.new" : "HEX_PRED_FALSE_NEW", - "if !Pv.new" : "HEX_PRED_FALSE_NEW", - "if !Pt.new" : "HEX_PRED_FALSE_NEW", -} - -# TODO: How to handle duplex/combined instructions where is a predicate? -# TODO: Extract and set conditional flag based on the instruction -def extract_predicates_rizin(ins_tmpl): - lines = [] - for k,v in preds.items(): - if ins_tmpl.syntax.startswith(k): - pred = "{0:s} = {1:s}; // {2:s}".format("hi->predicate", v, k) - lines = [pred] - if not lines: - lines = ["{0:s} = HEX_NOPRED;".format("hi->predicate")] - return lines - -pfs = { - ":rnd" : "HEX_PF_RND", - ":crnd" : "HEX_PF_CRND", - ":raw" : "HEX_PF_RAW", - ":chop" : "HEX_PF_CHOP", - ":sat" : "HEX_PF_SAT", - ":hi" : "HEX_PF_HI", - ":lo" : "HEX_PF_LO", - ":<<1" : "HEX_PF_LSH1", - ":<<16" : "HEX_PF_LSH16", - ":>>1" : "HEX_PF_RSH1", - ":neg" : "HEX_PF_NEG", - ":pos" : "HEX_PF_POS", - ":scale" : "HEX_PF_SCALE", - ":deprecated" : "HEX_PF_DEPRECATED" -} - -def extract_pf_rizin(ins_tmpl): - lines = [] - pfssorted = collections.OrderedDict(sorted(pfs.items())) - for k,v in pfssorted.items(): - if k in ins_tmpl.syntax: - pf = "{0:s} |= {1:s}; // {2:s}".format("hi->pf", v, k) - lines += [pf] - return lines - -def extract_name_rizin(ins_tmpl): - lines = [] - lines += ["hi->instruction = {0:s};".format(ins_tmpl.name)] - return lines - -def extract_fields_rizin(ins_tmpl): - lines = [] - sortf = lambda c: ins_tmpl.operands[c].index - sortedfields = sorted(ins_tmpl.encoding.fields, key = sortf) - op_count = 0 - # Set DUPLEX flag for those instructions - if ins_tmpl.is_duplex: - lines += ["hi->duplex = true;"] - # Handle branch specific fields - is_branch = False - if ins_tmpl.branch and ins_tmpl.branch.target: - is_branch = True - ti = ins_tmpl.branch.target.index # Target operand index - # if this is a loop, also mark it as a branch and get target - if "loop" in ins_tmpl.syntax: - is_branch = True - ti = 0 # Always 0 - - for n in sortedfields: - f = ins_tmpl.encoding.fields[n] - i = ins_tmpl.operands[n].index - slines = [] - - if f.no_mask_split: - mask = "((({0:s}) & 0x{1:x}) >> {2:d})".format("hi_u32", f.mask, f.mask_lower_pos) - else: - # Merge bits into the groups first, for the sake of speed - mask = make_sparse_mask("hi_u32", f.mask) - - fieldtype = "HEX_OP_TYPE_IMM" - if isinstance(ins_tmpl.operands[n], RegisterTemplate): - fieldtype = "HEX_OP_TYPE_REG" - # 1. Check if predicate register - if ins_tmpl.operands[n].is_predicate: - fieldtype = "HEX_OP_TYPE_PREDICATE" - val = "hi->ops[{0:d}].op.pred = {1:s};".format(i, mask) - # 2. Check if control register - elif ins_tmpl.operands[n].is_control: - fieldtype = "HEX_OP_TYPE_CONTROL" - val = "hi->ops[{0:d}].op.cr = {1:s};".format(i, mask) - # 3. Check if system control register - elif ins_tmpl.operands[n].is_system: - fieldtype = "HEX_OP_TYPE_SYSTEM" - val = "hi->ops[{0:d}].op.sys = {1:s};".format(i, mask) - # 4. Usual register - else: - fieldtype = "HEX_OP_TYPE_REG" - if ins_tmpl.operands[n].is_register_pair: - # TODO: Handle additional attributes - val = "hi->ops[{0:d}].op.reg = {1:s};".format(i, mask) - else: - val = "hi->ops[{0:d}].op.reg = {1:s}; // {2:s}".format(i, mask, ins_tmpl.operands[n].syntax) - # Optional value - elif isinstance(ins_tmpl.operands[n], OptionalTemplate): - fieldtype = "HEX_OP_TYPE_OPT" - # Immediate value - else: - val = "hi->ops[{0:d}].op.imm = {1:s}".format(i, mask) - # Perform sign extension (also applies to jump targets...) - # Also applies to the loops - - if ins_tmpl.operands[n].signed or (is_branch and i == ti): - # The immediate is already scaled at this point. Therefore the most significant bit is bit 24 (if we assume #r22:2) - signmask = "hi->ops[{0:d}].op.imm & (1 << {1:d})".format(i, f.mask_len + ins_tmpl.operands[n].scaled - 1) - signext = "hi->ops[{0:d}].op.imm |= (0xFFFFFFFF << {1:d});".format(i, f.mask_len + ins_tmpl.operands[n].scaled - 1) - slines += make_C_block([signext], "if ({0:s})".format(signmask)) - # Handle scaled operands - if ins_tmpl.operands[n].scaled: - val += " << {0:d}; // scaled".format(ins_tmpl.operands[n].scaled) - else: - val += ";" - - # We do not have operand for optional, so handle it's differently - if fieldtype == "HEX_OP_TYPE_OPT": - # Add IF here, because optional - opsft = "{0:s} |= {1:s}; // {2:s}".format("hi->pf", "HEX_PF_LSH1", "[:<<1]") - lines += make_C_block([opsft], "if ({0:s})".format(mask)) - else: - field = "hi->ops[{0:d}].type = {1:s};".format(i, fieldtype) - opattrs = [] - if isinstance(ins_tmpl.operands[n], RegisterTemplate): - # Check if a register pair - if ins_tmpl.operands[n].is_register_pair: - opattrs += ["hi->ops[{0:d}].attr |= HEX_OP_REG_PAIR;".format(i)] - lines += [field] + opattrs + [val] - lines += slines - op_count += 1 # Count only non-optional operands - - lines = ["hi->op_count = {0:d};".format(op_count)] + lines - return lines - -def extend_immediates_rizin(ins_tmpl): - elines = [] - # Note about duplex containers: - # In duplex containers only the second of two instructions (slot 1) can be expanded. - # Slot 1 are the high bits of an instruction, therefore: - # SLOT 1 ; SLOT 0 - # Rd = #u6 ; allocframe(#u5) - # The manual speaks of only two specific instructions (Rx = add (Rx, #s7) and Rd = #u6) - # which are expandable (But there seem to be more) - # Reference: Programmers Manual V62-V67 Chapter 10.3 - - if ins_tmpl.name in extendable_insn or (ins_tmpl.is_duplex \ - and ins_tmpl.syntax.split(';', 1)[0].strip() in extendable_duplex_syntax): - if ins_tmpl.imm_ops: - # Assume we only have one - it is clear in the list - op = ins_tmpl.imm_ext_op # imm_ext_op is by default set to imm_ops[0] - oi = op.index # Immediate operand index - # If there is an offset of the operand - apply it too - # Use "extend_offset(op, off)" function then - off = op.scaled - if off: - elines = ["hex_op_extend_off(&hi->ops[{0:d}], {1:d});".format(oi, off)] - else: - elines = ["hex_op_extend(&hi->ops[{0:d}]);".format(oi)] - return elines - -def extract_mnemonic_rizin(ins_tmpl): - lines = [] - # field -> token - sortf = lambda c: ins_tmpl.operands[c].index - sortedops = sorted(ins_tmpl.operands, key = sortf) - fmt = {} - args = [] - fmtstr = ins_tmpl.syntax - for n in sortedops: - o = ins_tmpl.operands[n] - i = ins_tmpl.operands[n].index - if isinstance(o, RegisterTemplate): - if o.is_predicate: - fmt[o.syntax] = "P%d" # + number from mask - args += ["hi->ops[{0:d}].op.pred".format(i)] - elif o.is_control: - if o.is_register_pair: - fmt[o.syntax] = "%s:%s" - args += ["hex_get_cntl_reg(hi->ops[{0:d}].op.cr + 1)".format(i)] - args += ["hex_get_cntl_reg(hi->ops[{0:d}].op.cr)".format(i)] - else: - fmt[o.syntax] = "%s" - args += ["hex_get_cntl_reg(hi->ops[{0:d}].op.cr)".format(i)] - elif o.is_system: - if o.is_register_pair: - fmt[o.syntax] = "%s:%s" - args += ["hex_get_sys_reg(hi->ops[{0:d}].op.sys + 1)".format(i)] - args += ["hex_get_sys_reg(hi->ops[{0:d}].op.sys)".format(i)] - else: - fmt[o.syntax] = "%s" - args += ["hex_get_sys_reg(hi->ops[{0:d}].op.sys)".format(i)] - else: - # DUPLEX - if ins_tmpl.is_duplex: - if o.is_register_pair: - fmt[o.syntax] = "%s" # + number from mask - args += ["hex_get_sub_regpair(hi->ops[{0:d}].op.reg)".format(i)] - else: - fmt[o.syntax] = "%s" # + number from mask - args += ["hex_get_sub_reg(hi->ops[{0:d}].op.reg)".format(i)] - # NOT DUPLEX - else: - if o.is_register_pair: - fmt[o.syntax] = "R%d:R%d" # + number from mask - args += ["hi->ops[{0:d}].op.reg + 1".format(i)] - args += ["hi->ops[{0:d}].op.reg".format(i)] - else: - fmt[o.syntax] = "R%d" # + number from mask - args += ["hi->ops[{0:d}].op.reg".format(i)] - elif isinstance(o, OptionalTemplate): - fmt[o.syntax] = "%s" - args += ["((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? \":<<1\" : \"\""] - elif isinstance(o, ImmediateTemplate): - fmt[o.syntax] = "0x%x" # TODO: Better representation, etc - # As soon as we extract the classes from the encoded instructions this should its info from it. - if ("JUMP_" in ins_tmpl.name or "CALL_" in ins_tmpl.name) and (i == len(ins_tmpl.operands)-1): - args += ["addr + (st32) hi->ops[{0:d}].op.imm".format(i)] - elif o.signed: - fmt[o.syntax] = "%d" - args += ["(st32) hi->ops[{0:d}].op.imm".format(i)] - else: - args += ["hi->ops[{0:d}].op.imm".format(i)] - else: - pass - - for k,v in fmt.items(): - fmtstr = fmtstr.replace(k,v,1) - if args: - mnem = "sprintf(hi->mnem, \"" + fmtstr + "\", " - mnem += ", ".join(args) - mnem += ");" - else: - mnem = "sprintf(hi->mnem, \"" + fmtstr + "\");" - - if mnem: - lines += [mnem] - - return lines - -def form_instruction_rizin(category, instruction): - inlines = [] - inlines += ["// Instruction: {0}: {1} | {2}".format(category, instruction.encoding.text, instruction.syntax)] - inlines += extract_name_rizin(instruction) - inlines += extract_fields_rizin(instruction) - inlines += extract_predicates_rizin(instruction) - inlines += extract_pf_rizin(instruction) - inlines += extend_immediates_rizin(instruction) - inlines += extract_mnemonic_rizin(instruction) - return inlines - -def const_extender_rizin(): - clines = ["// Handle constant extender"] - clines += ["hi->instruction = HEX_INS_IMMEXT;"] - clines += ["hi->op_count = 1;"] - clines += ["hi->ops[0].type = HEX_OP_TYPE_IMM;"] - clines += ["hi->ops[0].attr |= HEX_OP_CONST_EXT;"] - clines += ["hi->ops[0].op.imm = ((hi_u32 & 0x3FFF) | (((hi_u32 >> 16) & 0xFFF) << 14)) << 6;"] - clines += ["constant_extender = hi->ops[0].op.imm;"] - clines += ["sprintf(hi->mnem, \"immext(#0x%x)\", hi->ops[0].op.imm);"] - return clines - -def write_files_rizin(ins_class, ins_duplex, hex_insn_names, extendable_insn): - HEX_DISAS_FILENAME = "rizin/hexagon_disas.c" - HEX_INSN_FILENAME = "rizin/hexagon_insn.h" - HEX_ANALYSIS_FILENAME = "rizin/hexagon_analysis.c" - auto_header = ["// THIS FILE IS AUTOGENERATED - SEE IMPORTER.PY FILE", ""] - spdx = ["// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov ", "// SPDX-License-Identifier: LGPL-3.0-only", ""] - header_guard = ["#ifndef HEXAGON_INSN_H", "#define HEXAGON_INSN_H", ""] - - # FIXME: Dirty hack but ENOTIME! - ins_enum = ["HEX_INS_UNKNOWN,"] # Unknown instruction - ins_enum += ["HEX_INS_IMMEXT,"] # Constant extender - for i in hex_insn_names: - ins_enum += [i + ","] - hlines = make_C_block(ins_enum, "enum HEX_INS") - hlines[-1] = hlines[-1] + ";" # Finish the enum with semicolon - lines = auto_header + spdx + header_guard + hlines + ["", "#endif"] - with open(HEX_INSN_FILENAME, "w") as f: - for l in lines: - f.write(l + "\n") - - # At first - generate code for parsing duplexes - # ----------------------------------------------------------------------------- - lines = ["// DUPLEXES"] - inlines = [] - cat_switch = "switch ((((hi_u32 >> 29) & 0xF) << 1) | ((hi_u32 >> 13) & 1))" - dupsorted = collections.OrderedDict(sorted(ins_duplex.items())) - for k,v in dupsorted.items(): - vlines = [] - # Match by category, in hex format - case_beg = "case 0x{0:x}:".format(k) - for i in v: - # TODO: Extract common markers, rebalance to switches - mask = i.encoding.mask - val = i.encoding.value - vlines += make_C_block(form_instruction_rizin(k, i), "if ((hi_u32 & 0x{0:x}) == 0x{1:x})".format(mask, val), None, "break;") - inlines += make_C_block(vlines, case_beg, None, "break;") - inlines = make_C_block(inlines, cat_switch) - # Run duplexes only if parse bits are set - lines += make_C_block(inlines, "if (((hi_u32 >> 14) & 0x3) == 0)") - - # Now handle the non-compressed instructions - # ------------------------------------------------------------------------------- - inlines = [] - cat_switch = "switch ((hi_u32 >> 28) & 0xF)" - # At first - handle constant extender - const_case = "case 0x0:" - clines = const_extender_rizin() - inlines += make_C_block(clines, const_case, None, "break;") - # Then generate code for usual instructions - classsorted = collections.OrderedDict(sorted(ins_class.items())) - for k,v in classsorted.items(): - vlines = [] - # Match by category, in hex format - case_beg = "case 0x{0:x}:".format(k) - for i in v: - # TODO: Extract common markers, rebalance to switches - mask = i.encoding.mask & ~(0xf << 28) - val = i.encoding.value & ~(0xf << 28) - vlines += make_C_block(form_instruction_rizin(k, i), "if ((hi_u32 & 0x{0:x}) == 0x{1:x})".format(mask, val), None, "break;") - inlines += make_C_block(vlines, case_beg, None, "break;") - inlines = make_C_block(inlines, cat_switch) - lines += make_C_block(inlines, "else") # only run if non-duplex mode - - # Produce a RzAsm plugin C file finally - # --------------------------------------------------------------------------------- - includes = ["#include "] - includes += ["#include "] - includes += ["#include "] - includes += ["#include "] - includes += ["#include "] - includes += ["#include \"hexagon.h\""] - includes += ["#include \"hexagon_insn.h\""] - includes += [""] # for the sake of beauty - - # Add constantExtender definition - includes += ["extern ut32 constant_extender;"] - includes += [""] # for the sake of beauty - - # Add gcc deoptimization attribute for Rizin CI ASAN build - deoptimize_if_asan = ["#if ASAN"] - deoptimize_if_asan += ["#define NO_OPT_IF_ASAN __attribute__((optimize(0)))"] - deoptimize_if_asan += ["#else"] - deoptimize_if_asan += ["#define NO_OPT_IF_ASAN"] - deoptimize_if_asan += ["#endif"] - deoptimize_if_asan += [""] # for the sake of beauty - - # Wrap everything into one function - lines = auto_header + spdx + includes + deoptimize_if_asan + \ - make_C_block(lines, "NO_OPT_IF_ASAN int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr)", None, "return 4;") - with open(HEX_DISAS_FILENAME, "w") as f: - for l in lines: - f.write(l + "\n") - - # Generate analysis code - # --------------------------------------------------------------------------------- - - type_switch = "switch (hi->instruction)" - emulines = [] - for i in deco.inst_template_list: - ilines = [] - if i.branch: - if isinstance(i.branch.target, ImmediateTemplate): - ilines += ["// {0:s}".format(i.syntax)] - - if i.branch.type == "call": - ilines += ["op->type = RZ_ANALYSIS_OP_TYPE_CALL;"] - ilines += ["op->jump = op->addr + (st32) hi->ops[{0:d}].op.imm;".format(i.branch.target.index)] - else: - if i.branch.is_conditional: - ilines += ["op->type = RZ_ANALYSIS_OP_TYPE_CJMP;"] - else: - ilines += ["op->type = RZ_ANALYSIS_OP_TYPE_JMP;"] - ilines += ["op->jump = op->addr + (st32) hi->ops[{0:d}].op.imm;".format(i.branch.target.index)] - ilines += ["op->fail = op->addr + op->size;"] - emulines += make_C_block(ilines, "case {0:s}:".format(i.name), None, "break;") - if i.branch.type == "dealloc_return": - ilines += ["// {0:s}".format(i.syntax)] - ilines += ["op->type = RZ_ANALYSIS_OP_TYPE_RET;"]; - emulines += make_C_block(ilines, "case {0:s}:".format(i.name), None, "break;") - - emulines = make_C_block(emulines, type_switch, indent=False) - # Wrap everything into one function - lines = make_C_block(emulines, "int hexagon_analysis_instruction(HexInsn *hi, RzAnalysisOp *op)", None, "return op->size;") - - # Produce a RzAsm plugin C file finally - # --------------------------------------------------------------------------------- - includes = ["#include "] - includes += ["#include "] - includes += ["#include "] - includes += ["#include "] - includes += ["#include "] - includes += ["#include "] - includes += ["#include \"hexagon.h\""] - includes += ["#include \"hexagon_insn.h\""] - includes += [""] # for the sake of beauty - lines = auto_header + spdx + includes + lines - - with open(HEX_ANALYSIS_FILENAME, "w") as f: - for l in lines: - f.write(l + "\n") - - - # TODO: Export the sources into rizin repository - -# ------------------------------------------------------------------------------------ - -if __name__ == "__main__": - if sys.version_info < (3, 7): - print("This script needs Python version 3.7 or higher") - sys.exit() - - parser = argparse.ArgumentParser(description="Hexagon C disassembly generator") - args = parser.parse_args() - mp = ManualParser('80-n2040-36_b_hexagon_v62_prog_ref_manual.txt') - mp.go_to_instruction_set_start() - mp.find_encondings() - - hp = HeaderParser('hexagon_iset_v5.h') - hp.parse() - # So here we have objects of parsed tokens - hp.standarize_syntax(hp.duplex_inst_encodings) - hp.standarize_syntax(hp.other_inst_encodings) - inst_def_list = mp.instructions - inst_def_list.extend(hp.duplex_inst_encodings) - #inst_def_list.extend(hp.other_inst_encodings) - #print(inst_def_list) - - deco = HexagonInstructionDecoder(inst_def_list) - ins_class = {} # We pre-sort our instructions by ICLASS value - ins_duplex = {} # We pre-sort our duplex instructions by ICLASS too - for ins_tmpl in deco.inst_template_list: - hex_inst_struc = {} - hex_inst_struc["mask"] = ins_tmpl.encoding.mask - hex_inst_struc["syntax"] = ins_tmpl.syntax - ins_tmpl.name = generate_insn(ins_tmpl) - hex_insn_names += [ins_tmpl.name] # for instructions header enum - # separate parsing duplex instructions into another thing - dupbits = ins_tmpl.encoding.text[16:18] - duplex = 1 - if not dupbits == 'PP': - duplex = int(dupbits, 2) - - if not duplex == 0: - # for non-duplex instructions those are higher 4 bits - iclass = int(ins_tmpl.encoding.text[0:4], 2) - #print("{0} : {1} - {2}".format(iclass, ins_tmpl.encoding.text, ins_tmpl.syntax)) - #for tok in ins_tmpl.tokens: - # print("{0} : {1}".format(tok.s, tok.op)) - if iclass in ins_class: - ins_class[iclass] += [ins_tmpl] - else: - ins_class[iclass] = [ins_tmpl] - else: - # for duplex instructions those are high 3 bits + 13 bit - iclass = int(ins_tmpl.encoding.text[0:3] + ins_tmpl.encoding.text[18], 2) - if iclass in ins_duplex: - ins_duplex[iclass] += [ins_tmpl] - else: - ins_duplex[iclass] = [ins_tmpl] - - # ----------------------------------------------------------------------------------------------- - # Now parse the list of the instructions which are support the constant extender system - for i in deco.inst_template_list: - print(i.syntax) - extendable_insn = [] # The list of extendable instructions' names - extendable_duplex_syntax = [] - with open("const_extenders.txt") as f: - ext_ins = f.read().splitlines() - for ins_tmpl in deco.inst_template_list: - for ext_syntax in ext_ins: - normsyntax = standarize_syntax_objdump(ext_syntax.split('/', 1)[0]) - if ext_syntax.split('//')[-1].strip() == "Slot 1 duplex": - extendable_duplex_syntax += [normsyntax.strip()] - #print("{0:s} VS {1:s}".format(ins_tmpl.syntax, normsyntax)) - if ins_tmpl.syntax == normsyntax: - extendable_insn += [ins_tmpl.name] - print("{0:s} - {1:s}".format(ins_tmpl.name, ins_tmpl.syntax)) - - # ----------------------------------------------------------------------------------------------- - # TOOL SPECIFIC CODE - # Rizin specifics - write_files_rizin(ins_class, ins_duplex, hex_insn_names, extendable_insn) - print("Succesfully generated Rizin disassembly and analysis plugin") - diff --git a/optional_requirements.txt b/optional_requirements.txt new file mode 100644 index 00000000..240cf7f2 --- /dev/null +++ b/optional_requirements.txt @@ -0,0 +1 @@ +colorama~=0.4.3 \ No newline at end of file diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 00000000..4f8b146a --- /dev/null +++ b/requirements.txt @@ -0,0 +1,2 @@ +bitarray~=2.1.0 +setuptools~=45.2.0 \ No newline at end of file diff --git a/rizin/Makefile b/rizin/Makefile deleted file mode 100644 index cd2d100e..00000000 --- a/rizin/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -RZ_PLUGIN_PATH=$(shell rz -hh|grep USER_PLUGINS|awk '{print $$2}') -SO_EXT=$(shell uname|grep -q Darwin && echo dylib || echo so) - -CFLAGS?=-g -fPIC - -# RzAsm plugin -RZASM_NAME=hexagon_asm -RZASM_CFLAGS=$(CFLAGS) $(shell pkg-config --cflags rz_asm) -RZASM_LDFLAGS=$(CFLAGS) -shared $(shell pkg-config --libs rz_asm) -RZASM_OBJS=asm_hexagon.o hexagon.o hexagon_disas.o -RZASM_SRC=$(pathsubst %.o, %.c, $(RZASM_OBJS)) -RZASM_LIB=$(RZASM_NAME).$(SO_EXT) - -# RzAnalysis plugin -RZANALYSIS_NAME=hexagon_analysis -RZANALYSIS_CFLAGS=$(CFLAGS) $(shell pkg-config --cflags rz_analysis) -RZANALYSIS_LDFLAGS=$(CFLAGS) -shared $(shell pkg-config --libs rz_analysis) -RZANALYSIS_OBJS=analysis_hexagon.o hexagon.o hexagon_disas.o hexagon_analysis.o -RZANALYSIS_SRC=$(pathsubst %.o, %.c, $(RZANALYSIS_OBJS)) -RZANALYSIS_LIB=$(RZANALYSIS_NAME).$(SO_EXT) - -all: $(RZASM_LIB) $(RZANALYSIS_LIB) - -clean: - rm -f $(RZASM_LIB) $(RZANALYSIS_LIB) $(RASM_OBJS) $(RZANALYSIS_OBJS) - -$(RZASM_LIB): $(RASM_OBJS) - $(CC) $(RZASM_CFLAGS) $(RASM_LDFLAGS) $(RASM_OBJS) -o $(RASM_LIB) - -$(RZANALYSIS_LIB): $(RZANALYSIS_OBJS) - $(CC) $(RZANALYSIS_CFLAGS) $(RZANALYSIS_LDFLAGS) $(RZANALYSIS_OBJS) -o $(RZANALYSIS_LIB) - -%.o: %.c - $(CC) $(RZASM_CFLAGS) $(RZANALYSIS_CFLAGS) -c $< -o $@ - -install: - cp -f $(RZASM_NAME).$(SO_EXT) $(RZ_PLUGIN_PATH) - cp -f $(RZANALYSIS_NAME).$(SO_EXT) $(RZ_PLUGIN_PATH) - -uninstall: - rm -f $(RZ_PLUGIN_PATH)/$(RZASM_NAME).$(SO_EXT) - rm -f $(RZ_PLUGIN_PATH)/$(RZANALYSIS_NAME).$(SO_EXT) - diff --git a/rizin/analysis_hexagon.c b/rizin/analysis_hexagon.c deleted file mode 100644 index de9aeb2b..00000000 --- a/rizin/analysis_hexagon.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov -// SPDX-License-Identifier: LGPL-3.0-only - -#include -#include -#include -#include -#include -#include "hexagon.h" -#include "hexagon_insn.h" -#include "hexagon_analysis.h" - -static int hexagon_v6_op(RzAnal *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) { - HexInsn hi = {0};; - ut32 data = 0; - memset (op, 0, sizeof (RzAnalysisOp)); - data = rz_read_le32 (buf); - int size = hexagon_disasm_instruction (data, &hi, (ut32) addr); - op->size = size; - if (size <= 0) { - return size; - } - - op->addr = addr; - op->jump = op->fail = -1; - op->ptr = op->val = -1; - return hexagon_anal_instruction (&hi, op); -} - -static int set_reg_profile(RzAnalysis *analysis) { - // TODO: Add missing registers - const char *p = - "=PC pc\n" - "=SP r29\n" - "=BP r30\n" - "=LR r31\n" - "=SN r6\n" - "=ZF z\n" - "=SF s\n" - "=OF ov\n" - "=CF cy\n" - - "gpr r0 .32 0 0\n" - "gpr r1 .32 4 0\n" - "gpr r2 .32 8 0\n" - "gpr r3 .32 12 0\n" - "gpr r4 .32 16 0\n" - "gpr r5 .32 20 0\n" - "gpr r6 .32 24 0\n" - "gpr r7 .32 28 0\n" - "gpr r8 .32 32 0\n" - "gpr r9 .32 36 0\n" - "gpr r10 .32 40 0\n" - "gpr r11 .32 44 0\n" - "gpr r12 .32 48 0\n" - "gpr r13 .32 52 0\n" - "gpr r14 .32 56 0\n" - "gpr r15 .32 60 0\n" - "gpr r16 .32 64 0\n" - "gpr r17 .32 68 0\n" - "gpr r18 .32 72 0\n" - "gpr r19 .32 76 0\n" - "gpr r20 .32 80 0\n" - "gpr r21 .32 84 0\n" - "gpr r22 .32 88 0\n" - "gpr r23 .32 92 0\n" - "gpr r24 .32 96 0\n" - "gpr r25 .32 100 0\n" - "gpr r26 .32 104 0\n" - "gpr r27 .32 108 0\n" - "gpr r28 .32 112 0\n" - "gpr r29 .32 116 0\n" - "gpr r30 .32 120 0\n" - "gpr r31 .32 124 0\n" - "gpr pc .32 128 0\n" - - "gpr psw .32 132 0\n" - "gpr np .1 132.16 0\n" - "gpr ep .1 132.17 0\n" - "gpr ae .1 132.18 0\n" - "gpr id .1 132.19 0\n" - "flg cy .1 132.28 0\n" - "flg ov .1 132.29 0\n" - "flg s .1 132.30 0\n" - "flg z .1 132.31 0\n"; - - return rz_reg_set_profile_string (analysis->reg, p); -} - -RzAnalysisPlugin rz_analysis_plugin_hexagon = { - .name = "hexagon", - .desc = "Qualcomm Hexagon (QDSP6) V6", - .license = "LGPL3", - .arch = "hexagon", - .bits = 32, - .op = hexagon_v6_op, - .esil = true, - .set_reg_profile = set_reg_profile, -}; - -#ifndef RZ_PLUGIN_INCORE -RZ_API RzLibStruct rizin_plugin = { - .type = RZ_LIB_TYPE_ANAL, - .data = &rz_analysis_plugin_hexagon_v6, - .version = RZ_VERSION -}; -#endif diff --git a/rizin/cc-hexagon-32.sdb.txt b/rizin/cc-hexagon-32.sdb.txt deleted file mode 100644 index f6ea3532..00000000 --- a/rizin/cc-hexagon-32.sdb.txt +++ /dev/null @@ -1,11 +0,0 @@ -default.cc=hexagon - -hexagon=cc -cc.hexagon.arg0=r0 -cc.hexagon.arg1=r1 -cc.hexagon.arg2=r2 -cc.hexagon.arg3=r3 -cc.hexagon.arg4=r4 -cc.hexagon.arg5=r5 -cc.hexagon.argn=stack_rev -cc.hexagon.ret=r0 diff --git a/rizin/hexagon.c b/rizin/hexagon.c deleted file mode 100644 index 18eec693..00000000 --- a/rizin/hexagon.c +++ /dev/null @@ -1,245 +0,0 @@ -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov -// SPDX-License-Identifier: LGPL-3.0-only - -#include -#include -#include -#include -#include -#include -#include "hexagon.h" - -// TODO: Handle also control reg pairs -char* hex_get_cntl_reg(int opreg){ - switch (opreg) { - case HEX_REG_SA0: - return "SA0"; - case HEX_REG_LC0: - return "LC0"; - case HEX_REG_SA1: - return "SA1"; - case HEX_REG_LC1: - return "LC1"; - case HEX_REG_P: - return "P"; - case HEX_REG_M0: - return "M0"; - case HEX_REG_M1: - return "M1"; - case HEX_REG_USR: - return "USR"; - case HEX_REG_PC: - return "PC"; - case HEX_REG_UGP: - return "UGP"; - case HEX_REG_GP: - return "GP"; - case HEX_REG_CS0: - return "CS0"; - case HEX_REG_CS1: - return "CS1"; - case HEX_REG_UPCYCLELO: - return "UPCYCLELO"; - case HEX_REG_UPCYCLEHI: - return "UPCYCLEHI"; - case HEX_REG_FRAMELIMIT: - return "FRAMELIMIT"; - case HEX_REG_FRAMEKEY: - return "FRAMEKEY"; - case HEX_REG_PKTCOUNTLO: - return "PKTCOUNTLO"; - case HEX_REG_PKTCOUNTHI: - return "PKTCOUNTHI"; - case HEX_REG_UTIMERLO: - return "UTIMERLO"; - case HEX_REG_UTIMERHI: - return "UTIMERHI"; - default: - return ""; - } -} - -char* hex_get_sys_reg(int opreg) -{ - static char tmp[5]; - switch (opreg) { - case HEX_REG_SGP0: - return "SGP0"; - case HEX_REG_SGP1: - return "SGP1"; - case HEX_REG_STID: - return "STID"; - case HEX_REG_ELR: - return "ELR"; - case HEX_REG_BADVA0: - return "BADVA0"; - case HEX_REG_BADVA1: - return "BADVA1"; - case HEX_REG_SSR: - return "SSR"; - case HEX_REG_CCR: - return "CCR"; - case HEX_REG_HTID: - return "HTID"; - case HEX_REG_BADVA: - return "BADVA"; - case HEX_REG_IMASK: - return "IMASK"; - case HEX_REG_EVB: - return "EVB"; - case HEX_REG_MODECTL: - return "MODECTL"; - case HEX_REG_SYSCFG: - return "SYSCFG"; - case HEX_REG_IPEND: - return "IPEND"; - case HEX_REG_VID: - return "VID"; - case HEX_REG_IAD: - return "IAD"; - case HEX_REG_IEL: - return "IEL"; - case HEX_REG_IAHL: - return "IAHL"; - case HEX_REG_CFGBASE: - return "CFGBASE"; - case HEX_REG_DIAG: - return "DIAG"; - case HEX_REG_REV: - return "REV"; - case HEX_REG_PCYCLELO: - return "PCYCLELO"; - case HEX_REG_PCYCLEHI: - return "PCYCLEHI"; - case HEX_REG_ISDBST: - return "ISDBST"; - case HEX_REG_ISDBCFG0: - return "ISDBCFG0"; - case HEX_REG_ISDBCFG1: - return "ISDBCFG1"; - case HEX_REG_BRKPTPC0: - return "BRKPTPC0"; - case HEX_REG_BRKPTCFG0: - return "BRKPTCFG0"; - case HEX_REG_BRKPTPC1: - return "BRKPTPC1"; - case HEX_REG_BRKPTCFG1: - return "BRKPTCFG1"; - case HEX_REG_ISDBMBXIN: - return "ISDBMBXIN"; - case HEX_REG_ISDBMBXOUT: - return "ISDBMBXOUT"; - case HEX_REG_ISDBEN: - return "ISDBEN"; - case HEX_REG_ISDBGPR: - return "ISDBGPR"; - case HEX_REG_PMUCNT0: - return "PMUCNT0"; - case HEX_REG_PMUCNT1: - return "PMUCNT1"; - case HEX_REG_PMUCNT2: - return "PMUCNT2"; - case HEX_REG_PMUCNT3: - return "PMUCNT3"; - case HEX_REG_PMUEVTCFG: - return "PMUEVTCFG"; - case HEX_REG_PMUCFG: - return "PMUCFG"; - default: - sprintf(tmp, "S%d", opreg); - return tmp; - } -} - -char* hex_get_sub_reg(int opreg) -{ - switch (opreg) { - case HEX_SUB_REG_R0: - return "R0"; - case HEX_SUB_REG_R1: - return "R1"; - case HEX_SUB_REG_R2: - return "R2"; - case HEX_SUB_REG_R3: - return "R3"; - case HEX_SUB_REG_R4: - return "R4"; - case HEX_SUB_REG_R5: - return "R5"; - case HEX_SUB_REG_R6: - return "R6"; - case HEX_SUB_REG_R7: - return "R7"; - case HEX_SUB_REG_R16: - return "R16"; - case HEX_SUB_REG_R17: - return "R17"; - case HEX_SUB_REG_R18: - return "R18"; - case HEX_SUB_REG_R19: - return "R19"; - case HEX_SUB_REG_R20: - return "R20"; - case HEX_SUB_REG_R21: - return "R21"; - case HEX_SUB_REG_R22: - return "R22"; - case HEX_SUB_REG_R23: - return "R23"; - default: - return ""; - } -} - -char* hex_get_sub_regpair(int opreg) -{ - switch (opreg) { - case HEX_SUB_REGPAIR_R1_R0: - return "R1:R0"; - case HEX_SUB_REGPAIR_R3_R2: - return "R3:R2"; - case HEX_SUB_REGPAIR_R5_R4: - return "R5:R4"; - case HEX_SUB_REGPAIR_R7_R6: - return "R7:R6"; - case HEX_SUB_REGPAIR_R17_R16: - return "R17:R16"; - case HEX_SUB_REGPAIR_R19_R18: - return "R19:R18"; - case HEX_SUB_REGPAIR_R21_R20: - return "R21:R20"; - case HEX_SUB_REGPAIR_R23_R22: - return "R23:R22"; - default: - return ""; - } -} - -inline bool hex_if_duplex(uint32_t insn_word) -{ - if ((insn_word & (3 << 14)) == 0) { - return true; - } - return false; -} - -// Constant extender value -ut32 constant_extender = 1; - -void hex_op_extend(HexOp *op) -{ - if ((constant_extender != 1) && (op->type == HEX_OP_TYPE_IMM)) { - op->op.imm = ((op->op.imm) & 0x3F) | (constant_extender); - } - constant_extender = 1; -} - -void hex_op_extend_off(HexOp *op, int offset) -{ - if ((constant_extender != 1) && (op->type == HEX_OP_TYPE_IMM)) { - op->op.imm = (op->op.imm) >> offset; - hex_op_extend(op); - } -} - - diff --git a/rizin/hexagon.h b/rizin/hexagon.h deleted file mode 100644 index e5a89b0a..00000000 --- a/rizin/hexagon.h +++ /dev/null @@ -1,284 +0,0 @@ -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov -// SPDX-License-Identifier: LGPL-3.0-only - -#ifndef HEXAGON_H -#define HEXAGON_H - -// Predicates - declare the predicate state -typedef enum { - HEX_NOPRED, // no conditional execution - HEX_PRED_TRUE, // if (Pd) ... - HEX_PRED_FALSE, // if (!Pd) ... - HEX_PRED_TRUE_NEW, // if (Pd.new) ... - HEX_PRED_FALSE_NEW, // if (!Pd.new) ... -} HexPred; - -// Pre/post-fixes, different types -typedef enum { - HEX_PF_RND = 1, // :rnd - HEX_PF_CRND = 1<<1, // :crnd - HEX_PF_RAW = 1<<2, // :raw - HEX_PF_CHOP = 1<<3, // :chop - HEX_PF_SAT = 1<<4, // :sat - HEX_PF_HI = 1<<5, // :hi - HEX_PF_LO = 1<<6, // :lo - HEX_PF_LSH1 = 1<<7, // :<<1 - HEX_PF_LSH16 = 1<<8, // :<<16 - HEX_PF_RSH1 = 1<<9, // :>>1 - HEX_PF_NEG = 1<<10, // :neg - HEX_PF_POS = 1<<11, // :pos - HEX_PF_SCALE = 1<<12, // :scale, for FMA instructions - HEX_PF_DEPRECATED = 1<<15, // :deprecated -} HexPf; - -typedef enum { - HEX_OP_TYPE_IMM, - HEX_OP_TYPE_REG, - HEX_OP_TYPE_PREDICATE, - HEX_OP_TYPE_CONTROL, - HEX_OP_TYPE_SYSTEM, - HEX_OP_TYPE_OPT, // Do not really use in the C code -} HexOpType; - -// Attributes - .H/.L, const extender -typedef enum { - HEX_OP_CONST_EXT = 1 << 0, // Constant extender marker for Immediate - HEX_OP_REG_HI = 1 << 1, // Rn.H marker - HEX_OP_REG_LO = 1 << 2, // Rn.L marker - HEX_OP_REG_PAIR = 1 << 3, // Is this a register pair? -} HexOpAttr; - -typedef struct { - ut8 type; - union { - ut8 reg; // + additional Hi or Lo selector // + additional shift // + additional :brev // - ut32 imm; - ut8 pred; // predicates - P0-P3 registers - ut8 cr; // control register - ut8 sys; // system control register - } op; - ut8 attr; -} HexOp; - -typedef struct { - int instruction; - ut32 mask; - HexPred predicate; // predicate set if set - ut16 pf; // additional prefixes (bitmap) - bool duplex; // is part of duplex container? - bool compound; // is part of compound instruction? - bool last; // is last in instruction packet? - int shift; // Optional shift left is it true? - ut8 op_count; - HexOp ops[6]; - char mnem[128]; // Instruction mnemonic -} HexInsn; - -// Instruction container (currently only 2 instructions) -// Can handle duplexes -typedef struct { - bool duplex; - HexInsn ins[2]; // Or make it pointer + size? -} HexInsnCont; - -// Instruction packet (Maximum - 4 instructions) -// Can handle up to 4 instructions or 1 duplex + 2 instructions -// Can have a loop marks -typedef struct { - bool loop0; // :endloop0 marker - bool loop1; // :endloop1 marker - int cont_cnt; - HexInsnCont ins[4]; // Or make it pointer + size? -} HexInsnPkt; - -typedef enum { - HEX_INSN_CLASS_CEXT = 0, // Constant extender - HEX_INSN_CLASS_J1 = 1, // Jump - HEX_INSN_CLASS_J2 = 2, // Jump - HEX_INSN_CLASS_LD_ST = 3, // Load/Store - HEX_INSN_CLASS_LD_ST_COND_GP = 4, // Load/Store conditional or GP relative - HEX_INSN_CLASS_J3 = 5, // Jump - HEX_INSN_CLASS_CR = 6, // Control register instructions - HEX_INSN_CLASS_ALU32 = 7, // ALU32 - HEX_INSN_CLASS_XTYPE = 8, // XTYPE - HEX_INSN_CLASS_LD = 9, // Just load instructions - HEX_INSN_CLASS_ST = 10, // Just store instructions - HEX_INSN_CLASS_ALU32_1 = 11, // ALU32 - HEX_INSN_CLASS_XTYPE_1 = 12, // XTYPE again - HEX_INSN_CLASS_XTYPE_2 = 13, // XTYPE one more time - HEX_INSN_CLASS_XTYPE_3 = 14, // And again, XTYPE - HEX_INSN_CLASS_ALU32_2 = 12, // ALU32 again -} HEX_INSN_CLASS; - -typedef enum { - HEX_REG_R0 = 0, - HEX_REG_R1 = 1, - HEX_REG_R2 = 2, - HEX_REG_R3 = 3, - HEX_REG_R4 = 4, - HEX_REG_R5 = 5, - HEX_REG_R6 = 6, - HEX_REG_R7 = 7, - HEX_REG_R8 = 8, - HEX_REG_R9 = 9, - HEX_REG_R10 = 10, - HEX_REG_R11 = 11, - HEX_REG_R12 = 12, - HEX_REG_R13 = 13, - HEX_REG_R14 = 14, - HEX_REG_R15 = 15, - HEX_REG_R16 = 16, - HEX_REG_R17 = 17, - HEX_REG_R18 = 18, - HEX_REG_R19 = 19, - HEX_REG_R20 = 20, - HEX_REG_R21 = 21, - HEX_REG_R22 = 22, - HEX_REG_R23 = 23, - HEX_REG_R24 = 24, - HEX_REG_R25 = 25, - HEX_REG_R26 = 26, - HEX_REG_R27 = 27, - HEX_REG_R28 = 28, - HEX_REG_R29 = 29, - HEX_REG_R30 = 30, - HEX_REG_R31 = 31, -} HEX_REG; - -// TODO: Also add regpair values - -// Control registers -typedef enum { - // Loop registers - HEX_REG_SA0 = 0, // C0 - HEX_REG_LC0 = 1, // C1 - HEX_REG_SA1 = 2, // C2 - HEX_REG_LC1 = 3, // C3 - HEX_REG_P = 4, // C4 - 4 of 8bit registers - // C5 is reserved - // Modifier registers - HEX_REG_M0 = 6, // C6 - HEX_REG_M1 = 7, // C7 - HEX_REG_USR = 8, // C8 // User Status Register - HEX_REG_PC = 9, // C9 // Program counter - HEX_REG_UGP = 10, // C10 // User General Pointer - HEX_REG_GP = 11, // C11 // Global Pointer - // Circular Start registers - HEX_REG_CS0 = 12, // C12 - HEX_REG_CS1 = 13, // C13 - // Cycle Count registers - HEX_REG_UPCYCLELO = 14, // C14 - HEX_REG_UPCYCLEHI = 15, // C15 - HEX_REG_FRAMELIMIT = 16, // C16 // Stack Bounds register - HEX_REG_FRAMEKEY = 17, // C17 // Stack Smash register - // Packet Count registers - HEX_REG_PKTCOUNTLO = 18, // C18 - HEX_REG_PKTCOUNTHI = 19, // C19 - // C20 - C29 are reserved - // Qtimer registers - HEX_REG_UTIMERLO = 30, // C30 - HEX_REG_UTIMERHI = 31, // C31 -} HEX_CR_REG; - -// Supervisor control registers -typedef enum { - HEX_REG_SGP0 = 0, // S0 - HEX_REG_SGP1 = 1, // S1 - HEX_REG_STID = 2, // S2 - HEX_REG_ELR = 3, // S3 - HEX_REG_BADVA0 = 4, // S4 - HEX_REG_BADVA1 = 5, // S5 - HEX_REG_SSR = 6, // S6 - HEX_REG_CCR = 7, // S7 - HEX_REG_HTID = 8, // S8 - HEX_REG_BADVA = 9, // S9 - HEX_REG_IMASK = 10, // S10 - // S11 - S15 are reserved - HEX_REG_EVB = 16, // S16 - HEX_REG_MODECTL = 17, // S17 - HEX_REG_SYSCFG = 18, // S18 - // S19 is reserved - HEX_REG_IPEND = 20, // S20 - HEX_REG_VID = 21, // S21 - HEX_REG_IAD = 22, // S22 - // S23 is reserved - HEX_REG_IEL = 24, // S24 - // S25 is reserved - HEX_REG_IAHL = 26, // S26 - HEX_REG_CFGBASE = 27, // S27 - HEX_REG_DIAG = 28, // S28 - HEX_REG_REV = 29, // S29 - HEX_REG_PCYCLELO = 30, // S30 - HEX_REG_PCYCLEHI = 31, // S31 - HEX_REG_ISDBST = 32, // S32 - HEX_REG_ISDBCFG0 = 33, // S33 - HEX_REG_ISDBCFG1 = 34, // S34 - // S35 is reserved - HEX_REG_BRKPTPC0 = 36, // S36 - HEX_REG_BRKPTCFG0 = 37, // S37 - HEX_REG_BRKPTPC1 = 38, // S38 - HEX_REG_BRKPTCFG1 = 39, // S39 - HEX_REG_ISDBMBXIN = 40, // S40 - HEX_REG_ISDBMBXOUT = 41, // S41 - HEX_REG_ISDBEN = 42, // S42 - HEX_REG_ISDBGPR = 43, // S43 - // S44 - S47 are reserved - HEX_REG_PMUCNT0 = 48, // S48 - HEX_REG_PMUCNT1 = 49, // S49 - HEX_REG_PMUCNT2 = 50, // S50 - HEX_REG_PMUCNT3 = 51, // S51 - HEX_REG_PMUEVTCFG = 52, // S52 - HEX_REG_PMUCFG = 53, // S53 - // S54 - S63 are reserved -} HEX_SYSCR_REG; - -// Here are the register field values for subinstructions - -typedef enum { - HEX_SUB_REG_R0 = 0, // 0b0000 - HEX_SUB_REG_R1 = 1, // 0b0001 - HEX_SUB_REG_R2 = 2, // 0b0010 - HEX_SUB_REG_R3 = 3, // 0b0011 - HEX_SUB_REG_R4 = 4, // 0b0100 - HEX_SUB_REG_R5 = 5, // 0b0101 - HEX_SUB_REG_R6 = 6, // 0b0110 - HEX_SUB_REG_R7 = 7, // 0b0111 - HEX_SUB_REG_R16 = 8, // 0b1000 - HEX_SUB_REG_R17 = 9, // 0b1001 - HEX_SUB_REG_R18 = 10, // 0b1010 - HEX_SUB_REG_R19 = 11, // 0b1011 - HEX_SUB_REG_R20 = 12, // 0b1100 - HEX_SUB_REG_R21 = 13, // 0b1101 - HEX_SUB_REG_R22 = 14, // 0b1110 - HEX_SUB_REG_R23 = 15, // 0b1111 -} HEX_SUB_REG; - - -typedef enum { - HEX_SUB_REGPAIR_R1_R0 = 0, // 0b000 - HEX_SUB_REGPAIR_R3_R2 = 1, // 0b001 - HEX_SUB_REGPAIR_R5_R4 = 2, // 0b010 - HEX_SUB_REGPAIR_R7_R6 = 3, // 0b011 - HEX_SUB_REGPAIR_R17_R16 = 4, // 0b100 - HEX_SUB_REGPAIR_R19_R18 = 5, // 0b101 - HEX_SUB_REGPAIR_R21_R20 = 6, // 0b110 - HEX_SUB_REGPAIR_R23_R22 = 7, // 0b111 -} HEX_SUB_REGPAIR; - - -#define BIT_MASK(len) (BIT(len)-1) -#define BF_MASK(start, len) (BIT_MASK(len)<<(start)) -#define BF_PREP(x, start, len) (((x)&BIT_MASK(len))<<(start)) -#define BF_GET(y, start, len) (((y)>>(start)) & BIT_MASK(len)) -#define BF_GETB(y, start, end) (BF_GET((y), (start), (end) - (start) + 1) - -char* hex_get_cntl_reg(int opreg); -char* hex_get_sys_reg(int opreg); -char* hex_get_sub_reg(int opreg); -char* hex_get_sub_regpair(int opreg); -bool hex_if_duplex(ut32 insn_word); -void hex_op_extend(HexOp *op); -void hex_op_extend_off(HexOp *op, int offset); -int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr); - -#endif diff --git a/rizin/hexagon_analysis.c b/rizin/hexagon_analysis.c deleted file mode 100644 index 9d1748f6..00000000 --- a/rizin/hexagon_analysis.c +++ /dev/null @@ -1,1817 +0,0 @@ -// THIS FILE IS AUTOGENERATED - SEE IMPORTER.PY FILE - -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov -// SPDX-License-Identifier: LGPL-3.0-only - -#include -#include -#include -#include -#include -#include -#include "hexagon.h" -#include "hexagon_insn.h" - -int hexagon_analysis_instruction(HexInsn *hi, RzAnalysisOp *op) { - switch (hi->instruction) { - case HEX_INS_CALL__R22_2: { - // call #r22:2 - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - op->jump = op->addr + (st32) hi->ops[0].op.imm; - break; - } - case HEX_INS_IF__PU__CALL__R15_2: { - // if (Pu) call #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - break; - } - case HEX_INS_IF__NOT_PU_CALL__R15_2: { - // if !Pu call #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, #-1) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, #-1) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = tstbit (Rs, #0) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, #-1) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, #-1) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = tstbit (Rs, #0) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, #-1) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, #-1) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = tstbit (Rs, #0) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, #-1) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, #-1) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = tstbit (Rs, #0) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, #U5) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, #U5) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gtu (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gtu (Rs, #U5) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gtu (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gtu (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, #-1) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, #-1) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = tstbit (Rs, #0) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, #-1) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, #-1) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = tstbit (Rs, #0) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, #-1) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, #-1) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = tstbit (Rs, #0) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, #-1) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, #-1) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = tstbit (Rs, #0) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, #U5) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS___U5____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS___U5____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, #U5) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gtu (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gtu (Rs, #U5) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gtu (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gtu (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, Rt) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, Rt) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS__RT____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS__RT____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS__RT____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, Rt) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS__RT____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, Rt) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gtu (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gtu (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gtu (Rs, Rt) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gtu (Rs, Rt) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gtu (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gtu (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gtu (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gtu (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_JUMP__R22_2: { - // jump #r22:2 - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->jump = op->addr + (st32) hi->ops[0].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__PU__JUMP_NT__R15_2: { - // if (Pu) jump:nt #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__PU__JUMP_T__R15_2: { - // if (Pu) jump:t #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__NOT_PU_JUMP_NT__R15_2: { - // if !Pu jump:nt #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__NOT_PU_JUMP_T__R15_2: { - // if !Pu jump:t #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__PU_NEW__JUMP_NT__R15_2: { - // if (Pu.new) jump:nt #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__PU_NEW__JUMP_T__R15_2: { - // if (Pu.new) jump:t #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__NOT_PU_NEW_JUMP_NT__R15_2: { - // if !Pu.new jump:nt #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__NOT_PU_NEW_JUMP_T__R15_2: { - // if !Pu.new jump:t #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS__NOT____0__JUMP_NT__R13_2: { - // if (Rs != #0) jump:nt #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS__NOT____0__JUMP_T__R13_2: { - // if (Rs != #0) jump:t #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS_GT_EQ___0__JUMP_NT__R13_2: { - // if (Rs> = #0) jump:nt #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS_GT_EQ___0__JUMP_T__R13_2: { - // if (Rs> = #0) jump:t #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS__EQ___0__JUMP_NT__R13_2: { - // if (Rs == #0) jump:nt #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS__EQ___0__JUMP_T__R13_2: { - // if (Rs == #0) jump:t #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS_LT_EQ___0__JUMP_NT__R13_2: { - // if (Rs< = #0) jump:nt #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS_LT_EQ___0__JUMP_T__R13_2: { - // if (Rs< = #0) jump:t #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_RD____U6___JUMP__R9_2: { - // Rd = #U6 ; jump #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_RD___RS___JUMP__R9_2: { - // Rd = Rs ; jump #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_DEALLOC_RETURN: { - // dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__PS_NEW__DEALLOC_RETURN_NT: { - // if (Ps.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__PS__DEALLOC_RETURN: { - // if (Ps) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__PS_NEW__DEALLOC_RETURN_T: { - // if (Ps.new) dealloc_return:t - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__NOT_PS_NEW_DEALLOC_RETURN_NT: { - // if !Ps.new dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__NOT_PS_DEALLOC_RETURN: { - // if !Ps dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__NOT_PS_NEW_DEALLOC_RETURN_T: { - // if !Ps.new dealloc_return:t - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW__RT___JUMP_NT__R9_2: { - // if (cmp.eq (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW__RT___JUMP_T__R9_2: { - // if (cmp.eq (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW__RT___JUMP_NT__R9_2: { - // if (!cmp.eq (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW__RT___JUMP_T__R9_2: { - // if (!cmp.eq (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW__RT___JUMP_NT__R9_2: { - // if (cmp.gt (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW__RT___JUMP_T__R9_2: { - // if (cmp.gt (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW__RT___JUMP_NT__R9_2: { - // if (!cmp.gt (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW__RT___JUMP_T__R9_2: { - // if (!cmp.gt (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__NS_NEW__RT___JUMP_NT__R9_2: { - // if (cmp.gtu (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__NS_NEW__RT___JUMP_T__R9_2: { - // if (cmp.gtu (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__NS_NEW__RT___JUMP_NT__R9_2: { - // if (!cmp.gtu (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__NS_NEW__RT___JUMP_T__R9_2: { - // if (!cmp.gtu (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__RT__NS_NEW___JUMP_NT__R9_2: { - // if (cmp.gt (Rt, Ns.new)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__RT__NS_NEW___JUMP_T__R9_2: { - // if (cmp.gt (Rt, Ns.new)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__RT__NS_NEW___JUMP_NT__R9_2: { - // if (!cmp.gt (Rt, Ns.new)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__RT__NS_NEW___JUMP_T__R9_2: { - // if (!cmp.gt (Rt, Ns.new)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__RT__NS_NEW___JUMP_NT__R9_2: { - // if (cmp.gtu (Rt, Ns.new)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__RT__NS_NEW___JUMP_T__R9_2: { - // if (cmp.gtu (Rt, Ns.new)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__RT__NS_NEW___JUMP_NT__R9_2: { - // if (!cmp.gtu (Rt, Ns.new)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__RT__NS_NEW___JUMP_T__R9_2: { - // if (!cmp.gtu (Rt, Ns.new)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW___U5___JUMP_NT__R9_2: { - // if (cmp.eq (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW___U5___JUMP_T__R9_2: { - // if (cmp.eq (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW___U5___JUMP_NT__R9_2: { - // if (!cmp.eq (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW___U5___JUMP_T__R9_2: { - // if (!cmp.eq (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW___U5___JUMP_NT__R9_2: { - // if (cmp.gt (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW___U5___JUMP_T__R9_2: { - // if (cmp.gt (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW___U5___JUMP_NT__R9_2: { - // if (!cmp.gt (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW___U5___JUMP_T__R9_2: { - // if (!cmp.gt (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__NS_NEW___U5___JUMP_NT__R9_2: { - // if (cmp.gtu (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__NS_NEW___U5___JUMP_T__R9_2: { - // if (cmp.gtu (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__NS_NEW___U5___JUMP_NT__R9_2: { - // if (!cmp.gtu (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__NS_NEW___U5___JUMP_T__R9_2: { - // if (!cmp.gtu (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__TSTBIT__NS_NEW___0___JUMP_NT__R9_2: { - // if (tstbit (Ns.new, #0)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__TSTBIT__NS_NEW___0___JUMP_T__R9_2: { - // if (tstbit (Ns.new, #0)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_TSTBIT__NS_NEW___0___JUMP_NT__R9_2: { - // if (!tstbit (Ns.new, #0)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_TSTBIT__NS_NEW___0___JUMP_T__R9_2: { - // if (!tstbit (Ns.new, #0)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW____1___JUMP_NT__R9_2: { - // if (cmp.eq (Ns.new, #-1)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW____1___JUMP_T__R9_2: { - // if (cmp.eq (Ns.new, #-1)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW____1___JUMP_NT__R9_2: { - // if (!cmp.eq (Ns.new, #-1)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW____1___JUMP_T__R9_2: { - // if (!cmp.eq (Ns.new, #-1)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW____1___JUMP_NT__R9_2: { - // if (cmp.gt (Ns.new, #-1)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW____1___JUMP_T__R9_2: { - // if (cmp.gt (Ns.new, #-1)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW____1___JUMP_NT__R9_2: { - // if (!cmp.gt (Ns.new, #-1)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW____1___JUMP_T__R9_2: { - // if (!cmp.gt (Ns.new, #-1)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32) hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_DUPLEX_RD_____1___DEALLOC_RETURN: { - // Rd = #-1 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD_____1___IF___NOT__P0__DEALLOC_RETURN: { - // Rd = #-1 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD_____1___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = #-1 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD_____1___IF__P0__DEALLOC_RETURN: { - // Rd = #-1 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD_____1___IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = #-1 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___DEALLOC_RETURN: { - // Rd = #u6 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___IF___NOT__P0__DEALLOC_RETURN: { - // Rd = #u6 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = #u6 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___IF__P0__DEALLOC_RETURN: { - // Rd = #u6 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = #u6 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___DEALLOC_RETURN: { - // Rd = Rs ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___IF___NOT__P0__DEALLOC_RETURN: { - // Rd = Rs ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = Rs ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___IF__P0__DEALLOC_RETURN: { - // Rd = Rs ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = Rs ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____DEALLOC_RETURN: { - // Rd = add (Rs, #-1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = add (Rs, #-1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Rs, #-1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0__DEALLOC_RETURN: { - // Rd = add (Rs, #-1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Rs, #-1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____DEALLOC_RETURN: { - // Rd = add (Rs, #1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = add (Rs, #1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Rs, #1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0__DEALLOC_RETURN: { - // Rd = add (Rs, #1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Rs, #1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____DEALLOC_RETURN: { - // Rd = add (Sp, #u6:2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = add (Sp, #u6:2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Sp, #u6:2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0__DEALLOC_RETURN: { - // Rd = add (Sp, #u6:2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Sp, #u6:2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____DEALLOC_RETURN: { - // Rd = and (Rs, #1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = and (Rs, #1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = and (Rs, #1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0__DEALLOC_RETURN: { - // Rd = and (Rs, #1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = and (Rs, #1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____DEALLOC_RETURN: { - // Rd = and (Rs, #255) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = and (Rs, #255) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = and (Rs, #255) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0__DEALLOC_RETURN: { - // Rd = and (Rs, #255) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = and (Rs, #255) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____DEALLOC_RETURN: { - // Rd = memb (Rs + #u3:0) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memb (Rs + #u3:0) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memb (Rs + #u3:0) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0__DEALLOC_RETURN: { - // Rd = memb (Rs + #u3:0) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memb (Rs + #u3:0) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____DEALLOC_RETURN: { - // Rd = memh (Rs + #u3:1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memh (Rs + #u3:1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memh (Rs + #u3:1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0__DEALLOC_RETURN: { - // Rd = memh (Rs + #u3:1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memh (Rs + #u3:1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____DEALLOC_RETURN: { - // Rd = memub (Rs + #u4:0) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memub (Rs + #u4:0) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memub (Rs + #u4:0) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0__DEALLOC_RETURN: { - // Rd = memub (Rs + #u4:0) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memub (Rs + #u4:0) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____DEALLOC_RETURN: { - // Rd = memuh (Rs + #u3:1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memuh (Rs + #u3:1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memuh (Rs + #u3:1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__DEALLOC_RETURN: { - // Rd = memuh (Rs + #u3:1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memuh (Rs + #u3:1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOC_RETURN: { - // Rd = memw (Rs + #u4:2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memw (Rs + #u4:2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memw (Rs + #u4:2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__DEALLOC_RETURN: { - // Rd = memw (Rs + #u4:2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memw (Rs + #u4:2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOC_RETURN: { - // Rd = memw (Sp + #u5:2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memw (Sp + #u5:2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memw (Sp + #u5:2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__DEALLOC_RETURN: { - // Rd = memw (Sp + #u5:2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memw (Sp + #u5:2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOC_RETURN: { - // Rd = sxtb (Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = sxtb (Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = sxtb (Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__DEALLOC_RETURN: { - // Rd = sxtb (Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = sxtb (Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOC_RETURN: { - // Rd = sxth (Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = sxth (Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = sxth (Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__DEALLOC_RETURN: { - // Rd = sxth (Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = sxth (Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOC_RETURN: { - // Rd = zxth (Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = zxth (Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = zxth (Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__DEALLOC_RETURN: { - // Rd = zxth (Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = zxth (Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOC_RETURN: { - // Rdd = combine (#0, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#0, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#0, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#0, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#0, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOC_RETURN: { - // Rdd = combine (#0, Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#0, Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#0, Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#0, Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#0, Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOC_RETURN: { - // Rdd = combine (#1, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#1, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#1, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#1, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#1, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOC_RETURN: { - // Rdd = combine (#2, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#2, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#2, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#2, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#2, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOC_RETURN: { - // Rdd = combine (#3, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#3, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#3, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#3, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#3, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOC_RETURN: { - // Rdd = combine (Rs, #0) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (Rs, #0) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (Rs, #0) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (Rs, #0) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (Rs, #0) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOC_RETURN: { - // Rdd = memd (Sp + #u5:3) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = memd (Sp + #u5:3) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = memd (Sp + #u5:3) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__DEALLOC_RETURN: { - // Rdd = memd (Sp + #u5:3) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = memd (Sp + #u5:3) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____DEALLOC_RETURN: { - // Rx = add (Rs, Rx) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__DEALLOC_RETURN: { - // Rx = add (Rs, Rx) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rs, Rx) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__DEALLOC_RETURN: { - // Rx = add (Rs, Rx) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rs, Rx) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____DEALLOC_RETURN: { - // Rx = add (Rx, #s7) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__DEALLOC_RETURN: { - // Rx = add (Rx, #s7) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rx, #s7) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__DEALLOC_RETURN: { - // Rx = add (Rx, #s7) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rx, #s7) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____DEALLOC_RETURN: { - // Rx = add (Rx, Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rx = add (Rx, Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rx, Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__DEALLOC_RETURN: { - // Rx = add (Rx, Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rx, Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___DEALLOC_RETURN: { - // if (! p0) Rd = #0 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN: { - // if (! p0) Rd = #0 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // if (! p0) Rd = #0 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0__DEALLOC_RETURN: { - // if (! p0) Rd = #0 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT: { - // if (! p0) Rd = #0 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___DEALLOC_RETURN: { - // if (! p0.new) Rd = #0 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN: { - // if (! p0.new) Rd = #0 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // if (! p0.new) Rd = #0 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN: { - // if (! p0.new) Rd = #0 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT: { - // if (! p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___DEALLOC_RETURN: { - // if (p0) Rd = #0 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN: { - // if (p0) Rd = #0 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // if (p0) Rd = #0 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0__DEALLOC_RETURN: { - // if (p0) Rd = #0 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT: { - // if (p0) Rd = #0 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___DEALLOC_RETURN: { - // if (p0.new) Rd = #0 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN: { - // if (p0.new) Rd = #0 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // if (p0.new) Rd = #0 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN: { - // if (p0.new) Rd = #0 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT: { - // if (p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____DEALLOC_RETURN: { - // p0 = cmp.eq (Rs, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0__DEALLOC_RETURN: { - // p0 = cmp.eq (Rs, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // p0 = cmp.eq (Rs, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0__DEALLOC_RETURN: { - // p0 = cmp.eq (Rs, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // p0 = cmp.eq (Rs, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - } - return op->size; -} diff --git a/rizin/hexagon_disas.c b/rizin/hexagon_disas.c deleted file mode 100644 index 11e554b0..00000000 --- a/rizin/hexagon_disas.c +++ /dev/null @@ -1,45395 +0,0 @@ -// THIS FILE IS AUTOGENERATED - SEE IMPORTER.PY FILE - -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov -// SPDX-License-Identifier: LGPL-3.0-only - -#include -#include -#include -#include -#include -#include "hexagon.h" -#include "hexagon_insn.h" - -extern ut32 constant_extender; - -int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) { - // DUPLEXES - if (((hi_u32 >> 14) & 0x3) == 0) { - switch ((((hi_u32 >> 29) & 0xF) << 1) | ((hi_u32 >> 13) & 1)) { - case 0x0: { - if ((hi_u32 & 0xf000f000) == 0x10001000) { - // Instruction: 0: 0001IIIIuuuueeee0001iiiissssdddd | Re = memub (Ru + #U4:0) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMUB__RS____U4_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f000) == 0x1000) { - // Instruction: 0: 0000IIIIuuuueeee0001iiiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMUB__RS____U4_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f000) == 0x0) { - // Instruction: 0: 0000IIIIuuuueeee0000iiiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMW__RS____U4_2_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - break; - } - case 0x1: { - if ((hi_u32 & 0xf000ffc4) == 0x10003f40) { - // Instruction: 1: 0001iiiissssdddd0011111101---0-- | Rd = memub (Rs + #u4:0) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x10003f00) { - // Instruction: 1: 0001iiiissssdddd0011111100---0-- | Rd = memub (Rs + #u4:0) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003f45) { - // Instruction: 1: 0001iiiissssdddd0011111101---101 | Rd = memub (Rs + #u4:0) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003fc5) { - // Instruction: 1: 0001iiiissssdddd0011111111---101 | Rd = memub (Rs + #u4:0) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003f47) { - // Instruction: 1: 0001iiiissssdddd0011111101---111 | Rd = memub (Rs + #u4:0) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003fc7) { - // Instruction: 1: 0001iiiissssdddd0011111111---111 | Rd = memub (Rs + #u4:0) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003f44) { - // Instruction: 1: 0001iiiissssdddd0011111101---100 | Rd = memub (Rs + #u4:0) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003fc4) { - // Instruction: 1: 0001iiiissssdddd0011111111---100 | Rd = memub (Rs + #u4:0) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003f46) { - // Instruction: 1: 0001iiiissssdddd0011111101---110 | Rd = memub (Rs + #u4:0) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003fc6) { - // Instruction: 1: 0001iiiissssdddd0011111111---110 | Rd = memub (Rs + #u4:0) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x10003fc0) { - // Instruction: 1: 0001iiiissssdddd0011111111---0-- | Rd = memub (Rs + #u4:0) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x3f40) { - // Instruction: 1: 0000iiiissssdddd0011111101---0-- | Rd = memw (Rs + #u4:2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x3f00) { - // Instruction: 1: 0000iiiissssdddd0011111100---0-- | Rd = memw (Rs + #u4:2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3f45) { - // Instruction: 1: 0000iiiissssdddd0011111101---101 | Rd = memw (Rs + #u4:2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3fc5) { - // Instruction: 1: 0000iiiissssdddd0011111111---101 | Rd = memw (Rs + #u4:2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3f47) { - // Instruction: 1: 0000iiiissssdddd0011111101---111 | Rd = memw (Rs + #u4:2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3fc7) { - // Instruction: 1: 0000iiiissssdddd0011111111---111 | Rd = memw (Rs + #u4:2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3f44) { - // Instruction: 1: 0000iiiissssdddd0011111101---100 | Rd = memw (Rs + #u4:2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3fc4) { - // Instruction: 1: 0000iiiissssdddd0011111111---100 | Rd = memw (Rs + #u4:2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3f46) { - // Instruction: 1: 0000iiiissssdddd0011111101---110 | Rd = memw (Rs + #u4:2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3fc6) { - // Instruction: 1: 0000iiiissssdddd0011111111---110 | Rd = memw (Rs + #u4:2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x3fc0) { - // Instruction: 1: 0000iiiissssdddd0011111111---0-- | Rd = memw (Rs + #u4:2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0x10003c00) { - // Instruction: 1: 0001IIIIsssseeee0011110iiiiidddd | Re = memub (Rs + #U4:0) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RS____U4_0____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0x10003e00) { - // Instruction: 1: 0001IIIIsssseeee00111110iiiiiddd | Re = memub (Rs + #U4:0) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RS____U4_0____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x10003000) { - // Instruction: 1: 0001IIIIuuuueeee00110iiissssdddd | Re = memub (Ru + #U4:0) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x10002000) { - // Instruction: 1: 0001IIIIuuuueeee00100iiissssdddd | Re = memub (Ru + #U4:0) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x10002800) { - // Instruction: 1: 0001IIIIuuuueeee00101iiissssdddd | Re = memub (Ru + #U4:0) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMUH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0x3c00) { - // Instruction: 1: 0000IIIIsssseeee0011110iiiiidddd | Re = memw (Rs + #U4:2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RS____U4_2____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0x3e00) { - // Instruction: 1: 0000IIIIsssseeee00111110iiiiiddd | Re = memw (Rs + #U4:2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RS____U4_2____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x3000) { - // Instruction: 1: 0000IIIIuuuueeee00110iiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x2000) { - // Instruction: 1: 0000IIIIuuuueeee00100iiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x2800) { - // Instruction: 1: 0000IIIIuuuueeee00101iiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMUH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - break; - } - case 0x2: { - if ((hi_u32 & 0xf800ffc4) == 0x30001f40) { - // Instruction: 2: 00110iiissssdddd0001111101---0-- | Rd = memb (Rs + #u3:0) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x30001f00) { - // Instruction: 2: 00110iiissssdddd0001111100---0-- | Rd = memb (Rs + #u3:0) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001f45) { - // Instruction: 2: 00110iiissssdddd0001111101---101 | Rd = memb (Rs + #u3:0) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001fc5) { - // Instruction: 2: 00110iiissssdddd0001111111---101 | Rd = memb (Rs + #u3:0) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001f47) { - // Instruction: 2: 00110iiissssdddd0001111101---111 | Rd = memb (Rs + #u3:0) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001fc7) { - // Instruction: 2: 00110iiissssdddd0001111111---111 | Rd = memb (Rs + #u3:0) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001f44) { - // Instruction: 2: 00110iiissssdddd0001111101---100 | Rd = memb (Rs + #u3:0) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001fc4) { - // Instruction: 2: 00110iiissssdddd0001111111---100 | Rd = memb (Rs + #u3:0) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001f46) { - // Instruction: 2: 00110iiissssdddd0001111101---110 | Rd = memb (Rs + #u3:0) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001fc6) { - // Instruction: 2: 00110iiissssdddd0001111111---110 | Rd = memb (Rs + #u3:0) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x30001fc0) { - // Instruction: 2: 00110iiissssdddd0001111111---0-- | Rd = memb (Rs + #u3:0) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x20001f40) { - // Instruction: 2: 00100iiissssdddd0001111101---0-- | Rd = memh (Rs + #u3:1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x20001f00) { - // Instruction: 2: 00100iiissssdddd0001111100---0-- | Rd = memh (Rs + #u3:1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001f45) { - // Instruction: 2: 00100iiissssdddd0001111101---101 | Rd = memh (Rs + #u3:1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001fc5) { - // Instruction: 2: 00100iiissssdddd0001111111---101 | Rd = memh (Rs + #u3:1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001f47) { - // Instruction: 2: 00100iiissssdddd0001111101---111 | Rd = memh (Rs + #u3:1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001fc7) { - // Instruction: 2: 00100iiissssdddd0001111111---111 | Rd = memh (Rs + #u3:1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001f44) { - // Instruction: 2: 00100iiissssdddd0001111101---100 | Rd = memh (Rs + #u3:1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001fc4) { - // Instruction: 2: 00100iiissssdddd0001111111---100 | Rd = memh (Rs + #u3:1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001f46) { - // Instruction: 2: 00100iiissssdddd0001111101---110 | Rd = memh (Rs + #u3:1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001fc6) { - // Instruction: 2: 00100iiissssdddd0001111111---110 | Rd = memh (Rs + #u3:1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x20001fc0) { - // Instruction: 2: 00100iiissssdddd0001111111---0-- | Rd = memh (Rs + #u3:1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x28001f40) { - // Instruction: 2: 00101iiissssdddd0001111101---0-- | Rd = memuh (Rs + #u3:1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x28001f00) { - // Instruction: 2: 00101iiissssdddd0001111100---0-- | Rd = memuh (Rs + #u3:1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001f45) { - // Instruction: 2: 00101iiissssdddd0001111101---101 | Rd = memuh (Rs + #u3:1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001fc5) { - // Instruction: 2: 00101iiissssdddd0001111111---101 | Rd = memuh (Rs + #u3:1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001f47) { - // Instruction: 2: 00101iiissssdddd0001111101---111 | Rd = memuh (Rs + #u3:1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001fc7) { - // Instruction: 2: 00101iiissssdddd0001111111---111 | Rd = memuh (Rs + #u3:1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001f44) { - // Instruction: 2: 00101iiissssdddd0001111101---100 | Rd = memuh (Rs + #u3:1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001fc4) { - // Instruction: 2: 00101iiissssdddd0001111111---100 | Rd = memuh (Rs + #u3:1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001f46) { - // Instruction: 2: 00101iiissssdddd0001111101---110 | Rd = memuh (Rs + #u3:1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001fc6) { - // Instruction: 2: 00101iiissssdddd0001111111---110 | Rd = memuh (Rs + #u3:1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x28001fc0) { - // Instruction: 2: 00101iiissssdddd0001111111---0-- | Rd = memuh (Rs + #u3:1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc4) == 0x3c001f40) { - // Instruction: 2: 0011110iiiiidddd0001111101---0-- | Rd = memw (Sp + #u5:2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc4) == 0x3c001f00) { - // Instruction: 2: 0011110iiiiidddd0001111100---0-- | Rd = memw (Sp + #u5:2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001f45) { - // Instruction: 2: 0011110iiiiidddd0001111101---101 | Rd = memw (Sp + #u5:2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001fc5) { - // Instruction: 2: 0011110iiiiidddd0001111111---101 | Rd = memw (Sp + #u5:2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001f47) { - // Instruction: 2: 0011110iiiiidddd0001111101---111 | Rd = memw (Sp + #u5:2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001fc7) { - // Instruction: 2: 0011110iiiiidddd0001111111---111 | Rd = memw (Sp + #u5:2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001f44) { - // Instruction: 2: 0011110iiiiidddd0001111101---100 | Rd = memw (Sp + #u5:2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001fc4) { - // Instruction: 2: 0011110iiiiidddd0001111111---100 | Rd = memw (Sp + #u5:2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001f46) { - // Instruction: 2: 0011110iiiiidddd0001111101---110 | Rd = memw (Sp + #u5:2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001fc6) { - // Instruction: 2: 0011110iiiiidddd0001111111---110 | Rd = memw (Sp + #u5:2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc4) == 0x3c001fc0) { - // Instruction: 2: 0011110iiiiidddd0001111111---0-- | Rd = memw (Sp + #u5:2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x3e001f40) { - // Instruction: 2: 00111110iiiiiddd0001111101---0-- | Rdd = memd (Sp + #u5:3) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x3e001f00) { - // Instruction: 2: 00111110iiiiiddd0001111100---0-- | Rdd = memd (Sp + #u5:3) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001f45) { - // Instruction: 2: 00111110iiiiiddd0001111101---101 | Rdd = memd (Sp + #u5:3) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001fc5) { - // Instruction: 2: 00111110iiiiiddd0001111111---101 | Rdd = memd (Sp + #u5:3) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001f47) { - // Instruction: 2: 00111110iiiiiddd0001111101---111 | Rdd = memd (Sp + #u5:3) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001fc7) { - // Instruction: 2: 00111110iiiiiddd0001111111---111 | Rdd = memd (Sp + #u5:3) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001f44) { - // Instruction: 2: 00111110iiiiiddd0001111101---100 | Rdd = memd (Sp + #u5:3) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001fc4) { - // Instruction: 2: 00111110iiiiiddd0001111111---100 | Rdd = memd (Sp + #u5:3) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001f46) { - // Instruction: 2: 00111110iiiiiddd0001111101---110 | Rdd = memd (Sp + #u5:3) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001fc6) { - // Instruction: 2: 00111110iiiiiddd0001111111---110 | Rdd = memd (Sp + #u5:3) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x3e001fc0) { - // Instruction: 2: 00111110iiiiiddd0001111111---0-- | Rdd = memd (Sp + #u5:3) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x30001c00) { - // Instruction: 2: 00110IIIsssseeee0001110iiiiidddd | Re = memb (Rs + #U3:0) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMB__RS____U3_0____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x30001e00) { - // Instruction: 2: 00110IIIsssseeee00011110iiiiiddd | Re = memb (Rs + #U3:0) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMB__RS____U3_0____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x30001000) { - // Instruction: 2: 00110IIIuuuueeee00010iiissssdddd | Re = memb (Ru + #U3:0) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMB__RU____U3_0____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x20001c00) { - // Instruction: 2: 00100IIIsssseeee0001110iiiiidddd | Re = memh (Rs + #U3:1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RS____U3_1____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20001e00) { - // Instruction: 2: 00100IIIsssseeee00011110iiiiiddd | Re = memh (Rs + #U3:1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RS____U3_1____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x20001000) { - // Instruction: 2: 00100IIIuuuueeee00010iiissssdddd | Re = memh (Ru + #U3:1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RU____U3_1____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x20000000) { - // Instruction: 2: 00100IIIuuuueeee00000iiissssdddd | Re = memh (Ru + #U3:1) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RU____U3_1____RD___MEMH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x20000800) { - // Instruction: 2: 00100IIIuuuueeee00001iiissssdddd | Re = memh (Ru + #U3:1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RU____U3_1____RD___MEMUH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x28001c00) { - // Instruction: 2: 00101IIIsssseeee0001110iiiiidddd | Re = memuh (Rs + #U3:1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUH__RS____U3_1____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x28001e00) { - // Instruction: 2: 00101IIIsssseeee00011110iiiiiddd | Re = memuh (Rs + #U3:1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUH__RS____U3_1____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x28001000) { - // Instruction: 2: 00101IIIuuuueeee00010iiissssdddd | Re = memuh (Ru + #U3:1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUH__RU____U3_1____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x28000800) { - // Instruction: 2: 00101IIIuuuueeee00001iiissssdddd | Re = memuh (Ru + #U3:1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUH__RU____U3_1____RD___MEMUH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0x3c001c00) { - // Instruction: 2: 0011110IIIIIeeee0001110iiiiidddd | Re = memw (Sp + #U5:2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__SP____U5_2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0x3c001e00) { - // Instruction: 2: 0011110IIIIIeeee00011110iiiiiddd | Re = memw (Sp + #U5:2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__SP____U5_2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x3e001e00) { - // Instruction: 2: 00111110IIIIIeee00011110iiiiiddd | Ree = memd (Sp + #U5:3) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___MEMD__SP____U5_3____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xffc4ffc7) == 0x3f001fc5) { - // Instruction: 2: 0011111100---0--0001111111---101 | deallocframe ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___IF___NOT__P0__JUMPR_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; if (! p0) jumpr Lr"); - break; - } - if ((hi_u32 & 0xffc4ffc7) == 0x3f001fc7) { - // Instruction: 2: 0011111100---0--0001111111---111 | deallocframe ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; if (! p0.new) jumpr:nt Lr"); - break; - } - if ((hi_u32 & 0xffc4ffc7) == 0x3f001fc4) { - // Instruction: 2: 0011111100---0--0001111111---100 | deallocframe ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___IF__P0__JUMPR_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; if (p0) jumpr Lr"); - break; - } - if ((hi_u32 & 0xffc4ffc7) == 0x3f001fc6) { - // Instruction: 2: 0011111100---0--0001111111---110 | deallocframe ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; if (p0.new) jumpr:nt Lr"); - break; - } - if ((hi_u32 & 0xffc4ffc4) == 0x3f001fc0) { - // Instruction: 2: 0011111100---0--0001111111---0-- | deallocframe ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___JUMPR_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; jumpr Lr"); - break; - } - break; - } - case 0x3: { - if ((hi_u32 & 0xfc00ff00) == 0x28003900) { - // Instruction: 3: 001010IIIIIIdddd00111001ssss--ii | Rd = #U6 ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD____U6___P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003800) { - // Instruction: 3: 001010iiiiiidddd00111000ssssxxxx | Rd = #u6 ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD____U6___RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003800) { - // Instruction: 3: 001010iiiiiidddd00111000ssssxxxx | Rd = #u6 ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD____U6___RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003800) { - // Instruction: 3: 00110000uuuudddd00111000ssssxxxx | Rd = Ru ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___RU___RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003800) { - // Instruction: 3: 00110000uuuudddd00111000ssssxxxx | Rd = Ru ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___RU___RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003900) { - // Instruction: 3: 00110000uuuudddd00111001ssss--ii | Rd = Ru ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___RU___P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003800) { - // Instruction: 3: 00110011uuuudddd00111000ssssxxxx | Rd = add (Ru, #-1) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003800) { - // Instruction: 3: 00110011uuuudddd00111000ssssxxxx | Rd = add (Ru, #-1) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003900) { - // Instruction: 3: 00110011uuuudddd00111001ssss--ii | Rd = add (Ru, #-1) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003800) { - // Instruction: 3: 00110001uuuudddd00111000ssssxxxx | Rd = add (Ru, #1) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003800) { - // Instruction: 3: 00110001uuuudddd00111000ssssxxxx | Rd = add (Ru, #1) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003900) { - // Instruction: 3: 00110001uuuudddd00111001ssss--ii | Rd = add (Ru, #1) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003900) { - // Instruction: 3: 001011IIIIIIdddd00111001ssss--ii | Rd = add (Sp, #U6:2) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003800) { - // Instruction: 3: 001011iiiiiidddd00111000ssssxxxx | Rd = add (Sp, #u6:2) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003800) { - // Instruction: 3: 001011iiiiiidddd00111000ssssxxxx | Rd = add (Sp, #u6:2) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003800) { - // Instruction: 3: 00110010uuuudddd00111000ssssxxxx | Rd = and (Ru, #1) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003800) { - // Instruction: 3: 00110010uuuudddd00111000ssssxxxx | Rd = and (Ru, #1) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003900) { - // Instruction: 3: 00110010uuuudddd00111001ssss--ii | Rd = and (Ru, #1) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x37003800) { - // Instruction: 3: 00110111uuuudddd00111000ssssxxxx | Rd = and (Ru, #255) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x37003800) { - // Instruction: 3: 00110111uuuudddd00111000ssssxxxx | Rd = and (Ru, #255) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x37003900) { - // Instruction: 3: 00110111uuuudddd00111001ssss--ii | Rd = and (Ru, #255) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003800) { - // Instruction: 3: 00110101uuuudddd00111000ssssxxxx | Rd = sxtb (Ru) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003800) { - // Instruction: 3: 00110101uuuudddd00111000ssssxxxx | Rd = sxtb (Ru) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003900) { - // Instruction: 3: 00110101uuuudddd00111001ssss--ii | Rd = sxtb (Ru) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003800) { - // Instruction: 3: 00110100uuuudddd00111000ssssxxxx | Rd = sxth (Ru) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003800) { - // Instruction: 3: 00110100uuuudddd00111000ssssxxxx | Rd = sxth (Ru) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003900) { - // Instruction: 3: 00110100uuuudddd00111001ssss--ii | Rd = sxth (Ru) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003800) { - // Instruction: 3: 00110110uuuudddd00111000ssssxxxx | Rd = zxth (Ru) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003800) { - // Instruction: 3: 00110110uuuudddd00111000ssssxxxx | Rd = zxth (Ru) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003900) { - // Instruction: 3: 00110110uuuudddd00111001ssss--ii | Rd = zxth (Ru) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40fe40) == 0x3a003a00) { - // Instruction: 3: 0011101--0--eeee0011101--0--dddd | Re = #-1 ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD_____1; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fd18) == 0x3a003c00) { - // Instruction: 3: 0011101--0--eeee001111-0-ii00ddd | Re = #-1 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fd08) == 0x3a003d00) { - // Instruction: 3: 0011101--0--eeee001111-1ssss0ddd | Re = #-1 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fd18) == 0x3a003c08) { - // Instruction: 3: 0011101--0--eeee001111-0-ii01ddd | Re = #-1 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fd18) == 0x3a003c10) { - // Instruction: 3: 0011101--0--eeee001111-0-ii10ddd | Re = #-1 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fd18) == 0x3a003c18) { - // Instruction: 3: 0011101--0--eeee001111-0-ii11ddd | Re = #-1 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fd08) == 0x3a003d08) { - // Instruction: 3: 0011101--0--eeee001111-1ssss1ddd | Re = #-1 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fe70) == 0x3a003a70) { - // Instruction: 3: 0011101--0--eeee0011101--111dddd | Re = #-1 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE_____1___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fe70) == 0x3a003a50) { - // Instruction: 3: 0011101--0--eeee0011101--101dddd | Re = #-1 ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE_____1___IF___NOT__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fe70) == 0x3a003a60) { - // Instruction: 3: 0011101--0--eeee0011101--110dddd | Re = #-1 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE_____1___IF__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fe70) == 0x3a003a40) { - // Instruction: 3: 0011101--0--eeee0011101--100dddd | Re = #-1 ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE_____1___IF__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe40) == 0x28003a00) { - // Instruction: 3: 001010IIIIIIeeee0011101--0--dddd | Re = #U6 ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fc00) == 0x28002800) { - // Instruction: 3: 001010IIIIIIeeee001010iiiiiidddd | Re = #U6 ; Rd = #u6 - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD____U6; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3f0) >> 4); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = 0x%x", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003300) { - // Instruction: 3: 001010IIIIIIeeee00110011ssssdddd | Re = #U6 ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003100) { - // Instruction: 3: 001010IIIIIIeeee00110001ssssdddd | Re = #U6 ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fc00) == 0x28002c00) { - // Instruction: 3: 001010IIIIIIeeee001011iiiiiidddd | Re = #U6 ; Rd = add (Sp, #u6:2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___ADD__SP___U6_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (Sp, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003200) { - // Instruction: 3: 001010IIIIIIeeee00110010ssssdddd | Re = #U6 ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003700) { - // Instruction: 3: 001010IIIIIIeeee00110111ssssdddd | Re = #U6 ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x28003c00) { - // Instruction: 3: 001010IIIIIIeeee001111-0-ii00ddd | Re = #U6 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd08) == 0x28003d00) { - // Instruction: 3: 001010IIIIIIeeee001111-1ssss0ddd | Re = #U6 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x28003c08) { - // Instruction: 3: 001010IIIIIIeeee001111-0-ii01ddd | Re = #U6 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x28003c10) { - // Instruction: 3: 001010IIIIIIeeee001111-0-ii10ddd | Re = #U6 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x28003c18) { - // Instruction: 3: 001010IIIIIIeeee001111-0-ii11ddd | Re = #U6 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd08) == 0x28003d08) { - // Instruction: 3: 001010IIIIIIeeee001111-1ssss1ddd | Re = #U6 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x28003a70) { - // Instruction: 3: 001010IIIIIIeeee0011101--111dddd | Re = #U6 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE____U6___IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x28003a50) { - // Instruction: 3: 001010IIIIIIeeee0011101--101dddd | Re = #U6 ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE____U6___IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x28003a60) { - // Instruction: 3: 001010IIIIIIeeee0011101--110dddd | Re = #U6 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE____U6___IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x28003a40) { - // Instruction: 3: 001010IIIIIIeeee0011101--100dddd | Re = #U6 ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE____U6___IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003000) { - // Instruction: 3: 001010iiiiiieeee00110000ssssdddd | Re = #u6 ; Rd = Rs - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___RS; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003500) { - // Instruction: 3: 001010iiiiiieeee00110101ssssdddd | Re = #u6 ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003400) { - // Instruction: 3: 001010iiiiiieeee00110100ssssdddd | Re = #u6 ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003600) { - // Instruction: 3: 001010iiiiiieeee00110110ssssdddd | Re = #u6 ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x30003a00) { - // Instruction: 3: 00110000sssseeee0011101--0--dddd | Re = Rs ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___RS___RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x30003c00) { - // Instruction: 3: 00110000sssseeee001111-0-ii00ddd | Re = Rs ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x30003c08) { - // Instruction: 3: 00110000sssseeee001111-0-ii01ddd | Re = Rs ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x30003c10) { - // Instruction: 3: 00110000sssseeee001111-0-ii10ddd | Re = Rs ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x30003c18) { - // Instruction: 3: 00110000sssseeee001111-0-ii11ddd | Re = Rs ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x30003a70) { - // Instruction: 3: 00110000sssseeee0011101--111dddd | Re = Rs ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___RS___IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x30003a50) { - // Instruction: 3: 00110000sssseeee0011101--101dddd | Re = Rs ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___RS___IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x30003a60) { - // Instruction: 3: 00110000sssseeee0011101--110dddd | Re = Rs ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___RS___IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x30003a40) { - // Instruction: 3: 00110000sssseeee0011101--100dddd | Re = Rs ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___RS___IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003000) { - // Instruction: 3: 00110000uuuueeee00110000ssssdddd | Re = Ru ; Rd = Rs - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___RS; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003300) { - // Instruction: 3: 00110000uuuueeee00110011ssssdddd | Re = Ru ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003100) { - // Instruction: 3: 00110000uuuueeee00110001ssssdddd | Re = Ru ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003200) { - // Instruction: 3: 00110000uuuueeee00110010ssssdddd | Re = Ru ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003700) { - // Instruction: 3: 00110000uuuueeee00110111ssssdddd | Re = Ru ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003500) { - // Instruction: 3: 00110000uuuueeee00110101ssssdddd | Re = Ru ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003400) { - // Instruction: 3: 00110000uuuueeee00110100ssssdddd | Re = Ru ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003600) { - // Instruction: 3: 00110000uuuueeee00110110ssssdddd | Re = Ru ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x30003d00) { - // Instruction: 3: 00110000uuuueeee001111-1ssss0ddd | Re = Ru ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x30003d08) { - // Instruction: 3: 00110000uuuueeee001111-1ssss1ddd | Re = Ru ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x33003a00) { - // Instruction: 3: 00110011sssseeee0011101--0--dddd | Re = add (Rs, #-1) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x33003c00) { - // Instruction: 3: 00110011sssseeee001111-0-ii00ddd | Re = add (Rs, #-1) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x33003c08) { - // Instruction: 3: 00110011sssseeee001111-0-ii01ddd | Re = add (Rs, #-1) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x33003c10) { - // Instruction: 3: 00110011sssseeee001111-0-ii10ddd | Re = add (Rs, #-1) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x33003c18) { - // Instruction: 3: 00110011sssseeee001111-0-ii11ddd | Re = add (Rs, #-1) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x33003a70) { - // Instruction: 3: 00110011sssseeee0011101--111dddd | Re = add (Rs, #-1) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x33003a50) { - // Instruction: 3: 00110011sssseeee0011101--101dddd | Re = add (Rs, #-1) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x33003a60) { - // Instruction: 3: 00110011sssseeee0011101--110dddd | Re = add (Rs, #-1) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x33003a40) { - // Instruction: 3: 00110011sssseeee0011101--100dddd | Re = add (Rs, #-1) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x31003a00) { - // Instruction: 3: 00110001sssseeee0011101--0--dddd | Re = add (Rs, #1) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x31003c00) { - // Instruction: 3: 00110001sssseeee001111-0-ii00ddd | Re = add (Rs, #1) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x31003c08) { - // Instruction: 3: 00110001sssseeee001111-0-ii01ddd | Re = add (Rs, #1) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x31003c10) { - // Instruction: 3: 00110001sssseeee001111-0-ii10ddd | Re = add (Rs, #1) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x31003c18) { - // Instruction: 3: 00110001sssseeee001111-0-ii11ddd | Re = add (Rs, #1) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x31003a70) { - // Instruction: 3: 00110001sssseeee0011101--111dddd | Re = add (Rs, #1) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x31003a50) { - // Instruction: 3: 00110001sssseeee0011101--101dddd | Re = add (Rs, #1) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x31003a60) { - // Instruction: 3: 00110001sssseeee0011101--110dddd | Re = add (Rs, #1) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x31003a40) { - // Instruction: 3: 00110001sssseeee0011101--100dddd | Re = add (Rs, #1) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003300) { - // Instruction: 3: 00110011uuuueeee00110011ssssdddd | Re = add (Ru, #-1) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003700) { - // Instruction: 3: 00110011uuuueeee00110111ssssdddd | Re = add (Ru, #-1) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003500) { - // Instruction: 3: 00110011uuuueeee00110101ssssdddd | Re = add (Ru, #-1) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003400) { - // Instruction: 3: 00110011uuuueeee00110100ssssdddd | Re = add (Ru, #-1) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003600) { - // Instruction: 3: 00110011uuuueeee00110110ssssdddd | Re = add (Ru, #-1) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x33003d00) { - // Instruction: 3: 00110011uuuueeee001111-1ssss0ddd | Re = add (Ru, #-1) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x33003d08) { - // Instruction: 3: 00110011uuuueeee001111-1ssss1ddd | Re = add (Ru, #-1) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003300) { - // Instruction: 3: 00110001uuuueeee00110011ssssdddd | Re = add (Ru, #1) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003100) { - // Instruction: 3: 00110001uuuueeee00110001ssssdddd | Re = add (Ru, #1) ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003200) { - // Instruction: 3: 00110001uuuueeee00110010ssssdddd | Re = add (Ru, #1) ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003700) { - // Instruction: 3: 00110001uuuueeee00110111ssssdddd | Re = add (Ru, #1) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003500) { - // Instruction: 3: 00110001uuuueeee00110101ssssdddd | Re = add (Ru, #1) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003400) { - // Instruction: 3: 00110001uuuueeee00110100ssssdddd | Re = add (Ru, #1) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003600) { - // Instruction: 3: 00110001uuuueeee00110110ssssdddd | Re = add (Ru, #1) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x31003d00) { - // Instruction: 3: 00110001uuuueeee001111-1ssss0ddd | Re = add (Ru, #1) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x31003d08) { - // Instruction: 3: 00110001uuuueeee001111-1ssss1ddd | Re = add (Ru, #1) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe40) == 0x2c003a00) { - // Instruction: 3: 001011IIIIIIeeee0011101--0--dddd | Re = add (Sp, #U6:2) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003300) { - // Instruction: 3: 001011IIIIIIeeee00110011ssssdddd | Re = add (Sp, #U6:2) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003100) { - // Instruction: 3: 001011IIIIIIeeee00110001ssssdddd | Re = add (Sp, #U6:2) ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fc00) == 0x2c002c00) { - // Instruction: 3: 001011IIIIIIeeee001011iiiiiidddd | Re = add (Sp, #U6:2) ; Rd = add (Sp, #u6:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__SP___U6_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (Sp, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003200) { - // Instruction: 3: 001011IIIIIIeeee00110010ssssdddd | Re = add (Sp, #U6:2) ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003700) { - // Instruction: 3: 001011IIIIIIeeee00110111ssssdddd | Re = add (Sp, #U6:2) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x2c003c00) { - // Instruction: 3: 001011IIIIIIeeee001111-0-ii00ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd08) == 0x2c003d00) { - // Instruction: 3: 001011IIIIIIeeee001111-1ssss0ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x2c003c08) { - // Instruction: 3: 001011IIIIIIeeee001111-0-ii01ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x2c003c10) { - // Instruction: 3: 001011IIIIIIeeee001111-0-ii10ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x2c003c18) { - // Instruction: 3: 001011IIIIIIeeee001111-0-ii11ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd08) == 0x2c003d08) { - // Instruction: 3: 001011IIIIIIeeee001111-1ssss1ddd | Re = add (Sp, #U6:2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x2c003a70) { - // Instruction: 3: 001011IIIIIIeeee0011101--111dddd | Re = add (Sp, #U6:2) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x2c003a50) { - // Instruction: 3: 001011IIIIIIeeee0011101--101dddd | Re = add (Sp, #U6:2) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x2c003a60) { - // Instruction: 3: 001011IIIIIIeeee0011101--110dddd | Re = add (Sp, #U6:2) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x2c003a40) { - // Instruction: 3: 001011IIIIIIeeee0011101--100dddd | Re = add (Sp, #U6:2) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003000) { - // Instruction: 3: 001011iiiiiieeee00110000ssssdddd | Re = add (Sp, #u6:2) ; Rd = Rs - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___RS; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003500) { - // Instruction: 3: 001011iiiiiieeee00110101ssssdddd | Re = add (Sp, #u6:2) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003400) { - // Instruction: 3: 001011iiiiiieeee00110100ssssdddd | Re = add (Sp, #u6:2) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003600) { - // Instruction: 3: 001011iiiiiieeee00110110ssssdddd | Re = add (Sp, #u6:2) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x32003a00) { - // Instruction: 3: 00110010sssseeee0011101--0--dddd | Re = and (Rs, #1) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x32003c00) { - // Instruction: 3: 00110010sssseeee001111-0-ii00ddd | Re = and (Rs, #1) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x32003c08) { - // Instruction: 3: 00110010sssseeee001111-0-ii01ddd | Re = and (Rs, #1) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x32003c10) { - // Instruction: 3: 00110010sssseeee001111-0-ii10ddd | Re = and (Rs, #1) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x32003c18) { - // Instruction: 3: 00110010sssseeee001111-0-ii11ddd | Re = and (Rs, #1) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x32003a70) { - // Instruction: 3: 00110010sssseeee0011101--111dddd | Re = and (Rs, #1) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x32003a50) { - // Instruction: 3: 00110010sssseeee0011101--101dddd | Re = and (Rs, #1) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x32003a60) { - // Instruction: 3: 00110010sssseeee0011101--110dddd | Re = and (Rs, #1) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x32003a40) { - // Instruction: 3: 00110010sssseeee0011101--100dddd | Re = and (Rs, #1) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x37003a00) { - // Instruction: 3: 00110111sssseeee0011101--0--dddd | Re = and (Rs, #255) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x37003c00) { - // Instruction: 3: 00110111sssseeee001111-0-ii00ddd | Re = and (Rs, #255) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x37003c08) { - // Instruction: 3: 00110111sssseeee001111-0-ii01ddd | Re = and (Rs, #255) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x37003c10) { - // Instruction: 3: 00110111sssseeee001111-0-ii10ddd | Re = and (Rs, #255) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x37003c18) { - // Instruction: 3: 00110111sssseeee001111-0-ii11ddd | Re = and (Rs, #255) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x37003a70) { - // Instruction: 3: 00110111sssseeee0011101--111dddd | Re = and (Rs, #255) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x37003a50) { - // Instruction: 3: 00110111sssseeee0011101--101dddd | Re = and (Rs, #255) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x37003a60) { - // Instruction: 3: 00110111sssseeee0011101--110dddd | Re = and (Rs, #255) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x37003a40) { - // Instruction: 3: 00110111sssseeee0011101--100dddd | Re = and (Rs, #255) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003300) { - // Instruction: 3: 00110010uuuueeee00110011ssssdddd | Re = and (Ru, #1) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003200) { - // Instruction: 3: 00110010uuuueeee00110010ssssdddd | Re = and (Ru, #1) ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003700) { - // Instruction: 3: 00110010uuuueeee00110111ssssdddd | Re = and (Ru, #1) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003500) { - // Instruction: 3: 00110010uuuueeee00110101ssssdddd | Re = and (Ru, #1) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003400) { - // Instruction: 3: 00110010uuuueeee00110100ssssdddd | Re = and (Ru, #1) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003600) { - // Instruction: 3: 00110010uuuueeee00110110ssssdddd | Re = and (Ru, #1) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x32003d00) { - // Instruction: 3: 00110010uuuueeee001111-1ssss0ddd | Re = and (Ru, #1) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x32003d08) { - // Instruction: 3: 00110010uuuueeee001111-1ssss1ddd | Re = and (Ru, #1) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x37003700) { - // Instruction: 3: 00110111uuuueeee00110111ssssdddd | Re = and (Ru, #255) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x37003d00) { - // Instruction: 3: 00110111uuuueeee001111-1ssss0ddd | Re = and (Ru, #255) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x37003d08) { - // Instruction: 3: 00110111uuuueeee001111-1ssss1ddd | Re = and (Ru, #255) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x35003a00) { - // Instruction: 3: 00110101sssseeee0011101--0--dddd | Re = sxtb (Rs) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x35003c00) { - // Instruction: 3: 00110101sssseeee001111-0-ii00ddd | Re = sxtb (Rs) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x35003c08) { - // Instruction: 3: 00110101sssseeee001111-0-ii01ddd | Re = sxtb (Rs) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x35003c10) { - // Instruction: 3: 00110101sssseeee001111-0-ii10ddd | Re = sxtb (Rs) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x35003c18) { - // Instruction: 3: 00110101sssseeee001111-0-ii11ddd | Re = sxtb (Rs) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x35003a70) { - // Instruction: 3: 00110101sssseeee0011101--111dddd | Re = sxtb (Rs) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x35003a50) { - // Instruction: 3: 00110101sssseeee0011101--101dddd | Re = sxtb (Rs) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x35003a60) { - // Instruction: 3: 00110101sssseeee0011101--110dddd | Re = sxtb (Rs) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x35003a40) { - // Instruction: 3: 00110101sssseeee0011101--100dddd | Re = sxtb (Rs) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003700) { - // Instruction: 3: 00110101uuuueeee00110111ssssdddd | Re = sxtb (Ru) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003500) { - // Instruction: 3: 00110101uuuueeee00110101ssssdddd | Re = sxtb (Ru) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003600) { - // Instruction: 3: 00110101uuuueeee00110110ssssdddd | Re = sxtb (Ru) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x35003d00) { - // Instruction: 3: 00110101uuuueeee001111-1ssss0ddd | Re = sxtb (Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x35003d08) { - // Instruction: 3: 00110101uuuueeee001111-1ssss1ddd | Re = sxtb (Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x34003a00) { - // Instruction: 3: 00110100sssseeee0011101--0--dddd | Re = sxth (Rs) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x34003c00) { - // Instruction: 3: 00110100sssseeee001111-0-ii00ddd | Re = sxth (Rs) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x34003c08) { - // Instruction: 3: 00110100sssseeee001111-0-ii01ddd | Re = sxth (Rs) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x34003c10) { - // Instruction: 3: 00110100sssseeee001111-0-ii10ddd | Re = sxth (Rs) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x34003c18) { - // Instruction: 3: 00110100sssseeee001111-0-ii11ddd | Re = sxth (Rs) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x34003a70) { - // Instruction: 3: 00110100sssseeee0011101--111dddd | Re = sxth (Rs) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x34003a50) { - // Instruction: 3: 00110100sssseeee0011101--101dddd | Re = sxth (Rs) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x34003a60) { - // Instruction: 3: 00110100sssseeee0011101--110dddd | Re = sxth (Rs) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x34003a40) { - // Instruction: 3: 00110100sssseeee0011101--100dddd | Re = sxth (Rs) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003700) { - // Instruction: 3: 00110100uuuueeee00110111ssssdddd | Re = sxth (Ru) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003500) { - // Instruction: 3: 00110100uuuueeee00110101ssssdddd | Re = sxth (Ru) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003400) { - // Instruction: 3: 00110100uuuueeee00110100ssssdddd | Re = sxth (Ru) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003600) { - // Instruction: 3: 00110100uuuueeee00110110ssssdddd | Re = sxth (Ru) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x34003d00) { - // Instruction: 3: 00110100uuuueeee001111-1ssss0ddd | Re = sxth (Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x34003d08) { - // Instruction: 3: 00110100uuuueeee001111-1ssss1ddd | Re = sxth (Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x36003a00) { - // Instruction: 3: 00110110sssseeee0011101--0--dddd | Re = zxth (Rs) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x36003c00) { - // Instruction: 3: 00110110sssseeee001111-0-ii00ddd | Re = zxth (Rs) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x36003c08) { - // Instruction: 3: 00110110sssseeee001111-0-ii01ddd | Re = zxth (Rs) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x36003c10) { - // Instruction: 3: 00110110sssseeee001111-0-ii10ddd | Re = zxth (Rs) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x36003c18) { - // Instruction: 3: 00110110sssseeee001111-0-ii11ddd | Re = zxth (Rs) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x36003a70) { - // Instruction: 3: 00110110sssseeee0011101--111dddd | Re = zxth (Rs) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x36003a50) { - // Instruction: 3: 00110110sssseeee0011101--101dddd | Re = zxth (Rs) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x36003a60) { - // Instruction: 3: 00110110sssseeee0011101--110dddd | Re = zxth (Rs) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x36003a40) { - // Instruction: 3: 00110110sssseeee0011101--100dddd | Re = zxth (Rs) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003700) { - // Instruction: 3: 00110110uuuueeee00110111ssssdddd | Re = zxth (Ru) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003600) { - // Instruction: 3: 00110110uuuueeee00110110ssssdddd | Re = zxth (Ru) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x36003d00) { - // Instruction: 3: 00110110uuuueeee001111-1ssss0ddd | Re = zxth (Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x36003d08) { - // Instruction: 3: 00110110uuuueeee001111-1ssss1ddd | Re = zxth (Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c003c00) { - // Instruction: 3: 001111-0-II00eee001111-0-ii00ddd | Ree = combine (#0, #U2) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#0, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c003d00) { - // Instruction: 3: 001111-0-II00eee001111-1ssss0ddd | Ree = combine (#0, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c003c08) { - // Instruction: 3: 001111-0-II00eee001111-0-ii01ddd | Ree = combine (#0, #U2) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#1, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c003c10) { - // Instruction: 3: 001111-0-II00eee001111-0-ii10ddd | Ree = combine (#0, #U2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c003c18) { - // Instruction: 3: 001111-0-II00eee001111-0-ii11ddd | Ree = combine (#0, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c003d08) { - // Instruction: 3: 001111-0-II00eee001111-1ssss1ddd | Ree = combine (#0, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fd08) == 0x3d003d00) { - // Instruction: 3: 001111-1uuuu0eee001111-1ssss0ddd | Ree = combine (#0, Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fd08) == 0x3d003d08) { - // Instruction: 3: 001111-1uuuu0eee001111-1ssss1ddd | Ree = combine (#0, Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c083d00) { - // Instruction: 3: 001111-0-II01eee001111-1ssss0ddd | Ree = combine (#1, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c083c08) { - // Instruction: 3: 001111-0-II01eee001111-0-ii01ddd | Ree = combine (#1, #U2) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (#1, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c083c10) { - // Instruction: 3: 001111-0-II01eee001111-0-ii10ddd | Ree = combine (#1, #U2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c083c18) { - // Instruction: 3: 001111-0-II01eee001111-0-ii11ddd | Ree = combine (#1, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c083d08) { - // Instruction: 3: 001111-0-II01eee001111-1ssss1ddd | Ree = combine (#1, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c103d00) { - // Instruction: 3: 001111-0-II10eee001111-1ssss0ddd | Ree = combine (#2, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c103c10) { - // Instruction: 3: 001111-0-II10eee001111-0-ii10ddd | Ree = combine (#2, #U2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c103c18) { - // Instruction: 3: 001111-0-II10eee001111-0-ii11ddd | Ree = combine (#2, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c103d08) { - // Instruction: 3: 001111-0-II10eee001111-1ssss1ddd | Ree = combine (#2, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c183d00) { - // Instruction: 3: 001111-0-II11eee001111-1ssss0ddd | Ree = combine (#3, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c183c18) { - // Instruction: 3: 001111-0-II11eee001111-0-ii11ddd | Ree = combine (#3, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c183d08) { - // Instruction: 3: 001111-0-II11eee001111-1ssss1ddd | Ree = combine (#3, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fd08) == 0x3d083d08) { - // Instruction: 3: 001111-1uuuu1eee001111-1ssss1ddd | Ree = combine (Ru, #0) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x38003a00) { - // Instruction: 3: 00111000ssssxxxx0011101--0--dddd | Rx = add (Rs, Rx) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c00) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii00ddd | Rx = add (Rs, Rx) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c08) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii01ddd | Rx = add (Rs, Rx) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c10) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii10ddd | Rx = add (Rs, Rx) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c18) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii11ddd | Rx = add (Rs, Rx) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a70) { - // Instruction: 3: 00111000ssssxxxx0011101--111dddd | Rx = add (Rs, Rx) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a50) { - // Instruction: 3: 00111000ssssxxxx0011101--101dddd | Rx = add (Rs, Rx) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a60) { - // Instruction: 3: 00111000ssssxxxx0011101--110dddd | Rx = add (Rs, Rx) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a40) { - // Instruction: 3: 00111000ssssxxxx0011101--100dddd | Rx = add (Rs, Rx) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x38003d00) { - // Instruction: 3: 00111000uuuuxxxx001111-1ssss0ddd | Rx = add (Ru, Rx) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x38003d08) { - // Instruction: 3: 00111000uuuuxxxx001111-1ssss1ddd | Rx = add (Ru, Rx) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003900) { - // Instruction: 3: 00111000uuuuxxxx00111001ssss--ii | Rx = add (Ru, Rx) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe40) == 0x20003a00) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--0--dddd | Rx = add (Rx, #S7) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800fc00) == 0x20002800) { - // Instruction: 3: 00100IIIIIIIxxxx001010iiiiiidddd | Rx = add (Rx, #S7) ; Rd = #u6 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD____U6; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3f0) >> 4); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = 0x%x", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003300) { - // Instruction: 3: 00100IIIIIIIxxxx00110011ssssdddd | Rx = add (Rx, #S7) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003100) { - // Instruction: 3: 00100IIIIIIIxxxx00110001ssssdddd | Rx = add (Rx, #S7) ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fc00) == 0x20002c00) { - // Instruction: 3: 00100IIIIIIIxxxx001011iiiiiidddd | Rx = add (Rx, #S7) ; Rd = add (Sp, #u6:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ADD__SP___U6_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = add (Sp, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003200) { - // Instruction: 3: 00100IIIIIIIxxxx00110010ssssdddd | Rx = add (Rx, #S7) ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003700) { - // Instruction: 3: 00100IIIIIIIxxxx00110111ssssdddd | Rx = add (Rx, #S7) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fd18) == 0x20003c00) { - // Instruction: 3: 00100IIIIIIIxxxx001111-0-ii00ddd | Rx = add (Rx, #S7) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fd08) == 0x20003d00) { - // Instruction: 3: 00100IIIIIIIxxxx001111-1ssss0ddd | Rx = add (Rx, #S7) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fd18) == 0x20003c08) { - // Instruction: 3: 00100IIIIIIIxxxx001111-0-ii01ddd | Rx = add (Rx, #S7) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fd18) == 0x20003c10) { - // Instruction: 3: 00100IIIIIIIxxxx001111-0-ii10ddd | Rx = add (Rx, #S7) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fd18) == 0x20003c18) { - // Instruction: 3: 00100IIIIIIIxxxx001111-0-ii11ddd | Rx = add (Rx, #S7) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fd08) == 0x20003d08) { - // Instruction: 3: 00100IIIIIIIxxxx001111-1ssss1ddd | Rx = add (Rx, #S7) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe70) == 0x20003a70) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--111dddd | Rx = add (Rx, #S7) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe70) == 0x20003a50) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--101dddd | Rx = add (Rx, #S7) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe70) == 0x20003a60) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--110dddd | Rx = add (Rx, #S7) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe70) == 0x20003a40) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--100dddd | Rx = add (Rx, #S7) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003900) { - // Instruction: 3: 00100IIIIIIIxxxx00111001ssss--ii | Rx = add (Rx, #S7) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003000) { - // Instruction: 3: 00100iiiiiiixxxx00110000ssssdddd | Rx = add (Rx, #s7) ; Rd = Rs - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___RS; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003500) { - // Instruction: 3: 00100iiiiiiixxxx00110101ssssdddd | Rx = add (Rx, #s7) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003400) { - // Instruction: 3: 00100iiiiiiixxxx00110100ssssdddd | Rx = add (Rx, #s7) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003600) { - // Instruction: 3: 00100iiiiiiixxxx00110110ssssdddd | Rx = add (Rx, #s7) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x38003a00) { - // Instruction: 3: 00111000ssssxxxx0011101--0--dddd | Rx = add (Rx, Rs) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c00) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii00ddd | Rx = add (Rx, Rs) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c08) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii01ddd | Rx = add (Rx, Rs) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c10) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii10ddd | Rx = add (Rx, Rs) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c18) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii11ddd | Rx = add (Rx, Rs) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a70) { - // Instruction: 3: 00111000ssssxxxx0011101--111dddd | Rx = add (Rx, Rs) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a50) { - // Instruction: 3: 00111000ssssxxxx0011101--101dddd | Rx = add (Rx, Rs) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a60) { - // Instruction: 3: 00111000ssssxxxx0011101--110dddd | Rx = add (Rx, Rs) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a40) { - // Instruction: 3: 00111000ssssxxxx0011101--100dddd | Rx = add (Rx, Rs) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x38003d00) { - // Instruction: 3: 00111000uuuuxxxx001111-1ssss0ddd | Rx = add (Rx, Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x38003d08) { - // Instruction: 3: 00111000uuuuxxxx001111-1ssss1ddd | Rx = add (Rx, Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003900) { - // Instruction: 3: 00111000uuuuxxxx00111001ssss--ii | Rx = add (Rx, Ru) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003800) { - // Instruction: 3: 00111000uuuuyyyy00111000ssssxxxx | Ry = add (Ru, Ry) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RU__RY____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Ry) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003800) { - // Instruction: 3: 00111000uuuuyyyy00111000ssssxxxx | Ry = add (Ru, Ry) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RU__RY____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Ry) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800f800) == 0x20002000) { - // Instruction: 3: 00100IIIIIIIyyyy00100iiiiiiixxxx | Ry = add (Ry, #S7) ; Rx = add (Rx, #s7) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY___S7____RX___ADD__RX___S7_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7f0) >> 4); - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %d) ; %s = add (Rx, %d)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003800) { - // Instruction: 3: 00100iiiiiiiyyyy00111000ssssxxxx | Ry = add (Ry, #s7) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY___S7____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %d) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003800) { - // Instruction: 3: 00100iiiiiiiyyyy00111000ssssxxxx | Ry = add (Ry, #s7) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY___S7____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %d) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003800) { - // Instruction: 3: 00111000uuuuyyyy00111000ssssxxxx | Ry = add (Ry, Ru) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY__RU____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %s) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003800) { - // Instruction: 3: 00111000uuuuyyyy00111000ssssxxxx | Ry = add (Ry, Ru) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY__RU____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %s) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a703c00) { - // Instruction: 3: 0011101--111eeee001111-0-ii00ddd | if (! p0) Re = #0 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a703d00) { - // Instruction: 3: 0011101--111eeee001111-1ssss0ddd | if (! p0) Re = #0 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a703c08) { - // Instruction: 3: 0011101--111eeee001111-0-ii01ddd | if (! p0) Re = #0 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a703c10) { - // Instruction: 3: 0011101--111eeee001111-0-ii10ddd | if (! p0) Re = #0 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a703c18) { - // Instruction: 3: 0011101--111eeee001111-0-ii11ddd | if (! p0) Re = #0 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a703d08) { - // Instruction: 3: 0011101--111eeee001111-1ssss1ddd | if (! p0) Re = #0 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a703a70) { - // Instruction: 3: 0011101--111eeee0011101--111dddd | if (! p0) Re = #0 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a503c00) { - // Instruction: 3: 0011101--101eeee001111-0-ii00ddd | if (! p0.new) Re = #0 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a503d00) { - // Instruction: 3: 0011101--101eeee001111-1ssss0ddd | if (! p0.new) Re = #0 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a503c08) { - // Instruction: 3: 0011101--101eeee001111-0-ii01ddd | if (! p0.new) Re = #0 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a503c10) { - // Instruction: 3: 0011101--101eeee001111-0-ii10ddd | if (! p0.new) Re = #0 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a503c18) { - // Instruction: 3: 0011101--101eeee001111-0-ii11ddd | if (! p0.new) Re = #0 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a503d08) { - // Instruction: 3: 0011101--101eeee001111-1ssss1ddd | if (! p0.new) Re = #0 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a503a70) { - // Instruction: 3: 0011101--101eeee0011101--111dddd | if (! p0.new) Re = #0 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a503a50) { - // Instruction: 3: 0011101--101eeee0011101--101dddd | if (! p0.new) Re = #0 ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___IF___NOT__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a503a60) { - // Instruction: 3: 0011101--101eeee0011101--110dddd | if (! p0.new) Re = #0 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___IF__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a603c00) { - // Instruction: 3: 0011101--110eeee001111-0-ii00ddd | if (p0) Re = #0 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a603d00) { - // Instruction: 3: 0011101--110eeee001111-1ssss0ddd | if (p0) Re = #0 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a603c08) { - // Instruction: 3: 0011101--110eeee001111-0-ii01ddd | if (p0) Re = #0 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a603c10) { - // Instruction: 3: 0011101--110eeee001111-0-ii10ddd | if (p0) Re = #0 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a603c18) { - // Instruction: 3: 0011101--110eeee001111-0-ii11ddd | if (p0) Re = #0 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a603d08) { - // Instruction: 3: 0011101--110eeee001111-1ssss1ddd | if (p0) Re = #0 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a603a70) { - // Instruction: 3: 0011101--110eeee0011101--111dddd | if (p0) Re = #0 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a603a60) { - // Instruction: 3: 0011101--110eeee0011101--110dddd | if (p0) Re = #0 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___IF__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a403c00) { - // Instruction: 3: 0011101--100eeee001111-0-ii00ddd | if (p0.new) Re = #0 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a403d00) { - // Instruction: 3: 0011101--100eeee001111-1ssss0ddd | if (p0.new) Re = #0 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a403c08) { - // Instruction: 3: 0011101--100eeee001111-0-ii01ddd | if (p0.new) Re = #0 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a403c10) { - // Instruction: 3: 0011101--100eeee001111-0-ii10ddd | if (p0.new) Re = #0 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a403c18) { - // Instruction: 3: 0011101--100eeee001111-0-ii11ddd | if (p0.new) Re = #0 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a403d08) { - // Instruction: 3: 0011101--100eeee001111-1ssss1ddd | if (p0.new) Re = #0 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a403a70) { - // Instruction: 3: 0011101--100eeee0011101--111dddd | if (p0.new) Re = #0 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a403a50) { - // Instruction: 3: 0011101--100eeee0011101--101dddd | if (p0.new) Re = #0 ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___IF___NOT__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a403a60) { - // Instruction: 3: 0011101--100eeee0011101--110dddd | if (p0.new) Re = #0 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___IF__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a403a40) { - // Instruction: 3: 0011101--100eeee0011101--100dddd | if (p0.new) Re = #0 ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___IF__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x39003a00) { - // Instruction: 3: 00111001ssss--II0011101--0--dddd | p0 = cmp.eq (Rs, #U2) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x39003c00) { - // Instruction: 3: 00111001ssss--II001111-0-ii00ddd | p0 = cmp.eq (Rs, #U2) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x39003c08) { - // Instruction: 3: 00111001ssss--II001111-0-ii01ddd | p0 = cmp.eq (Rs, #U2) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x39003c10) { - // Instruction: 3: 00111001ssss--II001111-0-ii10ddd | p0 = cmp.eq (Rs, #U2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x39003c18) { - // Instruction: 3: 00111001ssss--II001111-0-ii11ddd | p0 = cmp.eq (Rs, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x39003a70) { - // Instruction: 3: 00111001ssss--II0011101--111dddd | p0 = cmp.eq (Rs, #U2) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x39003a50) { - // Instruction: 3: 00111001ssss--II0011101--101dddd | p0 = cmp.eq (Rs, #U2) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x39003a60) { - // Instruction: 3: 00111001ssss--II0011101--110dddd | p0 = cmp.eq (Rs, #U2) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x39003a40) { - // Instruction: 3: 00111001ssss--II0011101--100dddd | p0 = cmp.eq (Rs, #U2) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x39003d00) { - // Instruction: 3: 00111001uuuu--II001111-1ssss0ddd | p0 = cmp.eq (Ru, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x39003d08) { - // Instruction: 3: 00111001uuuu--II001111-1ssss1ddd | p0 = cmp.eq (Ru, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x39003900) { - // Instruction: 3: 00111001uuuu--II00111001ssss--ii | p0 = cmp.eq (Ru, #U2) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - break; - } - case 0x4: { - if ((hi_u32 & 0xfe40f000) == 0x5a001000) { - // Instruction: 4: 0101101--0--eeee0001iiiissssdddd | Re = #-1 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40f000) == 0x5a000000) { - // Instruction: 4: 0101101--0--eeee0000iiiissssdddd | Re = #-1 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x48001000) { - // Instruction: 4: 010010IIIIIIeeee0001iiiissssdddd | Re = #U6 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x48000000) { - // Instruction: 4: 010010IIIIIIeeee0000iiiissssdddd | Re = #U6 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x50001000) { - // Instruction: 4: 01010000uuuueeee0001iiiissssdddd | Re = Ru ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x50000000) { - // Instruction: 4: 01010000uuuueeee0000iiiissssdddd | Re = Ru ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x53001000) { - // Instruction: 4: 01010011uuuueeee0001iiiissssdddd | Re = add (Ru, #-1) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x53000000) { - // Instruction: 4: 01010011uuuueeee0000iiiissssdddd | Re = add (Ru, #-1) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x51001000) { - // Instruction: 4: 01010001uuuueeee0001iiiissssdddd | Re = add (Ru, #1) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x51000000) { - // Instruction: 4: 01010001uuuueeee0000iiiissssdddd | Re = add (Ru, #1) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x4c001000) { - // Instruction: 4: 010011IIIIIIeeee0001iiiissssdddd | Re = add (Sp, #U6:2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x4c000000) { - // Instruction: 4: 010011IIIIIIeeee0000iiiissssdddd | Re = add (Sp, #U6:2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x52001000) { - // Instruction: 4: 01010010uuuueeee0001iiiissssdddd | Re = and (Ru, #1) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x52000000) { - // Instruction: 4: 01010010uuuueeee0000iiiissssdddd | Re = and (Ru, #1) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x57001000) { - // Instruction: 4: 01010111uuuueeee0001iiiissssdddd | Re = and (Ru, #255) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x57000000) { - // Instruction: 4: 01010111uuuueeee0000iiiissssdddd | Re = and (Ru, #255) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x55001000) { - // Instruction: 4: 01010101uuuueeee0001iiiissssdddd | Re = sxtb (Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x55000000) { - // Instruction: 4: 01010101uuuueeee0000iiiissssdddd | Re = sxtb (Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x54001000) { - // Instruction: 4: 01010100uuuueeee0001iiiissssdddd | Re = sxth (Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x54000000) { - // Instruction: 4: 01010100uuuueeee0000iiiissssdddd | Re = sxth (Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x56001000) { - // Instruction: 4: 01010110uuuueeee0001iiiissssdddd | Re = zxth (Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x56000000) { - // Instruction: 4: 01010110uuuueeee0000iiiissssdddd | Re = zxth (Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c001000) { - // Instruction: 4: 010111-0-II00eee0001iiiissssdddd | Ree = combine (#0, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c000000) { - // Instruction: 4: 010111-0-II00eee0000iiiissssdddd | Ree = combine (#0, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x5d001000) { - // Instruction: 4: 010111-1uuuu0eee0001iiiissssdddd | Ree = combine (#0, Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x5d000000) { - // Instruction: 4: 010111-1uuuu0eee0000iiiissssdddd | Ree = combine (#0, Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c081000) { - // Instruction: 4: 010111-0-II01eee0001iiiissssdddd | Ree = combine (#1, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c080000) { - // Instruction: 4: 010111-0-II01eee0000iiiissssdddd | Ree = combine (#1, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c101000) { - // Instruction: 4: 010111-0-II10eee0001iiiissssdddd | Ree = combine (#2, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c100000) { - // Instruction: 4: 010111-0-II10eee0000iiiissssdddd | Ree = combine (#2, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c181000) { - // Instruction: 4: 010111-0-II11eee0001iiiissssdddd | Ree = combine (#3, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c180000) { - // Instruction: 4: 010111-0-II11eee0000iiiissssdddd | Ree = combine (#3, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x5d081000) { - // Instruction: 4: 010111-1uuuu1eee0001iiiissssdddd | Ree = combine (Ru, #0) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x5d080000) { - // Instruction: 4: 010111-1uuuu1eee0000iiiissssdddd | Ree = combine (Ru, #0) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x58001000) { - // Instruction: 4: 01011000uuuuxxxx0001iiiissssdddd | Rx = add (Ru, Rx) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x58000000) { - // Instruction: 4: 01011000uuuuxxxx0000iiiissssdddd | Rx = add (Ru, Rx) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f000) == 0x40001000) { - // Instruction: 4: 01000IIIIIIIxxxx0001iiiissssdddd | Rx = add (Rx, #S7) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f000) == 0x40000000) { - // Instruction: 4: 01000IIIIIIIxxxx0000iiiissssdddd | Rx = add (Rx, #S7) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x58001000) { - // Instruction: 4: 01011000uuuuxxxx0001iiiissssdddd | Rx = add (Rx, Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x58000000) { - // Instruction: 4: 01011000uuuuxxxx0000iiiissssdddd | Rx = add (Rx, Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a701000) { - // Instruction: 4: 0101101--111eeee0001iiiissssdddd | if (! p0) Re = #0 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a700000) { - // Instruction: 4: 0101101--111eeee0000iiiissssdddd | if (! p0) Re = #0 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a501000) { - // Instruction: 4: 0101101--101eeee0001iiiissssdddd | if (! p0.new) Re = #0 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a500000) { - // Instruction: 4: 0101101--101eeee0000iiiissssdddd | if (! p0.new) Re = #0 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a601000) { - // Instruction: 4: 0101101--110eeee0001iiiissssdddd | if (p0) Re = #0 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a600000) { - // Instruction: 4: 0101101--110eeee0000iiiissssdddd | if (p0) Re = #0 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a401000) { - // Instruction: 4: 0101101--100eeee0001iiiissssdddd | if (p0.new) Re = #0 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a400000) { - // Instruction: 4: 0101101--100eeee0000iiiissssdddd | if (p0.new) Re = #0 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x59001000) { - // Instruction: 4: 01011001uuuu--II0001iiiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x59000000) { - // Instruction: 4: 01011001uuuu--II0000iiiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - break; - } - case 0x5: { - if ((hi_u32 & 0xfe40ffc4) == 0x5a003f40) { - // Instruction: 5: 0101101--0--dddd0011111101---0-- | Rd = #-1 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD_____1___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc4) == 0x5a003f00) { - // Instruction: 5: 0101101--0--dddd0011111100---0-- | Rd = #-1 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD_____1___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003f45) { - // Instruction: 5: 0101101--0--dddd0011111101---101 | Rd = #-1 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003fc5) { - // Instruction: 5: 0101101--0--dddd0011111111---101 | Rd = #-1 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003f47) { - // Instruction: 5: 0101101--0--dddd0011111101---111 | Rd = #-1 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003fc7) { - // Instruction: 5: 0101101--0--dddd0011111111---111 | Rd = #-1 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003f44) { - // Instruction: 5: 0101101--0--dddd0011111101---100 | Rd = #-1 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003fc4) { - // Instruction: 5: 0101101--0--dddd0011111111---100 | Rd = #-1 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003f46) { - // Instruction: 5: 0101101--0--dddd0011111101---110 | Rd = #-1 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003fc6) { - // Instruction: 5: 0101101--0--dddd0011111111---110 | Rd = #-1 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc4) == 0x5a003fc0) { - // Instruction: 5: 0101101--0--dddd0011111111---0-- | Rd = #-1 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x48003f40) { - // Instruction: 5: 010010iiiiiidddd0011111101---0-- | Rd = #u6 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD____U6___DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x48003f00) { - // Instruction: 5: 010010iiiiiidddd0011111100---0-- | Rd = #u6 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD____U6___DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003f45) { - // Instruction: 5: 010010iiiiiidddd0011111101---101 | Rd = #u6 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003fc5) { - // Instruction: 5: 010010iiiiiidddd0011111111---101 | Rd = #u6 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003f47) { - // Instruction: 5: 010010iiiiiidddd0011111101---111 | Rd = #u6 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003fc7) { - // Instruction: 5: 010010iiiiiidddd0011111111---111 | Rd = #u6 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003f44) { - // Instruction: 5: 010010iiiiiidddd0011111101---100 | Rd = #u6 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003fc4) { - // Instruction: 5: 010010iiiiiidddd0011111111---100 | Rd = #u6 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003f46) { - // Instruction: 5: 010010iiiiiidddd0011111101---110 | Rd = #u6 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003fc6) { - // Instruction: 5: 010010iiiiiidddd0011111111---110 | Rd = #u6 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x48003fc0) { - // Instruction: 5: 010010iiiiiidddd0011111111---0-- | Rd = #u6 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x50003f40) { - // Instruction: 5: 01010000ssssdddd0011111101---0-- | Rd = Rs ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___RS___DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x50003f00) { - // Instruction: 5: 01010000ssssdddd0011111100---0-- | Rd = Rs ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___RS___DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003f45) { - // Instruction: 5: 01010000ssssdddd0011111101---101 | Rd = Rs ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003fc5) { - // Instruction: 5: 01010000ssssdddd0011111111---101 | Rd = Rs ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003f47) { - // Instruction: 5: 01010000ssssdddd0011111101---111 | Rd = Rs ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003fc7) { - // Instruction: 5: 01010000ssssdddd0011111111---111 | Rd = Rs ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003f44) { - // Instruction: 5: 01010000ssssdddd0011111101---100 | Rd = Rs ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003fc4) { - // Instruction: 5: 01010000ssssdddd0011111111---100 | Rd = Rs ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003f46) { - // Instruction: 5: 01010000ssssdddd0011111101---110 | Rd = Rs ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003fc6) { - // Instruction: 5: 01010000ssssdddd0011111111---110 | Rd = Rs ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x50003fc0) { - // Instruction: 5: 01010000ssssdddd0011111111---0-- | Rd = Rs ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x53003f40) { - // Instruction: 5: 01010011ssssdddd0011111101---0-- | Rd = add (Rs, #-1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x53003f00) { - // Instruction: 5: 01010011ssssdddd0011111100---0-- | Rd = add (Rs, #-1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003f45) { - // Instruction: 5: 01010011ssssdddd0011111101---101 | Rd = add (Rs, #-1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003fc5) { - // Instruction: 5: 01010011ssssdddd0011111111---101 | Rd = add (Rs, #-1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003f47) { - // Instruction: 5: 01010011ssssdddd0011111101---111 | Rd = add (Rs, #-1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003fc7) { - // Instruction: 5: 01010011ssssdddd0011111111---111 | Rd = add (Rs, #-1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003f44) { - // Instruction: 5: 01010011ssssdddd0011111101---100 | Rd = add (Rs, #-1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003fc4) { - // Instruction: 5: 01010011ssssdddd0011111111---100 | Rd = add (Rs, #-1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003f46) { - // Instruction: 5: 01010011ssssdddd0011111101---110 | Rd = add (Rs, #-1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003fc6) { - // Instruction: 5: 01010011ssssdddd0011111111---110 | Rd = add (Rs, #-1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x53003fc0) { - // Instruction: 5: 01010011ssssdddd0011111111---0-- | Rd = add (Rs, #-1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x51003f40) { - // Instruction: 5: 01010001ssssdddd0011111101---0-- | Rd = add (Rs, #1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x51003f00) { - // Instruction: 5: 01010001ssssdddd0011111100---0-- | Rd = add (Rs, #1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003f45) { - // Instruction: 5: 01010001ssssdddd0011111101---101 | Rd = add (Rs, #1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003fc5) { - // Instruction: 5: 01010001ssssdddd0011111111---101 | Rd = add (Rs, #1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003f47) { - // Instruction: 5: 01010001ssssdddd0011111101---111 | Rd = add (Rs, #1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003fc7) { - // Instruction: 5: 01010001ssssdddd0011111111---111 | Rd = add (Rs, #1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003f44) { - // Instruction: 5: 01010001ssssdddd0011111101---100 | Rd = add (Rs, #1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003fc4) { - // Instruction: 5: 01010001ssssdddd0011111111---100 | Rd = add (Rs, #1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003f46) { - // Instruction: 5: 01010001ssssdddd0011111101---110 | Rd = add (Rs, #1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003fc6) { - // Instruction: 5: 01010001ssssdddd0011111111---110 | Rd = add (Rs, #1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x51003fc0) { - // Instruction: 5: 01010001ssssdddd0011111111---0-- | Rd = add (Rs, #1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x4c003f40) { - // Instruction: 5: 010011iiiiiidddd0011111101---0-- | Rd = add (Sp, #u6:2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x4c003f00) { - // Instruction: 5: 010011iiiiiidddd0011111100---0-- | Rd = add (Sp, #u6:2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003f45) { - // Instruction: 5: 010011iiiiiidddd0011111101---101 | Rd = add (Sp, #u6:2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003fc5) { - // Instruction: 5: 010011iiiiiidddd0011111111---101 | Rd = add (Sp, #u6:2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003f47) { - // Instruction: 5: 010011iiiiiidddd0011111101---111 | Rd = add (Sp, #u6:2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003fc7) { - // Instruction: 5: 010011iiiiiidddd0011111111---111 | Rd = add (Sp, #u6:2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003f44) { - // Instruction: 5: 010011iiiiiidddd0011111101---100 | Rd = add (Sp, #u6:2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003fc4) { - // Instruction: 5: 010011iiiiiidddd0011111111---100 | Rd = add (Sp, #u6:2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003f46) { - // Instruction: 5: 010011iiiiiidddd0011111101---110 | Rd = add (Sp, #u6:2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003fc6) { - // Instruction: 5: 010011iiiiiidddd0011111111---110 | Rd = add (Sp, #u6:2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x4c003fc0) { - // Instruction: 5: 010011iiiiiidddd0011111111---0-- | Rd = add (Sp, #u6:2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x52003f40) { - // Instruction: 5: 01010010ssssdddd0011111101---0-- | Rd = and (Rs, #1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x52003f00) { - // Instruction: 5: 01010010ssssdddd0011111100---0-- | Rd = and (Rs, #1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003f45) { - // Instruction: 5: 01010010ssssdddd0011111101---101 | Rd = and (Rs, #1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003fc5) { - // Instruction: 5: 01010010ssssdddd0011111111---101 | Rd = and (Rs, #1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003f47) { - // Instruction: 5: 01010010ssssdddd0011111101---111 | Rd = and (Rs, #1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003fc7) { - // Instruction: 5: 01010010ssssdddd0011111111---111 | Rd = and (Rs, #1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003f44) { - // Instruction: 5: 01010010ssssdddd0011111101---100 | Rd = and (Rs, #1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003fc4) { - // Instruction: 5: 01010010ssssdddd0011111111---100 | Rd = and (Rs, #1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003f46) { - // Instruction: 5: 01010010ssssdddd0011111101---110 | Rd = and (Rs, #1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003fc6) { - // Instruction: 5: 01010010ssssdddd0011111111---110 | Rd = and (Rs, #1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x52003fc0) { - // Instruction: 5: 01010010ssssdddd0011111111---0-- | Rd = and (Rs, #1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x57003f40) { - // Instruction: 5: 01010111ssssdddd0011111101---0-- | Rd = and (Rs, #255) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x57003f00) { - // Instruction: 5: 01010111ssssdddd0011111100---0-- | Rd = and (Rs, #255) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003f45) { - // Instruction: 5: 01010111ssssdddd0011111101---101 | Rd = and (Rs, #255) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003fc5) { - // Instruction: 5: 01010111ssssdddd0011111111---101 | Rd = and (Rs, #255) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003f47) { - // Instruction: 5: 01010111ssssdddd0011111101---111 | Rd = and (Rs, #255) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003fc7) { - // Instruction: 5: 01010111ssssdddd0011111111---111 | Rd = and (Rs, #255) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003f44) { - // Instruction: 5: 01010111ssssdddd0011111101---100 | Rd = and (Rs, #255) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003fc4) { - // Instruction: 5: 01010111ssssdddd0011111111---100 | Rd = and (Rs, #255) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003f46) { - // Instruction: 5: 01010111ssssdddd0011111101---110 | Rd = and (Rs, #255) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003fc6) { - // Instruction: 5: 01010111ssssdddd0011111111---110 | Rd = and (Rs, #255) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x57003fc0) { - // Instruction: 5: 01010111ssssdddd0011111111---0-- | Rd = and (Rs, #255) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x55003f40) { - // Instruction: 5: 01010101ssssdddd0011111101---0-- | Rd = sxtb (Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x55003f00) { - // Instruction: 5: 01010101ssssdddd0011111100---0-- | Rd = sxtb (Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003f45) { - // Instruction: 5: 01010101ssssdddd0011111101---101 | Rd = sxtb (Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003fc5) { - // Instruction: 5: 01010101ssssdddd0011111111---101 | Rd = sxtb (Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003f47) { - // Instruction: 5: 01010101ssssdddd0011111101---111 | Rd = sxtb (Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003fc7) { - // Instruction: 5: 01010101ssssdddd0011111111---111 | Rd = sxtb (Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003f44) { - // Instruction: 5: 01010101ssssdddd0011111101---100 | Rd = sxtb (Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003fc4) { - // Instruction: 5: 01010101ssssdddd0011111111---100 | Rd = sxtb (Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003f46) { - // Instruction: 5: 01010101ssssdddd0011111101---110 | Rd = sxtb (Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003fc6) { - // Instruction: 5: 01010101ssssdddd0011111111---110 | Rd = sxtb (Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x55003fc0) { - // Instruction: 5: 01010101ssssdddd0011111111---0-- | Rd = sxtb (Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x54003f40) { - // Instruction: 5: 01010100ssssdddd0011111101---0-- | Rd = sxth (Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x54003f00) { - // Instruction: 5: 01010100ssssdddd0011111100---0-- | Rd = sxth (Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003f45) { - // Instruction: 5: 01010100ssssdddd0011111101---101 | Rd = sxth (Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003fc5) { - // Instruction: 5: 01010100ssssdddd0011111111---101 | Rd = sxth (Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003f47) { - // Instruction: 5: 01010100ssssdddd0011111101---111 | Rd = sxth (Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003fc7) { - // Instruction: 5: 01010100ssssdddd0011111111---111 | Rd = sxth (Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003f44) { - // Instruction: 5: 01010100ssssdddd0011111101---100 | Rd = sxth (Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003fc4) { - // Instruction: 5: 01010100ssssdddd0011111111---100 | Rd = sxth (Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003f46) { - // Instruction: 5: 01010100ssssdddd0011111101---110 | Rd = sxth (Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003fc6) { - // Instruction: 5: 01010100ssssdddd0011111111---110 | Rd = sxth (Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x54003fc0) { - // Instruction: 5: 01010100ssssdddd0011111111---0-- | Rd = sxth (Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x56003f40) { - // Instruction: 5: 01010110ssssdddd0011111101---0-- | Rd = zxth (Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x56003f00) { - // Instruction: 5: 01010110ssssdddd0011111100---0-- | Rd = zxth (Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003f45) { - // Instruction: 5: 01010110ssssdddd0011111101---101 | Rd = zxth (Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003fc5) { - // Instruction: 5: 01010110ssssdddd0011111111---101 | Rd = zxth (Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003f47) { - // Instruction: 5: 01010110ssssdddd0011111101---111 | Rd = zxth (Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003fc7) { - // Instruction: 5: 01010110ssssdddd0011111111---111 | Rd = zxth (Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003f44) { - // Instruction: 5: 01010110ssssdddd0011111101---100 | Rd = zxth (Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003fc4) { - // Instruction: 5: 01010110ssssdddd0011111111---100 | Rd = zxth (Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003f46) { - // Instruction: 5: 01010110ssssdddd0011111101---110 | Rd = zxth (Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003fc6) { - // Instruction: 5: 01010110ssssdddd0011111111---110 | Rd = zxth (Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x56003fc0) { - // Instruction: 5: 01010110ssssdddd0011111111---0-- | Rd = zxth (Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c003f40) { - // Instruction: 5: 010111-0-ii00ddd0011111101---0-- | Rdd = combine (#0, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c003f00) { - // Instruction: 5: 010111-0-ii00ddd0011111100---0-- | Rdd = combine (#0, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003f45) { - // Instruction: 5: 010111-0-ii00ddd0011111101---101 | Rdd = combine (#0, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003fc5) { - // Instruction: 5: 010111-0-ii00ddd0011111111---101 | Rdd = combine (#0, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003f47) { - // Instruction: 5: 010111-0-ii00ddd0011111101---111 | Rdd = combine (#0, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003fc7) { - // Instruction: 5: 010111-0-ii00ddd0011111111---111 | Rdd = combine (#0, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003f44) { - // Instruction: 5: 010111-0-ii00ddd0011111101---100 | Rdd = combine (#0, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003fc4) { - // Instruction: 5: 010111-0-ii00ddd0011111111---100 | Rdd = combine (#0, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003f46) { - // Instruction: 5: 010111-0-ii00ddd0011111101---110 | Rdd = combine (#0, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003fc6) { - // Instruction: 5: 010111-0-ii00ddd0011111111---110 | Rdd = combine (#0, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c003fc0) { - // Instruction: 5: 010111-0-ii00ddd0011111111---0-- | Rdd = combine (#0, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d003f40) { - // Instruction: 5: 010111-1ssss0ddd0011111101---0-- | Rdd = combine (#0, Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d003f00) { - // Instruction: 5: 010111-1ssss0ddd0011111100---0-- | Rdd = combine (#0, Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003f45) { - // Instruction: 5: 010111-1ssss0ddd0011111101---101 | Rdd = combine (#0, Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003fc5) { - // Instruction: 5: 010111-1ssss0ddd0011111111---101 | Rdd = combine (#0, Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003f47) { - // Instruction: 5: 010111-1ssss0ddd0011111101---111 | Rdd = combine (#0, Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003fc7) { - // Instruction: 5: 010111-1ssss0ddd0011111111---111 | Rdd = combine (#0, Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003f44) { - // Instruction: 5: 010111-1ssss0ddd0011111101---100 | Rdd = combine (#0, Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003fc4) { - // Instruction: 5: 010111-1ssss0ddd0011111111---100 | Rdd = combine (#0, Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003f46) { - // Instruction: 5: 010111-1ssss0ddd0011111101---110 | Rdd = combine (#0, Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003fc6) { - // Instruction: 5: 010111-1ssss0ddd0011111111---110 | Rdd = combine (#0, Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d003fc0) { - // Instruction: 5: 010111-1ssss0ddd0011111111---0-- | Rdd = combine (#0, Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c083f40) { - // Instruction: 5: 010111-0-ii01ddd0011111101---0-- | Rdd = combine (#1, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c083f00) { - // Instruction: 5: 010111-0-ii01ddd0011111100---0-- | Rdd = combine (#1, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083f45) { - // Instruction: 5: 010111-0-ii01ddd0011111101---101 | Rdd = combine (#1, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083fc5) { - // Instruction: 5: 010111-0-ii01ddd0011111111---101 | Rdd = combine (#1, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083f47) { - // Instruction: 5: 010111-0-ii01ddd0011111101---111 | Rdd = combine (#1, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083fc7) { - // Instruction: 5: 010111-0-ii01ddd0011111111---111 | Rdd = combine (#1, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083f44) { - // Instruction: 5: 010111-0-ii01ddd0011111101---100 | Rdd = combine (#1, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083fc4) { - // Instruction: 5: 010111-0-ii01ddd0011111111---100 | Rdd = combine (#1, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083f46) { - // Instruction: 5: 010111-0-ii01ddd0011111101---110 | Rdd = combine (#1, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083fc6) { - // Instruction: 5: 010111-0-ii01ddd0011111111---110 | Rdd = combine (#1, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c083fc0) { - // Instruction: 5: 010111-0-ii01ddd0011111111---0-- | Rdd = combine (#1, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c103f40) { - // Instruction: 5: 010111-0-ii10ddd0011111101---0-- | Rdd = combine (#2, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c103f00) { - // Instruction: 5: 010111-0-ii10ddd0011111100---0-- | Rdd = combine (#2, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103f45) { - // Instruction: 5: 010111-0-ii10ddd0011111101---101 | Rdd = combine (#2, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103fc5) { - // Instruction: 5: 010111-0-ii10ddd0011111111---101 | Rdd = combine (#2, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103f47) { - // Instruction: 5: 010111-0-ii10ddd0011111101---111 | Rdd = combine (#2, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103fc7) { - // Instruction: 5: 010111-0-ii10ddd0011111111---111 | Rdd = combine (#2, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103f44) { - // Instruction: 5: 010111-0-ii10ddd0011111101---100 | Rdd = combine (#2, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103fc4) { - // Instruction: 5: 010111-0-ii10ddd0011111111---100 | Rdd = combine (#2, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103f46) { - // Instruction: 5: 010111-0-ii10ddd0011111101---110 | Rdd = combine (#2, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103fc6) { - // Instruction: 5: 010111-0-ii10ddd0011111111---110 | Rdd = combine (#2, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c103fc0) { - // Instruction: 5: 010111-0-ii10ddd0011111111---0-- | Rdd = combine (#2, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c183f40) { - // Instruction: 5: 010111-0-ii11ddd0011111101---0-- | Rdd = combine (#3, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c183f00) { - // Instruction: 5: 010111-0-ii11ddd0011111100---0-- | Rdd = combine (#3, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183f45) { - // Instruction: 5: 010111-0-ii11ddd0011111101---101 | Rdd = combine (#3, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183fc5) { - // Instruction: 5: 010111-0-ii11ddd0011111111---101 | Rdd = combine (#3, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183f47) { - // Instruction: 5: 010111-0-ii11ddd0011111101---111 | Rdd = combine (#3, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183fc7) { - // Instruction: 5: 010111-0-ii11ddd0011111111---111 | Rdd = combine (#3, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183f44) { - // Instruction: 5: 010111-0-ii11ddd0011111101---100 | Rdd = combine (#3, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183fc4) { - // Instruction: 5: 010111-0-ii11ddd0011111111---100 | Rdd = combine (#3, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183f46) { - // Instruction: 5: 010111-0-ii11ddd0011111101---110 | Rdd = combine (#3, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183fc6) { - // Instruction: 5: 010111-0-ii11ddd0011111111---110 | Rdd = combine (#3, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c183fc0) { - // Instruction: 5: 010111-0-ii11ddd0011111111---0-- | Rdd = combine (#3, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d083f40) { - // Instruction: 5: 010111-1ssss1ddd0011111101---0-- | Rdd = combine (Rs, #0) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d083f00) { - // Instruction: 5: 010111-1ssss1ddd0011111100---0-- | Rdd = combine (Rs, #0) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083f45) { - // Instruction: 5: 010111-1ssss1ddd0011111101---101 | Rdd = combine (Rs, #0) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083fc5) { - // Instruction: 5: 010111-1ssss1ddd0011111111---101 | Rdd = combine (Rs, #0) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083f47) { - // Instruction: 5: 010111-1ssss1ddd0011111101---111 | Rdd = combine (Rs, #0) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083fc7) { - // Instruction: 5: 010111-1ssss1ddd0011111111---111 | Rdd = combine (Rs, #0) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083f44) { - // Instruction: 5: 010111-1ssss1ddd0011111101---100 | Rdd = combine (Rs, #0) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083fc4) { - // Instruction: 5: 010111-1ssss1ddd0011111111---100 | Rdd = combine (Rs, #0) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083f46) { - // Instruction: 5: 010111-1ssss1ddd0011111101---110 | Rdd = combine (Rs, #0) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083fc6) { - // Instruction: 5: 010111-1ssss1ddd0011111111---110 | Rdd = combine (Rs, #0) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d083fc0) { - // Instruction: 5: 010111-1ssss1ddd0011111111---0-- | Rdd = combine (Rs, #0) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40f800) == 0x5a003000) { - // Instruction: 5: 0101101--0--eeee00110iiissssdddd | Re = #-1 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40f800) == 0x5a002000) { - // Instruction: 5: 0101101--0--eeee00100iiissssdddd | Re = #-1 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40f800) == 0x5a002800) { - // Instruction: 5: 0101101--0--eeee00101iiissssdddd | Re = #-1 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40fe00) == 0x5a003c00) { - // Instruction: 5: 0101101--0--eeee0011110iiiiidddd | Re = #-1 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x5a003e00) { - // Instruction: 5: 0101101--0--eeee00111110iiiiiddd | Re = #-1 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x48003000) { - // Instruction: 5: 010010IIIIIIeeee00110iiissssdddd | Re = #U6 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x48002000) { - // Instruction: 5: 010010IIIIIIeeee00100iiissssdddd | Re = #U6 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x48002800) { - // Instruction: 5: 010010IIIIIIeeee00101iiissssdddd | Re = #U6 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x48003c00) { - // Instruction: 5: 010010IIIIIIeeee0011110iiiiidddd | Re = #U6 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x48003e00) { - // Instruction: 5: 010010IIIIIIeeee00111110iiiiiddd | Re = #U6 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x50003c00) { - // Instruction: 5: 01010000sssseeee0011110iiiiidddd | Re = Rs ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x50003e00) { - // Instruction: 5: 01010000sssseeee00111110iiiiiddd | Re = Rs ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x50003000) { - // Instruction: 5: 01010000uuuueeee00110iiissssdddd | Re = Ru ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x50002000) { - // Instruction: 5: 01010000uuuueeee00100iiissssdddd | Re = Ru ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x50002800) { - // Instruction: 5: 01010000uuuueeee00101iiissssdddd | Re = Ru ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x53003c00) { - // Instruction: 5: 01010011sssseeee0011110iiiiidddd | Re = add (Rs, #-1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x53003e00) { - // Instruction: 5: 01010011sssseeee00111110iiiiiddd | Re = add (Rs, #-1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x51003c00) { - // Instruction: 5: 01010001sssseeee0011110iiiiidddd | Re = add (Rs, #1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x51003e00) { - // Instruction: 5: 01010001sssseeee00111110iiiiiddd | Re = add (Rs, #1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x53003000) { - // Instruction: 5: 01010011uuuueeee00110iiissssdddd | Re = add (Ru, #-1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x53002000) { - // Instruction: 5: 01010011uuuueeee00100iiissssdddd | Re = add (Ru, #-1) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x53002800) { - // Instruction: 5: 01010011uuuueeee00101iiissssdddd | Re = add (Ru, #-1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x51003000) { - // Instruction: 5: 01010001uuuueeee00110iiissssdddd | Re = add (Ru, #1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x51002000) { - // Instruction: 5: 01010001uuuueeee00100iiissssdddd | Re = add (Ru, #1) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x51002800) { - // Instruction: 5: 01010001uuuueeee00101iiissssdddd | Re = add (Ru, #1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x4c003000) { - // Instruction: 5: 010011IIIIIIeeee00110iiissssdddd | Re = add (Sp, #U6:2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x4c002000) { - // Instruction: 5: 010011IIIIIIeeee00100iiissssdddd | Re = add (Sp, #U6:2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x4c002800) { - // Instruction: 5: 010011IIIIIIeeee00101iiissssdddd | Re = add (Sp, #U6:2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x4c003c00) { - // Instruction: 5: 010011IIIIIIeeee0011110iiiiidddd | Re = add (Sp, #U6:2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x4c003e00) { - // Instruction: 5: 010011IIIIIIeeee00111110iiiiiddd | Re = add (Sp, #U6:2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x52003c00) { - // Instruction: 5: 01010010sssseeee0011110iiiiidddd | Re = and (Rs, #1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x52003e00) { - // Instruction: 5: 01010010sssseeee00111110iiiiiddd | Re = and (Rs, #1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x57003c00) { - // Instruction: 5: 01010111sssseeee0011110iiiiidddd | Re = and (Rs, #255) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x57003e00) { - // Instruction: 5: 01010111sssseeee00111110iiiiiddd | Re = and (Rs, #255) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x52003000) { - // Instruction: 5: 01010010uuuueeee00110iiissssdddd | Re = and (Ru, #1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x52002000) { - // Instruction: 5: 01010010uuuueeee00100iiissssdddd | Re = and (Ru, #1) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x52002800) { - // Instruction: 5: 01010010uuuueeee00101iiissssdddd | Re = and (Ru, #1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x57003000) { - // Instruction: 5: 01010111uuuueeee00110iiissssdddd | Re = and (Ru, #255) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x57002000) { - // Instruction: 5: 01010111uuuueeee00100iiissssdddd | Re = and (Ru, #255) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x57002800) { - // Instruction: 5: 01010111uuuueeee00101iiissssdddd | Re = and (Ru, #255) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x55003c00) { - // Instruction: 5: 01010101sssseeee0011110iiiiidddd | Re = sxtb (Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x55003e00) { - // Instruction: 5: 01010101sssseeee00111110iiiiiddd | Re = sxtb (Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x55003000) { - // Instruction: 5: 01010101uuuueeee00110iiissssdddd | Re = sxtb (Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x55002000) { - // Instruction: 5: 01010101uuuueeee00100iiissssdddd | Re = sxtb (Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x55002800) { - // Instruction: 5: 01010101uuuueeee00101iiissssdddd | Re = sxtb (Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x54003c00) { - // Instruction: 5: 01010100sssseeee0011110iiiiidddd | Re = sxth (Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x54003e00) { - // Instruction: 5: 01010100sssseeee00111110iiiiiddd | Re = sxth (Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x54003000) { - // Instruction: 5: 01010100uuuueeee00110iiissssdddd | Re = sxth (Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x54002000) { - // Instruction: 5: 01010100uuuueeee00100iiissssdddd | Re = sxth (Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x54002800) { - // Instruction: 5: 01010100uuuueeee00101iiissssdddd | Re = sxth (Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x56003c00) { - // Instruction: 5: 01010110sssseeee0011110iiiiidddd | Re = zxth (Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x56003e00) { - // Instruction: 5: 01010110sssseeee00111110iiiiiddd | Re = zxth (Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x56003000) { - // Instruction: 5: 01010110uuuueeee00110iiissssdddd | Re = zxth (Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x56002000) { - // Instruction: 5: 01010110uuuueeee00100iiissssdddd | Re = zxth (Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x56002800) { - // Instruction: 5: 01010110uuuueeee00101iiissssdddd | Re = zxth (Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c003000) { - // Instruction: 5: 010111-0-II00eee00110iiissssdddd | Ree = combine (#0, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c002000) { - // Instruction: 5: 010111-0-II00eee00100iiissssdddd | Ree = combine (#0, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c002800) { - // Instruction: 5: 010111-0-II00eee00101iiissssdddd | Ree = combine (#0, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x5c003c00) { - // Instruction: 5: 010111-0-II00eee0011110iiiiidddd | Ree = combine (#0, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x5c003e00) { - // Instruction: 5: 010111-0-II00eee00111110iiiiiddd | Ree = combine (#0, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x5d003c00) { - // Instruction: 5: 010111-1ssss0eee0011110iiiiidddd | Ree = combine (#0, Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x5d003e00) { - // Instruction: 5: 010111-1ssss0eee00111110iiiiiddd | Ree = combine (#0, Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d003000) { - // Instruction: 5: 010111-1uuuu0eee00110iiissssdddd | Ree = combine (#0, Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d002000) { - // Instruction: 5: 010111-1uuuu0eee00100iiissssdddd | Ree = combine (#0, Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d002800) { - // Instruction: 5: 010111-1uuuu0eee00101iiissssdddd | Ree = combine (#0, Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c083000) { - // Instruction: 5: 010111-0-II01eee00110iiissssdddd | Ree = combine (#1, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c082000) { - // Instruction: 5: 010111-0-II01eee00100iiissssdddd | Ree = combine (#1, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c082800) { - // Instruction: 5: 010111-0-II01eee00101iiissssdddd | Ree = combine (#1, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x5c083c00) { - // Instruction: 5: 010111-0-II01eee0011110iiiiidddd | Ree = combine (#1, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x5c083e00) { - // Instruction: 5: 010111-0-II01eee00111110iiiiiddd | Ree = combine (#1, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c103000) { - // Instruction: 5: 010111-0-II10eee00110iiissssdddd | Ree = combine (#2, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c102000) { - // Instruction: 5: 010111-0-II10eee00100iiissssdddd | Ree = combine (#2, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c102800) { - // Instruction: 5: 010111-0-II10eee00101iiissssdddd | Ree = combine (#2, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x5c103c00) { - // Instruction: 5: 010111-0-II10eee0011110iiiiidddd | Ree = combine (#2, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x5c103e00) { - // Instruction: 5: 010111-0-II10eee00111110iiiiiddd | Ree = combine (#2, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c183000) { - // Instruction: 5: 010111-0-II11eee00110iiissssdddd | Ree = combine (#3, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c182000) { - // Instruction: 5: 010111-0-II11eee00100iiissssdddd | Ree = combine (#3, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c182800) { - // Instruction: 5: 010111-0-II11eee00101iiissssdddd | Ree = combine (#3, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x5c183c00) { - // Instruction: 5: 010111-0-II11eee0011110iiiiidddd | Ree = combine (#3, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x5c183e00) { - // Instruction: 5: 010111-0-II11eee00111110iiiiiddd | Ree = combine (#3, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x5d083c00) { - // Instruction: 5: 010111-1ssss1eee0011110iiiiidddd | Ree = combine (Rs, #0) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RS___0____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x5d083e00) { - // Instruction: 5: 010111-1ssss1eee00111110iiiiiddd | Ree = combine (Rs, #0) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RS___0____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d083000) { - // Instruction: 5: 010111-1uuuu1eee00110iiissssdddd | Ree = combine (Ru, #0) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d082000) { - // Instruction: 5: 010111-1uuuu1eee00100iiissssdddd | Ree = combine (Ru, #0) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d082800) { - // Instruction: 5: 010111-1uuuu1eee00101iiissssdddd | Ree = combine (Ru, #0) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x58003c00) { - // Instruction: 5: 01011000ssssxxxx0011110iiiiidddd | Rx = add (Rs, Rx) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x58003e00) { - // Instruction: 5: 01011000ssssxxxx00111110iiiiiddd | Rx = add (Rs, Rx) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003f40) { - // Instruction: 5: 01011000ssssxxxx0011111101---0-- | Rx = add (Rs, Rx) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003f00) { - // Instruction: 5: 01011000ssssxxxx0011111100---0-- | Rx = add (Rs, Rx) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f45) { - // Instruction: 5: 01011000ssssxxxx0011111101---101 | Rx = add (Rs, Rx) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc5) { - // Instruction: 5: 01011000ssssxxxx0011111111---101 | Rx = add (Rs, Rx) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f47) { - // Instruction: 5: 01011000ssssxxxx0011111101---111 | Rx = add (Rs, Rx) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc7) { - // Instruction: 5: 01011000ssssxxxx0011111111---111 | Rx = add (Rs, Rx) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f44) { - // Instruction: 5: 01011000ssssxxxx0011111101---100 | Rx = add (Rs, Rx) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc4) { - // Instruction: 5: 01011000ssssxxxx0011111111---100 | Rx = add (Rs, Rx) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f46) { - // Instruction: 5: 01011000ssssxxxx0011111101---110 | Rx = add (Rs, Rx) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc6) { - // Instruction: 5: 01011000ssssxxxx0011111111---110 | Rx = add (Rs, Rx) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003fc0) { - // Instruction: 5: 01011000ssssxxxx0011111111---0-- | Rx = add (Rs, Rx) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58003000) { - // Instruction: 5: 01011000uuuuxxxx00110iiissssdddd | Rx = add (Ru, Rx) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58002000) { - // Instruction: 5: 01011000uuuuxxxx00100iiissssdddd | Rx = add (Ru, Rx) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58002800) { - // Instruction: 5: 01011000uuuuxxxx00101iiissssdddd | Rx = add (Ru, Rx) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x40003000) { - // Instruction: 5: 01000IIIIIIIxxxx00110iiissssdddd | Rx = add (Rx, #S7) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x40002000) { - // Instruction: 5: 01000IIIIIIIxxxx00100iiissssdddd | Rx = add (Rx, #S7) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x40002800) { - // Instruction: 5: 01000IIIIIIIxxxx00101iiissssdddd | Rx = add (Rx, #S7) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x40003c00) { - // Instruction: 5: 01000IIIIIIIxxxx0011110iiiiidddd | Rx = add (Rx, #S7) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x40003e00) { - // Instruction: 5: 01000IIIIIIIxxxx00111110iiiiiddd | Rx = add (Rx, #S7) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x40003f40) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---0-- | Rx = add (Rx, #s7) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x40003f00) { - // Instruction: 5: 01000iiiiiiixxxx0011111100---0-- | Rx = add (Rx, #s7) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003f45) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---101 | Rx = add (Rx, #s7) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003fc5) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---101 | Rx = add (Rx, #s7) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003f47) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---111 | Rx = add (Rx, #s7) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003fc7) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---111 | Rx = add (Rx, #s7) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003f44) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---100 | Rx = add (Rx, #s7) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003fc4) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---100 | Rx = add (Rx, #s7) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003f46) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---110 | Rx = add (Rx, #s7) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003fc6) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---110 | Rx = add (Rx, #s7) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x40003fc0) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---0-- | Rx = add (Rx, #s7) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x58003c00) { - // Instruction: 5: 01011000ssssxxxx0011110iiiiidddd | Rx = add (Rx, Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x58003e00) { - // Instruction: 5: 01011000ssssxxxx00111110iiiiiddd | Rx = add (Rx, Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003f40) { - // Instruction: 5: 01011000ssssxxxx0011111101---0-- | Rx = add (Rx, Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003f00) { - // Instruction: 5: 01011000ssssxxxx0011111100---0-- | Rx = add (Rx, Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f45) { - // Instruction: 5: 01011000ssssxxxx0011111101---101 | Rx = add (Rx, Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc5) { - // Instruction: 5: 01011000ssssxxxx0011111111---101 | Rx = add (Rx, Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f47) { - // Instruction: 5: 01011000ssssxxxx0011111101---111 | Rx = add (Rx, Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc7) { - // Instruction: 5: 01011000ssssxxxx0011111111---111 | Rx = add (Rx, Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f44) { - // Instruction: 5: 01011000ssssxxxx0011111101---100 | Rx = add (Rx, Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc4) { - // Instruction: 5: 01011000ssssxxxx0011111111---100 | Rx = add (Rx, Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f46) { - // Instruction: 5: 01011000ssssxxxx0011111101---110 | Rx = add (Rx, Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc6) { - // Instruction: 5: 01011000ssssxxxx0011111111---110 | Rx = add (Rx, Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003fc0) { - // Instruction: 5: 01011000ssssxxxx0011111111---0-- | Rx = add (Rx, Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58003000) { - // Instruction: 5: 01011000uuuuxxxx00110iiissssdddd | Rx = add (Rx, Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58002000) { - // Instruction: 5: 01011000uuuuxxxx00100iiissssdddd | Rx = add (Rx, Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58002800) { - // Instruction: 5: 01011000uuuuxxxx00101iiissssdddd | Rx = add (Rx, Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a703f40) { - // Instruction: 5: 0101101--111dddd0011111101---0-- | if (! p0) Rd = #0 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a703f00) { - // Instruction: 5: 0101101--111dddd0011111100---0-- | if (! p0) Rd = #0 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703f45) { - // Instruction: 5: 0101101--111dddd0011111101---101 | if (! p0) Rd = #0 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703fc5) { - // Instruction: 5: 0101101--111dddd0011111111---101 | if (! p0) Rd = #0 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703f47) { - // Instruction: 5: 0101101--111dddd0011111101---111 | if (! p0) Rd = #0 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703fc7) { - // Instruction: 5: 0101101--111dddd0011111111---111 | if (! p0) Rd = #0 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703f44) { - // Instruction: 5: 0101101--111dddd0011111101---100 | if (! p0) Rd = #0 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703fc4) { - // Instruction: 5: 0101101--111dddd0011111111---100 | if (! p0) Rd = #0 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703f46) { - // Instruction: 5: 0101101--111dddd0011111101---110 | if (! p0) Rd = #0 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703fc6) { - // Instruction: 5: 0101101--111dddd0011111111---110 | if (! p0) Rd = #0 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a703fc0) { - // Instruction: 5: 0101101--111dddd0011111111---0-- | if (! p0) Rd = #0 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a703000) { - // Instruction: 5: 0101101--111eeee00110iiissssdddd | if (! p0) Re = #0 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a702000) { - // Instruction: 5: 0101101--111eeee00100iiissssdddd | if (! p0) Re = #0 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a702800) { - // Instruction: 5: 0101101--111eeee00101iiissssdddd | if (! p0) Re = #0 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x5a703c00) { - // Instruction: 5: 0101101--111eeee0011110iiiiidddd | if (! p0) Re = #0 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x5a703e00) { - // Instruction: 5: 0101101--111eeee00111110iiiiiddd | if (! p0) Re = #0 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a503f40) { - // Instruction: 5: 0101101--101dddd0011111101---0-- | if (! p0.new) Rd = #0 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a503f00) { - // Instruction: 5: 0101101--101dddd0011111100---0-- | if (! p0.new) Rd = #0 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503f45) { - // Instruction: 5: 0101101--101dddd0011111101---101 | if (! p0.new) Rd = #0 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503fc5) { - // Instruction: 5: 0101101--101dddd0011111111---101 | if (! p0.new) Rd = #0 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503f47) { - // Instruction: 5: 0101101--101dddd0011111101---111 | if (! p0.new) Rd = #0 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503fc7) { - // Instruction: 5: 0101101--101dddd0011111111---111 | if (! p0.new) Rd = #0 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503f44) { - // Instruction: 5: 0101101--101dddd0011111101---100 | if (! p0.new) Rd = #0 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503fc4) { - // Instruction: 5: 0101101--101dddd0011111111---100 | if (! p0.new) Rd = #0 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503f46) { - // Instruction: 5: 0101101--101dddd0011111101---110 | if (! p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503fc6) { - // Instruction: 5: 0101101--101dddd0011111111---110 | if (! p0.new) Rd = #0 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a503fc0) { - // Instruction: 5: 0101101--101dddd0011111111---0-- | if (! p0.new) Rd = #0 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a503000) { - // Instruction: 5: 0101101--101eeee00110iiissssdddd | if (! p0.new) Re = #0 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a502000) { - // Instruction: 5: 0101101--101eeee00100iiissssdddd | if (! p0.new) Re = #0 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a502800) { - // Instruction: 5: 0101101--101eeee00101iiissssdddd | if (! p0.new) Re = #0 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x5a503c00) { - // Instruction: 5: 0101101--101eeee0011110iiiiidddd | if (! p0.new) Re = #0 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x5a503e00) { - // Instruction: 5: 0101101--101eeee00111110iiiiiddd | if (! p0.new) Re = #0 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a603f40) { - // Instruction: 5: 0101101--110dddd0011111101---0-- | if (p0) Rd = #0 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a603f00) { - // Instruction: 5: 0101101--110dddd0011111100---0-- | if (p0) Rd = #0 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603f45) { - // Instruction: 5: 0101101--110dddd0011111101---101 | if (p0) Rd = #0 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603fc5) { - // Instruction: 5: 0101101--110dddd0011111111---101 | if (p0) Rd = #0 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603f47) { - // Instruction: 5: 0101101--110dddd0011111101---111 | if (p0) Rd = #0 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603fc7) { - // Instruction: 5: 0101101--110dddd0011111111---111 | if (p0) Rd = #0 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603f44) { - // Instruction: 5: 0101101--110dddd0011111101---100 | if (p0) Rd = #0 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603fc4) { - // Instruction: 5: 0101101--110dddd0011111111---100 | if (p0) Rd = #0 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603f46) { - // Instruction: 5: 0101101--110dddd0011111101---110 | if (p0) Rd = #0 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603fc6) { - // Instruction: 5: 0101101--110dddd0011111111---110 | if (p0) Rd = #0 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a603fc0) { - // Instruction: 5: 0101101--110dddd0011111111---0-- | if (p0) Rd = #0 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a603000) { - // Instruction: 5: 0101101--110eeee00110iiissssdddd | if (p0) Re = #0 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a602000) { - // Instruction: 5: 0101101--110eeee00100iiissssdddd | if (p0) Re = #0 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a602800) { - // Instruction: 5: 0101101--110eeee00101iiissssdddd | if (p0) Re = #0 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x5a603c00) { - // Instruction: 5: 0101101--110eeee0011110iiiiidddd | if (p0) Re = #0 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x5a603e00) { - // Instruction: 5: 0101101--110eeee00111110iiiiiddd | if (p0) Re = #0 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a403f40) { - // Instruction: 5: 0101101--100dddd0011111101---0-- | if (p0.new) Rd = #0 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a403f00) { - // Instruction: 5: 0101101--100dddd0011111100---0-- | if (p0.new) Rd = #0 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403f45) { - // Instruction: 5: 0101101--100dddd0011111101---101 | if (p0.new) Rd = #0 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403fc5) { - // Instruction: 5: 0101101--100dddd0011111111---101 | if (p0.new) Rd = #0 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403f47) { - // Instruction: 5: 0101101--100dddd0011111101---111 | if (p0.new) Rd = #0 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403fc7) { - // Instruction: 5: 0101101--100dddd0011111111---111 | if (p0.new) Rd = #0 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403f44) { - // Instruction: 5: 0101101--100dddd0011111101---100 | if (p0.new) Rd = #0 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403fc4) { - // Instruction: 5: 0101101--100dddd0011111111---100 | if (p0.new) Rd = #0 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403f46) { - // Instruction: 5: 0101101--100dddd0011111101---110 | if (p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403fc6) { - // Instruction: 5: 0101101--100dddd0011111111---110 | if (p0.new) Rd = #0 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a403fc0) { - // Instruction: 5: 0101101--100dddd0011111111---0-- | if (p0.new) Rd = #0 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a403000) { - // Instruction: 5: 0101101--100eeee00110iiissssdddd | if (p0.new) Re = #0 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a402000) { - // Instruction: 5: 0101101--100eeee00100iiissssdddd | if (p0.new) Re = #0 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a402800) { - // Instruction: 5: 0101101--100eeee00101iiissssdddd | if (p0.new) Re = #0 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x5a403c00) { - // Instruction: 5: 0101101--100eeee0011110iiiiidddd | if (p0.new) Re = #0 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x5a403e00) { - // Instruction: 5: 0101101--100eeee00111110iiiiiddd | if (p0.new) Re = #0 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x59003c00) { - // Instruction: 5: 01011001ssss--II0011110iiiiidddd | p0 = cmp.eq (Rs, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x59003e00) { - // Instruction: 5: 01011001ssss--II00111110iiiiiddd | p0 = cmp.eq (Rs, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x59003f40) { - // Instruction: 5: 01011001ssss--ii0011111101---0-- | p0 = cmp.eq (Rs, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x59003f00) { - // Instruction: 5: 01011001ssss--ii0011111100---0-- | p0 = cmp.eq (Rs, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003f45) { - // Instruction: 5: 01011001ssss--ii0011111101---101 | p0 = cmp.eq (Rs, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003fc5) { - // Instruction: 5: 01011001ssss--ii0011111111---101 | p0 = cmp.eq (Rs, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003f47) { - // Instruction: 5: 01011001ssss--ii0011111101---111 | p0 = cmp.eq (Rs, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003fc7) { - // Instruction: 5: 01011001ssss--ii0011111111---111 | p0 = cmp.eq (Rs, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003f44) { - // Instruction: 5: 01011001ssss--ii0011111101---100 | p0 = cmp.eq (Rs, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003fc4) { - // Instruction: 5: 01011001ssss--ii0011111111---100 | p0 = cmp.eq (Rs, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003f46) { - // Instruction: 5: 01011001ssss--ii0011111101---110 | p0 = cmp.eq (Rs, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003fc6) { - // Instruction: 5: 01011001ssss--ii0011111111---110 | p0 = cmp.eq (Rs, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x59003fc0) { - // Instruction: 5: 01011001ssss--ii0011111111---0-- | p0 = cmp.eq (Rs, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x59003000) { - // Instruction: 5: 01011001uuuu--II00110iiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x59002000) { - // Instruction: 5: 01011001uuuu--II00100iiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x59002800) { - // Instruction: 5: 01011001uuuu--II00101iiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - break; - } - case 0x6: { - if ((hi_u32 & 0xfe40f000) == 0x7a001000) { - // Instruction: 6: 0111101--0--dddd0001iiiisssstttt | Rd = #-1 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe40f000) == 0x7a000000) { - // Instruction: 6: 0111101--0--dddd0000iiiisssstttt | Rd = #-1 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x68001000) { - // Instruction: 6: 011010IIIIIIdddd0001iiiisssstttt | Rd = #U6 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x68000000) { - // Instruction: 6: 011010IIIIIIdddd0000iiiisssstttt | Rd = #U6 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x70001000) { - // Instruction: 6: 01110000uuuudddd0001iiiisssstttt | Rd = Ru ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x70000000) { - // Instruction: 6: 01110000uuuudddd0000iiiisssstttt | Rd = Ru ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x73001000) { - // Instruction: 6: 01110011uuuudddd0001iiiisssstttt | Rd = add (Ru, #-1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x73000000) { - // Instruction: 6: 01110011uuuudddd0000iiiisssstttt | Rd = add (Ru, #-1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x71001000) { - // Instruction: 6: 01110001uuuudddd0001iiiisssstttt | Rd = add (Ru, #1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x71000000) { - // Instruction: 6: 01110001uuuudddd0000iiiisssstttt | Rd = add (Ru, #1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x6c001000) { - // Instruction: 6: 011011IIIIIIdddd0001iiiisssstttt | Rd = add (Sp, #U6:2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x6c000000) { - // Instruction: 6: 011011IIIIIIdddd0000iiiisssstttt | Rd = add (Sp, #U6:2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x72001000) { - // Instruction: 6: 01110010uuuudddd0001iiiisssstttt | Rd = and (Ru, #1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x72000000) { - // Instruction: 6: 01110010uuuudddd0000iiiisssstttt | Rd = and (Ru, #1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x77001000) { - // Instruction: 6: 01110111uuuudddd0001iiiisssstttt | Rd = and (Ru, #255) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x77000000) { - // Instruction: 6: 01110111uuuudddd0000iiiisssstttt | Rd = and (Ru, #255) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x75001000) { - // Instruction: 6: 01110101uuuudddd0001iiiisssstttt | Rd = sxtb (Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x75000000) { - // Instruction: 6: 01110101uuuudddd0000iiiisssstttt | Rd = sxtb (Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x74001000) { - // Instruction: 6: 01110100uuuudddd0001iiiisssstttt | Rd = sxth (Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x74000000) { - // Instruction: 6: 01110100uuuudddd0000iiiisssstttt | Rd = sxth (Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x76001000) { - // Instruction: 6: 01110110uuuudddd0001iiiisssstttt | Rd = zxth (Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x76000000) { - // Instruction: 6: 01110110uuuudddd0000iiiisssstttt | Rd = zxth (Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c001000) { - // Instruction: 6: 011111-0-II00ddd0001iiiisssstttt | Rdd = combine (#0, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c000000) { - // Instruction: 6: 011111-0-II00ddd0000iiiisssstttt | Rdd = combine (#0, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x7d001000) { - // Instruction: 6: 011111-1uuuu0ddd0001iiiisssstttt | Rdd = combine (#0, Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x7d000000) { - // Instruction: 6: 011111-1uuuu0ddd0000iiiisssstttt | Rdd = combine (#0, Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c081000) { - // Instruction: 6: 011111-0-II01ddd0001iiiisssstttt | Rdd = combine (#1, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c080000) { - // Instruction: 6: 011111-0-II01ddd0000iiiisssstttt | Rdd = combine (#1, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c101000) { - // Instruction: 6: 011111-0-II10ddd0001iiiisssstttt | Rdd = combine (#2, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c100000) { - // Instruction: 6: 011111-0-II10ddd0000iiiisssstttt | Rdd = combine (#2, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c181000) { - // Instruction: 6: 011111-0-II11ddd0001iiiisssstttt | Rdd = combine (#3, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c180000) { - // Instruction: 6: 011111-0-II11ddd0000iiiisssstttt | Rdd = combine (#3, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x7d081000) { - // Instruction: 6: 011111-1uuuu1ddd0001iiiisssstttt | Rdd = combine (Ru, #0) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x7d080000) { - // Instruction: 6: 011111-1uuuu1ddd0000iiiisssstttt | Rdd = combine (Ru, #0) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x78001000) { - // Instruction: 6: 01111000uuuuxxxx0001iiiisssstttt | Rx = add (Ru, Rx) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x78000000) { - // Instruction: 6: 01111000uuuuxxxx0000iiiisssstttt | Rx = add (Ru, Rx) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x60001000) { - // Instruction: 6: 01100IIIIIIIxxxx0001iiiisssstttt | Rx = add (Rx, #S7) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x60000000) { - // Instruction: 6: 01100IIIIIIIxxxx0000iiiisssstttt | Rx = add (Rx, #S7) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x78001000) { - // Instruction: 6: 01111000uuuuxxxx0001iiiisssstttt | Rx = add (Rx, Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x78000000) { - // Instruction: 6: 01111000uuuuxxxx0000iiiisssstttt | Rx = add (Rx, Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a701000) { - // Instruction: 6: 0111101--111dddd0001iiiisssstttt | if (! p0) Rd = #0 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a700000) { - // Instruction: 6: 0111101--111dddd0000iiiisssstttt | if (! p0) Rd = #0 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a501000) { - // Instruction: 6: 0111101--101dddd0001iiiisssstttt | if (! p0.new) Rd = #0 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a500000) { - // Instruction: 6: 0111101--101dddd0000iiiisssstttt | if (! p0.new) Rd = #0 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a601000) { - // Instruction: 6: 0111101--110dddd0001iiiisssstttt | if (p0) Rd = #0 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a600000) { - // Instruction: 6: 0111101--110dddd0000iiiisssstttt | if (p0) Rd = #0 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a401000) { - // Instruction: 6: 0111101--100dddd0001iiiisssstttt | if (p0.new) Rd = #0 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a400000) { - // Instruction: 6: 0111101--100dddd0000iiiisssstttt | if (p0.new) Rd = #0 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x79001000) { - // Instruction: 6: 01111001uuuu--II0001iiiisssstttt | p0 = cmp.eq (Ru, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x79000000) { - // Instruction: 6: 01111001uuuu--II0000iiiisssstttt | p0 = cmp.eq (Ru, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - break; - } - case 0x7: { - if ((hi_u32 & 0xfe40fe00) == 0x7a003c00) { - // Instruction: 7: 0111101--0--dddd0011110iiiii---- | Rd = #-1 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD_____1___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x7a003200) { - // Instruction: 7: 0111101--0--dddd00110010ssssiiii | Rd = #-1 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x7a003300) { - // Instruction: 7: 0111101--0--dddd00110011ssssiiii | Rd = #-1 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fe00) == 0x7a002a00) { - // Instruction: 7: 0111101--0--dddd0010101iiiiiittt | Rd = #-1 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe40f800) == 0x7a002000) { - // Instruction: 7: 0111101--0--dddd00100iiisssstttt | Rd = #-1 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x7a003000) { - // Instruction: 7: 0111101--0--dddd00110000ssssiiii | Rd = #-1 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x7a003100) { - // Instruction: 7: 0111101--0--dddd00110001ssssiiii | Rd = #-1 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fe00) == 0x7a002800) { - // Instruction: 7: 0111101--0--dddd0010100iiiiitttt | Rd = #-1 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x68003c00) { - // Instruction: 7: 011010IIIIIIdddd0011110iiiii---- | Rd = #U6 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD____U6___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x68003200) { - // Instruction: 7: 011010IIIIIIdddd00110010ssssiiii | Rd = #U6 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x68003300) { - // Instruction: 7: 011010IIIIIIdddd00110011ssssiiii | Rd = #U6 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x68002a00) { - // Instruction: 7: 011010IIIIIIdddd0010101iiiiiittt | Rd = #U6 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x68002000) { - // Instruction: 7: 011010IIIIIIdddd00100iiisssstttt | Rd = #U6 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x68003000) { - // Instruction: 7: 011010IIIIIIdddd00110000ssssiiii | Rd = #U6 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x68003100) { - // Instruction: 7: 011010IIIIIIdddd00110001ssssiiii | Rd = #U6 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x68002800) { - // Instruction: 7: 011010IIIIIIdddd0010100iiiiitttt | Rd = #U6 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x70003c00) { - // Instruction: 7: 01110000ssssdddd0011110iiiii---- | Rd = Rs ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___RS___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x70002a00) { - // Instruction: 7: 01110000ssssdddd0010101iiiiiittt | Rd = Rs ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___RS___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x70002800) { - // Instruction: 7: 01110000ssssdddd0010100iiiiitttt | Rd = Rs ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___RS___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x70003200) { - // Instruction: 7: 01110000uuuudddd00110010ssssiiii | Rd = Ru ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x70003300) { - // Instruction: 7: 01110000uuuudddd00110011ssssiiii | Rd = Ru ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x70002000) { - // Instruction: 7: 01110000uuuudddd00100iiisssstttt | Rd = Ru ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x70003000) { - // Instruction: 7: 01110000uuuudddd00110000ssssiiii | Rd = Ru ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x70003100) { - // Instruction: 7: 01110000uuuudddd00110001ssssiiii | Rd = Ru ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x73003c00) { - // Instruction: 7: 01110011ssssdddd0011110iiiii---- | Rd = add (Rs, #-1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x73002a00) { - // Instruction: 7: 01110011ssssdddd0010101iiiiiittt | Rd = add (Rs, #-1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x73002800) { - // Instruction: 7: 01110011ssssdddd0010100iiiiitttt | Rd = add (Rs, #-1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x71003c00) { - // Instruction: 7: 01110001ssssdddd0011110iiiii---- | Rd = add (Rs, #1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x71002a00) { - // Instruction: 7: 01110001ssssdddd0010101iiiiiittt | Rd = add (Rs, #1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x71002800) { - // Instruction: 7: 01110001ssssdddd0010100iiiiitttt | Rd = add (Rs, #1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x73003200) { - // Instruction: 7: 01110011uuuudddd00110010ssssiiii | Rd = add (Ru, #-1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x73003300) { - // Instruction: 7: 01110011uuuudddd00110011ssssiiii | Rd = add (Ru, #-1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x73002000) { - // Instruction: 7: 01110011uuuudddd00100iiisssstttt | Rd = add (Ru, #-1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x73003000) { - // Instruction: 7: 01110011uuuudddd00110000ssssiiii | Rd = add (Ru, #-1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x73003100) { - // Instruction: 7: 01110011uuuudddd00110001ssssiiii | Rd = add (Ru, #-1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x71003200) { - // Instruction: 7: 01110001uuuudddd00110010ssssiiii | Rd = add (Ru, #1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x71003300) { - // Instruction: 7: 01110001uuuudddd00110011ssssiiii | Rd = add (Ru, #1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x71002000) { - // Instruction: 7: 01110001uuuudddd00100iiisssstttt | Rd = add (Ru, #1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x71003000) { - // Instruction: 7: 01110001uuuudddd00110000ssssiiii | Rd = add (Ru, #1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x71003100) { - // Instruction: 7: 01110001uuuudddd00110001ssssiiii | Rd = add (Ru, #1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x6c003c00) { - // Instruction: 7: 011011IIIIIIdddd0011110iiiii---- | Rd = add (Sp, #U6:2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x6c003200) { - // Instruction: 7: 011011IIIIIIdddd00110010ssssiiii | Rd = add (Sp, #U6:2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x6c003300) { - // Instruction: 7: 011011IIIIIIdddd00110011ssssiiii | Rd = add (Sp, #U6:2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x6c002a00) { - // Instruction: 7: 011011IIIIIIdddd0010101iiiiiittt | Rd = add (Sp, #U6:2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x6c002000) { - // Instruction: 7: 011011IIIIIIdddd00100iiisssstttt | Rd = add (Sp, #U6:2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x6c003000) { - // Instruction: 7: 011011IIIIIIdddd00110000ssssiiii | Rd = add (Sp, #U6:2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x6c003100) { - // Instruction: 7: 011011IIIIIIdddd00110001ssssiiii | Rd = add (Sp, #U6:2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x6c002800) { - // Instruction: 7: 011011IIIIIIdddd0010100iiiiitttt | Rd = add (Sp, #U6:2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x72003c00) { - // Instruction: 7: 01110010ssssdddd0011110iiiii---- | Rd = and (Rs, #1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x72002a00) { - // Instruction: 7: 01110010ssssdddd0010101iiiiiittt | Rd = and (Rs, #1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x72002800) { - // Instruction: 7: 01110010ssssdddd0010100iiiiitttt | Rd = and (Rs, #1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x77003c00) { - // Instruction: 7: 01110111ssssdddd0011110iiiii---- | Rd = and (Rs, #255) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x77002a00) { - // Instruction: 7: 01110111ssssdddd0010101iiiiiittt | Rd = and (Rs, #255) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x77002800) { - // Instruction: 7: 01110111ssssdddd0010100iiiiitttt | Rd = and (Rs, #255) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x72003200) { - // Instruction: 7: 01110010uuuudddd00110010ssssiiii | Rd = and (Ru, #1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x72003300) { - // Instruction: 7: 01110010uuuudddd00110011ssssiiii | Rd = and (Ru, #1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x72002000) { - // Instruction: 7: 01110010uuuudddd00100iiisssstttt | Rd = and (Ru, #1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x72003000) { - // Instruction: 7: 01110010uuuudddd00110000ssssiiii | Rd = and (Ru, #1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x72003100) { - // Instruction: 7: 01110010uuuudddd00110001ssssiiii | Rd = and (Ru, #1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x77003200) { - // Instruction: 7: 01110111uuuudddd00110010ssssiiii | Rd = and (Ru, #255) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x77003300) { - // Instruction: 7: 01110111uuuudddd00110011ssssiiii | Rd = and (Ru, #255) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x77002000) { - // Instruction: 7: 01110111uuuudddd00100iiisssstttt | Rd = and (Ru, #255) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x77003000) { - // Instruction: 7: 01110111uuuudddd00110000ssssiiii | Rd = and (Ru, #255) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x77003100) { - // Instruction: 7: 01110111uuuudddd00110001ssssiiii | Rd = and (Ru, #255) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x75003c00) { - // Instruction: 7: 01110101ssssdddd0011110iiiii---- | Rd = sxtb (Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x75002a00) { - // Instruction: 7: 01110101ssssdddd0010101iiiiiittt | Rd = sxtb (Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x75002800) { - // Instruction: 7: 01110101ssssdddd0010100iiiiitttt | Rd = sxtb (Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x75003200) { - // Instruction: 7: 01110101uuuudddd00110010ssssiiii | Rd = sxtb (Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x75003300) { - // Instruction: 7: 01110101uuuudddd00110011ssssiiii | Rd = sxtb (Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x75002000) { - // Instruction: 7: 01110101uuuudddd00100iiisssstttt | Rd = sxtb (Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x75003000) { - // Instruction: 7: 01110101uuuudddd00110000ssssiiii | Rd = sxtb (Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x75003100) { - // Instruction: 7: 01110101uuuudddd00110001ssssiiii | Rd = sxtb (Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x74003c00) { - // Instruction: 7: 01110100ssssdddd0011110iiiii---- | Rd = sxth (Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x74002a00) { - // Instruction: 7: 01110100ssssdddd0010101iiiiiittt | Rd = sxth (Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x74002800) { - // Instruction: 7: 01110100ssssdddd0010100iiiiitttt | Rd = sxth (Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x74003200) { - // Instruction: 7: 01110100uuuudddd00110010ssssiiii | Rd = sxth (Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x74003300) { - // Instruction: 7: 01110100uuuudddd00110011ssssiiii | Rd = sxth (Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x74002000) { - // Instruction: 7: 01110100uuuudddd00100iiisssstttt | Rd = sxth (Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x74003000) { - // Instruction: 7: 01110100uuuudddd00110000ssssiiii | Rd = sxth (Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x74003100) { - // Instruction: 7: 01110100uuuudddd00110001ssssiiii | Rd = sxth (Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x76003c00) { - // Instruction: 7: 01110110ssssdddd0011110iiiii---- | Rd = zxth (Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x76002a00) { - // Instruction: 7: 01110110ssssdddd0010101iiiiiittt | Rd = zxth (Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x76002800) { - // Instruction: 7: 01110110ssssdddd0010100iiiiitttt | Rd = zxth (Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x76003200) { - // Instruction: 7: 01110110uuuudddd00110010ssssiiii | Rd = zxth (Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x76003300) { - // Instruction: 7: 01110110uuuudddd00110011ssssiiii | Rd = zxth (Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x76002000) { - // Instruction: 7: 01110110uuuudddd00100iiisssstttt | Rd = zxth (Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x76003000) { - // Instruction: 7: 01110110uuuudddd00110000ssssiiii | Rd = zxth (Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x76003100) { - // Instruction: 7: 01110110uuuudddd00110001ssssiiii | Rd = zxth (Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c003c00) { - // Instruction: 7: 011111-0-II00ddd0011110iiiii---- | Rdd = combine (#0, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c003200) { - // Instruction: 7: 011111-0-II00ddd00110010ssssiiii | Rdd = combine (#0, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c003300) { - // Instruction: 7: 011111-0-II00ddd00110011ssssiiii | Rdd = combine (#0, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c002a00) { - // Instruction: 7: 011111-0-II00ddd0010101iiiiiittt | Rdd = combine (#0, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x7c002000) { - // Instruction: 7: 011111-0-II00ddd00100iiisssstttt | Rdd = combine (#0, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c003000) { - // Instruction: 7: 011111-0-II00ddd00110000ssssiiii | Rdd = combine (#0, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c003100) { - // Instruction: 7: 011111-0-II00ddd00110001ssssiiii | Rdd = combine (#0, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c002800) { - // Instruction: 7: 011111-0-II00ddd0010100iiiiitttt | Rdd = combine (#0, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d003c00) { - // Instruction: 7: 011111-1ssss0ddd0011110iiiii---- | Rdd = combine (#0, Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d002a00) { - // Instruction: 7: 011111-1ssss0ddd0010101iiiiiittt | Rdd = combine (#0, Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d002800) { - // Instruction: 7: 011111-1ssss0ddd0010100iiiiitttt | Rdd = combine (#0, Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d003200) { - // Instruction: 7: 011111-1uuuu0ddd00110010ssssiiii | Rdd = combine (#0, Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d003300) { - // Instruction: 7: 011111-1uuuu0ddd00110011ssssiiii | Rdd = combine (#0, Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x7d002000) { - // Instruction: 7: 011111-1uuuu0ddd00100iiisssstttt | Rdd = combine (#0, Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d003000) { - // Instruction: 7: 011111-1uuuu0ddd00110000ssssiiii | Rdd = combine (#0, Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d003100) { - // Instruction: 7: 011111-1uuuu0ddd00110001ssssiiii | Rdd = combine (#0, Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c083c00) { - // Instruction: 7: 011111-0-II01ddd0011110iiiii---- | Rdd = combine (#1, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c083200) { - // Instruction: 7: 011111-0-II01ddd00110010ssssiiii | Rdd = combine (#1, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c083300) { - // Instruction: 7: 011111-0-II01ddd00110011ssssiiii | Rdd = combine (#1, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c082a00) { - // Instruction: 7: 011111-0-II01ddd0010101iiiiiittt | Rdd = combine (#1, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x7c082000) { - // Instruction: 7: 011111-0-II01ddd00100iiisssstttt | Rdd = combine (#1, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c083000) { - // Instruction: 7: 011111-0-II01ddd00110000ssssiiii | Rdd = combine (#1, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c083100) { - // Instruction: 7: 011111-0-II01ddd00110001ssssiiii | Rdd = combine (#1, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c082800) { - // Instruction: 7: 011111-0-II01ddd0010100iiiiitttt | Rdd = combine (#1, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c103c00) { - // Instruction: 7: 011111-0-II10ddd0011110iiiii---- | Rdd = combine (#2, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c103200) { - // Instruction: 7: 011111-0-II10ddd00110010ssssiiii | Rdd = combine (#2, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c103300) { - // Instruction: 7: 011111-0-II10ddd00110011ssssiiii | Rdd = combine (#2, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c102a00) { - // Instruction: 7: 011111-0-II10ddd0010101iiiiiittt | Rdd = combine (#2, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x7c102000) { - // Instruction: 7: 011111-0-II10ddd00100iiisssstttt | Rdd = combine (#2, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c103000) { - // Instruction: 7: 011111-0-II10ddd00110000ssssiiii | Rdd = combine (#2, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c103100) { - // Instruction: 7: 011111-0-II10ddd00110001ssssiiii | Rdd = combine (#2, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c102800) { - // Instruction: 7: 011111-0-II10ddd0010100iiiiitttt | Rdd = combine (#2, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c183c00) { - // Instruction: 7: 011111-0-II11ddd0011110iiiii---- | Rdd = combine (#3, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c183200) { - // Instruction: 7: 011111-0-II11ddd00110010ssssiiii | Rdd = combine (#3, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c183300) { - // Instruction: 7: 011111-0-II11ddd00110011ssssiiii | Rdd = combine (#3, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c182a00) { - // Instruction: 7: 011111-0-II11ddd0010101iiiiiittt | Rdd = combine (#3, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x7c182000) { - // Instruction: 7: 011111-0-II11ddd00100iiisssstttt | Rdd = combine (#3, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c183000) { - // Instruction: 7: 011111-0-II11ddd00110000ssssiiii | Rdd = combine (#3, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c183100) { - // Instruction: 7: 011111-0-II11ddd00110001ssssiiii | Rdd = combine (#3, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c182800) { - // Instruction: 7: 011111-0-II11ddd0010100iiiiitttt | Rdd = combine (#3, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d083c00) { - // Instruction: 7: 011111-1ssss1ddd0011110iiiii---- | Rdd = combine (Rs, #0) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d082a00) { - // Instruction: 7: 011111-1ssss1ddd0010101iiiiiittt | Rdd = combine (Rs, #0) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d082800) { - // Instruction: 7: 011111-1ssss1ddd0010100iiiiitttt | Rdd = combine (Rs, #0) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d083200) { - // Instruction: 7: 011111-1uuuu1ddd00110010ssssiiii | Rdd = combine (Ru, #0) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d083300) { - // Instruction: 7: 011111-1uuuu1ddd00110011ssssiiii | Rdd = combine (Ru, #0) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x7d082000) { - // Instruction: 7: 011111-1uuuu1ddd00100iiisssstttt | Rdd = combine (Ru, #0) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d083000) { - // Instruction: 7: 011111-1uuuu1ddd00110000ssssiiii | Rdd = combine (Ru, #0) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d083100) { - // Instruction: 7: 011111-1uuuu1ddd00110001ssssiiii | Rdd = combine (Ru, #0) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78003c00) { - // Instruction: 7: 01111000ssssxxxx0011110iiiii---- | Rx = add (Rs, Rx) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78002a00) { - // Instruction: 7: 01111000ssssxxxx0010101iiiiiittt | Rx = add (Rs, Rx) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78002800) { - // Instruction: 7: 01111000ssssxxxx0010100iiiiitttt | Rx = add (Rs, Rx) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003200) { - // Instruction: 7: 01111000uuuuxxxx00110010ssssiiii | Rx = add (Ru, Rx) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003300) { - // Instruction: 7: 01111000uuuuxxxx00110011ssssiiii | Rx = add (Ru, Rx) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x78002000) { - // Instruction: 7: 01111000uuuuxxxx00100iiisssstttt | Rx = add (Ru, Rx) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003000) { - // Instruction: 7: 01111000uuuuxxxx00110000ssssiiii | Rx = add (Ru, Rx) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003100) { - // Instruction: 7: 01111000uuuuxxxx00110001ssssiiii | Rx = add (Ru, Rx) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x60003c00) { - // Instruction: 7: 01100IIIIIIIxxxx0011110iiiii---- | Rx = add (Rx, #S7) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x60003200) { - // Instruction: 7: 01100IIIIIIIxxxx00110010ssssiiii | Rx = add (Rx, #S7) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x60003300) { - // Instruction: 7: 01100IIIIIIIxxxx00110011ssssiiii | Rx = add (Rx, #S7) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x60002a00) { - // Instruction: 7: 01100IIIIIIIxxxx0010101iiiiiittt | Rx = add (Rx, #S7) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800f800) == 0x60002000) { - // Instruction: 7: 01100IIIIIIIxxxx00100iiisssstttt | Rx = add (Rx, #S7) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x60003000) { - // Instruction: 7: 01100IIIIIIIxxxx00110000ssssiiii | Rx = add (Rx, #S7) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x60003100) { - // Instruction: 7: 01100IIIIIIIxxxx00110001ssssiiii | Rx = add (Rx, #S7) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x60002800) { - // Instruction: 7: 01100IIIIIIIxxxx0010100iiiiitttt | Rx = add (Rx, #S7) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78003c00) { - // Instruction: 7: 01111000ssssxxxx0011110iiiii---- | Rx = add (Rx, Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78002a00) { - // Instruction: 7: 01111000ssssxxxx0010101iiiiiittt | Rx = add (Rx, Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78002800) { - // Instruction: 7: 01111000ssssxxxx0010100iiiiitttt | Rx = add (Rx, Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003200) { - // Instruction: 7: 01111000uuuuxxxx00110010ssssiiii | Rx = add (Rx, Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003300) { - // Instruction: 7: 01111000uuuuxxxx00110011ssssiiii | Rx = add (Rx, Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x78002000) { - // Instruction: 7: 01111000uuuuxxxx00100iiisssstttt | Rx = add (Rx, Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003000) { - // Instruction: 7: 01111000uuuuxxxx00110000ssssiiii | Rx = add (Rx, Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003100) { - // Instruction: 7: 01111000uuuuxxxx00110001ssssiiii | Rx = add (Rx, Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a703c00) { - // Instruction: 7: 0111101--111dddd0011110iiiii---- | if (! p0) Rd = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a703200) { - // Instruction: 7: 0111101--111dddd00110010ssssiiii | if (! p0) Rd = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a703300) { - // Instruction: 7: 0111101--111dddd00110011ssssiiii | if (! p0) Rd = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a702a00) { - // Instruction: 7: 0111101--111dddd0010101iiiiiittt | if (! p0) Rd = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x7a702000) { - // Instruction: 7: 0111101--111dddd00100iiisssstttt | if (! p0) Rd = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a703000) { - // Instruction: 7: 0111101--111dddd00110000ssssiiii | if (! p0) Rd = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a703100) { - // Instruction: 7: 0111101--111dddd00110001ssssiiii | if (! p0) Rd = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a702800) { - // Instruction: 7: 0111101--111dddd0010100iiiiitttt | if (! p0) Rd = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a503c00) { - // Instruction: 7: 0111101--101dddd0011110iiiii---- | if (! p0.new) Rd = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a503200) { - // Instruction: 7: 0111101--101dddd00110010ssssiiii | if (! p0.new) Rd = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a503300) { - // Instruction: 7: 0111101--101dddd00110011ssssiiii | if (! p0.new) Rd = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a502a00) { - // Instruction: 7: 0111101--101dddd0010101iiiiiittt | if (! p0.new) Rd = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x7a502000) { - // Instruction: 7: 0111101--101dddd00100iiisssstttt | if (! p0.new) Rd = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a503000) { - // Instruction: 7: 0111101--101dddd00110000ssssiiii | if (! p0.new) Rd = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a503100) { - // Instruction: 7: 0111101--101dddd00110001ssssiiii | if (! p0.new) Rd = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a502800) { - // Instruction: 7: 0111101--101dddd0010100iiiiitttt | if (! p0.new) Rd = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a603c00) { - // Instruction: 7: 0111101--110dddd0011110iiiii---- | if (p0) Rd = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a603200) { - // Instruction: 7: 0111101--110dddd00110010ssssiiii | if (p0) Rd = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a603300) { - // Instruction: 7: 0111101--110dddd00110011ssssiiii | if (p0) Rd = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a602a00) { - // Instruction: 7: 0111101--110dddd0010101iiiiiittt | if (p0) Rd = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x7a602000) { - // Instruction: 7: 0111101--110dddd00100iiisssstttt | if (p0) Rd = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a603000) { - // Instruction: 7: 0111101--110dddd00110000ssssiiii | if (p0) Rd = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a603100) { - // Instruction: 7: 0111101--110dddd00110001ssssiiii | if (p0) Rd = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a602800) { - // Instruction: 7: 0111101--110dddd0010100iiiiitttt | if (p0) Rd = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a403c00) { - // Instruction: 7: 0111101--100dddd0011110iiiii---- | if (p0.new) Rd = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a403200) { - // Instruction: 7: 0111101--100dddd00110010ssssiiii | if (p0.new) Rd = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a403300) { - // Instruction: 7: 0111101--100dddd00110011ssssiiii | if (p0.new) Rd = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a402a00) { - // Instruction: 7: 0111101--100dddd0010101iiiiiittt | if (p0.new) Rd = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32) hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x7a402000) { - // Instruction: 7: 0111101--100dddd00100iiisssstttt | if (p0.new) Rd = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a403000) { - // Instruction: 7: 0111101--100dddd00110000ssssiiii | if (p0.new) Rd = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a403100) { - // Instruction: 7: 0111101--100dddd00110001ssssiiii | if (p0.new) Rd = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a402800) { - // Instruction: 7: 0111101--100dddd0010100iiiiitttt | if (p0.new) Rd = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x79003c00) { - // Instruction: 7: 01111001ssss--II0011110iiiii---- | p0 = cmp.eq (Rs, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x79002a00) { - // Instruction: 7: 01111001ssss--II0010101iiiiiittt | p0 = cmp.eq (Rs, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x79002800) { - // Instruction: 7: 01111001ssss--II0010100iiiiitttt | p0 = cmp.eq (Rs, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x79003200) { - // Instruction: 7: 01111001uuuu--II00110010ssssiiii | p0 = cmp.eq (Ru, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x79003300) { - // Instruction: 7: 01111001uuuu--II00110011ssssiiii | p0 = cmp.eq (Ru, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x79002000) { - // Instruction: 7: 01111001uuuu--II00100iiisssstttt | p0 = cmp.eq (Ru, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x79003000) { - // Instruction: 7: 01111001uuuu--II00110000ssssiiii | p0 = cmp.eq (Ru, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x79003100) { - // Instruction: 7: 01111001uuuu--II00110001ssssiiii | p0 = cmp.eq (Ru, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - break; - } - case 0x8: { - if ((hi_u32 & 0xf000f000) == 0x90001000) { - // Instruction: 8: 1001IIIIuuuudddd0001iiiisssstttt | Rd = memub (Ru + #U4:0) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0x90000000) { - // Instruction: 8: 1001IIIIuuuudddd0000iiiisssstttt | Rd = memub (Ru + #U4:0) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0x80001000) { - // Instruction: 8: 1000IIIIuuuudddd0001iiiisssstttt | Rd = memw (Ru + #U4:2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0x80000000) { - // Instruction: 8: 1000IIIIuuuudddd0000iiiisssstttt | Rd = memw (Ru + #U4:2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - break; - } - case 0x9: { - if ((hi_u32 & 0xf800f000) == 0x90003000) { - // Instruction: 9: 10010IIIuuuudddd0011iiiisssstttt | Rd = memb (Ru + #U3:0) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x90002000) { - // Instruction: 9: 10010IIIuuuudddd0010iiiisssstttt | Rd = memb (Ru + #U3:0) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x80003000) { - // Instruction: 9: 10000IIIuuuudddd0011iiiisssstttt | Rd = memh (Ru + #U3:1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x80002000) { - // Instruction: 9: 10000IIIuuuudddd0010iiiisssstttt | Rd = memh (Ru + #U3:1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x88003000) { - // Instruction: 9: 10001IIIuuuudddd0011iiiisssstttt | Rd = memuh (Ru + #U3:1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x88002000) { - // Instruction: 9: 10001IIIuuuudddd0010iiiisssstttt | Rd = memuh (Ru + #U3:1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f000) == 0x9c003000) { - // Instruction: 9: 1001110IIIIIdddd0011iiiisssstttt | Rd = memw (Sp + #U5:2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f000) == 0x9c002000) { - // Instruction: 9: 1001110IIIIIdddd0010iiiisssstttt | Rd = memw (Sp + #U5:2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x9e003000) { - // Instruction: 9: 10011110IIIIIddd0011iiiisssstttt | Rdd = memd (Sp + #U5:3) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x9e002000) { - // Instruction: 9: 10011110IIIIIddd0010iiiisssstttt | Rdd = memd (Sp + #U5:3) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xffc4f000) == 0x9f003000) { - // Instruction: 9: 1001111100---0--0011iiiisssstttt | deallocframe ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMB__RS____U4_0____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xffc4f000) == 0x9f002000) { - // Instruction: 9: 1001111100---0--0010iiiisssstttt | deallocframe ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__RS____U4_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - break; - } - case 0xa: { - if ((hi_u32 & 0xf000f000) == 0xb0001000) { - // Instruction: 10: 1011IIIIuuuuvvvv0001iiiisssstttt | memb (Ru + #U4:0) = Rv ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RV___MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0xb0000000) { - // Instruction: 10: 1011IIIIuuuuvvvv0000iiiisssstttt | memb (Ru + #U4:0) = Rv ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RV___MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0xa0001000) { - // Instruction: 10: 1010IIIIuuuuvvvv0001iiiisssstttt | memw (Ru + #U4:2) = Rv ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RV___MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0xa0000000) { - // Instruction: 10: 1010IIIIuuuuvvvv0000iiiisssstttt | memw (Ru + #U4:2) = Rv ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RV___MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - break; - } - case 0xb: { - if ((hi_u32 & 0xf000fe00) == 0xb0003c00) { - // Instruction: 11: 1011IIIIsssstttt0011110iiiii---- | memb (Rs + #U4:0) = Rt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0____RT___ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xb0002a00) { - // Instruction: 11: 1011IIIIssssvvvv0010101iiiiiittt | memb (Rs + #U4:0) = Rv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0____RV___MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), (st32) hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xb0002800) { - // Instruction: 11: 1011IIIIssssvvvv0010100iiiiitttt | memb (Rs + #U4:0) = Rv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0____RV___MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xb0003200) { - // Instruction: 11: 1011IIIIuuuutttt00110010ssssiiii | memb (Ru + #U4:0) = Rt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RT___MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xb0003300) { - // Instruction: 11: 1011IIIIuuuutttt00110011ssssiiii | memb (Ru + #U4:0) = Rt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RT___MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xb0003000) { - // Instruction: 11: 1011IIIIuuuutttt00110000ssssiiii | memb (Ru + #U4:0) = Rt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RT___MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xb0003100) { - // Instruction: 11: 1011IIIIuuuutttt00110001ssssiiii | memb (Ru + #U4:0) = Rt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RT___MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0xb0002000) { - // Instruction: 11: 1011IIIIuuuuvvvv00100iiisssstttt | memb (Ru + #U4:0) = Rv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RV___MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xa0003c00) { - // Instruction: 11: 1010IIIIsssstttt0011110iiiii---- | memw (Rs + #U4:2) = Rt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2____RT___ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xa0002a00) { - // Instruction: 11: 1010IIIIssssvvvv0010101iiiiiittt | memw (Rs + #U4:2) = Rv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2____RV___MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), (st32) hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xa0002800) { - // Instruction: 11: 1010IIIIssssvvvv0010100iiiiitttt | memw (Rs + #U4:2) = Rv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2____RV___MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xa0003200) { - // Instruction: 11: 1010IIIIuuuutttt00110010ssssiiii | memw (Ru + #U4:2) = Rt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RT___MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xa0003300) { - // Instruction: 11: 1010IIIIuuuutttt00110011ssssiiii | memw (Ru + #U4:2) = Rt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RT___MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xa0003000) { - // Instruction: 11: 1010IIIIuuuutttt00110000ssssiiii | memw (Ru + #U4:2) = Rt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RT___MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xa0003100) { - // Instruction: 11: 1010IIIIuuuutttt00110001ssssiiii | memw (Ru + #U4:2) = Rt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RT___MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0xa0002000) { - // Instruction: 11: 1010IIIIuuuuvvvv00100iiisssstttt | memw (Ru + #U4:2) = Rv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RV___MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - break; - } - case 0xc: { - if ((hi_u32 & 0xf000fe00) == 0xd0001c00) { - // Instruction: 12: 1101IIIIssssdddd0001110iiiii---- | Rd = memub (Rs + #U4:0) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xd0000a00) { - // Instruction: 12: 1101IIIIssssdddd0000101iiiiiittt | Rd = memub (Rs + #U4:0) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32) hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xd0000800) { - // Instruction: 12: 1101IIIIssssdddd0000100iiiiitttt | Rd = memub (Rs + #U4:0) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xd0001200) { - // Instruction: 12: 1101IIIIuuuudddd00010010ssssiiii | Rd = memub (Ru + #U4:0) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xd0001300) { - // Instruction: 12: 1101IIIIuuuudddd00010011ssssiiii | Rd = memub (Ru + #U4:0) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0xd0000000) { - // Instruction: 12: 1101IIIIuuuudddd00000iiisssstttt | Rd = memub (Ru + #U4:0) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xd0001000) { - // Instruction: 12: 1101IIIIuuuudddd00010000ssssiiii | Rd = memub (Ru + #U4:0) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xd0001100) { - // Instruction: 12: 1101IIIIuuuudddd00010001ssssiiii | Rd = memub (Ru + #U4:0) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xc0001c00) { - // Instruction: 12: 1100IIIIssssdddd0001110iiiii---- | Rd = memw (Rs + #U4:2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xc0000a00) { - // Instruction: 12: 1100IIIIssssdddd0000101iiiiiittt | Rd = memw (Rs + #U4:2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32) hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xc0000800) { - // Instruction: 12: 1100IIIIssssdddd0000100iiiiitttt | Rd = memw (Rs + #U4:2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xc0001200) { - // Instruction: 12: 1100IIIIuuuudddd00010010ssssiiii | Rd = memw (Ru + #U4:2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xc0001300) { - // Instruction: 12: 1100IIIIuuuudddd00010011ssssiiii | Rd = memw (Ru + #U4:2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0xc0000000) { - // Instruction: 12: 1100IIIIuuuudddd00000iiisssstttt | Rd = memw (Ru + #U4:2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xc0001000) { - // Instruction: 12: 1100IIIIuuuudddd00010000ssssiiii | Rd = memw (Ru + #U4:2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xc0001100) { - // Instruction: 12: 1100IIIIuuuudddd00010001ssssiiii | Rd = memw (Ru + #U4:2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - break; - } - case 0xd: { - if ((hi_u32 & 0xf800fe00) == 0xd0003c00) { - // Instruction: 13: 11010IIIssssdddd0011110iiiii---- | Rd = memb (Rs + #U3:0) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xd0002a00) { - // Instruction: 13: 11010IIIssssdddd0010101iiiiiittt | Rd = memb (Rs + #U3:0) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32) hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xd0002800) { - // Instruction: 13: 11010IIIssssdddd0010100iiiiitttt | Rd = memb (Rs + #U3:0) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xd0003200) { - // Instruction: 13: 11010IIIuuuudddd00110010ssssiiii | Rd = memb (Ru + #U3:0) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xd0003300) { - // Instruction: 13: 11010IIIuuuudddd00110011ssssiiii | Rd = memb (Ru + #U3:0) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0xd0002000) { - // Instruction: 13: 11010IIIuuuudddd00100iiisssstttt | Rd = memb (Ru + #U3:0) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xd0003000) { - // Instruction: 13: 11010IIIuuuudddd00110000ssssiiii | Rd = memb (Ru + #U3:0) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xd0003100) { - // Instruction: 13: 11010IIIuuuudddd00110001ssssiiii | Rd = memb (Ru + #U3:0) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc0003c00) { - // Instruction: 13: 11000IIIssssdddd0011110iiiii---- | Rd = memh (Rs + #U3:1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc0002a00) { - // Instruction: 13: 11000IIIssssdddd0010101iiiiiittt | Rd = memh (Rs + #U3:1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32) hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc0002800) { - // Instruction: 13: 11000IIIssssdddd0010100iiiiitttt | Rd = memh (Rs + #U3:1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc0003200) { - // Instruction: 13: 11000IIIuuuudddd00110010ssssiiii | Rd = memh (Ru + #U3:1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc0003300) { - // Instruction: 13: 11000IIIuuuudddd00110011ssssiiii | Rd = memh (Ru + #U3:1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0xc0002000) { - // Instruction: 13: 11000IIIuuuudddd00100iiisssstttt | Rd = memh (Ru + #U3:1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc0003000) { - // Instruction: 13: 11000IIIuuuudddd00110000ssssiiii | Rd = memh (Ru + #U3:1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc0003100) { - // Instruction: 13: 11000IIIuuuudddd00110001ssssiiii | Rd = memh (Ru + #U3:1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc8003c00) { - // Instruction: 13: 11001IIIssssdddd0011110iiiii---- | Rd = memuh (Rs + #U3:1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc8002a00) { - // Instruction: 13: 11001IIIssssdddd0010101iiiiiittt | Rd = memuh (Rs + #U3:1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32) hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc8002800) { - // Instruction: 13: 11001IIIssssdddd0010100iiiiitttt | Rd = memuh (Rs + #U3:1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc8003200) { - // Instruction: 13: 11001IIIuuuudddd00110010ssssiiii | Rd = memuh (Ru + #U3:1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc8003300) { - // Instruction: 13: 11001IIIuuuudddd00110011ssssiiii | Rd = memuh (Ru + #U3:1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0xc8002000) { - // Instruction: 13: 11001IIIuuuudddd00100iiisssstttt | Rd = memuh (Ru + #U3:1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc8003000) { - // Instruction: 13: 11001IIIuuuudddd00110000ssssiiii | Rd = memuh (Ru + #U3:1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc8003100) { - // Instruction: 13: 11001IIIuuuudddd00110001ssssiiii | Rd = memuh (Ru + #U3:1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xdc003c00) { - // Instruction: 13: 1101110IIIIIdddd0011110iiiii---- | Rd = memw (Sp + #U5:2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xdc003200) { - // Instruction: 13: 1101110IIIIIdddd00110010ssssiiii | Rd = memw (Sp + #U5:2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xdc003300) { - // Instruction: 13: 1101110IIIIIdddd00110011ssssiiii | Rd = memw (Sp + #U5:2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xdc002a00) { - // Instruction: 13: 1101110IIIIIdddd0010101iiiiiittt | Rd = memw (Sp + #U5:2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f800) == 0xdc002000) { - // Instruction: 13: 1101110IIIIIdddd00100iiisssstttt | Rd = memw (Sp + #U5:2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xdc003000) { - // Instruction: 13: 1101110IIIIIdddd00110000ssssiiii | Rd = memw (Sp + #U5:2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xdc003100) { - // Instruction: 13: 1101110IIIIIdddd00110001ssssiiii | Rd = memw (Sp + #U5:2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xdc002800) { - // Instruction: 13: 1101110IIIIIdddd0010100iiiiitttt | Rd = memw (Sp + #U5:2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xde003c00) { - // Instruction: 13: 11011110IIIIIddd0011110iiiii---- | Rdd = memd (Sp + #U5:3) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xde003200) { - // Instruction: 13: 11011110IIIIIddd00110010ssssiiii | Rdd = memd (Sp + #U5:3) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xde003300) { - // Instruction: 13: 11011110IIIIIddd00110011ssssiiii | Rdd = memd (Sp + #U5:3) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xde002a00) { - // Instruction: 13: 11011110IIIIIddd0010101iiiiiittt | Rdd = memd (Sp + #U5:3) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00f800) == 0xde002000) { - // Instruction: 13: 11011110IIIIIddd00100iiisssstttt | Rdd = memd (Sp + #U5:3) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xde003000) { - // Instruction: 13: 11011110IIIIIddd00110000ssssiiii | Rdd = memd (Sp + #U5:3) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xde003100) { - // Instruction: 13: 11011110IIIIIddd00110001ssssiiii | Rdd = memd (Sp + #U5:3) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xde002800) { - // Instruction: 13: 11011110IIIIIddd0010100iiiiitttt | Rdd = memd (Sp + #U5:3) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xffc4ff00) == 0xdf003200) { - // Instruction: 13: 1101111100---0--00110010ssssiiii | deallocframe ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMB__RS____U4_0_____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xffc4ff00) == 0xdf003300) { - // Instruction: 13: 1101111100---0--00110011ssssiiii | deallocframe ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMB__RS____U4_0_____1; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xffc4fe00) == 0xdf002a00) { - // Instruction: 13: 1101111100---0--0010101iiiiiittt | deallocframe ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMD__SP____S6_3____RTT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memd (Sp + %d) = %s", (st32) hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xffc4f800) == 0xdf002000) { - // Instruction: 13: 1101111100---0--00100iiisssstttt | deallocframe ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMH__RS____U3_1____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xffc4ff00) == 0xdf003000) { - // Instruction: 13: 1101111100---0--00110000ssssiiii | deallocframe ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__RS____U4_2_____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xffc4ff00) == 0xdf003100) { - // Instruction: 13: 1101111100---0--00110001ssssiiii | deallocframe ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__RS____U4_2_____1; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xffc4fe00) == 0xdf002800) { - // Instruction: 13: 1101111100---0--0010100iiiiitttt | deallocframe ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__SP____U5_2____RT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memw (Sp + 0x%x) = %s", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - break; - } - case 0xe: { - if ((hi_u32 & 0xff00fe00) == 0xf2001c00) { - // Instruction: 14: 11110010ssssIIII0001110iiiii---- | memb (Rs + #U4:0) = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____0___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf2000a00) { - // Instruction: 14: 11110010ssssIIII0000101iiiiiittt | memb (Rs + #U4:0) = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____0___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf2000800) { - // Instruction: 14: 11110010ssssIIII0000100iiiiitttt | memb (Rs + #U4:0) = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____0___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf3001c00) { - // Instruction: 14: 11110011ssssIIII0001110iiiii---- | memb (Rs + #U4:0) = #1 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____1___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf3000a00) { - // Instruction: 14: 11110011ssssIIII0000101iiiiiittt | memb (Rs + #U4:0) = #1 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____1___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf3000800) { - // Instruction: 14: 11110011ssssIIII0000100iiiiitttt | memb (Rs + #U4:0) = #1 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____1___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf2001200) { - // Instruction: 14: 11110010uuuuIIII00010010ssssiiii | memb (Ru + #U4:0) = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf2001300) { - // Instruction: 14: 11110010uuuuIIII00010011ssssiiii | memb (Ru + #U4:0) = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0xf2000000) { - // Instruction: 14: 11110010uuuuIIII00000iiisssstttt | memb (Ru + #U4:0) = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf2001000) { - // Instruction: 14: 11110010uuuuIIII00010000ssssiiii | memb (Ru + #U4:0) = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf2001100) { - // Instruction: 14: 11110010uuuuIIII00010001ssssiiii | memb (Ru + #U4:0) = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf3001200) { - // Instruction: 14: 11110011uuuuIIII00010010ssssiiii | memb (Ru + #U4:0) = #1 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf3001300) { - // Instruction: 14: 11110011uuuuIIII00010011ssssiiii | memb (Ru + #U4:0) = #1 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0xf3000000) { - // Instruction: 14: 11110011uuuuIIII00000iiisssstttt | memb (Ru + #U4:0) = #1 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf3001000) { - // Instruction: 14: 11110011uuuuIIII00010000ssssiiii | memb (Ru + #U4:0) = #1 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf3001100) { - // Instruction: 14: 11110011uuuuIIII00010001ssssiiii | memb (Ru + #U4:0) = #1 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xea001c00) { - // Instruction: 14: 1110101IIIIIIttt0001110iiiii---- | memd (Sp + #S6:3) = Rtt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; allocframe (0x%x)", (st32) hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xea001200) { - // Instruction: 14: 1110101IIIIIIttt00010010ssssiiii | memd (Sp + #S6:3) = Rtt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memb (%s + 0x%x) = #0", (st32) hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xea001300) { - // Instruction: 14: 1110101IIIIIIttt00010011ssssiiii | memd (Sp + #S6:3) = Rtt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memb (%s + 0x%x) = #1", (st32) hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xea001000) { - // Instruction: 14: 1110101IIIIIIttt00010000ssssiiii | memd (Sp + #S6:3) = Rtt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memw (%s + 0x%x) = #0", (st32) hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xea001100) { - // Instruction: 14: 1110101IIIIIIttt00010001ssssiiii | memd (Sp + #S6:3) = Rtt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memw (%s + 0x%x) = #1", (st32) hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xea000a00) { - // Instruction: 14: 1110101IIIIIIvvv0000101iiiiiittt | memd (Sp + #S6:3) = Rvv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RVV___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memd (Sp + %d) = %s", (st32) hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f800) == 0xea000000) { - // Instruction: 14: 1110101IIIIIIvvv00000iiisssstttt | memd (Sp + #S6:3) = Rvv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RVV___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memh (%s + 0x%x) = %s", (st32) hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xea000800) { - // Instruction: 14: 1110101IIIIIIvvv0000100iiiiitttt | memd (Sp + #S6:3) = Rvv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RVV___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memw (Sp + 0x%x) = %s", (st32) hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xe0001c00) { - // Instruction: 14: 11100IIIsssstttt0001110iiiii---- | memh (Rs + #U3:1) = Rt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMH__RS____U3_1____RT___ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xe0000a00) { - // Instruction: 14: 11100IIIssssvvvv0000101iiiiiittt | memh (Rs + #U3:1) = Rv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMH__RS____U3_1____RV___MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), (st32) hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xe0000800) { - // Instruction: 14: 11100IIIssssvvvv0000100iiiiitttt | memh (Rs + #U3:1) = Rv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMH__RS____U3_1____RV___MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xe0001200) { - // Instruction: 14: 11100IIIuuuutttt00010010ssssiiii | memh (Ru + #U3:1) = Rt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RT___MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xe0001300) { - // Instruction: 14: 11100IIIuuuutttt00010011ssssiiii | memh (Ru + #U3:1) = Rt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RT___MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xe0001000) { - // Instruction: 14: 11100IIIuuuutttt00010000ssssiiii | memh (Ru + #U3:1) = Rt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RT___MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xe0001100) { - // Instruction: 14: 11100IIIuuuutttt00010001ssssiiii | memh (Ru + #U3:1) = Rt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RT___MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0xe0000000) { - // Instruction: 14: 11100IIIuuuuvvvv00000iiisssstttt | memh (Ru + #U3:1) = Rv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RV___MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf0001c00) { - // Instruction: 14: 11110000ssssIIII0001110iiiii---- | memw (Rs + #U4:2) = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____0___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf0000a00) { - // Instruction: 14: 11110000ssssIIII0000101iiiiiittt | memw (Rs + #U4:2) = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____0___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf0000800) { - // Instruction: 14: 11110000ssssIIII0000100iiiiitttt | memw (Rs + #U4:2) = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____0___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf1001c00) { - // Instruction: 14: 11110001ssssIIII0001110iiiii---- | memw (Rs + #U4:2) = #1 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____1___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf1000a00) { - // Instruction: 14: 11110001ssssIIII0000101iiiiiittt | memw (Rs + #U4:2) = #1 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____1___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf1000800) { - // Instruction: 14: 11110001ssssIIII0000100iiiiitttt | memw (Rs + #U4:2) = #1 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____1___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf0001200) { - // Instruction: 14: 11110000uuuuIIII00010010ssssiiii | memw (Ru + #U4:2) = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf0001300) { - // Instruction: 14: 11110000uuuuIIII00010011ssssiiii | memw (Ru + #U4:2) = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0xf0000000) { - // Instruction: 14: 11110000uuuuIIII00000iiisssstttt | memw (Ru + #U4:2) = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf0001000) { - // Instruction: 14: 11110000uuuuIIII00010000ssssiiii | memw (Ru + #U4:2) = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf0001100) { - // Instruction: 14: 11110000uuuuIIII00010001ssssiiii | memw (Ru + #U4:2) = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf1001200) { - // Instruction: 14: 11110001uuuuIIII00010010ssssiiii | memw (Ru + #U4:2) = #1 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf1001300) { - // Instruction: 14: 11110001uuuuIIII00010011ssssiiii | memw (Ru + #U4:2) = #1 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0xf1000000) { - // Instruction: 14: 11110001uuuuIIII00000iiisssstttt | memw (Ru + #U4:2) = #1 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf1001000) { - // Instruction: 14: 11110001uuuuIIII00010000ssssiiii | memw (Ru + #U4:2) = #1 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf1001100) { - // Instruction: 14: 11110001uuuuIIII00010001ssssiiii | memw (Ru + #U4:2) = #1 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xe8001c00) { - // Instruction: 14: 1110100IIIIItttt0001110iiiii---- | memw (Sp + #U5:2) = Rt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; allocframe (0x%x)", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xe8001200) { - // Instruction: 14: 1110100IIIIItttt00010010ssssiiii | memw (Sp + #U5:2) = Rt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memb (%s + 0x%x) = #0", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xe8001300) { - // Instruction: 14: 1110100IIIIItttt00010011ssssiiii | memw (Sp + #U5:2) = Rt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memb (%s + 0x%x) = #1", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xe8001000) { - // Instruction: 14: 1110100IIIIItttt00010000ssssiiii | memw (Sp + #U5:2) = Rt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memw (%s + 0x%x) = #0", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xe8001100) { - // Instruction: 14: 1110100IIIIItttt00010001ssssiiii | memw (Sp + #U5:2) = Rt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memw (%s + 0x%x) = #1", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xe8000a00) { - // Instruction: 14: 1110100IIIIIvvvv0000101iiiiiittt | memw (Sp + #U5:2) = Rv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RV___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memd (Sp + %d) = %s", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), (st32) hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f800) == 0xe8000000) { - // Instruction: 14: 1110100IIIIIvvvv00000iiisssstttt | memw (Sp + #U5:2) = Rv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RV___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memh (%s + 0x%x) = %s", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xe8000800) { - // Instruction: 14: 1110100IIIIIvvvv0000100iiiiitttt | memw (Sp + #U5:2) = Rv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RV___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rv - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memw (Sp + 0x%x) = %s", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - break; - } - } - } - else { - switch ((hi_u32 >> 28) & 0xF) { - case 0x0: { - // Handle constant extender - hi->instruction = HEX_INS_IMMEXT; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].attr |= HEX_OP_CONST_EXT; - hi->ops[0].op.imm = ((hi_u32 & 0x3FFF) | (((hi_u32 >> 16) & 0xFFF) << 14)) << 6; - constant_extender = hi->ops[0].op.imm; - sprintf(hi->mnem, "immext(#0x%x)", hi->ops[0].op.imm); - break; - } - case 0x1: { - if ((hi_u32 & 0xfc02300) == 0x1800000) { - // Instruction: 1: 0001000110iissssPP0---00iiiiiii- | p0 = cmp.eq (Rs, #-1) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, #-1) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1800100) { - // Instruction: 1: 0001000110iissssPP0---01iiiiiii- | p0 = cmp.gt (Rs, #-1) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, #-1) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1800300) { - // Instruction: 1: 0001000110iissssPP0---11iiiiiii- | p0 = tstbit (Rs, #0) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = tstbit (R%d, #0) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1802000) { - // Instruction: 1: 0001000110iissssPP1---00iiiiiii- | p0 = cmp.eq (Rs, #-1) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, #-1) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1802100) { - // Instruction: 1: 0001000110iissssPP1---01iiiiiii- | p0 = cmp.gt (Rs, #-1) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, #-1) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1802300) { - // Instruction: 1: 0001000110iissssPP1---11iiiiiii- | p0 = tstbit (Rs, #0) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = tstbit (R%d, #0) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c00000) { - // Instruction: 1: 0001000111iissssPP0---00iiiiiii- | p0 = cmp.eq (Rs, #-1) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, #-1) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c00100) { - // Instruction: 1: 0001000111iissssPP0---01iiiiiii- | p0 = cmp.gt (Rs, #-1) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, #-1) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c00300) { - // Instruction: 1: 0001000111iissssPP0---11iiiiiii- | p0 = tstbit (Rs, #0) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = tstbit (R%d, #0) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c02000) { - // Instruction: 1: 0001000111iissssPP1---00iiiiiii- | p0 = cmp.eq (Rs, #-1) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, #-1) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c02100) { - // Instruction: 1: 0001000111iissssPP1---01iiiiiii- | p0 = cmp.gt (Rs, #-1) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, #-1) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c02300) { - // Instruction: 1: 0001000111iissssPP1---11iiiiiii- | p0 = tstbit (Rs, #0) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = tstbit (R%d, #0) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x0) { - // Instruction: 1: 0001000000iissssPP0IIIIIiiiiiii- | p0 = cmp.eq (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, 0x%x) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2000) { - // Instruction: 1: 0001000000iissssPP1IIIIIiiiiiii- | p0 = cmp.eq (Rs, #U5) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, 0x%x) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x400000) { - // Instruction: 1: 0001000001iissssPP0IIIIIiiiiiii- | p0 = cmp.eq (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, 0x%x) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x402000) { - // Instruction: 1: 0001000001iissssPP1IIIIIiiiiiii- | p0 = cmp.eq (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, 0x%x) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x800000) { - // Instruction: 1: 0001000010iissssPP0IIIIIiiiiiii- | p0 = cmp.gt (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, 0x%x) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x802000) { - // Instruction: 1: 0001000010iissssPP1IIIIIiiiiiii- | p0 = cmp.gt (Rs, #U5) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, 0x%x) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0xc00000) { - // Instruction: 1: 0001000011iissssPP0IIIIIiiiiiii- | p0 = cmp.gt (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, 0x%x) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0xc02000) { - // Instruction: 1: 0001000011iissssPP1IIIIIiiiiiii- | p0 = cmp.gt (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, 0x%x) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1000000) { - // Instruction: 1: 0001000100iissssPP0IIIIIiiiiiii- | p0 = cmp.gtu (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, 0x%x) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1002000) { - // Instruction: 1: 0001000100iissssPP1IIIIIiiiiiii- | p0 = cmp.gtu (Rs, #U5) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, 0x%x) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1400000) { - // Instruction: 1: 0001000101iissssPP0IIIIIiiiiiii- | p0 = cmp.gtu (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, 0x%x) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1402000) { - // Instruction: 1: 0001000101iissssPP1IIIIIiiiiiii- | p0 = cmp.gtu (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, 0x%x) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3800000) { - // Instruction: 1: 0001001110iissssPP0---00iiiiiii- | p1 = cmp.eq (Rs, #-1) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, #-1) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3800100) { - // Instruction: 1: 0001001110iissssPP0---01iiiiiii- | p1 = cmp.gt (Rs, #-1) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, #-1) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3800300) { - // Instruction: 1: 0001001110iissssPP0---11iiiiiii- | p1 = tstbit (Rs, #0) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = tstbit (R%d, #0) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3802000) { - // Instruction: 1: 0001001110iissssPP1---00iiiiiii- | p1 = cmp.eq (Rs, #-1) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, #-1) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3802100) { - // Instruction: 1: 0001001110iissssPP1---01iiiiiii- | p1 = cmp.gt (Rs, #-1) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, #-1) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3802300) { - // Instruction: 1: 0001001110iissssPP1---11iiiiiii- | p1 = tstbit (Rs, #0) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = tstbit (R%d, #0) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c00000) { - // Instruction: 1: 0001001111iissssPP0---00iiiiiii- | p1 = cmp.eq (Rs, #-1) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, #-1) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c00100) { - // Instruction: 1: 0001001111iissssPP0---01iiiiiii- | p1 = cmp.gt (Rs, #-1) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, #-1) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c00300) { - // Instruction: 1: 0001001111iissssPP0---11iiiiiii- | p1 = tstbit (Rs, #0) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = tstbit (R%d, #0) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c02000) { - // Instruction: 1: 0001001111iissssPP1---00iiiiiii- | p1 = cmp.eq (Rs, #-1) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, #-1) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c02100) { - // Instruction: 1: 0001001111iissssPP1---01iiiiiii- | p1 = cmp.gt (Rs, #-1) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, #-1) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c02300) { - // Instruction: 1: 0001001111iissssPP1---11iiiiiii- | p1 = tstbit (Rs, #0) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = tstbit (R%d, #0) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2000000) { - // Instruction: 1: 0001001000iissssPP0IIIIIiiiiiii- | p1 = cmp.eq (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, 0x%x) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2002000) { - // Instruction: 1: 0001001000iissssPP1IIIIIiiiiiii- | p1 = cmp.eq (Rs, #U5) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, 0x%x) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2400000) { - // Instruction: 1: 0001001001iissssPP0IIIIIiiiiiii- | p1 = cmp.eq (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, 0x%x) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2402000) { - // Instruction: 1: 0001001001iissssPP1IIIIIiiiiiii- | p1 = cmp.eq (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, 0x%x) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2800000) { - // Instruction: 1: 0001001010iissssPP0IIIIIiiiiiii- | p1 = cmp.gt (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS___U5____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, 0x%x) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2802000) { - // Instruction: 1: 0001001010iissssPP1IIIIIiiiiiii- | p1 = cmp.gt (Rs, #U5) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS___U5____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, 0x%x) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2c00000) { - // Instruction: 1: 0001001011iissssPP0IIIIIiiiiiii- | p1 = cmp.gt (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, 0x%x) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2c02000) { - // Instruction: 1: 0001001011iissssPP1IIIIIiiiiiii- | p1 = cmp.gt (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, 0x%x) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x3000000) { - // Instruction: 1: 0001001100iissssPP0IIIIIiiiiiii- | p1 = cmp.gtu (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, 0x%x) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x3002000) { - // Instruction: 1: 0001001100iissssPP1IIIIIiiiiiii- | p1 = cmp.gtu (Rs, #U5) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, 0x%x) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x3400000) { - // Instruction: 1: 0001001101iissssPP0IIIIIiiiiiii- | p1 = cmp.gtu (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, 0x%x) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x3402000) { - // Instruction: 1: 0001001101iissssPP1IIIIIiiiiiii- | p1 = cmp.gtu (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, 0x%x) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4000000) { - // Instruction: 1: 0001010000iissssPP00ttttiiiiiii- | p0 = cmp.eq (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, R%d) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4001000) { - // Instruction: 1: 0001010000iissssPP01ttttiiiiiii- | p1 = cmp.eq (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, R%d) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4002000) { - // Instruction: 1: 0001010000iissssPP10ttttiiiiiii- | p0 = cmp.eq (Rs, Rt) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, R%d) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4003000) { - // Instruction: 1: 0001010000iissssPP11ttttiiiiiii- | p1 = cmp.eq (Rs, Rt) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, R%d) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4400000) { - // Instruction: 1: 0001010001iissssPP00ttttiiiiiii- | p0 = cmp.eq (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, R%d) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4401000) { - // Instruction: 1: 0001010001iissssPP01ttttiiiiiii- | p1 = cmp.eq (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, R%d) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4402000) { - // Instruction: 1: 0001010001iissssPP10ttttiiiiiii- | p0 = cmp.eq (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, R%d) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4403000) { - // Instruction: 1: 0001010001iissssPP11ttttiiiiiii- | p1 = cmp.eq (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, R%d) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4800000) { - // Instruction: 1: 0001010010iissssPP00ttttiiiiiii- | p0 = cmp.gt (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS__RT____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, R%d) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4801000) { - // Instruction: 1: 0001010010iissssPP01ttttiiiiiii- | p1 = cmp.gt (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS__RT____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, R%d) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4802000) { - // Instruction: 1: 0001010010iissssPP10ttttiiiiiii- | p0 = cmp.gt (Rs, Rt) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS__RT____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, R%d) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4803000) { - // Instruction: 1: 0001010010iissssPP11ttttiiiiiii- | p1 = cmp.gt (Rs, Rt) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS__RT____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, R%d) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4c00000) { - // Instruction: 1: 0001010011iissssPP00ttttiiiiiii- | p0 = cmp.gt (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, R%d) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4c01000) { - // Instruction: 1: 0001010011iissssPP01ttttiiiiiii- | p1 = cmp.gt (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, R%d) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4c02000) { - // Instruction: 1: 0001010011iissssPP10ttttiiiiiii- | p0 = cmp.gt (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, R%d) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4c03000) { - // Instruction: 1: 0001010011iissssPP11ttttiiiiiii- | p1 = cmp.gt (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, R%d) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5000000) { - // Instruction: 1: 0001010100iissssPP00ttttiiiiiii- | p0 = cmp.gtu (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, R%d) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5001000) { - // Instruction: 1: 0001010100iissssPP01ttttiiiiiii- | p1 = cmp.gtu (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, R%d) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5002000) { - // Instruction: 1: 0001010100iissssPP10ttttiiiiiii- | p0 = cmp.gtu (Rs, Rt) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, R%d) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5003000) { - // Instruction: 1: 0001010100iissssPP11ttttiiiiiii- | p1 = cmp.gtu (Rs, Rt) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, R%d) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5400000) { - // Instruction: 1: 0001010101iissssPP00ttttiiiiiii- | p0 = cmp.gtu (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, R%d) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5401000) { - // Instruction: 1: 0001010101iissssPP01ttttiiiiiii- | p1 = cmp.gtu (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, R%d) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5402000) { - // Instruction: 1: 0001010101iissssPP10ttttiiiiiii- | p0 = cmp.gtu (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, R%d) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5403000) { - // Instruction: 1: 0001010101iissssPP11ttttiiiiiii- | p1 = cmp.gtu (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, R%d) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x6000000) { - // Instruction: 1: 00010110--iiddddPPIIIIIIiiiiiii- | Rd = #U6 ; jump #r9:2 - hi->instruction = HEX_INS_MULT_RD____U6___JUMP__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = 0x%x ; jump 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x7000000) { - // Instruction: 1: 00010111--iissssPP--ddddiiiiiii- | Rd = Rs ; jump #r9:2 - hi->instruction = HEX_INS_MULT_RD___RS___JUMP__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0xf00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0xf0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = R%d ; jump 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - break; - } - case 0x2: { - if ((hi_u32 & 0xfc02000) == 0x0) { - // Instruction: 2: 0010000000ii-sssPP0tttttiiiiiii- | if (cmp.eq (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.eq (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2000) { - // Instruction: 2: 0010000000ii-sssPP1tttttiiiiiii- | if (cmp.eq (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.eq (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x400000) { - // Instruction: 2: 0010000001ii-sssPP0tttttiiiiiii- | if (!cmp.eq (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.eq (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x402000) { - // Instruction: 2: 0010000001ii-sssPP1tttttiiiiiii- | if (!cmp.eq (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.eq (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x800000) { - // Instruction: 2: 0010000010ii-sssPP0tttttiiiiiii- | if (cmp.gt (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x802000) { - // Instruction: 2: 0010000010ii-sssPP1tttttiiiiiii- | if (cmp.gt (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0xc00000) { - // Instruction: 2: 0010000011ii-sssPP0tttttiiiiiii- | if (!cmp.gt (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0xc02000) { - // Instruction: 2: 0010000011ii-sssPP1tttttiiiiiii- | if (!cmp.gt (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1000000) { - // Instruction: 2: 0010000100ii-sssPP0tttttiiiiiii- | if (cmp.gtu (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1002000) { - // Instruction: 2: 0010000100ii-sssPP1tttttiiiiiii- | if (cmp.gtu (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1400000) { - // Instruction: 2: 0010000101ii-sssPP0tttttiiiiiii- | if (!cmp.gtu (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1402000) { - // Instruction: 2: 0010000101ii-sssPP1tttttiiiiiii- | if (!cmp.gtu (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1800000) { - // Instruction: 2: 0010000110ii-sssPP0tttttiiiiiii- | if (cmp.gt (Rt, Ns.new)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__RT__NS_NEW___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1802000) { - // Instruction: 2: 0010000110ii-sssPP1tttttiiiiiii- | if (cmp.gt (Rt, Ns.new)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__RT__NS_NEW___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1c00000) { - // Instruction: 2: 0010000111ii-sssPP0tttttiiiiiii- | if (!cmp.gt (Rt, Ns.new)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__RT__NS_NEW___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1c02000) { - // Instruction: 2: 0010000111ii-sssPP1tttttiiiiiii- | if (!cmp.gt (Rt, Ns.new)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__RT__NS_NEW___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2000000) { - // Instruction: 2: 0010001000ii-sssPP0tttttiiiiiii- | if (cmp.gtu (Rt, Ns.new)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__RT__NS_NEW___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2002000) { - // Instruction: 2: 0010001000ii-sssPP1tttttiiiiiii- | if (cmp.gtu (Rt, Ns.new)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__RT__NS_NEW___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2400000) { - // Instruction: 2: 0010001001ii-sssPP0tttttiiiiiii- | if (!cmp.gtu (Rt, Ns.new)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__RT__NS_NEW___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2402000) { - // Instruction: 2: 0010001001ii-sssPP1tttttiiiiiii- | if (!cmp.gtu (Rt, Ns.new)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__RT__NS_NEW___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4000000) { - // Instruction: 2: 0010010000ii-sssPP0IIIIIiiiiiii- | if (cmp.eq (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (cmp.eq (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4002000) { - // Instruction: 2: 0010010000ii-sssPP1IIIIIiiiiiii- | if (cmp.eq (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (cmp.eq (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4400000) { - // Instruction: 2: 0010010001ii-sssPP0IIIIIiiiiiii- | if (!cmp.eq (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (!cmp.eq (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4402000) { - // Instruction: 2: 0010010001ii-sssPP1IIIIIiiiiiii- | if (!cmp.eq (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (!cmp.eq (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4800000) { - // Instruction: 2: 0010010010ii-sssPP0IIIIIiiiiiii- | if (cmp.gt (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (cmp.gt (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4802000) { - // Instruction: 2: 0010010010ii-sssPP1IIIIIiiiiiii- | if (cmp.gt (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (cmp.gt (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4c00000) { - // Instruction: 2: 0010010011ii-sssPP0IIIIIiiiiiii- | if (!cmp.gt (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (!cmp.gt (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4c02000) { - // Instruction: 2: 0010010011ii-sssPP1IIIIIiiiiiii- | if (!cmp.gt (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (!cmp.gt (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5000000) { - // Instruction: 2: 0010010100ii-sssPP0IIIIIiiiiiii- | if (cmp.gtu (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5002000) { - // Instruction: 2: 0010010100ii-sssPP1IIIIIiiiiiii- | if (cmp.gtu (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5400000) { - // Instruction: 2: 0010010101ii-sssPP0IIIIIiiiiiii- | if (!cmp.gtu (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5402000) { - // Instruction: 2: 0010010101ii-sssPP1IIIIIiiiiiii- | if (!cmp.gtu (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5800000) { - // Instruction: 2: 0010010110ii-sssPP0-----iiiiiii- | if (tstbit (Ns.new, #0)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__TSTBIT__NS_NEW___0___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (tstbit (R%d, #0)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5802000) { - // Instruction: 2: 0010010110ii-sssPP1-----iiiiiii- | if (tstbit (Ns.new, #0)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__TSTBIT__NS_NEW___0___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (tstbit (R%d, #0)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5c00000) { - // Instruction: 2: 0010010111ii-sssPP0-----iiiiiii- | if (!tstbit (Ns.new, #0)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_TSTBIT__NS_NEW___0___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!tstbit (R%d, #0)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5c02000) { - // Instruction: 2: 0010010111ii-sssPP1-----iiiiiii- | if (!tstbit (Ns.new, #0)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_TSTBIT__NS_NEW___0___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!tstbit (R%d, #0)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6000000) { - // Instruction: 2: 0010011000ii-sssPP0-----iiiiiii- | if (cmp.eq (Ns.new, #-1)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW____1___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.eq (R%d, #-1)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6002000) { - // Instruction: 2: 0010011000ii-sssPP1-----iiiiiii- | if (cmp.eq (Ns.new, #-1)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW____1___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.eq (R%d, #-1)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6400000) { - // Instruction: 2: 0010011001ii-sssPP0-----iiiiiii- | if (!cmp.eq (Ns.new, #-1)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW____1___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.eq (R%d, #-1)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6402000) { - // Instruction: 2: 0010011001ii-sssPP1-----iiiiiii- | if (!cmp.eq (Ns.new, #-1)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW____1___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.eq (R%d, #-1)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6800000) { - // Instruction: 2: 0010011010ii-sssPP0-----iiiiiii- | if (cmp.gt (Ns.new, #-1)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW____1___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, #-1)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6802000) { - // Instruction: 2: 0010011010ii-sssPP1-----iiiiiii- | if (cmp.gt (Ns.new, #-1)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW____1___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, #-1)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6c00000) { - // Instruction: 2: 0010011011ii-sssPP0-----iiiiiii- | if (!cmp.gt (Ns.new, #-1)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW____1___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, #-1)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6c02000) { - // Instruction: 2: 0010011011ii-sssPP1-----iiiiiii- | if (!cmp.gt (Ns.new, #-1)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW____1___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, #-1)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - break; - } - case 0x3: { - if ((hi_u32 & 0xfe00000) == 0xac00000) { - // Instruction: 3: 00111010110sssssPPittttti--ddddd | Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_RDD___MEMD__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xc00000) { - // Instruction: 3: 00110000110sssssPPitttttivvddddd | if (Pv) Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RDD___MEMD__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1c00000) { - // Instruction: 3: 00110001110sssssPPitttttivvddddd | if !Pv Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RDD___MEMD__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2c00000) { - // Instruction: 3: 00110010110sssssPPitttttivvddddd | if (Pv.new) Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RDD___MEMD__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3c00000) { - // Instruction: 3: 00110011110sssssPPitttttivvddddd | if !Pv.new Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RDD___MEMD__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa000000) { - // Instruction: 3: 00111010000sssssPPittttti--ddddd | Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMB__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x0) { - // Instruction: 3: 00110000000sssssPPitttttivvddddd | if (Pv) Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1000000) { - // Instruction: 3: 00110001000sssssPPitttttivvddddd | if !Pv Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2000000) { - // Instruction: 3: 00110010000sssssPPitttttivvddddd | if (Pv.new) Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3000000) { - // Instruction: 3: 00110011000sssssPPitttttivvddddd | if !Pv.new Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa400000) { - // Instruction: 3: 00111010010sssssPPittttti--ddddd | Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMH__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x400000) { - // Instruction: 3: 00110000010sssssPPitttttivvddddd | if (Pv) Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1400000) { - // Instruction: 3: 00110001010sssssPPitttttivvddddd | if !Pv Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2400000) { - // Instruction: 3: 00110010010sssssPPitttttivvddddd | if (Pv.new) Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3400000) { - // Instruction: 3: 00110011010sssssPPitttttivvddddd | if !Pv.new Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa200000) { - // Instruction: 3: 00111010001sssssPPittttti--ddddd | Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMUB__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x200000) { - // Instruction: 3: 00110000001sssssPPitttttivvddddd | if (Pv) Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMUB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1200000) { - // Instruction: 3: 00110001001sssssPPitttttivvddddd | if !Pv Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMUB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2200000) { - // Instruction: 3: 00110010001sssssPPitttttivvddddd | if (Pv.new) Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMUB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3200000) { - // Instruction: 3: 00110011001sssssPPitttttivvddddd | if !Pv.new Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMUB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa600000) { - // Instruction: 3: 00111010011sssssPPittttti--ddddd | Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMUH__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x600000) { - // Instruction: 3: 00110000011sssssPPitttttivvddddd | if (Pv) Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMUH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1600000) { - // Instruction: 3: 00110001011sssssPPitttttivvddddd | if !Pv Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMUH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2600000) { - // Instruction: 3: 00110010011sssssPPitttttivvddddd | if (Pv.new) Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMUH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3600000) { - // Instruction: 3: 00110011011sssssPPitttttivvddddd | if !Pv.new Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMUH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa800000) { - // Instruction: 3: 00111010100sssssPPittttti--ddddd | Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMW__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x800000) { - // Instruction: 3: 00110000100sssssPPitttttivvddddd | if (Pv) Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMW__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1800000) { - // Instruction: 3: 00110001100sssssPPitttttivvddddd | if !Pv Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMW__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2800000) { - // Instruction: 3: 00110010100sssssPPitttttivvddddd | if (Pv.new) Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMW__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3800000) { - // Instruction: 3: 00110011100sssssPPitttttivvddddd | if !Pv.new Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMW__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xe000000) { - // Instruction: 3: 00111110-00sssssPP0iiiiii00ttttt | memb (Rs + #u6:0) += Rt - hi->instruction = HEX_INS_MEMB__RS____U6_0___PLUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) += R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe000020) { - // Instruction: 3: 00111110-00sssssPP0iiiiii01ttttt | memb (Rs + #u6:0) -= Rt - hi->instruction = HEX_INS_MEMB__RS____U6_0___MINUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) -= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe000040) { - // Instruction: 3: 00111110-00sssssPP0iiiiii10ttttt | memb (Rs + #u6:0) &= Rt - hi->instruction = HEX_INS_MEMB__RS____U6_0___AND_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) &= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe000060) { - // Instruction: 3: 00111110-00sssssPP0iiiiii11ttttt | memb (Rs + #u6:0) |= Rt - hi->instruction = HEX_INS_MEMB__RS____U6_0___OR_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) |= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xf000000) { - // Instruction: 3: 00111111-00sssssPP0iiiiii00IIIII | memb (Rs + #u6:0) += #U5 - hi->instruction = HEX_INS_MEMB__RS____U6_0___PLUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) += 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf000020) { - // Instruction: 3: 00111111-00sssssPP0iiiiii01IIIII | memb (Rs + #u6:0) -= #U5 - hi->instruction = HEX_INS_MEMB__RS____U6_0___MINUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) -= 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf000040) { - // Instruction: 3: 00111111-00sssssPP0iiiiii10IIIII | memb (Rs + #u6:0) = clrbit (#U5) - hi->instruction = HEX_INS_MEMB__RS____U6_0____CLRBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) = clrbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf000060) { - // Instruction: 3: 00111111-00sssssPP0iiiiii11IIIII | memb (Rs + #u6:0) = setbit (#U5) - hi->instruction = HEX_INS_MEMB__RS____U6_0____SETBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) = setbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xe200000) { - // Instruction: 3: 00111110-01sssssPP0iiiiii00ttttt | memh (Rs + #u6:1) += Rt - hi->instruction = HEX_INS_MEMH__RS____U6_1___PLUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) += R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe200020) { - // Instruction: 3: 00111110-01sssssPP0iiiiii01ttttt | memh (Rs + #u6:1) -= Rt - hi->instruction = HEX_INS_MEMH__RS____U6_1___MINUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) -= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe200040) { - // Instruction: 3: 00111110-01sssssPP0iiiiii10ttttt | memh (Rs + #u6:1) &= Rt - hi->instruction = HEX_INS_MEMH__RS____U6_1___AND_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) &= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe200060) { - // Instruction: 3: 00111110-01sssssPP0iiiiii11ttttt | memh (Rs + #u6:1) |= Rt - hi->instruction = HEX_INS_MEMH__RS____U6_1___OR_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) |= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xf200000) { - // Instruction: 3: 00111111-01sssssPP0iiiiii00IIIII | memh (Rs + #u6:1) += #U5 - hi->instruction = HEX_INS_MEMH__RS____U6_1___PLUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) += 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf200020) { - // Instruction: 3: 00111111-01sssssPP0iiiiii01IIIII | memh (Rs + #u6:1) -= #U5 - hi->instruction = HEX_INS_MEMH__RS____U6_1___MINUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) -= 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf200040) { - // Instruction: 3: 00111111-01sssssPP0iiiiii10IIIII | memh (Rs + #u6:1) = clrbit (#U5) - hi->instruction = HEX_INS_MEMH__RS____U6_1____CLRBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) = clrbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf200060) { - // Instruction: 3: 00111111-01sssssPP0iiiiii11IIIII | memh (Rs + #u6:1) = setbit (#U5) - hi->instruction = HEX_INS_MEMH__RS____U6_1____SETBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) = setbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xe400000) { - // Instruction: 3: 00111110-10sssssPP0iiiiii00ttttt | memw (Rs + #u6:2) += Rt - hi->instruction = HEX_INS_MEMW__RS____U6_2___PLUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) += R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe400020) { - // Instruction: 3: 00111110-10sssssPP0iiiiii01ttttt | memw (Rs + #u6:2) -= Rt - hi->instruction = HEX_INS_MEMW__RS____U6_2___MINUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) -= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe400040) { - // Instruction: 3: 00111110-10sssssPP0iiiiii10ttttt | memw (Rs + #u6:2) &= Rt - hi->instruction = HEX_INS_MEMW__RS____U6_2___AND_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) &= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe400060) { - // Instruction: 3: 00111110-10sssssPP0iiiiii11ttttt | memw (Rs + #u6:2) |= Rt - hi->instruction = HEX_INS_MEMW__RS____U6_2___OR_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) |= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xf400000) { - // Instruction: 3: 00111111-10sssssPP0iiiiii00IIIII | memw (Rs + #u6:2) += #U5 - hi->instruction = HEX_INS_MEMW__RS____U6_2___PLUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) += 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf400020) { - // Instruction: 3: 00111111-10sssssPP0iiiiii01IIIII | memw (Rs + #u6:2) -= #U5 - hi->instruction = HEX_INS_MEMW__RS____U6_2___MINUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) -= 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf400040) { - // Instruction: 3: 00111111-10sssssPP0iiiiii10IIIII | memw (Rs + #u6:2) = clrbit (#U5) - hi->instruction = HEX_INS_MEMW__RS____U6_2____CLRBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) = clrbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf400060) { - // Instruction: 3: 00111111-10sssssPP0iiiiii11IIIII | memw (Rs + #u6:2) = setbit (#U5) - hi->instruction = HEX_INS_MEMW__RS____U6_2____SETBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) = setbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00018) == 0xba00000) { - // Instruction: 3: 00111011101sssssPPiuuuuui--00ttt | memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x4a00000) { - // Instruction: 3: 00110100101sssssPPiuuuuuivv00ttt | if (Pv) memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x5a00000) { - // Instruction: 3: 00110101101sssssPPiuuuuuivv00ttt | if !Pv memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x6a00000) { - // Instruction: 3: 00110110101sssssPPiuuuuuivv00ttt | if (Pv.new) memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x7a00000) { - // Instruction: 3: 00110111101sssssPPiuuuuuivv00ttt | if !Pv.new memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xba00008) { - // Instruction: 3: 00111011101sssssPPiuuuuui--01ttt | memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x4a00008) { - // Instruction: 3: 00110100101sssssPPiuuuuuivv01ttt | if (Pv) memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x5a00008) { - // Instruction: 3: 00110101101sssssPPiuuuuuivv01ttt | if !Pv memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x6a00008) { - // Instruction: 3: 00110110101sssssPPiuuuuuivv01ttt | if (Pv.new) memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x7a00008) { - // Instruction: 3: 00110111101sssssPPiuuuuuivv01ttt | if !Pv.new memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xba00010) { - // Instruction: 3: 00111011101sssssPPiuuuuui--10ttt | memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x4a00010) { - // Instruction: 3: 00110100101sssssPPiuuuuuivv10ttt | if (Pv) memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x5a00010) { - // Instruction: 3: 00110101101sssssPPiuuuuuivv10ttt | if !Pv memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x6a00010) { - // Instruction: 3: 00110110101sssssPPiuuuuuivv10ttt | if (Pv.new) memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x7a00010) { - // Instruction: 3: 00110111101sssssPPiuuuuuivv10ttt | if !Pv.new memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xbc00000) { - // Instruction: 3: 00111011110sssssPPiuuuuui--ttttt | memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_MEMD__RS___RU_____U2____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4c00000) { - // Instruction: 3: 00110100110sssssPPiuuuuuivvttttt | if (Pv) memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_IF__PV__MEMD__RS___RU_____U2____RTT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg + 1, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5c00000) { - // Instruction: 3: 00110101110sssssPPiuuuuuivvttttt | if !Pv memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_MEMD__RS___RU_____U2____RTT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg + 1, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6c00000) { - // Instruction: 3: 00110110110sssssPPiuuuuuivvttttt | if (Pv.new) memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_IF__PV_NEW__MEMD__RS___RU_____U2____RTT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg + 1, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7c00000) { - // Instruction: 3: 00110111110sssssPPiuuuuuivvttttt | if !Pv.new memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMD__RS___RU_____U2____RTT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg + 1, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xb000000) { - // Instruction: 3: 00111011000sssssPPiuuuuui--ttttt | memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_MEMB__RS___RU_____U2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xe600000) == 0xc000000) { - // Instruction: 3: 0011110--00sssssPPIiiiiiiIIIIIII | memb (Rs + #u6:0) = #S8 - hi->instruction = HEX_INS_MEMB__RS____U6_0_____S8; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0x7f) >> 0)); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d + 0x%x) = %d", hi->ops[0].op.reg, hi->ops[1].op.imm, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4000000) { - // Instruction: 3: 00110100000sssssPPiuuuuuivvttttt | if (Pv) memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMB__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5000000) { - // Instruction: 3: 00110101000sssssPPiuuuuuivvttttt | if !Pv memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6000000) { - // Instruction: 3: 00110110000sssssPPiuuuuuivvttttt | if (Pv.new) memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7000000) { - // Instruction: 3: 00110111000sssssPPiuuuuuivvttttt | if !Pv.new memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8000000) { - // Instruction: 3: 00111000000sssssPPIiiiiiivvIIIII | if (Pv) memb (Rs + #u6:0) = #S6 - hi->instruction = HEX_INS_IF__PV__MEMB__RS____U6_0_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8800000) { - // Instruction: 3: 00111000100sssssPPIiiiiiivvIIIII | if !Pv memb (Rs + #u6:0) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS____U6_0_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9000000) { - // Instruction: 3: 00111001000sssssPPIiiiiiivvIIIII | if (Pv.new) memb (Rs + #u6:0) = #S6 - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS____U6_0_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9800000) { - // Instruction: 3: 00111001100sssssPPIiiiiiivvIIIII | if !Pv.new memb (Rs + #u6:0) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS____U6_0_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xb400000) { - // Instruction: 3: 00111011010sssssPPiuuuuui--ttttt | memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_MEMH__RS___RU_____U2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xb600000) { - // Instruction: 3: 00111011011sssssPPiuuuuui--ttttt | memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_MEMH__RS___RU_____U2____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xe600000) == 0xc200000) { - // Instruction: 3: 0011110--01sssssPPIiiiiiiIIIIIII | memh (Rs + #u6:1) = #S8 - hi->instruction = HEX_INS_MEMH__RS____U6_1_____S8; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0x7f) >> 0)); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 1); - sprintf(hi->mnem, "memh (R%d + 0x%x) = %d", hi->ops[0].op.reg, hi->ops[1].op.imm, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4400000) { - // Instruction: 3: 00110100010sssssPPiuuuuuivvttttt | if (Pv) memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMH__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4600000) { - // Instruction: 3: 00110100011sssssPPiuuuuuivvttttt | if (Pv) memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_IF__PV__MEMH__RS___RU_____U2____RT_H; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5400000) { - // Instruction: 3: 00110101010sssssPPiuuuuuivvttttt | if !Pv memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5600000) { - // Instruction: 3: 00110101011sssssPPiuuuuuivvttttt | if !Pv memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS___RU_____U2____RT_H; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6400000) { - // Instruction: 3: 00110110010sssssPPiuuuuuivvttttt | if (Pv.new) memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6600000) { - // Instruction: 3: 00110110011sssssPPiuuuuuivvttttt | if (Pv.new) memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS___RU_____U2____RT_H; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7400000) { - // Instruction: 3: 00110111010sssssPPiuuuuuivvttttt | if !Pv.new memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7600000) { - // Instruction: 3: 00110111011sssssPPiuuuuuivvttttt | if !Pv.new memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS___RU_____U2____RT_H; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8200000) { - // Instruction: 3: 00111000001sssssPPIiiiiiivvIIIII | if (Pv) memh (Rs + #u6:1) = #S6 - hi->instruction = HEX_INS_IF__PV__MEMH__RS____U6_1_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8a00000) { - // Instruction: 3: 00111000101sssssPPIiiiiiivvIIIII | if !Pv memh (Rs + #u6:1) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS____U6_1_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9200000) { - // Instruction: 3: 00111001001sssssPPIiiiiiivvIIIII | if (Pv.new) memh (Rs + #u6:1) = #S6 - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS____U6_1_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9a00000) { - // Instruction: 3: 00111001101sssssPPIiiiiiivvIIIII | if !Pv.new memh (Rs + #u6:1) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS____U6_1_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xb800000) { - // Instruction: 3: 00111011100sssssPPiuuuuui--ttttt | memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_MEMW__RS___RU_____U2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xe600000) == 0xc400000) { - // Instruction: 3: 0011110--10sssssPPIiiiiiiIIIIIII | memw (Rs + #u6:2) = #S8 - hi->instruction = HEX_INS_MEMW__RS____U6_2_____S8; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0x7f) >> 0)); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "memw (R%d + 0x%x) = %d", hi->ops[0].op.reg, hi->ops[1].op.imm, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4800000) { - // Instruction: 3: 00110100100sssssPPiuuuuuivvttttt | if (Pv) memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMW__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5800000) { - // Instruction: 3: 00110101100sssssPPiuuuuuivvttttt | if !Pv memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6800000) { - // Instruction: 3: 00110110100sssssPPiuuuuuivvttttt | if (Pv.new) memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7800000) { - // Instruction: 3: 00110111100sssssPPiuuuuuivvttttt | if !Pv.new memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32) & 0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8400000) { - // Instruction: 3: 00111000010sssssPPIiiiiiivvIIIII | if (Pv) memw (Rs + #u6:2) = #S6 - hi->instruction = HEX_INS_IF__PV__MEMW__RS____U6_2_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8c00000) { - // Instruction: 3: 00111000110sssssPPIiiiiiivvIIIII | if !Pv memw (Rs + #u6:2) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS____U6_2_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9400000) { - // Instruction: 3: 00111001010sssssPPIiiiiiivvIIIII | if (Pv.new) memw (Rs + #u6:2) = #S6 - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS____U6_2_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9c00000) { - // Instruction: 3: 00111001110sssssPPIiiiiiivvIIIII | if !Pv.new memw (Rs + #u6:2) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS____U6_2_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f80) >> 7) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - break; - } - case 0x4: { - if ((hi_u32 & 0x9e00000) == 0x9c00000) { - // Instruction: 4: 01001ii1110iiiiiPPiiiiiiiiiddddd | Rdd = memd (gp + #u16:3) - hi->instruction = HEX_INS_RDD___MEMD__GP____U16_3_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (gp + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1c00000) { - // Instruction: 4: 01000001110sssssPP0ttiiiiiiddddd | if (Pt) Rdd = memd (Rs + #u6:3) - hi->instruction = HEX_INS_IF__PT__RDD___MEMD__RS____U6_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 3; // scaled - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend_off(&hi->ops[3], 3); - sprintf(hi->mnem, "if (P%d) R%d:R%d = memd (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3c00000) { - // Instruction: 4: 01000011110sssssPP0ttiiiiiiddddd | if (Pt.new) Rdd = memd (Rs + #u6:3) - hi->instruction = HEX_INS_IF__PT_NEW__RDD___MEMD__RS____U6_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 3; // scaled - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend_off(&hi->ops[3], 3); - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = memd (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5c00000) { - // Instruction: 4: 01000101110sssssPP0ttiiiiiiddddd | if !Pt Rdd = memd (Rs + #u6:3) - hi->instruction = HEX_INS_IF__NOT_PT_RDD___MEMD__RS____U6_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 3; // scaled - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend_off(&hi->ops[3], 3); - sprintf(hi->mnem, "if !P%d R%d:R%d = memd (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7c00000) { - // Instruction: 4: 01000111110sssssPP0ttiiiiiiddddd | if !Pt.new Rdd = memd (Rs + #u6:3) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RDD___MEMD__RS____U6_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 3; // scaled - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend_off(&hi->ops[3], 3); - sprintf(hi->mnem, "if !P%d.new R%d:R%d = memd (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9000000) { - // Instruction: 4: 01001ii1000iiiiiPPiiiiiiiiiddddd | Rd = memb (gp + #u16:0) - hi->instruction = HEX_INS_RD___MEMB__GP____U16_0_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1000000) { - // Instruction: 4: 01000001000sssssPP0ttiiiiiiddddd | if (Pt) Rd = memb (Rs + #u6:0) - hi->instruction = HEX_INS_IF__PT__RD___MEMB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d) R%d = memb (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3000000) { - // Instruction: 4: 01000011000sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memb (Rs + #u6:0) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d.new) R%d = memb (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5000000) { - // Instruction: 4: 01000101000sssssPP0ttiiiiiiddddd | if !Pt Rd = memb (Rs + #u6:0) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d R%d = memb (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7000000) { - // Instruction: 4: 01000111000sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memb (Rs + #u6:0) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d.new R%d = memb (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9400000) { - // Instruction: 4: 01001ii1010iiiiiPPiiiiiiiiiddddd | Rd = memh (gp + #u16:1) - hi->instruction = HEX_INS_RD___MEMH__GP____U16_1_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1400000) { - // Instruction: 4: 01000001010sssssPP0ttiiiiiiddddd | if (Pt) Rd = memh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__PT__RD___MEMH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if (P%d) R%d = memh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3400000) { - // Instruction: 4: 01000011010sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if (P%d.new) R%d = memh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5400000) { - // Instruction: 4: 01000101010sssssPP0ttiiiiiiddddd | if !Pt Rd = memh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if !P%d R%d = memh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7400000) { - // Instruction: 4: 01000111010sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if !P%d.new R%d = memh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9200000) { - // Instruction: 4: 01001ii1001iiiiiPPiiiiiiiiiddddd | Rd = memub (gp + #u16:0) - hi->instruction = HEX_INS_RD___MEMUB__GP____U16_0_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1200000) { - // Instruction: 4: 01000001001sssssPP0ttiiiiiiddddd | if (Pt) Rd = memub (Rs + #u6:0) - hi->instruction = HEX_INS_IF__PT__RD___MEMUB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d) R%d = memub (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3200000) { - // Instruction: 4: 01000011001sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memub (Rs + #u6:0) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d.new) R%d = memub (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5200000) { - // Instruction: 4: 01000101001sssssPP0ttiiiiiiddddd | if !Pt Rd = memub (Rs + #u6:0) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d R%d = memub (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7200000) { - // Instruction: 4: 01000111001sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memub (Rs + #u6:0) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d.new R%d = memub (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9600000) { - // Instruction: 4: 01001ii1011iiiiiPPiiiiiiiiiddddd | Rd = memuh (gp + #u16:1) - hi->instruction = HEX_INS_RD___MEMUH__GP____U16_1_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1600000) { - // Instruction: 4: 01000001011sssssPP0ttiiiiiiddddd | if (Pt) Rd = memuh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__PT__RD___MEMUH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if (P%d) R%d = memuh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3600000) { - // Instruction: 4: 01000011011sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memuh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if (P%d.new) R%d = memuh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5600000) { - // Instruction: 4: 01000101011sssssPP0ttiiiiiiddddd | if !Pt Rd = memuh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if !P%d R%d = memuh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7600000) { - // Instruction: 4: 01000111011sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memuh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if !P%d.new R%d = memuh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9800000) { - // Instruction: 4: 01001ii1100iiiiiPPiiiiiiiiiddddd | Rd = memw (gp + #u16:2) - hi->instruction = HEX_INS_RD___MEMW__GP____U16_2_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "R%d = memw (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1800000) { - // Instruction: 4: 01000001100sssssPP0ttiiiiiiddddd | if (Pt) Rd = memw (Rs + #u6:2) - hi->instruction = HEX_INS_IF__PT__RD___MEMW__RS____U6_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 2; // scaled - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend_off(&hi->ops[3], 2); - sprintf(hi->mnem, "if (P%d) R%d = memw (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3800000) { - // Instruction: 4: 01000011100sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memw (Rs + #u6:2) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMW__RS____U6_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 2; // scaled - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend_off(&hi->ops[3], 2); - sprintf(hi->mnem, "if (P%d.new) R%d = memw (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5800000) { - // Instruction: 4: 01000101100sssssPP0ttiiiiiiddddd | if !Pt Rd = memw (Rs + #u6:2) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMW__RS____U6_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 2; // scaled - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend_off(&hi->ops[3], 2); - sprintf(hi->mnem, "if !P%d R%d = memw (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7800000) { - // Instruction: 4: 01000111100sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memw (Rs + #u6:2) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMW__RS____U6_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x7e0) >> 5) << 2; // scaled - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend_off(&hi->ops[3], 2); - sprintf(hi->mnem, "if !P%d.new R%d = memw (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e01800) == 0x8a00000) { - // Instruction: 4: 01001ii0101iiiiiPPi00tttiiiiiiii | memb (gp + #u16:0) = Nt.new - hi->instruction = HEX_INS_MEMB__GP____U16_0____NT_NEW; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[0]); - sprintf(hi->mnem, "memb (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0xa00000) { - // Instruction: 4: 01000000101sssssPPi00tttiiiii0vv | if (Pv) memb (Rs + #u6:0) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMB__RS____U6_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x2a00000) { - // Instruction: 4: 01000010101sssssPPi00tttiiiii0vv | if (Pv.new) memb (Rs + #u6:0) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS____U6_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x4a00000) { - // Instruction: 4: 01000100101sssssPPi00tttiiiii0vv | if !Pv memb (Rs + #u6:0) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS____U6_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x6a00000) { - // Instruction: 4: 01000110101sssssPPi00tttiiiii0vv | if !Pv.new memb (Rs + #u6:0) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS____U6_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e01800) == 0x8a00800) { - // Instruction: 4: 01001ii0101iiiiiPPi01tttiiiiiiii | memh (gp + #u16:1) = Nt.new - hi->instruction = HEX_INS_MEMH__GP____U16_1____NT_NEW; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0xa00800) { - // Instruction: 4: 01000000101sssssPPi01tttiiiii0vv | if (Pv) memh (Rs + #u6:1) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMH__RS____U6_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x2a00800) { - // Instruction: 4: 01000010101sssssPPi01tttiiiii0vv | if (Pv.new) memh (Rs + #u6:1) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS____U6_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x4a00800) { - // Instruction: 4: 01000100101sssssPPi01tttiiiii0vv | if !Pv memh (Rs + #u6:1) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS____U6_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x6a00800) { - // Instruction: 4: 01000110101sssssPPi01tttiiiii0vv | if !Pv.new memh (Rs + #u6:1) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS____U6_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e01800) == 0x8a01000) { - // Instruction: 4: 01001ii0101iiiiiPPi10tttiiiiiiii | memw (gp + #u16:2) = Nt.new - hi->instruction = HEX_INS_MEMW__GP____U16_2____NT_NEW; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0xa01000) { - // Instruction: 4: 01000000101sssssPPi10tttiiiii0vv | if (Pv) memw (Rs + #u6:2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMW__RS____U6_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x2a01000) { - // Instruction: 4: 01000010101sssssPPi10tttiiiii0vv | if (Pv.new) memw (Rs + #u6:2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS____U6_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x4a01000) { - // Instruction: 4: 01000100101sssssPPi10tttiiiii0vv | if !Pv memw (Rs + #u6:2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS____U6_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x6a01000) { - // Instruction: 4: 01000110101sssssPPi10tttiiiii0vv | if !Pv.new memw (Rs + #u6:2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS____U6_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8c00000) { - // Instruction: 4: 01001ii0110iiiiiPPitttttiiiiiiii | memd (gp + #u16:3) = Rtt - hi->instruction = HEX_INS_MEMD__GP____U16_3____RTT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 3; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (gp + 0x%x) = R%d:R%d", hi->ops[0].op.imm, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0xc00000) { - // Instruction: 4: 01000000110sssssPPitttttiiiii0vv | if (Pv) memd (Rs + #u6:3) = Rtt - hi->instruction = HEX_INS_IF__PV__MEMD__RS____U6_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 3; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "if (P%d) memd (R%d + 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2c00000) { - // Instruction: 4: 01000010110sssssPPitttttiiiii0vv | if (Pv.new) memd (Rs + #u6:3) = Rtt - hi->instruction = HEX_INS_IF__PV_NEW__MEMD__RS____U6_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 3; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "if (P%d.new) memd (R%d + 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4c00000) { - // Instruction: 4: 01000100110sssssPPitttttiiiii0vv | if !Pv memd (Rs + #u6:3) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_MEMD__RS____U6_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 3; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "if !P%d memd (R%d + 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6c00000) { - // Instruction: 4: 01000110110sssssPPitttttiiiii0vv | if !Pv.new memd (Rs + #u6:3) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMD__RS____U6_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 3; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "if !P%d.new memd (R%d + 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8000000) { - // Instruction: 4: 01001ii0000iiiiiPPitttttiiiiiiii | memb (gp + #u16:0) = Rt - hi->instruction = HEX_INS_MEMB__GP____U16_0____RT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[0]); - sprintf(hi->mnem, "memb (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x0) { - // Instruction: 4: 01000000000sssssPPitttttiiiii0vv | if (Pv) memb (Rs + #u6:0) = Rt - hi->instruction = HEX_INS_IF__PV__MEMB__RS____U6_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2000000) { - // Instruction: 4: 01000010000sssssPPitttttiiiii0vv | if (Pv.new) memb (Rs + #u6:0) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS____U6_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4000000) { - // Instruction: 4: 01000100000sssssPPitttttiiiii0vv | if !Pv memb (Rs + #u6:0) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS____U6_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6000000) { - // Instruction: 4: 01000110000sssssPPitttttiiiii0vv | if !Pv.new memb (Rs + #u6:0) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS____U6_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8400000) { - // Instruction: 4: 01001ii0010iiiiiPPitttttiiiiiiii | memh (gp + #u16:1) = Rt - hi->instruction = HEX_INS_MEMH__GP____U16_1____RT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8600000) { - // Instruction: 4: 01001ii0011iiiiiPPitttttiiiiiiii | memh (gp + #u16:1) = Rt.H - hi->instruction = HEX_INS_MEMH__GP____U16_1____RT_H; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (gp + 0x%x) = R%d.H", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x400000) { - // Instruction: 4: 01000000010sssssPPitttttiiiii0vv | if (Pv) memh (Rs + #u6:1) = Rt - hi->instruction = HEX_INS_IF__PV__MEMH__RS____U6_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "if (P%d) memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x600000) { - // Instruction: 4: 01000000011sssssPPitttttiiiii0vv | if (Pv) memh (Rs + #u6:1) = Rt.H - hi->instruction = HEX_INS_IF__PV__MEMH__RS____U6_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2400000) { - // Instruction: 4: 01000010010sssssPPitttttiiiii0vv | if (Pv.new) memh (Rs + #u6:1) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS____U6_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "if (P%d.new) memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2600000) { - // Instruction: 4: 01000010011sssssPPitttttiiiii0vv | if (Pv.new) memh (Rs + #u6:1) = Rt.H - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS____U6_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4400000) { - // Instruction: 4: 01000100010sssssPPitttttiiiii0vv | if !Pv memh (Rs + #u6:1) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS____U6_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4600000) { - // Instruction: 4: 01000100011sssssPPitttttiiiii0vv | if !Pv memh (Rs + #u6:1) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS____U6_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6400000) { - // Instruction: 4: 01000110010sssssPPitttttiiiii0vv | if !Pv.new memh (Rs + #u6:1) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS____U6_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "if !P%d.new memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6600000) { - // Instruction: 4: 01000110011sssssPPitttttiiiii0vv | if !Pv.new memh (Rs + #u6:1) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS____U6_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8800000) { - // Instruction: 4: 01001ii0100iiiiiPPitttttiiiiiiii | memw (gp + #u16:2) = Rt - hi->instruction = HEX_INS_MEMW__GP____U16_2____RT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x800000) { - // Instruction: 4: 01000000100sssssPPitttttiiiii0vv | if (Pv) memw (Rs + #u6:2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMW__RS____U6_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (P%d) memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2800000) { - // Instruction: 4: 01000010100sssssPPitttttiiiii0vv | if (Pv.new) memw (Rs + #u6:2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS____U6_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (P%d.new) memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4800000) { - // Instruction: 4: 01000100100sssssPPitttttiiiii0vv | if !Pv memw (Rs + #u6:2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS____U6_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if !P%d memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6800000) { - // Instruction: 4: 01000110100sssssPPitttttiiiii0vv | if !Pv.new memw (Rs + #u6:2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS____U6_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if !P%d.new memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - break; - } - case 0x5: { - if ((hi_u32 & 0xfe00000) == 0xa00000) { - // Instruction: 5: 01010000101sssssPP-------------- | callr Rs - hi->instruction = HEX_INS_CALLR_RS; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "callr R%d", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1000000) { - // Instruction: 5: 01010001000sssssPP----uu-------- | if (Pu) callr Rs - hi->instruction = HEX_INS_IF__PU__CALLR_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) callr R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1200000) { - // Instruction: 5: 01010001001sssssPP----uu-------- | if !Pu callr Rs - hi->instruction = HEX_INS_IF__NOT_PU_CALLR_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d callr R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2a00000) { - // Instruction: 5: 01010010101sssssPP-------------- | hintjr (Rs) - hi->instruction = HEX_INS_HINTJR__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "hintjr (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2800000) { - // Instruction: 5: 01010010100sssssPP-------------- | jumpr Rs - hi->instruction = HEX_INS_JUMPR_RS; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "jumpr R%d", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3400000) { - // Instruction: 5: 01010011010sssssPP-00-uu-------- | if (Pu) jumpr:nt Rs - hi->instruction = HEX_INS_IF__PU__JUMPR_NT_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) jumpr:nt R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3400800) { - // Instruction: 5: 01010011010sssssPP-01-uu-------- | if (Pu.new) jumpr:nt Rs - hi->instruction = HEX_INS_IF__PU_NEW__JUMPR_NT_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) jumpr:nt R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3401000) { - // Instruction: 5: 01010011010sssssPP-10-uu-------- | if (Pu) jumpr:t Rs - hi->instruction = HEX_INS_IF__PU__JUMPR_T_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) jumpr:t R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3401800) { - // Instruction: 5: 01010011010sssssPP-11-uu-------- | if (Pu.new) jumpr:t Rs - hi->instruction = HEX_INS_IF__PU_NEW__JUMPR_T_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) jumpr:t R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3600000) { - // Instruction: 5: 01010011011sssssPP-00-uu-------- | if !Pu jumpr:nt Rs - hi->instruction = HEX_INS_IF__NOT_PU_JUMPR_NT_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d jumpr:nt R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3600800) { - // Instruction: 5: 01010011011sssssPP-01-uu-------- | if !Pu.new jumpr:nt Rs - hi->instruction = HEX_INS_IF__NOT_PU_NEW_JUMPR_NT_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new jumpr:nt R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3601000) { - // Instruction: 5: 01010011011sssssPP-10-uu-------- | if !Pu jumpr:t Rs - hi->instruction = HEX_INS_IF__NOT_PU_JUMPR_T_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d jumpr:t R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3601800) { - // Instruction: 5: 01010011011sssssPP-11-uu-------- | if !Pu.new jumpr:t Rs - hi->instruction = HEX_INS_IF__NOT_PU_NEW_JUMPR_T_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new jumpr:t R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xe000001) == 0xa000000) { - // Instruction: 5: 0101101iiiiiiiiiPPiiiiiiiiiiiii0 | call #r22:2 - hi->instruction = HEX_INS_CALL__R22_2; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1ff0000) >> 3) | ((hi_u32 & 0x3ffe) >> 1)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 23)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 23); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "call 0x%x", addr + (st32) hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xf200800) == 0xd000000) { - // Instruction: 5: 01011101ii0iiiiiPPi-0-uuiiiiiii- | if (Pu) call #r15:2 - hi->instruction = HEX_INS_IF__PU__CALL__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "if (P%d) call 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf200800) == 0xd200000) { - // Instruction: 5: 01011101ii1iiiiiPPi-0-uuiiiiiii- | if !Pu call #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_CALL__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "if !P%d call 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xe000000) == 0x8000000) { - // Instruction: 5: 0101100iiiiiiiiiPPiiiiiiiiiiiii- | jump #r22:2 - hi->instruction = HEX_INS_JUMP__R22_2; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1ff0000) >> 3) | ((hi_u32 & 0x3ffe) >> 1)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 23)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 23); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "jump 0x%x", addr + (st32) hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc000000) { - // Instruction: 5: 01011100ii0iiiiiPPi00-uuiiiiiii- | if (Pu) jump:nt #r15:2 - hi->instruction = HEX_INS_IF__PU__JUMP_NT__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) jump:nt 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc001000) { - // Instruction: 5: 01011100ii0iiiiiPPi10-uuiiiiiii- | if (Pu) jump:t #r15:2 - hi->instruction = HEX_INS_IF__PU__JUMP_T__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) jump:t 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc200000) { - // Instruction: 5: 01011100ii1iiiiiPPi00-uuiiiiiii- | if !Pu jump:nt #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_JUMP_NT__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d jump:nt 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc201000) { - // Instruction: 5: 01011100ii1iiiiiPPi10-uuiiiiiii- | if !Pu jump:t #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_JUMP_T__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d jump:t 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc000800) { - // Instruction: 5: 01011100ii0iiiiiPPi01-uuiiiiiii- | if (Pu.new) jump:nt #r15:2 - hi->instruction = HEX_INS_IF__PU_NEW__JUMP_NT__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) jump:nt 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc001800) { - // Instruction: 5: 01011100ii0iiiiiPPi11-uuiiiiiii- | if (Pu.new) jump:t #r15:2 - hi->instruction = HEX_INS_IF__PU_NEW__JUMP_T__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) jump:t 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc200800) { - // Instruction: 5: 01011100ii1iiiiiPPi01-uuiiiiiii- | if !Pu.new jump:nt #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_NEW_JUMP_NT__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new jump:nt 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc201800) { - // Instruction: 5: 01011100ii1iiiiiPPi11-uuiiiiiii- | if !Pu.new jump:t #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_NEW_JUMP_T__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new jump:t 0x%x", hi->ops[0].op.pred, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5a00000) { - // Instruction: 5: 01010101101sssssPP---------ddddd | Rd = icdatar (Rs) - hi->instruction = HEX_INS_RD___ICDATAR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = icdatar (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5e00000) { - // Instruction: 5: 01010101111sssssPP---------ddddd | Rd = ictagr (Rs) - hi->instruction = HEX_INS_RD___ICTAGR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ictagr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0x6c00800) { - // Instruction: 5: 01010110110sssssPP001----------- | icinvidx (Rs) - hi->instruction = HEX_INS_ICINVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "icinvidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5c00000) { - // Instruction: 5: 01010101110sssssPP-ttttt-------- | ictagw (Rs, Rt) - hi->instruction = HEX_INS_ICTAGW__RS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "ictagw (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0x6c01000) { - // Instruction: 5: 01010110110-----PP010----------- | ickill - hi->instruction = HEX_INS_ICKILL; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "ickill"); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x7e00000) { - // Instruction: 5: 01010111111-----PP00----000----- | rte - hi->instruction = HEX_INS_RTE; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "rte"); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x7e01000) { - // Instruction: 5: 01010111111-----PP01----000----- | rteunlock - hi->instruction = HEX_INS_RTEUNLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "rteunlock"); - break; - } - if ((hi_u32 & 0xfe03800) == 0x6c00000) { - // Instruction: 5: 01010110110sssssPP000----------- | icinva (Rs) - hi->instruction = HEX_INS_ICINVA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "icinva (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfff23ff) == 0x7c00002) { - // Instruction: 5: 0101011111000000PP0---0000000010 | isync - hi->instruction = HEX_INS_ISYNC; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "isync"); - break; - } - if ((hi_u32 & 0xfc00000) == 0x4400000) { - // Instruction: 5: 0101010001------PP-iiiii---iii-- | pause (#u8) - hi->instruction = HEX_INS_PAUSE___U8_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 5) | ((hi_u32 & 0x1c) >> 2)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "pause (0x%x)", hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x4000000) { - // Instruction: 5: 0101010000------PP-iiiii---iii-- | trap0 (#u8) - hi->instruction = HEX_INS_TRAP0___U8_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 5) | ((hi_u32 & 0x1c) >> 2)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "trap0 (0x%x)", hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x4800000) { - // Instruction: 5: 0101010010------PP-iiiii---iii-- | trap1 (#u8) - hi->instruction = HEX_INS_TRAP1___U8_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 5) | ((hi_u32 & 0x1c) >> 2)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "trap1 (0x%x)", hi->ops[0].op.imm); - break; - } - break; - } - case 0x6: { - if ((hi_u32 & 0xff02090) == 0xb002090) { - // Instruction: 6: 011010110000--ssPP1---tt1--1--dd | Pd = fastcorner9 (Ps, Pt) - hi->instruction = HEX_INS_PD___FASTCORNER9__PS__PT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = fastcorner9 (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02090) == 0xb102090) { - // Instruction: 6: 011010110001--ssPP1---tt1--1--dd | Pd = !fastcorner9 (Ps, Pt) - hi->instruction = HEX_INS_PD____NOT_FASTCORNER9__PS__PT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !fastcorner9 (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb800000) { - // Instruction: 6: 011010111000--ssPP0-----------dd | Pd = any8 (Ps) - hi->instruction = HEX_INS_PD___ANY8__PS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = any8 (P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xba00000) { - // Instruction: 6: 011010111010--ssPP0-----------dd | Pd = all8 (Ps) - hi->instruction = HEX_INS_PD___ALL8__PS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = all8 (P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xfe00000) == 0x0) { - // Instruction: 6: 01100000000sssssPP-iiiii---ii--- | loop0 (#r7:2, Rs) - hi->instruction = HEX_INS_LOOP0___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "loop0 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x200000) { - // Instruction: 6: 01100000001sssssPP-iiiii---ii--- | loop1 (#r7:2, Rs) - hi->instruction = HEX_INS_LOOP1___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "loop1 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9000000) { - // Instruction: 6: 01101001000IIIIIPP-iiiiiIIIii-II | loop0 (#r7:2, #U10) - hi->instruction = HEX_INS_LOOP0___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "loop0 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9200000) { - // Instruction: 6: 01101001001IIIIIPP-iiiiiIIIii-II | loop1 (#r7:2, #U10) - hi->instruction = HEX_INS_LOOP1___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "loop1 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfff0000) == 0xa490000) { - // Instruction: 6: 0110101001001001PP-iiiiii--ddddd | Rd = add (pc, #u6) - hi->instruction = HEX_INS_RD___ADD__PC___U6_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1f80) >> 7); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = add (pc, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa00000) { - // Instruction: 6: 01100000101sssssPP-iiiii---ii--- | p3 = sp1loop0 (#r7:2, Rs) - hi->instruction = HEX_INS_P3___SP1LOOP0___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp1loop0 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xc00000) { - // Instruction: 6: 01100000110sssssPP-iiiii---ii--- | p3 = sp2loop0 (#r7:2, Rs) - hi->instruction = HEX_INS_P3___SP2LOOP0___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp2loop0 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xe00000) { - // Instruction: 6: 01100000111sssssPP-iiiii---ii--- | p3 = sp3loop0 (#r7:2, Rs) - hi->instruction = HEX_INS_P3___SP3LOOP0___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp3loop0 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9a00000) { - // Instruction: 6: 01101001101IIIIIPP-iiiiiIIIii-II | p3 = sp1loop0 (#r7:2, #U10) - hi->instruction = HEX_INS_P3___SP1LOOP0___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp1loop0 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9c00000) { - // Instruction: 6: 01101001110IIIIIPP-iiiiiIIIii-II | p3 = sp2loop0 (#r7:2, #U10) - hi->instruction = HEX_INS_P3___SP2LOOP0___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp2loop0 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9e00000) { - // Instruction: 6: 01101001111IIIIIPP-iiiiiIIIii-II | p3 = sp3loop0 (#r7:2, #U10) - hi->instruction = HEX_INS_P3___SP3LOOP0___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp3loop0 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff02000) == 0xb000000) { - // Instruction: 6: 011010110000--ssPP0---tt------dd | Pd = and (Pt, Ps) - hi->instruction = HEX_INS_PD___AND__PT__PS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb100000) { - // Instruction: 6: 011010110001--ssPP0---ttuu----dd | Pd = and (Ps, and (Pt, Pu)) - hi->instruction = HEX_INS_PD___AND__PS__AND__PT__PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, and (P%d, P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb200000) { - // Instruction: 6: 011010110010--ssPP0---tt------dd | Pd = or (Pt, Ps) - hi->instruction = HEX_INS_PD___OR__PT__PS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb300000) { - // Instruction: 6: 011010110011--ssPP0---ttuu----dd | Pd = and (Ps, or (Pt, Pu)) - hi->instruction = HEX_INS_PD___AND__PS__OR__PT__PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, or (P%d, P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb400000) { - // Instruction: 6: 011010110100--ssPP0---tt------dd | Pd = xor (Ps, Pt) - hi->instruction = HEX_INS_PD___XOR__PS__PT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = xor (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb500000) { - // Instruction: 6: 011010110101--ssPP0---ttuu----dd | Pd = or (Ps, and (Pt, Pu)) - hi->instruction = HEX_INS_PD___OR__PS__AND__PT__PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, and (P%d, P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb600000) { - // Instruction: 6: 011010110110--ssPP0---tt------dd | Pd = and (Pt, !Ps) - hi->instruction = HEX_INS_PD___AND__PT___NOT_PS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, !P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb700000) { - // Instruction: 6: 011010110111--ssPP0---ttuu----dd | Pd = or (Ps, or (Pt, Pu)) - hi->instruction = HEX_INS_PD___OR__PS__OR__PT__PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, or (P%d, P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb900000) { - // Instruction: 6: 011010111001--ssPP0---ttuu----dd | Pd = and (Ps, and (Pt, !Pu)) - hi->instruction = HEX_INS_PD___AND__PS__AND__PT___NOT_PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, and (P%d, !P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbb00000) { - // Instruction: 6: 011010111011--ssPP0---ttuu----dd | Pd = and (Ps, or (Pt, !Pu)) - hi->instruction = HEX_INS_PD___AND__PS__OR__PT___NOT_PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, or (P%d, !P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbc00000) { - // Instruction: 6: 011010111100--ssPP0-----------dd | Pd = not (Ps) - hi->instruction = HEX_INS_PD___NOT__PS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = not (P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbd00000) { - // Instruction: 6: 011010111101--ssPP0---ttuu----dd | Pd = or (Ps, and (Pt, !Pu)) - hi->instruction = HEX_INS_PD___OR__PS__AND__PT___NOT_PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, and (P%d, !P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbe00000) { - // Instruction: 6: 011010111110--ssPP0---tt------dd | Pd = or (Pt, !Ps) - hi->instruction = HEX_INS_PD___OR__PT___NOT_PS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, !P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbf00000) { - // Instruction: 6: 011010111111--ssPP0---ttuu----dd | Pd = or (Ps, or (Pt, !Pu)) - hi->instruction = HEX_INS_PD___OR__PS__OR__PT___NOT_PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, or (P%d, !P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2200000) { - // Instruction: 6: 01100010001sssssPP---------ddddd | Cd = Rs - hi->instruction = HEX_INS_CD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_CONTROL; - hi->ops[0].op.cr = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = R%d", hex_get_cntl_reg(hi->ops[0].op.cr), hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3200000) { - // Instruction: 6: 01100011001sssssPP---------ddddd | Cdd = Rss - hi->instruction = HEX_INS_CDD___RSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_CONTROL; - hi->ops[0].op.cr = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%sd = R%d:R%d", hex_get_cntl_reg(hi->ops[0].op.cr), hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8000000) { - // Instruction: 6: 01101000000sssssPP---------ddddd | Rdd = Css - hi->instruction = HEX_INS_RDD___CSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_CONTROL; - hi->ops[1].op.cr = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = %ss", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hex_get_cntl_reg(hi->ops[1].op.cr)); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa000000) { - // Instruction: 6: 01101010000sssssPP---------ddddd | Rd = Cs - hi->instruction = HEX_INS_RD___CS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_CONTROL; - hi->ops[1].op.cr = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = %s", hi->ops[0].op.reg, hex_get_cntl_reg(hi->ops[1].op.cr)); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1000000) { - // Instruction: 6: 0110000100isssssPPi0iiiiiiiiiii- | if (Rs != #0) jump:nt #r13:2 - hi->instruction = HEX_INS_IF__RS__NOT____0__JUMP_NT__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d != #0) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1001000) { - // Instruction: 6: 0110000100isssssPPi1iiiiiiiiiii- | if (Rs != #0) jump:t #r13:2 - hi->instruction = HEX_INS_IF__RS__NOT____0__JUMP_T__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d != #0) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1400000) { - // Instruction: 6: 0110000101isssssPPi0iiiiiiiiiii- | if (Rs> = #0) jump:nt #r13:2 - hi->instruction = HEX_INS_IF__RS_GT_EQ___0__JUMP_NT__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d> = #0) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1401000) { - // Instruction: 6: 0110000101isssssPPi1iiiiiiiiiii- | if (Rs> = #0) jump:t #r13:2 - hi->instruction = HEX_INS_IF__RS_GT_EQ___0__JUMP_T__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d> = #0) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1800000) { - // Instruction: 6: 0110000110isssssPPi0iiiiiiiiiii- | if (Rs == #0) jump:nt #r13:2 - hi->instruction = HEX_INS_IF__RS__EQ___0__JUMP_NT__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d == #0) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1801000) { - // Instruction: 6: 0110000110isssssPPi1iiiiiiiiiii- | if (Rs == #0) jump:t #r13:2 - hi->instruction = HEX_INS_IF__RS__EQ___0__JUMP_T__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d == #0) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1c00000) { - // Instruction: 6: 0110000111isssssPPi0iiiiiiiiiii- | if (Rs< = #0) jump:nt #r13:2 - hi->instruction = HEX_INS_IF__RS_LT_EQ___0__JUMP_NT__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d< = #0) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1c01000) { - // Instruction: 6: 0110000111isssssPPi1iiiiiiiiiii- | if (Rs< = #0) jump:t #r13:2 - hi->instruction = HEX_INS_IF__RS_LT_EQ___0__JUMP_T__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d< = #0) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2000000) { - // Instruction: 6: 01100010000sssssPP---------ddddd | Gd = Rs - hi->instruction = HEX_INS_GD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Gd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3000000) { - // Instruction: 6: 01100011000sssssPP---------ddddd | Gdd = Rss - hi->instruction = HEX_INS_GDD___RSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Gd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%dd = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8200000) { - // Instruction: 6: 01101000001sssssPP---------ddddd | Rdd = Gss - hi->instruction = HEX_INS_RDD___GSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Gs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = R%ds", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa200000) { - // Instruction: 6: 01101010001sssssPP---------ddddd | Rd = Gs - hi->instruction = HEX_INS_RD___GS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Gs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000060) { - // Instruction: 6: 01100100000sssssPP------011----- | ciad (Rs) - hi->instruction = HEX_INS_CIAD__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "ciad (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5000000) { - // Instruction: 6: 01100101000xxxxxPP-------------- | crswap (Rx, sgp0) - hi->instruction = HEX_INS_CRSWAP__RX__SGP0_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "crswap (R%d, sgp0)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5200000) { - // Instruction: 6: 01100101001xxxxxPP-------------- | crswap (Rx, sgp1) - hi->instruction = HEX_INS_CRSWAP__RX__SGP1_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "crswap (R%d, sgp1)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfc0001f) == 0xd800000) { - // Instruction: 6: 0110110110-xxxxxPP---------00000 | crswap (Rxx, sgp1:0) - hi->instruction = HEX_INS_CRSWAP__RXX__SGP1_0_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "crswap (R%d:R%d, sgp1:0)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000020) { - // Instruction: 6: 01100100000sssssPP------001----- | cswi (Rs) - hi->instruction = HEX_INS_CSWI__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "cswi (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6000000) { - // Instruction: 6: 01100110000sssssPP---------ddddd | Rd = getimask (Rs) - hi->instruction = HEX_INS_RD___GETIMASK__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = getimask (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200020) { - // Instruction: 6: 01101100001-----PP------001----- | tlblock - hi->instruction = HEX_INS_TLBLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "tlblock"); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200060) { - // Instruction: 6: 01101100001-----PP------011----- | k0lock - hi->instruction = HEX_INS_K0LOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "k0lock"); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200040) { - // Instruction: 6: 01101100001-----PP------010----- | tlbunlock - hi->instruction = HEX_INS_TLBUNLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "tlbunlock"); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200080) { - // Instruction: 6: 01101100001-----PP------100----- | k0unlock - hi->instruction = HEX_INS_K0UNLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "k0unlock"); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6600000) { - // Instruction: 6: 01100110011sssssPP---------ddddd | Rd = iassignr (Rs) - hi->instruction = HEX_INS_RD___IASSIGNR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = iassignr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000040) { - // Instruction: 6: 01100100000sssssPP------010----- | iassignw (Rs) - hi->instruction = HEX_INS_IASSIGNW__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "iassignw (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4600040) { - // Instruction: 6: 01100100011sssssPP------010----- | nmi (Rs) - hi->instruction = HEX_INS_NMI__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "nmi (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4400020) { - // Instruction: 6: 01100100010sssssPP------001----- | resume (Rs) - hi->instruction = HEX_INS_RESUME__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "resume (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4800000) { - // Instruction: 6: 01100100100sssssPP----tt000----- | setimask (Pt, Rs) - hi->instruction = HEX_INS_SETIMASK__PT__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "setimask (P%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4800060) { - // Instruction: 6: 01100100100sssssPP------011----- | siad (Rs) - hi->instruction = HEX_INS_SIAD__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "siad (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4600020) { - // Instruction: 6: 01100100011sssssPP------001----- | start (Rs) - hi->instruction = HEX_INS_START__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "start (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4600000) { - // Instruction: 6: 01100100011sssssPP------000----- | stop (Rs) - hi->instruction = HEX_INS_STOP__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "stop (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000000) { - // Instruction: 6: 01100100000sssssPP------000----- | swi (Rs) - hi->instruction = HEX_INS_SWI__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "swi (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xc000000) { - // Instruction: 6: 01101100000sssssPP0ttttt-------- | tlbw (Rss, Rt) - hi->instruction = HEX_INS_TLBW__RSS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "tlbw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xc400000) { - // Instruction: 6: 01101100010sssssPP---------ddddd | Rdd = tlbr (Rs) - hi->instruction = HEX_INS_RDD___TLBR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = tlbr (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xc800000) { - // Instruction: 6: 01101100100sssssPP---------ddddd | Rd = tlbp (Rs) - hi->instruction = HEX_INS_RD___TLBP__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = tlbp (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xca00000) { - // Instruction: 6: 01101100101sssssPP-------------- | tlbinvasid (Rs) - hi->instruction = HEX_INS_TLBINVASID__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "tlbinvasid (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xcc00000) { - // Instruction: 6: 01101100110sssssPP0ttttt---ddddd | Rd = ctlbw (Rss, Rt) - hi->instruction = HEX_INS_RD___CTLBW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ctlbw (R%d:R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xce00000) { - // Instruction: 6: 01101100111sssssPP---------ddddd | Rd = tlboc (Rss) - hi->instruction = HEX_INS_RD___TLBOC__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = tlboc (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7000000) { - // Instruction: 6: 0110011100-sssssPP--------dddddd | Sd = Rs - hi->instruction = HEX_INS_SD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_SYSTEM; - hi->ops[0].op.sys = (((hi_u32) & 0x3f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = R%d", hex_get_sys_reg(hi->ops[0].op.sys), hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc00000) == 0xd000000) { - // Instruction: 6: 0110110100-sssssPP--------dddddd | Sdd = Rss - hi->instruction = HEX_INS_SDD___RSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_SYSTEM; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.sys = (((hi_u32) & 0x3f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s:%s = R%d:R%d", hex_get_sys_reg(hi->ops[0].op.sys + 1), hex_get_sys_reg(hi->ops[0].op.sys), hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0xe800000) { - // Instruction: 6: 011011101-ssssssPP---------ddddd | Rd = Ss - hi->instruction = HEX_INS_RD___SS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_SYSTEM; - hi->ops[1].op.sys = (((hi_u32) & 0x3f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = %s", hi->ops[0].op.reg, hex_get_sys_reg(hi->ops[1].op.sys)); - break; - } - if ((hi_u32 & 0xf800000) == 0xf000000) { - // Instruction: 6: 011011110-ssssssPP---------ddddd | Rdd = Sss - hi->instruction = HEX_INS_RDD___SSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_SYSTEM; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.sys = (((hi_u32) & 0x3f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = %s:%s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hex_get_sys_reg(hi->ops[1].op.sys + 1), hex_get_sys_reg(hi->ops[1].op.sys)); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4400000) { - // Instruction: 6: 01100100010sssssPP------000----- | wait (Rs) - hi->instruction = HEX_INS_WAIT__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "wait (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200000) { - // Instruction: 6: 01101100001-----PP------000----- | brkpt - hi->instruction = HEX_INS_BRKPT; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "brkpt"); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2400000) { - // Instruction: 6: 01100010010sssssPP-------------- | trace (Rs) - hi->instruction = HEX_INS_TRACE__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "trace (R%d)", hi->ops[0].op.reg); - break; - } - break; - } - case 0x7: { - if ((hi_u32 & 0xfc00000) == 0x6000000) { - // Instruction: 7: 0111011000isssssPPiiiiiiiiiddddd | Rd = and (Rs, #s10) - hi->instruction = HEX_INS_RD___AND__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = and (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x6800000) { - // Instruction: 7: 0111011010isssssPPiiiiiiiiiddddd | Rd = or (Rs, #s10) - hi->instruction = HEX_INS_RD___OR__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = or (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0xf000000) { - // Instruction: 7: 01111111--------PP-------------- | nop - hi->instruction = HEX_INS_NOP; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "nop"); - break; - } - if ((hi_u32 & 0xfc00000) == 0x6400000) { - // Instruction: 7: 0111011001isssssPPiiiiiiiiiddddd | Rd = sub (#s10, Rs) - hi->instruction = HEX_INS_RD___SUB___S10__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[1].op.imm & (1 << 9)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 9); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = sub (%d, R%d)", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xa00000) { - // Instruction: 7: 01110000101sssssPP0--------ddddd | Rd = sxtb (Rs) - hi->instruction = HEX_INS_RD___SXTB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sxtb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xe00000) { - // Instruction: 7: 01110000111sssssPP0--------ddddd | Rd = sxth (Rs) - hi->instruction = HEX_INS_RD___SXTH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sxth (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf200000) == 0x1200000) { - // Instruction: 7: 01110001ii1xxxxxPPiiiiiiiiiiiiii | Rx.L = #u16 - hi->instruction = HEX_INS_RX_L____U16; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 8) | ((hi_u32 & 0x3fff) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d.L = 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf200000) == 0x2200000) { - // Instruction: 7: 01110010ii1xxxxxPPiiiiiiiiiiiiii | Rx.H = #u16 - hi->instruction = HEX_INS_RX_H____U16; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 8) | ((hi_u32 & 0x3fff) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d.H = 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x8000000) { - // Instruction: 7: 01111000ii-iiiiiPPiiiiiiiiiddddd | Rd = #s16 - hi->instruction = HEX_INS_RD____S16; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 8) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[1].op.imm & (1 << 15)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 15); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = %d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x600000) { - // Instruction: 7: 01110000011sssssPP0--------ddddd | Rd = Rs - hi->instruction = HEX_INS_RD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xc00000) { - // Instruction: 7: 01110000110sssssPP0--------ddddd | Rd = zxth (Rs) - hi->instruction = HEX_INS_RD___ZXTH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = zxth (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf602000) == 0x3002000) { - // Instruction: 7: 01110011-00sssssPP1iiiiiiiiddddd | Rdd = combine (Rs, #s8) - hi->instruction = HEX_INS_RDD___COMBINE__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d:R%d = combine (R%d, %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602000) == 0x3202000) { - // Instruction: 7: 01110011-01sssssPP1iiiiiiiiddddd | Rdd = combine (#s8, Rs) - hi->instruction = HEX_INS_RDD___COMBINE___S8__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[1].op.imm & (1 << 7)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d:R%d = combine (%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0xc000000) { - // Instruction: 7: 011111000IIIIIIIPPIiiiiiiiiddddd | Rdd = combine (#s8, #S8) - hi->instruction = HEX_INS_RDD___COMBINE___S8___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[1].op.imm & (1 << 7)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x7f0000) >> 15) | ((hi_u32 & 0x2000) >> 13)); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d:R%d = combine (%d, %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0xc800000) { - // Instruction: 7: 011111001--IIIIIPPIiiiiiiiiddddd | Rdd = combine (#s8, #U6) - hi->instruction = HEX_INS_RDD___COMBINE___S8___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[1].op.imm & (1 << 7)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x2000) >> 13)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d:R%d = combine (%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x3000000) { - // Instruction: 7: 011100110uusssssPP0iiiiiiiiddddd | Rd = mux (Pu, Rs, #s8) - hi->instruction = HEX_INS_RD___MUX__PU__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "R%d = mux (P%d, R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x3800000) { - // Instruction: 7: 011100111uusssssPP0iiiiiiiiddddd | Rd = mux (Pu, #s8, Rs) - hi->instruction = HEX_INS_RD___MUX__PU___S8__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = mux (P%d, %d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xe000000) == 0xa000000) { - // Instruction: 7: 0111101uuIIIIIIIPPIiiiiiiiiddddd | Rd = mux (Pu, #s8, #S8) - hi->instruction = HEX_INS_RD___MUX__PU___S8___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x1800000) >> 23); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x7f0000) >> 15) | ((hi_u32 & 0x2000) >> 13)); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = mux (P%d, %d, %d)", hi->ops[0].op.reg, hi->ops[1].op.pred, (st32) hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x0) { - // Instruction: 7: 01110000000sssssPP0--------ddddd | Rd = aslh (Rs) - hi->instruction = HEX_INS_RD___ASLH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = aslh (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x200000) { - // Instruction: 7: 01110000001sssssPP0--------ddddd | Rd = asrh (Rs) - hi->instruction = HEX_INS_RD___ASRH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asrh (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf802000) == 0x4000000) { - // Instruction: 7: 011101000uusssssPP0iiiiiiiiddddd | if (Pu) Rd = add (Rs, #s8) - hi->instruction = HEX_INS_IF__PU__RD___ADD__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d) R%d = add (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x4002000) { - // Instruction: 7: 011101000uusssssPP1iiiiiiiiddddd | if (Pu.new) Rd = add (Rs, #s8) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ADD__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d.new) R%d = add (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x4800000) { - // Instruction: 7: 011101001uusssssPP0iiiiiiiiddddd | if !Pu Rd = add (Rs, #s8) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ADD__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d R%d = add (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x4802000) { - // Instruction: 7: 011101001uusssssPP1iiiiiiiiddddd | if !Pu.new Rd = add (Rs, #s8) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ADD__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d.new R%d = add (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x2000) { - // Instruction: 7: 01110000000sssssPP1-00uu---ddddd | if (Pu) Rd = aslh (Rs) - hi->instruction = HEX_INS_IF__PU__RD___ASLH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = aslh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x2400) { - // Instruction: 7: 01110000000sssssPP1-01uu---ddddd | if (Pu.new) Rd = aslh (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ASLH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = aslh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x2800) { - // Instruction: 7: 01110000000sssssPP1-10uu---ddddd | if !Pu Rd = aslh (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ASLH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = aslh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x2c00) { - // Instruction: 7: 01110000000sssssPP1-11uu---ddddd | if !Pu.new Rd = aslh (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ASLH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = aslh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x202000) { - // Instruction: 7: 01110000001sssssPP1-00uu---ddddd | if (Pu) Rd = asrh (Rs) - hi->instruction = HEX_INS_IF__PU__RD___ASRH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = asrh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x202400) { - // Instruction: 7: 01110000001sssssPP1-01uu---ddddd | if (Pu.new) Rd = asrh (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ASRH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = asrh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x202800) { - // Instruction: 7: 01110000001sssssPP1-10uu---ddddd | if !Pu Rd = asrh (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ASRH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = asrh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x202c00) { - // Instruction: 7: 01110000001sssssPP1-11uu---ddddd | if !Pu.new Rd = asrh (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ASRH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = asrh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xa02000) { - // Instruction: 7: 01110000101sssssPP1-00uu---ddddd | if (Pu) Rd = sxtb (Rs) - hi->instruction = HEX_INS_IF__PU__RD___SXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = sxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xa02400) { - // Instruction: 7: 01110000101sssssPP1-01uu---ddddd | if (Pu.new) Rd = sxtb (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___SXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = sxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xa02800) { - // Instruction: 7: 01110000101sssssPP1-10uu---ddddd | if !Pu Rd = sxtb (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___SXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = sxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xa02c00) { - // Instruction: 7: 01110000101sssssPP1-11uu---ddddd | if !Pu.new Rd = sxtb (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___SXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = sxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xe02000) { - // Instruction: 7: 01110000111sssssPP1-00uu---ddddd | if (Pu) Rd = sxth (Rs) - hi->instruction = HEX_INS_IF__PU__RD___SXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = sxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xe02400) { - // Instruction: 7: 01110000111sssssPP1-01uu---ddddd | if (Pu.new) Rd = sxth (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___SXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = sxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xe02800) { - // Instruction: 7: 01110000111sssssPP1-10uu---ddddd | if !Pu Rd = sxth (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___SXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = sxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xe02c00) { - // Instruction: 7: 01110000111sssssPP1-11uu---ddddd | if !Pu.new Rd = sxth (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___SXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = sxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf902000) == 0xe000000) { - // Instruction: 7: 011111100uu0iiiiPP0iiiiiiiiddddd | if (Pu) Rd = #s12 - hi->instruction = HEX_INS_IF__PU__RD____S12; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf0000) >> 8) | ((hi_u32 & 0x1fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf902000) == 0xe002000) { - // Instruction: 7: 011111100uu0iiiiPP1iiiiiiiiddddd | if (Pu.new) Rd = #s12 - hi->instruction = HEX_INS_IF__PU_NEW__RD____S12; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf0000) >> 8) | ((hi_u32 & 0x1fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf902000) == 0xe800000) { - // Instruction: 7: 011111101uu0iiiiPP0iiiiiiiiddddd | if !Pu Rd = #s12 - hi->instruction = HEX_INS_IF__NOT_PU_RD____S12; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf0000) >> 8) | ((hi_u32 & 0x1fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf902000) == 0xe802000) { - // Instruction: 7: 011111101uu0iiiiPP1iiiiiiiiddddd | if !Pu.new Rd = #s12 - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD____S12; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf0000) >> 8) | ((hi_u32 & 0x1fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x802000) { - // Instruction: 7: 01110000100sssssPP1-00uu---ddddd | if (Pu) Rd = zxtb (Rs) - hi->instruction = HEX_INS_IF__PU__RD___ZXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = zxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x802400) { - // Instruction: 7: 01110000100sssssPP1-01uu---ddddd | if (Pu.new) Rd = zxtb (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ZXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = zxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x802800) { - // Instruction: 7: 01110000100sssssPP1-10uu---ddddd | if !Pu Rd = zxtb (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ZXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = zxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x802c00) { - // Instruction: 7: 01110000100sssssPP1-11uu---ddddd | if !Pu.new Rd = zxtb (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ZXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = zxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xc02000) { - // Instruction: 7: 01110000110sssssPP1-00uu---ddddd | if (Pu) Rd = zxth (Rs) - hi->instruction = HEX_INS_IF__PU__RD___ZXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = zxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xc02400) { - // Instruction: 7: 01110000110sssssPP1-01uu---ddddd | if (Pu.new) Rd = zxth (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ZXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = zxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xc02800) { - // Instruction: 7: 01110000110sssssPP1-10uu---ddddd | if !Pu Rd = zxth (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ZXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = zxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xc02c00) { - // Instruction: 7: 01110000110sssssPP1-11uu---ddddd | if !Pu.new Rd = zxth (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ZXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = zxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc0001c) == 0x5000000) { - // Instruction: 7: 0111010100isssssPPiiiiiiiii000dd | Pd = cmp.eq (Rs, #s10) - hi->instruction = HEX_INS_PD___CMP_EQ__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmp.eq (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc0001c) == 0x5000010) { - // Instruction: 7: 0111010100isssssPPiiiiiiiii100dd | Pd = !cmp.eq (Rs, #s10) - hi->instruction = HEX_INS_PD____NOT_CMP_EQ__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = !cmp.eq (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc0001c) == 0x5400000) { - // Instruction: 7: 0111010101isssssPPiiiiiiiii000dd | Pd = cmp.gt (Rs, #s10) - hi->instruction = HEX_INS_PD___CMP_GT__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmp.gt (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc0001c) == 0x5400010) { - // Instruction: 7: 0111010101isssssPPiiiiiiiii100dd | Pd = !cmp.gt (Rs, #s10) - hi->instruction = HEX_INS_PD____NOT_CMP_GT__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = !cmp.gt (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe0001c) == 0x5800000) { - // Instruction: 7: 01110101100sssssPPiiiiiiiii000dd | Pd = cmp.gtu (Rs, #u9) - hi->instruction = HEX_INS_PD___CMP_GTU__RS___U9_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3fe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmp.gtu (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe0001c) == 0x5800010) { - // Instruction: 7: 01110101100sssssPPiiiiiiiii100dd | Pd = !cmp.gtu (Rs, #u9) - hi->instruction = HEX_INS_PD____NOT_CMP_GTU__RS___U9_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3fe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = !cmp.gtu (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602000) == 0x3402000) { - // Instruction: 7: 01110011-10sssssPP1iiiiiiiiddddd | Rd = cmp.eq (Rs, #s8) - hi->instruction = HEX_INS_RD___CMP_EQ__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = cmp.eq (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602000) == 0x3602000) { - // Instruction: 7: 01110011-11sssssPP1iiiiiiiiddddd | Rd = !cmp.eq (Rs, #s8) - hi->instruction = HEX_INS_RD____NOT_CMP_EQ__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = !cmp.eq (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - break; - } - case 0x8: { - if ((hi_u32 & 0xfe000e0) == 0x8000c0) { - // Instruction: 8: 10000000100sssssPP------110ddddd | Rdd = abs (Rss) - hi->instruction = HEX_INS_RDD___ABS__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = abs (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc800080) { - // Instruction: 8: 10001100100sssssPP------100ddddd | Rd = abs (Rs) - hi->instruction = HEX_INS_RD___ABS__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = abs (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc8000a0) { - // Instruction: 8: 10001100100sssssPP------101ddddd | Rd = abs (Rs) :sat - hi->instruction = HEX_INS_RD___ABS__RS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = abs (R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x800080) { - // Instruction: 8: 10000000100sssssPP------100ddddd | Rdd = not (Rss) - hi->instruction = HEX_INS_RDD___NOT__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = not (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000a0) { - // Instruction: 8: 10000000100sssssPP------101ddddd | Rdd = neg (Rss) - hi->instruction = HEX_INS_RDD___NEG__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = neg (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc8000c0) { - // Instruction: 8: 10001100100sssssPP------110ddddd | Rd = neg (Rs) :sat - hi->instruction = HEX_INS_RD___NEG__RS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = neg (R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8c00020) { - // Instruction: 8: 10001000110sssssPP------001ddddd | Rd = round (Rss) :sat - hi->instruction = HEX_INS_RD___ROUND__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = round (R%d:R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020c0) == 0xce00000) { - // Instruction: 8: 10001100111sssssPP0iiiii00-ddddd | Rd = cround (Rs, #u5) - hi->instruction = HEX_INS_RD___CROUND__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cround (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020c0) == 0xce00080) { - // Instruction: 8: 10001100111sssssPP0iiiii10-ddddd | Rd = round (Rs, #u5) - hi->instruction = HEX_INS_RD___ROUND__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = round (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020c0) == 0xce000c0) { - // Instruction: 8: 10001100111sssssPP0iiiii11-ddddd | Rd = round (Rs, #u5) :sat - hi->instruction = HEX_INS_RD___ROUND__RS___U5___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = round (R%d, 0x%x) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4400000) { - // Instruction: 8: 1000010001-sssssPP------00-ddddd | Rdd = sxtw (Rs) - hi->instruction = HEX_INS_RDD___SXTW__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = sxtw (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x400080) { - // Instruction: 8: 10000000010sssssPP------100ddddd | Rdd = vabsh (Rss) - hi->instruction = HEX_INS_RDD___VABSH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsh (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000a0) { - // Instruction: 8: 10000000010sssssPP------101ddddd | Rdd = vabsh (Rss) :sat - hi->instruction = HEX_INS_RDD___VABSH__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vabsh (R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000c0) { - // Instruction: 8: 10000000010sssssPP------110ddddd | Rdd = vabsw (Rss) - hi->instruction = HEX_INS_RDD___VABSW__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsw (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000e0) { - // Instruction: 8: 10000000010sssssPP------111ddddd | Rdd = vabsw (Rss) :sat - hi->instruction = HEX_INS_RDD___VABSW__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vabsw (R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8400000) { - // Instruction: 8: 10001000010sssssPP------000ddddd | Rd = clb (Rss) - hi->instruction = HEX_INS_RD___CLB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = clb (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8400040) { - // Instruction: 8: 10001000010sssssPP------010ddddd | Rd = cl0 (Rss) - hi->instruction = HEX_INS_RD___CL0__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cl0 (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8400080) { - // Instruction: 8: 10001000010sssssPP------100ddddd | Rd = cl1 (Rss) - hi->instruction = HEX_INS_RD___CL1__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cl1 (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8600000) { - // Instruction: 8: 10001000011sssssPP------000ddddd | Rd = normamt (Rss) - hi->instruction = HEX_INS_RD___NORMAMT__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = normamt (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8600040) { - // Instruction: 8: 10001000011sssssPPiiiiii010ddddd | Rd = add (clb (Rss), #s6) - hi->instruction = HEX_INS_RD___ADD__CLB__RSS____S6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (clb (R%d:R%d), %d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200000) { - // Instruction: 8: 10001100001sssssPPiiiiii000ddddd | Rd = add (clb (Rs), #s6) - hi->instruction = HEX_INS_RD___ADD__CLB__RS____S6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (clb (R%d), %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc000080) { - // Instruction: 8: 10001100000sssssPP------100ddddd | Rd = clb (Rs) - hi->instruction = HEX_INS_RD___CLB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = clb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc0000a0) { - // Instruction: 8: 10001100000sssssPP------101ddddd | Rd = cl0 (Rs) - hi->instruction = HEX_INS_RD___CL0__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cl0 (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc0000c0) { - // Instruction: 8: 10001100000sssssPP------110ddddd | Rd = cl1 (Rs) - hi->instruction = HEX_INS_RD___CL1__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cl1 (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc0000e0) { - // Instruction: 8: 10001100000sssssPP------111ddddd | Rd = normamt (Rs) - hi->instruction = HEX_INS_RD___NORMAMT__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = normamt (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8600060) { - // Instruction: 8: 10001000011sssssPP------011ddddd | Rd = popcount (Rss) - hi->instruction = HEX_INS_RD___POPCOUNT__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = popcount (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8e00040) { - // Instruction: 8: 10001000111sssssPP------010ddddd | Rd = ct0 (Rss) - hi->instruction = HEX_INS_RD___CT0__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ct0 (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8e00080) { - // Instruction: 8: 10001000111sssssPP------100ddddd | Rd = ct1 (Rss) - hi->instruction = HEX_INS_RD___CT1__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ct1 (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc400080) { - // Instruction: 8: 10001100010sssssPP------100ddddd | Rd = ct0 (Rs) - hi->instruction = HEX_INS_RD___CT0__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ct0 (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc4000a0) { - // Instruction: 8: 10001100010sssssPP------101ddddd | Rd = ct1 (Rs) - hi->instruction = HEX_INS_RD___CT1__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ct1 (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x1000000) { - // Instruction: 8: 10000001IIIsssssPPiiiiiiIIIddddd | Rdd = extractu (Rss, #u6, #U6) - hi->instruction = HEX_INS_RDD___EXTRACTU__RSS___U6___U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xe00000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = extractu (R%d:R%d, 0x%x, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0xa000000) { - // Instruction: 8: 10001010IIIsssssPPiiiiiiIIIddddd | Rdd = extract (Rss, #u6, #U6) - hi->instruction = HEX_INS_RDD___EXTRACT__RSS___U6___U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xe00000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = extract (R%d:R%d, 0x%x, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0xd000000) { - // Instruction: 8: 100011010IIsssssPP0iiiiiIIIddddd | Rd = extractu (Rs, #u5, #U5) - hi->instruction = HEX_INS_RD___EXTRACTU__RS___U5___U5_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = extractu (R%d, 0x%x, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0xd800000) { - // Instruction: 8: 100011011IIsssssPP0iiiiiIIIddddd | Rd = extract (Rs, #u5, #U5) - hi->instruction = HEX_INS_RD___EXTRACT__RS___U5___U5_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = extract (R%d, 0x%x, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x3000000) { - // Instruction: 8: 10000011IIIsssssPPiiiiiiIIIxxxxx | Rxx = insert (Rss, #u6, #U6) - hi->instruction = HEX_INS_RXX___INSERT__RSS___U6___U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xe00000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = insert (R%d:R%d, 0x%x, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0xf000000) { - // Instruction: 8: 100011110IIsssssPP0iiiiiIIIxxxxx | Rx = insert (Rs, #u5, #U5) - hi->instruction = HEX_INS_RX___INSERT__RS___U5___U5_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = insert (R%d, 0x%x, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc00080) { - // Instruction: 8: 10000000110sssssPP------100ddddd | Rdd = deinterleave (Rss) - hi->instruction = HEX_INS_RDD___DEINTERLEAVE__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = deinterleave (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc000a0) { - // Instruction: 8: 10000000110sssssPP------101ddddd | Rdd = interleave (Rss) - hi->instruction = HEX_INS_RDD___INTERLEAVE__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = interleave (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc000c0) { - // Instruction: 8: 10000000110sssssPP------110ddddd | Rdd = brev (Rss) - hi->instruction = HEX_INS_RDD___BREV__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = brev (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc4000c0) { - // Instruction: 8: 10001100010sssssPP------110ddddd | Rd = brev (Rs) - hi->instruction = HEX_INS_RD___BREV__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = brev (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xcc00000) { - // Instruction: 8: 10001100110sssssPP0iiiii000ddddd | Rd = setbit (Rs, #u5) - hi->instruction = HEX_INS_RD___SETBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = setbit (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xcc00020) { - // Instruction: 8: 10001100110sssssPP0iiiii001ddddd | Rd = clrbit (Rs, #u5) - hi->instruction = HEX_INS_RD___CLRBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = clrbit (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xcc00040) { - // Instruction: 8: 10001100110sssssPP0iiiii010ddddd | Rd = togglebit (Rs, #u5) - hi->instruction = HEX_INS_RD___TOGGLEBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = togglebit (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8c00080) { - // Instruction: 8: 10001000110sssssPP0iiiii100ddddd | Rdd = bitsplit (Rs, #u5) - hi->instruction = HEX_INS_RDD___BITSPLIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = bitsplit (R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7000000) { - // Instruction: 8: 1000011100isssssPPIIIIIIiiixxxxx | Rx = tableidxb (Rs, #u4, #S6) :raw - hi->instruction = HEX_INS_RX___TABLEIDXB__RS___U4___S6___RAW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3f00) >> 8); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = tableidxb (R%d, 0x%x, %d) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7400000) { - // Instruction: 8: 1000011101isssssPPIIIIIIiiixxxxx | Rx = tableidxh (Rs, #u4, #S6) :raw - hi->instruction = HEX_INS_RX___TABLEIDXH__RS___U4___S6___RAW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3f00) >> 8); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = tableidxh (R%d, 0x%x, %d) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7800000) { - // Instruction: 8: 1000011110isssssPPIIIIIIiiixxxxx | Rx = tableidxw (Rs, #u4, #S6) :raw - hi->instruction = HEX_INS_RX___TABLEIDXW__RS___U4___S6___RAW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3f00) >> 8); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = tableidxw (R%d, 0x%x, %d) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7c00000) { - // Instruction: 8: 1000011111isssssPPIIIIIIiiixxxxx | Rx = tableidxd (Rs, #u4, #S6) :raw - hi->instruction = HEX_INS_RX___TABLEIDXD__RS___U4___S6___RAW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x3f00) >> 8); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = tableidxd (R%d, 0x%x, %d) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000e0) { - // Instruction: 8: 10000000100sssssPP------111ddddd | Rdd = vconj (Rss) :sat - hi->instruction = HEX_INS_RDD___VCONJ__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vconj (R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5e00000) { - // Instruction: 8: 10000101111sssssPP0iiiii------dd | Pd = sfclass (Rs, #u5) - hi->instruction = HEX_INS_PD___SFCLASS__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = sfclass (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800000) { - // Instruction: 8: 100001001--sssssPP------000ddddd | Rdd = convert_sf2df (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_SF2DF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_sf2df (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000020) { - // Instruction: 8: 10001000000sssssPP------001ddddd | Rd = convert_df2sf (Rss) - hi->instruction = HEX_INS_RD___CONVERT_DF2SF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_df2sf (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe00040) { - // Instruction: 8: 10000000111sssssPP0-----010ddddd | Rdd = convert_ud2df (Rss) - hi->instruction = HEX_INS_RDD___CONVERT_UD2DF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_ud2df (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe00060) { - // Instruction: 8: 10000000111sssssPP0-----011ddddd | Rdd = convert_d2df (Rss) - hi->instruction = HEX_INS_RDD___CONVERT_D2DF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_d2df (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800020) { - // Instruction: 8: 100001001--sssssPP------001ddddd | Rdd = convert_uw2df (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_UW2DF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_uw2df (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800040) { - // Instruction: 8: 100001001--sssssPP------010ddddd | Rdd = convert_w2df (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_W2DF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_w2df (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8200020) { - // Instruction: 8: 10001000001sssssPP------001ddddd | Rd = convert_ud2sf (Rss) - hi->instruction = HEX_INS_RD___CONVERT_UD2SF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_ud2sf (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8400020) { - // Instruction: 8: 10001000010sssssPP------001ddddd | Rd = convert_d2sf (Rss) - hi->instruction = HEX_INS_RD___CONVERT_D2SF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_d2sf (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb200000) { - // Instruction: 8: 10001011001sssssPP------000ddddd | Rd = convert_uw2sf (Rs) - hi->instruction = HEX_INS_RD___CONVERT_UW2SF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_uw2sf (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb400000) { - // Instruction: 8: 10001011010sssssPP------000ddddd | Rd = convert_w2sf (Rs) - hi->instruction = HEX_INS_RD___CONVERT_W2SF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_w2sf (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe00000) { - // Instruction: 8: 10000000111sssssPP0-----000ddddd | Rdd = convert_df2d (Rss) - hi->instruction = HEX_INS_RDD___CONVERT_DF2D__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_df2d (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe00020) { - // Instruction: 8: 10000000111sssssPP0-----001ddddd | Rdd = convert_df2ud (Rss) - hi->instruction = HEX_INS_RDD___CONVERT_DF2UD__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_df2ud (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe000c0) { - // Instruction: 8: 10000000111sssssPP0-----110ddddd | Rdd = convert_df2d (Rss) :chop - hi->instruction = HEX_INS_RDD___CONVERT_DF2D__RSS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d:R%d = convert_df2d (R%d:R%d) :chop", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe000e0) { - // Instruction: 8: 10000000111sssssPP0-----111ddddd | Rdd = convert_df2ud (Rss) :chop - hi->instruction = HEX_INS_RDD___CONVERT_DF2UD__RSS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d:R%d = convert_df2ud (R%d:R%d) :chop", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800060) { - // Instruction: 8: 100001001--sssssPP------011ddddd | Rdd = convert_sf2ud (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_SF2UD__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_sf2ud (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800080) { - // Instruction: 8: 100001001--sssssPP------100ddddd | Rdd = convert_sf2d (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_SF2D__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_sf2d (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x48000a0) { - // Instruction: 8: 100001001--sssssPP------101ddddd | Rdd = convert_sf2ud (Rs) :ch - hi->instruction = HEX_INS_RDD___CONVERT_SF2UD__RS___CH; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_sf2ud (R%d) :ch", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x48000c0) { - // Instruction: 8: 100001001--sssssPP------110ddddd | Rdd = convert_sf2d (Rs) :chop - hi->instruction = HEX_INS_RDD___CONVERT_SF2D__RS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d:R%d = convert_sf2d (R%d) :chop", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8600020) { - // Instruction: 8: 10001000011sssssPP------001ddddd | Rd = convert_df2uw (Rss) - hi->instruction = HEX_INS_RD___CONVERT_DF2UW__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_df2uw (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8800020) { - // Instruction: 8: 10001000100sssssPP------001ddddd | Rd = convert_df2w (Rss) - hi->instruction = HEX_INS_RD___CONVERT_DF2W__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_df2w (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8a00020) { - // Instruction: 8: 10001000101sssssPP------001ddddd | Rd = convert_df2uw (Rss) :chop - hi->instruction = HEX_INS_RD___CONVERT_DF2UW__RSS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d = convert_df2uw (R%d:R%d) :chop", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8e00020) { - // Instruction: 8: 10001000111sssssPP------001ddddd | Rd = convert_df2w (Rss) :chop - hi->instruction = HEX_INS_RD___CONVERT_DF2W__RSS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d = convert_df2w (R%d:R%d) :chop", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb600000) { - // Instruction: 8: 10001011011sssssPP------000ddddd | Rd = convert_sf2uw (Rs) - hi->instruction = HEX_INS_RD___CONVERT_SF2UW__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_sf2uw (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb600020) { - // Instruction: 8: 10001011011sssssPP------001ddddd | Rd = convert_sf2uw (Rs) :chop - hi->instruction = HEX_INS_RD___CONVERT_SF2UW__RS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d = convert_sf2uw (R%d) :chop", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb800000) { - // Instruction: 8: 10001011100sssssPP------000ddddd | Rd = convert_sf2w (Rs) - hi->instruction = HEX_INS_RD___CONVERT_SF2W__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_sf2w (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb800020) { - // Instruction: 8: 10001011100sssssPP------001ddddd | Rd = convert_sf2w (Rs) :chop - hi->instruction = HEX_INS_RD___CONVERT_SF2W__RS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d = convert_sf2w (R%d) :chop", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xba00000) { - // Instruction: 8: 10001011101sssssPP------000ddddd | Rd = sffixupr (Rs) - hi->instruction = HEX_INS_RD___SFFIXUPR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sffixupr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xbe00000) { - // Instruction: 8: 10001011111sssssPP------0eeddddd | Rd, Pe = sfinvsqrta (Rs) - hi->instruction = HEX_INS_RD__PE___SFINVSQRTA__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d, P%d = sfinvsqrta (R%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8c00000) { - // Instruction: 8: 10001000110sssssPP------000ddddd | Rd = sat (Rss) - hi->instruction = HEX_INS_RD___SAT__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sat (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xcc00080) { - // Instruction: 8: 10001100110sssssPP------100ddddd | Rd = sath (Rs) - hi->instruction = HEX_INS_RD___SATH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sath (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xcc000a0) { - // Instruction: 8: 10001100110sssssPP------101ddddd | Rd = satuh (Rs) - hi->instruction = HEX_INS_RD___SATUH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = satuh (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xcc000c0) { - // Instruction: 8: 10001100110sssssPP------110ddddd | Rd = satub (Rs) - hi->instruction = HEX_INS_RD___SATUB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = satub (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xcc000e0) { - // Instruction: 8: 10001100110sssssPP------111ddddd | Rd = satb (Rs) - hi->instruction = HEX_INS_RD___SATB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = satb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc8000e0) { - // Instruction: 8: 10001100100sssssPP------111ddddd | Rd = swiz (Rs) - hi->instruction = HEX_INS_RD___SWIZ__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = swiz (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8800080) { - // Instruction: 8: 10001000100sssssPP------100ddddd | Rd = vrndwh (Rss) - hi->instruction = HEX_INS_RD___VRNDWH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vrndwh (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x88000c0) { - // Instruction: 8: 10001000100sssssPP------110ddddd | Rd = vrndwh (Rss) :sat - hi->instruction = HEX_INS_RD___VRNDWH__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vrndwh (R%d:R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000000) { - // Instruction: 8: 10001000000sssssPP------000ddddd | Rd = vsathub (Rss) - hi->instruction = HEX_INS_RD___VSATHUB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsathub (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000040) { - // Instruction: 8: 10001000000sssssPP------010ddddd | Rd = vsatwh (Rss) - hi->instruction = HEX_INS_RD___VSATWH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsatwh (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000080) { - // Instruction: 8: 10001000000sssssPP------100ddddd | Rd = vsatwuh (Rss) - hi->instruction = HEX_INS_RD___VSATWUH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsatwuh (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x80000c0) { - // Instruction: 8: 10001000000sssssPP------110ddddd | Rd = vsathb (Rss) - hi->instruction = HEX_INS_RD___VSATHB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsathb (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800000) { - // Instruction: 8: 1000110010-sssssPP------00-ddddd | Rd = vsathb (Rs) - hi->instruction = HEX_INS_RD___VSATHB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsathb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800040) { - // Instruction: 8: 1000110010-sssssPP------01-ddddd | Rd = vsathub (Rs) - hi->instruction = HEX_INS_RD___VSATHUB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsathub (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x80) { - // Instruction: 8: 10000000000sssssPP------100ddddd | Rdd = vsathub (Rss) - hi->instruction = HEX_INS_RDD___VSATHUB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsathub (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xa0) { - // Instruction: 8: 10000000000sssssPP------101ddddd | Rdd = vsatwuh (Rss) - hi->instruction = HEX_INS_RDD___VSATWUH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsatwuh (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc0) { - // Instruction: 8: 10000000000sssssPP------110ddddd | Rdd = vsatwh (Rss) - hi->instruction = HEX_INS_RDD___VSATWH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsatwh (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xe0) { - // Instruction: 8: 10000000000sssssPP------111ddddd | Rdd = vsathb (Rss) - hi->instruction = HEX_INS_RDD___VSATHB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsathb (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4400080) { - // Instruction: 8: 1000010001-sssssPP------10-ddddd | Rdd = vsplatb (Rs) - hi->instruction = HEX_INS_RDD___VSPLATB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsplatb (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc4000e0) { - // Instruction: 8: 10001100010sssssPP------111ddddd | Rd = vsplatb (Rs) - hi->instruction = HEX_INS_RD___VSPLATB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsplatb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4400040) { - // Instruction: 8: 1000010001-sssssPP------01-ddddd | Rdd = vsplath (Rs) - hi->instruction = HEX_INS_RDD___VSPLATH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsplath (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4000000) { - // Instruction: 8: 1000010000-sssssPP------00-ddddd | Rdd = vsxtbh (Rs) - hi->instruction = HEX_INS_RDD___VSXTBH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsxtbh (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4000080) { - // Instruction: 8: 1000010000-sssssPP------10-ddddd | Rdd = vsxthw (Rs) - hi->instruction = HEX_INS_RDD___VSXTHW__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsxthw (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8800000) { - // Instruction: 8: 10001000100sssssPP------000ddddd | Rd = vtrunohb (Rss) - hi->instruction = HEX_INS_RD___VTRUNOHB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vtrunohb (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8800040) { - // Instruction: 8: 10001000100sssssPP------010ddddd | Rd = vtrunehb (Rss) - hi->instruction = HEX_INS_RD___VTRUNEHB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vtrunehb (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4000040) { - // Instruction: 8: 1000010000-sssssPP------01-ddddd | Rdd = vzxtbh (Rs) - hi->instruction = HEX_INS_RDD___VZXTBH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vzxtbh (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x40000c0) { - // Instruction: 8: 1000010000-sssssPP------11-ddddd | Rdd = vzxthw (Rs) - hi->instruction = HEX_INS_RDD___VZXTHW__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vzxthw (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5800000) { - // Instruction: 8: 10000101100sssssPPiiiiii------dd | Pd = bitsclr (Rs, #u6) - hi->instruction = HEX_INS_PD___BITSCLR__RS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = bitsclr (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5a00000) { - // Instruction: 8: 10000101101sssssPPiiiiii------dd | Pd = !bitsclr (Rs, #u6) - hi->instruction = HEX_INS_PD____NOT_BITSCLR__RS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !bitsclr (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x6000000) { - // Instruction: 8: 10000110--------PP----tt---ddddd | Rdd = mask (Pt) - hi->instruction = HEX_INS_RDD___MASK__PT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mask (P%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5400000) { - // Instruction: 8: 10000101010sssssPP------------dd | Pd = Rs - hi->instruction = HEX_INS_PD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf400000) == 0x9400000) { - // Instruction: 8: 10001001-1----ssPP---------ddddd | Rd = Ps - hi->instruction = HEX_INS_RD___PS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = P%d", hi->ops[0].op.reg, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5000000) { - // Instruction: 8: 10000101000sssssPP0iiiii------dd | Pd = tstbit (Rs, #u5) - hi->instruction = HEX_INS_PD___TSTBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = tstbit (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5200000) { - // Instruction: 8: 10000101001sssssPP0iiiii------dd | Pd = !tstbit (Rs, #u5) - hi->instruction = HEX_INS_PD____NOT_TSTBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !tstbit (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf600000) == 0x9000000) { - // Instruction: 8: 10001001-00---ssPP----tt---ddddd | Rd = vitpack (Ps, Pt) - hi->instruction = HEX_INS_RD___VITPACK__PS__PT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vitpack (P%d, P%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x0) { - // Instruction: 8: 10000000000sssssPPiiiiii000ddddd | Rdd = asr (Rss, #u6) - hi->instruction = HEX_INS_RDD___ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x20) { - // Instruction: 8: 10000000000sssssPPiiiiii001ddddd | Rdd = lsr (Rss, #u6) - hi->instruction = HEX_INS_RDD___LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x40) { - // Instruction: 8: 10000000000sssssPPiiiiii010ddddd | Rdd = asl (Rss, #u6) - hi->instruction = HEX_INS_RDD___ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x60) { - // Instruction: 8: 10000000000sssssPPiiiiii011ddddd | Rdd = rol (Rss, #u6) - hi->instruction = HEX_INS_RDD___ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc000000) { - // Instruction: 8: 10001100000sssssPP0iiiii000ddddd | Rd = asr (Rs, #u5) - hi->instruction = HEX_INS_RD___ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc000020) { - // Instruction: 8: 10001100000sssssPP0iiiii001ddddd | Rd = lsr (Rs, #u5) - hi->instruction = HEX_INS_RD___LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc000040) { - // Instruction: 8: 10001100000sssssPP0iiiii010ddddd | Rd = asl (Rs, #u5) - hi->instruction = HEX_INS_RD___ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc000060) { - // Instruction: 8: 10001100000sssssPP0iiiii011ddddd | Rd = rol (Rs, #u5) - hi->instruction = HEX_INS_RD___ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000000) { - // Instruction: 8: 1000001000-sssssPPiiiiii000xxxxx | Rxx -= asr (Rss, #u6) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000020) { - // Instruction: 8: 1000001000-sssssPPiiiiii001xxxxx | Rxx -= lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX__MINUS_EQ__LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000040) { - // Instruction: 8: 1000001000-sssssPPiiiiii010xxxxx | Rxx -= asl (Rss, #u6) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000060) { - // Instruction: 8: 1000001000-sssssPPiiiiii011xxxxx | Rxx -= rol (Rss, #u6) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000080) { - // Instruction: 8: 1000001000-sssssPPiiiiii100xxxxx | Rxx += asr (Rss, #u6) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x20000a0) { - // Instruction: 8: 1000001000-sssssPPiiiiii101xxxxx | Rxx += lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX__PLUS_EQ__LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x20000c0) { - // Instruction: 8: 1000001000-sssssPPiiiiii110xxxxx | Rxx += asl (Rss, #u6) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x20000e0) { - // Instruction: 8: 1000001000-sssssPPiiiiii111xxxxx | Rxx += rol (Rss, #u6) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000000) { - // Instruction: 8: 1000111000-sssssPP0iiiii000xxxxx | Rx -= asr (Rs, #u5) - hi->instruction = HEX_INS_RX__MINUS_EQ__ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000020) { - // Instruction: 8: 1000111000-sssssPP0iiiii001xxxxx | Rx -= lsr (Rs, #u5) - hi->instruction = HEX_INS_RX__MINUS_EQ__LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000040) { - // Instruction: 8: 1000111000-sssssPP0iiiii010xxxxx | Rx -= asl (Rs, #u5) - hi->instruction = HEX_INS_RX__MINUS_EQ__ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000060) { - // Instruction: 8: 1000111000-sssssPP0iiiii011xxxxx | Rx -= rol (Rs, #u5) - hi->instruction = HEX_INS_RX__MINUS_EQ__ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000080) { - // Instruction: 8: 1000111000-sssssPP0iiiii100xxxxx | Rx += asr (Rs, #u5) - hi->instruction = HEX_INS_RX__PLUS_EQ__ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe0000a0) { - // Instruction: 8: 1000111000-sssssPP0iiiii101xxxxx | Rx += lsr (Rs, #u5) - hi->instruction = HEX_INS_RX__PLUS_EQ__LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe0000c0) { - // Instruction: 8: 1000111000-sssssPP0iiiii110xxxxx | Rx += asl (Rs, #u5) - hi->instruction = HEX_INS_RX__PLUS_EQ__ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe0000e0) { - // Instruction: 8: 1000111000-sssssPP0iiiii111xxxxx | Rx += rol (Rs, #u5) - hi->instruction = HEX_INS_RX__PLUS_EQ__ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400000) { - // Instruction: 8: 1000001001-sssssPPiiiiii000xxxxx | Rxx &= asr (Rss, #u6) - hi->instruction = HEX_INS_RXX__AND_EQ__ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400020) { - // Instruction: 8: 1000001001-sssssPPiiiiii001xxxxx | Rxx &= lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX__AND_EQ__LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400040) { - // Instruction: 8: 1000001001-sssssPPiiiiii010xxxxx | Rxx &= asl (Rss, #u6) - hi->instruction = HEX_INS_RXX__AND_EQ__ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400060) { - // Instruction: 8: 1000001001-sssssPPiiiiii011xxxxx | Rxx &= rol (Rss, #u6) - hi->instruction = HEX_INS_RXX__AND_EQ__ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400080) { - // Instruction: 8: 1000001001-sssssPPiiiiii100xxxxx | Rxx |= asr (Rss, #u6) - hi->instruction = HEX_INS_RXX__OR_EQ__ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x24000a0) { - // Instruction: 8: 1000001001-sssssPPiiiiii101xxxxx | Rxx |= lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX__OR_EQ__LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x24000c0) { - // Instruction: 8: 1000001001-sssssPPiiiiii110xxxxx | Rxx |= asl (Rss, #u6) - hi->instruction = HEX_INS_RXX__OR_EQ__ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x24000e0) { - // Instruction: 8: 1000001001-sssssPPiiiiii111xxxxx | Rxx |= rol (Rss, #u6) - hi->instruction = HEX_INS_RXX__OR_EQ__ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2800020) { - // Instruction: 8: 1000001010-sssssPPiiiiii001xxxxx | Rxx ^= lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX____LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2800040) { - // Instruction: 8: 1000001010-sssssPPiiiiii010xxxxx | Rxx ^= asl (Rss, #u6) - hi->instruction = HEX_INS_RXX____ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2800060) { - // Instruction: 8: 1000001010-sssssPPiiiiii011xxxxx | Rxx ^= rol (Rss, #u6) - hi->instruction = HEX_INS_RXX____ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400000) { - // Instruction: 8: 1000111001-sssssPP0iiiii000xxxxx | Rx &= asr (Rs, #u5) - hi->instruction = HEX_INS_RX__AND_EQ__ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400020) { - // Instruction: 8: 1000111001-sssssPP0iiiii001xxxxx | Rx &= lsr (Rs, #u5) - hi->instruction = HEX_INS_RX__AND_EQ__LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400040) { - // Instruction: 8: 1000111001-sssssPP0iiiii010xxxxx | Rx &= asl (Rs, #u5) - hi->instruction = HEX_INS_RX__AND_EQ__ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400060) { - // Instruction: 8: 1000111001-sssssPP0iiiii011xxxxx | Rx &= rol (Rs, #u5) - hi->instruction = HEX_INS_RX__AND_EQ__ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400080) { - // Instruction: 8: 1000111001-sssssPP0iiiii100xxxxx | Rx |= asr (Rs, #u5) - hi->instruction = HEX_INS_RX__OR_EQ__ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe4000a0) { - // Instruction: 8: 1000111001-sssssPP0iiiii101xxxxx | Rx |= lsr (Rs, #u5) - hi->instruction = HEX_INS_RX__OR_EQ__LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe4000c0) { - // Instruction: 8: 1000111001-sssssPP0iiiii110xxxxx | Rx |= asl (Rs, #u5) - hi->instruction = HEX_INS_RX__OR_EQ__ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe4000e0) { - // Instruction: 8: 1000111001-sssssPP0iiiii111xxxxx | Rx |= rol (Rs, #u5) - hi->instruction = HEX_INS_RX__OR_EQ__ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe800020) { - // Instruction: 8: 1000111010-sssssPP0iiiii001xxxxx | Rx ^= lsr (Rs, #u5) - hi->instruction = HEX_INS_RX____LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe800040) { - // Instruction: 8: 1000111010-sssssPP0iiiii010xxxxx | Rx ^= asl (Rs, #u5) - hi->instruction = HEX_INS_RX____ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe800060) { - // Instruction: 8: 1000111010-sssssPP0iiiii011xxxxx | Rx ^= rol (Rs, #u5) - hi->instruction = HEX_INS_RX____ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc000e0) { - // Instruction: 8: 10000000110sssssPPiiiiii111ddddd | Rdd = asr (Rss, #u6) :rnd - hi->instruction = HEX_INS_RDD___ASR__RSS___U6___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = asr (R%d:R%d, 0x%x) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc400000) { - // Instruction: 8: 10001100010sssssPP0iiiii000ddddd | Rd = asr (Rs, #u5) :rnd - hi->instruction = HEX_INS_RD___ASR__RS___U5___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = asr (R%d, 0x%x) :rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc400040) { - // Instruction: 8: 10001100010sssssPP0iiiii010ddddd | Rd = asl (Rs, #u5) :sat - hi->instruction = HEX_INS_RD___ASL__RS___U5___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = asl (R%d, 0x%x) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x800000) { - // Instruction: 8: 10000000100sssssPP00iiii000ddddd | Rdd = vasrh (Rss, #u4) - hi->instruction = HEX_INS_RDD___VASRH__RSS___U4_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vasrh (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x800020) { - // Instruction: 8: 10000000100sssssPP00iiii001ddddd | Rdd = vlsrh (Rss, #u4) - hi->instruction = HEX_INS_RDD___VLSRH__RSS___U4_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlsrh (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x800040) { - // Instruction: 8: 10000000100sssssPP00iiii010ddddd | Rdd = vaslh (Rss, #u4) - hi->instruction = HEX_INS_RDD___VASLH__RSS___U4_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaslh (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x200000) { - // Instruction: 8: 10000000001sssssPP00iiii000ddddd | Rdd = vasrh (Rss, #u4) :raw - hi->instruction = HEX_INS_RDD___VASRH__RSS___U4___RAW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d:R%d = vasrh (R%d:R%d, 0x%x) :raw", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x8600080) { - // Instruction: 8: 10001000011sssssPP00iiii100ddddd | Rd = vasrhub (Rss, #u4) :raw - hi->instruction = HEX_INS_RD___VASRHUB__RSS___U4___RAW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = vasrhub (R%d:R%d, 0x%x) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x86000a0) { - // Instruction: 8: 10001000011sssssPP00iiii101ddddd | Rd = vasrhub (Rss, #u4) :sat - hi->instruction = HEX_INS_RD___VASRHUB__RSS___U4___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vasrhub (R%d:R%d, 0x%x) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x400000) { - // Instruction: 8: 10000000010sssssPP0iiiii000ddddd | Rdd = vasrw (Rss, #u5) - hi->instruction = HEX_INS_RDD___VASRW__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vasrw (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x400020) { - // Instruction: 8: 10000000010sssssPP0iiiii001ddddd | Rdd = vlsrw (Rss, #u5) - hi->instruction = HEX_INS_RDD___VLSRW__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlsrw (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x400040) { - // Instruction: 8: 10000000010sssssPP0iiiii010ddddd | Rdd = vaslw (Rss, #u5) - hi->instruction = HEX_INS_RDD___VASLW__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaslw (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8c00040) { - // Instruction: 8: 10001000110sssssPP0iiiii010ddddd | Rd = vasrw (Rss, #u5) - hi->instruction = HEX_INS_RD___VASRW__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vasrw (R%d:R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - break; - } - case 0x9: { - if ((hi_u32 & 0x9e00000) == 0x1c00000) { - // Instruction: 9: 10010ii1110sssssPPiiiiiiiiiddddd | Rdd = memd (Rs + #s11:3) - hi->instruction = HEX_INS_RDD___MEMD__RS____S11_3_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 13)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 13); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "R%d:R%d = memd (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9c00000) { - // Instruction: 9: 10011001110xxxxxPPu0--0iiiiddddd | Rdd = memd (Rx ++ #s4:3:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMD__RX_____S4_3_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9c00200) { - // Instruction: 9: 10011001110xxxxxPPu0--1-0--ddddd | Rdd = memd (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMD__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xbc01000) { - // Instruction: 9: 10011011110eeeeePP01IIII-IIddddd | Rdd = memd (Re = #U6) - hi->instruction = HEX_INS_RDD___MEMD__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d:R%d = memd (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xbc00000) { - // Instruction: 9: 10011011110xxxxxPP00---iiiiddddd | Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_RDD___MEMD__RX_____S4_3_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xdc01000) { - // Instruction: 9: 10011101110tttttPPi1IIIIiIIddddd | Rdd = memd (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RDD___MEMD__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d:R%d = memd (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xdc00000) { - // Instruction: 9: 10011101110xxxxxPPu0----0--ddddd | Rdd = memd (Rx ++ Mu) - hi->instruction = HEX_INS_RDD___MEMD__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xfc00000) { - // Instruction: 9: 10011111110xxxxxPPu0----0--ddddd | Rdd = memd (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RDD___MEMD__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xbc02000) { - // Instruction: 9: 10011011110xxxxxPP100ttiiiiddddd | if (Pt) Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_IF__PT__RDD___MEMD__RX_____S4_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xbc02800) { - // Instruction: 9: 10011011110xxxxxPP101ttiiiiddddd | if !Pt Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_IF__NOT_PT_RDD___MEMD__RX_____S4_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xbc03000) { - // Instruction: 9: 10011011110xxxxxPP110ttiiiiddddd | if (Pt.new) Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_IF__PT_NEW__RDD___MEMD__RX_____S4_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xbc03800) { - // Instruction: 9: 10011011110xxxxxPP111ttiiiiddddd | if !Pt.new Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RDD___MEMD__RX_____S4_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xfc02080) { - // Instruction: 9: 10011111110iiiiiPP100tti1--ddddd | if (Pt) Rdd = memd (#u6) - hi->instruction = HEX_INS_IF__PT__RDD___MEMD___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d:R%d = memd (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xfc02880) { - // Instruction: 9: 10011111110iiiiiPP101tti1--ddddd | if !Pt Rdd = memd (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RDD___MEMD___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d:R%d = memd (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xfc03080) { - // Instruction: 9: 10011111110iiiiiPP110tti1--ddddd | if (Pt.new) Rdd = memd (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RDD___MEMD___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = memd (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xfc03880) { - // Instruction: 9: 10011111110iiiiiPP111tti1--ddddd | if !Pt.new Rdd = memd (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RDD___MEMD___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d:R%d = memd (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1000000) { - // Instruction: 9: 10010ii1000sssssPPiiiiiiiiiddddd | Rd = memb (Rs + #s11:0) - hi->instruction = HEX_INS_RD___MEMB__RS____S11_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memb (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9000000) { - // Instruction: 9: 10011001000xxxxxPPu0--0iiiiddddd | Rd = memb (Rx ++ #s4:0:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMB__RX_____S4_0_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9000200) { - // Instruction: 9: 10011001000xxxxxPPu0--1-0--ddddd | Rd = memb (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMB__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb001000) { - // Instruction: 9: 10011011000eeeeePP01IIII-IIddddd | Rd = memb (Re = #U6) - hi->instruction = HEX_INS_RD___MEMB__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memb (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb000000) { - // Instruction: 9: 10011011000xxxxxPP00---iiiiddddd | Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_RD___MEMB__RX_____S4_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd001000) { - // Instruction: 9: 10011101000tttttPPi1IIIIiIIddddd | Rd = memb (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMB__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memb (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd000000) { - // Instruction: 9: 10011101000xxxxxPPu0----0--ddddd | Rd = memb (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMB__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf000000) { - // Instruction: 9: 10011111000xxxxxPPu0----0--ddddd | Rd = memb (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMB__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb002000) { - // Instruction: 9: 10011011000xxxxxPP100ttiiiiddddd | if (Pt) Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__PT__RD___MEMB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d = memb (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb002800) { - // Instruction: 9: 10011011000xxxxxPP101ttiiiiddddd | if !Pt Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memb (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb003000) { - // Instruction: 9: 10011011000xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memb (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb003800) { - // Instruction: 9: 10011011000xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memb (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf002080) { - // Instruction: 9: 10011111000iiiiiPP100tti1--ddddd | if (Pt) Rd = memb (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memb (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf002880) { - // Instruction: 9: 10011111000iiiiiPP101tti1--ddddd | if !Pt Rd = memb (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memb (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf003080) { - // Instruction: 9: 10011111000iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memb (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memb (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf003880) { - // Instruction: 9: 10011111000iiiiiPP111tti1--ddddd | if !Pt.new Rd = memb (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memb (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x800000) { - // Instruction: 9: 10010ii0100sssssPPiiiiiiiiiyyyyy | Ryy = memb_fifo (Rs + #s11:0) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RS____S11_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8800000) { - // Instruction: 9: 10011000100xxxxxPPu0--0iiiiyyyyy | Ryy = memb_fifo (Rx ++ #s4:0:circ (Mu)) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX_____S4_0_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8800200) { - // Instruction: 9: 10011000100xxxxxPPu0--1-0--yyyyy | Ryy = memb_fifo (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa801000) { - // Instruction: 9: 10011010100eeeeePP01IIII-IIyyyyy | Ryy = memb_fifo (Re = #U6) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa800000) { - // Instruction: 9: 10011010100xxxxxPP00---iiiiyyyyy | Ryy = memb_fifo (Rx ++ #s4:0) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX_____S4_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xc801000) { - // Instruction: 9: 10011100100tttttPPi1IIIIiIIyyyyy | Ryy = memb_fifo (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xc800000) { - // Instruction: 9: 10011100100xxxxxPPu0----0--yyyyy | Ryy = memb_fifo (Rx ++ Mu) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xe800000) { - // Instruction: 9: 10011110100xxxxxPPu0----0--yyyyy | Ryy = memb_fifo (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x400000) { - // Instruction: 9: 10010ii0010sssssPPiiiiiiiiiyyyyy | Ryy = memh_fifo (Rs + #s11:1) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8400000) { - // Instruction: 9: 10011000010xxxxxPPu0--0iiiiyyyyy | Ryy = memh_fifo (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8400200) { - // Instruction: 9: 10011000010xxxxxPPu0--1-0--yyyyy | Ryy = memh_fifo (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa401000) { - // Instruction: 9: 10011010010eeeeePP01IIII-IIyyyyy | Ryy = memh_fifo (Re = #U6) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa400000) { - // Instruction: 9: 10011010010xxxxxPP00---iiiiyyyyy | Ryy = memh_fifo (Rx ++ #s4:1) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xc401000) { - // Instruction: 9: 10011100010tttttPPi1IIIIiIIyyyyy | Ryy = memh_fifo (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xc400000) { - // Instruction: 9: 10011100010xxxxxPPu0----0--yyyyy | Ryy = memh_fifo (Rx ++ Mu) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xe400000) { - // Instruction: 9: 10011110010xxxxxPPu0----0--yyyyy | Ryy = memh_fifo (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1400000) { - // Instruction: 9: 10010ii1010sssssPPiiiiiiiiiddddd | Rd = memh (Rs + #s11:1) - hi->instruction = HEX_INS_RD___MEMH__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "R%d = memh (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9400000) { - // Instruction: 9: 10011001010xxxxxPPu0--0iiiiddddd | Rd = memh (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMH__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9400200) { - // Instruction: 9: 10011001010xxxxxPPu0--1-0--ddddd | Rd = memh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb401000) { - // Instruction: 9: 10011011010eeeeePP01IIII-IIddddd | Rd = memh (Re = #U6) - hi->instruction = HEX_INS_RD___MEMH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memh (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb400000) { - // Instruction: 9: 10011011010xxxxxPP00---iiiiddddd | Rd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_RD___MEMH__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd401000) { - // Instruction: 9: 10011101010tttttPPi1IIIIiIIddddd | Rd = memh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd400000) { - // Instruction: 9: 10011101010xxxxxPPu0----0--ddddd | Rd = memh (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf400000) { - // Instruction: 9: 10011111010xxxxxPPu0----0--ddddd | Rd = memh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb402000) { - // Instruction: 9: 10011011010xxxxxPP100ttiiiiddddd | if (Pt) Pd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__PT__PD___MEMH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) P%d = memh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb402800) { - // Instruction: 9: 10011011010xxxxxPP101ttiiiiddddd | if !Pt Rd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb403000) { - // Instruction: 9: 10011011010xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb403800) { - // Instruction: 9: 10011011010xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf402080) { - // Instruction: 9: 10011111010iiiiiPP100tti1--ddddd | if (Pt) Rd = memh (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf402880) { - // Instruction: 9: 10011111010iiiiiPP101tti1--ddddd | if !Pt Rd = memh (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf403080) { - // Instruction: 9: 10011111010iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memh (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf403880) { - // Instruction: 9: 10011111010iiiiiPP111tti1--ddddd | if !Pt.new Rd = memh (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1200000) { - // Instruction: 9: 10010ii1001sssssPPiiiiiiiiiddddd | Rd = memub (Rs + #s11:0) - hi->instruction = HEX_INS_RD___MEMUB__RS____S11_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memub (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9200000) { - // Instruction: 9: 10011001001xxxxxPPu0--0iiiiddddd | Rd = memub (Rx ++ #s4:0:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUB__RX_____S4_0_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9200200) { - // Instruction: 9: 10011001001xxxxxPPu0--1-0--ddddd | Rd = memub (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUB__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb201000) { - // Instruction: 9: 10011011001eeeeePP01IIII-IIddddd | Rd = memub (Re = #U6) - hi->instruction = HEX_INS_RD___MEMUB__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memub (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb200000) { - // Instruction: 9: 10011011001xxxxxPP00---iiiiddddd | Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_RD___MEMUB__RX_____S4_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd201000) { - // Instruction: 9: 10011101001tttttPPi1IIIIiIIddddd | Rd = memub (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMUB__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memub (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd200000) { - // Instruction: 9: 10011101001xxxxxPPu0----0--ddddd | Rd = memub (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMUB__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf200000) { - // Instruction: 9: 10011111001xxxxxPPu0----0--ddddd | Rd = memub (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMUB__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb202000) { - // Instruction: 9: 10011011001xxxxxPP100ttiiiiddddd | if (Pt) Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__PT__RD___MEMUB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d = memub (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb202800) { - // Instruction: 9: 10011011001xxxxxPP101ttiiiiddddd | if !Pt Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memub (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb203000) { - // Instruction: 9: 10011011001xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memub (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb203800) { - // Instruction: 9: 10011011001xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memub (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf202080) { - // Instruction: 9: 10011111001iiiiiPP100tti1--ddddd | if (Pt) Rd = memub (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMUB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memub (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf202880) { - // Instruction: 9: 10011111001iiiiiPP101tti1--ddddd | if !Pt Rd = memub (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memub (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf203080) { - // Instruction: 9: 10011111001iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memub (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memub (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf203880) { - // Instruction: 9: 10011111001iiiiiPP111tti1--ddddd | if !Pt.new Rd = memub (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memub (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1600000) { - // Instruction: 9: 10010ii1011sssssPPiiiiiiiiiddddd | Rd = memuh (Rs + #s11:1) - hi->instruction = HEX_INS_RD___MEMUH__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "R%d = memuh (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9600000) { - // Instruction: 9: 10011001011xxxxxPPu0--0iiiiddddd | Rd = memuh (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUH__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9600200) { - // Instruction: 9: 10011001011xxxxxPPu0--1-0--ddddd | Rd = memuh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb601000) { - // Instruction: 9: 10011011011eeeeePP01IIII-IIddddd | Rd = memuh (Re = #U6) - hi->instruction = HEX_INS_RD___MEMUH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memuh (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb600000) { - // Instruction: 9: 10011011011xxxxxPP00---iiiiddddd | Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_RD___MEMUH__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd601000) { - // Instruction: 9: 10011101011tttttPPi1IIIIiIIddddd | Rd = memuh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMUH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memuh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd600000) { - // Instruction: 9: 10011101011xxxxxPPu0----0--ddddd | Rd = memuh (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMUH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf600000) { - // Instruction: 9: 10011111011xxxxxPPu0----0--ddddd | Rd = memuh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMUH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb602000) { - // Instruction: 9: 10011011011xxxxxPP100ttiiiiddddd | if (Pt) Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__PT__RD___MEMUH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d = memuh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb602800) { - // Instruction: 9: 10011011011xxxxxPP101ttiiiiddddd | if !Pt Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memuh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb603000) { - // Instruction: 9: 10011011011xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memuh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb603800) { - // Instruction: 9: 10011011011xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memuh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf602080) { - // Instruction: 9: 10011111011iiiiiPP100tti1--ddddd | if (Pt) Rd = memuh (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMUH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memuh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf602880) { - // Instruction: 9: 10011111011iiiiiPP101tti1--ddddd | if !Pt Rd = memuh (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memuh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf603080) { - // Instruction: 9: 10011111011iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memuh (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memuh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf603880) { - // Instruction: 9: 10011111011iiiiiPP111tti1--ddddd | if !Pt.new Rd = memuh (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memuh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1800000) { - // Instruction: 9: 10010ii1100sssssPPiiiiiiiiiddddd | Rd = memw (Rs + #s11:2) - hi->instruction = HEX_INS_RD___MEMW__RS____S11_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 12)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 12); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "R%d = memw (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9800000) { - // Instruction: 9: 10011001100xxxxxPPu0--0iiiiddddd | Rd = memw (Rx ++ #s4:2:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMW__RX_____S4_2_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9800200) { - // Instruction: 9: 10011001100xxxxxPPu0--1-0--ddddd | Rd = memw (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMW__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb801000) { - // Instruction: 9: 10011011100eeeeePP01IIII-IIddddd | Rd = memw (Re = #U6) - hi->instruction = HEX_INS_RD___MEMW__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memw (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb800000) { - // Instruction: 9: 10011011100xxxxxPP00---iiiiddddd | Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_RD___MEMW__RX_____S4_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd801000) { - // Instruction: 9: 10011101100tttttPPi1IIIIiIIddddd | Rd = memw (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMW__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memw (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd800000) { - // Instruction: 9: 10011101100xxxxxPPu0----0--ddddd | Rd = memw (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMW__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf800000) { - // Instruction: 9: 10011111100xxxxxPPu0----0--ddddd | Rd = memw (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMW__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb802000) { - // Instruction: 9: 10011011100xxxxxPP100ttiiiiddddd | if (Pt) Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_IF__PT__RD___MEMW__RX_____S4_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d = memw (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb802800) { - // Instruction: 9: 10011011100xxxxxPP101ttiiiiddddd | if !Pt Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMW__RX_____S4_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memw (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb803000) { - // Instruction: 9: 10011011100xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMW__RX_____S4_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memw (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb803800) { - // Instruction: 9: 10011011100xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMW__RX_____S4_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memw (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf802080) { - // Instruction: 9: 10011111100iiiiiPP100tti1--ddddd | if (Pt) Rd = memw (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMW___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memw (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf802880) { - // Instruction: 9: 10011111100iiiiiPP101tti1--ddddd | if !Pt Rd = memw (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMW___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memw (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf803080) { - // Instruction: 9: 10011111100iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memw (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMW___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memw (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf803880) { - // Instruction: 9: 10011111100iiiiiPP111tti1--ddddd | if !Pt.new Rd = memw (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMW___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memw (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfff201f) == 0x1e001e) { - // Instruction: 9: 1001000000011110PP0--------11110 | deallocframe - hi->instruction = HEX_INS_DEALLOCFRAME; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe"); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e001e) { - // Instruction: 9: 1001011000011110PP0000-----11110 | dealloc_return - hi->instruction = HEX_INS_DEALLOC_RETURN; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dealloc_return"); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e081e) { - // Instruction: 9: 1001011000011110PP0010ss---11110 | if (Ps.new) dealloc_return:nt - hi->instruction = HEX_INS_IF__PS_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (P%d.new) dealloc_return:nt", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e101e) { - // Instruction: 9: 1001011000011110PP0100ss---11110 | if (Ps) dealloc_return - hi->instruction = HEX_INS_IF__PS__DEALLOC_RETURN; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (P%d) dealloc_return", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e181e) { - // Instruction: 9: 1001011000011110PP0110ss---11110 | if (Ps.new) dealloc_return:t - hi->instruction = HEX_INS_IF__PS_NEW__DEALLOC_RETURN_T; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (P%d.new) dealloc_return:t", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e281e) { - // Instruction: 9: 1001011000011110PP1010ss---11110 | if !Ps.new dealloc_return:nt - hi->instruction = HEX_INS_IF__NOT_PS_NEW_DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if !P%d.new dealloc_return:nt", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e301e) { - // Instruction: 9: 1001011000011110PP1100ss---11110 | if !Ps dealloc_return - hi->instruction = HEX_INS_IF__NOT_PS_DEALLOC_RETURN; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if !P%d dealloc_return", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e381e) { - // Instruction: 9: 1001011000011110PP1110ss---11110 | if !Ps.new dealloc_return:t - hi->instruction = HEX_INS_IF__NOT_PS_NEW_DEALLOC_RETURN_T; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if !P%d.new dealloc_return:t", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0x9e00000) == 0x200000) { - // Instruction: 9: 10010ii0001sssssPPiiiiiiiiiddddd | Rd = membh (Rs + #s11:1) - hi->instruction = HEX_INS_RD___MEMBH__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x600000) { - // Instruction: 9: 10010ii0011sssssPPiiiiiiiiiddddd | Rd = memubh (Rs + #s11:1) - hi->instruction = HEX_INS_RD___MEMUBH__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0xa00000) { - // Instruction: 9: 10010ii0101sssssPPiiiiiiiiiddddd | Rdd = memubh (Rs + #s11:2) - hi->instruction = HEX_INS_RDD___MEMUBH__RS____S11_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 12)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 12); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0xe00000) { - // Instruction: 9: 10010ii0111sssssPPiiiiiiiiiddddd | Rdd = membh (Rs + #s11:2) - hi->instruction = HEX_INS_RDD___MEMBH__RS____S11_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 12)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 12); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8200000) { - // Instruction: 9: 10011000001xxxxxPPu0--0iiiiddddd | Rd = membh (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMBH__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8200200) { - // Instruction: 9: 10011000001xxxxxPPu0--1-0--ddddd | Rd = membh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMBH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8600000) { - // Instruction: 9: 10011000011xxxxxPPu0--0iiiiddddd | Rd = memubh (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUBH__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8600200) { - // Instruction: 9: 10011000011xxxxxPPu0--1-0--ddddd | Rd = memubh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUBH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8a00000) { - // Instruction: 9: 10011000101xxxxxPPu0--0iiiiddddd | Rdd = memubh (Rx ++ #s4:2:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMUBH__RX_____S4_2_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8a00200) { - // Instruction: 9: 10011000101xxxxxPPu0--1-0--ddddd | Rdd = memubh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMUBH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8e00000) { - // Instruction: 9: 10011000111xxxxxPPu0--0iiiiddddd | Rdd = membh (Rx ++ #s4:2:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMBH__RX_____S4_2_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8e00200) { - // Instruction: 9: 10011000111xxxxxPPu0--1-0--ddddd | Rdd = membh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMBH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa201000) { - // Instruction: 9: 10011010001eeeeePP01IIII-IIddddd | Rd = membh (Re = #U6) - hi->instruction = HEX_INS_RD___MEMBH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa200000) { - // Instruction: 9: 10011010001xxxxxPP00---iiiiddddd | Rd = membh (Rx ++ #s4:1) - hi->instruction = HEX_INS_RD___MEMBH__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa601000) { - // Instruction: 9: 10011010011eeeeePP01IIII-IIddddd | Rd = memubh (Re = #U6) - hi->instruction = HEX_INS_RD___MEMUBH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa600000) { - // Instruction: 9: 10011010011xxxxxPP00---iiiiddddd | Rd = memubh (Rx ++ #s4:1) - hi->instruction = HEX_INS_RD___MEMUBH__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xaa01000) { - // Instruction: 9: 10011010101eeeeePP01IIII-IIddddd | Rdd = memubh (Re = #U6) - hi->instruction = HEX_INS_RDD___MEMUBH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xaa00000) { - // Instruction: 9: 10011010101xxxxxPP00---iiiiddddd | Rdd = memubh (Rx ++ #s4:2) - hi->instruction = HEX_INS_RDD___MEMUBH__RX_____S4_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xae01000) { - // Instruction: 9: 10011010111eeeeePP01IIII-IIddddd | Rdd = membh (Re = #U6) - hi->instruction = HEX_INS_RDD___MEMBH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xae00000) { - // Instruction: 9: 10011010111xxxxxPP00---iiiiddddd | Rdd = membh (Rx ++ #s4:2) - hi->instruction = HEX_INS_RDD___MEMBH__RX_____S4_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xc201000) { - // Instruction: 9: 10011100001tttttPPi1IIIIiIIddddd | Rd = membh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMBH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xc200000) { - // Instruction: 9: 10011100001xxxxxPPu0----0--ddddd | Rd = membh (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMBH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01000) == 0xc601000) { - // Instruction: 9: 10011100011tttttPPi1IIIIiIIddddd | Rd = memubh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMUBH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xc600000) { - // Instruction: 9: 10011100011xxxxxPPu0----0--ddddd | Rd = memubh (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMUBH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01000) == 0xca01000) { - // Instruction: 9: 10011100101tttttPPi1IIIIiIIddddd | Rdd = memubh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RDD___MEMUBH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xca00000) { - // Instruction: 9: 10011100101xxxxxPPu0----0--ddddd | Rdd = memubh (Rx ++ Mu) - hi->instruction = HEX_INS_RDD___MEMUBH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01000) == 0xce01000) { - // Instruction: 9: 10011100111tttttPPi1IIIIiIIddddd | Rdd = membh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RDD___MEMBH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xce00000) { - // Instruction: 9: 10011100111xxxxxPPu0----0--ddddd | Rdd = membh (Rx ++ Mu) - hi->instruction = HEX_INS_RDD___MEMBH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xe200000) { - // Instruction: 9: 10011110001xxxxxPPu0----0--ddddd | Rd = membh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMBH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xe600000) { - // Instruction: 9: 10011110011xxxxxPPu0----0--ddddd | Rd = memubh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMUBH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xea00000) { - // Instruction: 9: 10011110101xxxxxPPu0----0--ddddd | Rdd = memubh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RDD___MEMUBH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xee00000) { - // Instruction: 9: 10011110111xxxxxPPu0----0--ddddd | Rdd = membh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RDD___MEMBH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02020) == 0x2002000) { - // Instruction: 9: 10010010000sssssPP1ttttt--0ddddd | Rd = memw_phys (Rs, Rt) - hi->instruction = HEX_INS_RD___MEMW_PHYS__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw_phys (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03020) == 0x2000000) { - // Instruction: 9: 10010010000sssssPP00------0ddddd | Rd = memw_locked (Rs) - hi->instruction = HEX_INS_RD___MEMW_LOCKED__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw_locked (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe03020) == 0x2001000) { - // Instruction: 9: 10010010000sssssPP01------0ddddd | Rdd = memd_locked (Rs) - hi->instruction = HEX_INS_RDD___MEMD_LOCKED__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd_locked (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x4000000) { - // Instruction: 9: 10010100000sssssPP0--iiiiiiiiiii | dcfetch (Rs + #u11:3) - hi->instruction = HEX_INS_DCFETCH__RS____U11_3_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x7ff) >> 0) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dcfetch (R%d + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - break; - } - case 0xa: { - if ((hi_u32 & 0x9e01800) == 0x1a00000) { - // Instruction: 10: 10100ii1101sssssPPi00tttiiiiiiii | memb (Rs + #s11:0) = Nt.new - hi->instruction = HEX_INS_MEMB__RS____S11_0____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)); - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d + %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a00002) { - // Instruction: 10: 10101001101xxxxxPPu00ttt0-----1- | memb (Rx ++ I:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMB__RX____I_CIRC__MU_____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a00000) { - // Instruction: 10: 10101001101xxxxxPPu00ttt0iiii-0- | memb (Rx ++ #s4:0:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMB__RX_____S4_0_CIRC__MU_____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[1].op.imm & (1 << 3)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03880) == 0xba00080) { - // Instruction: 10: 10101011101eeeeePP000ttt1-IIIIII | memb (Re = #U6) = Nt.new - hi->instruction = HEX_INS_MEMB__RE____U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03882) == 0xba00000) { - // Instruction: 10: 10101011101xxxxxPP000ttt0iiii-0- | memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[1].op.imm & (1 << 3)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda00080) { - // Instruction: 10: 10101101101uuuuuPPi00ttt1iIIIIII | memb (Ru << #u2 + #U6) = Nt.new - hi->instruction = HEX_INS_MEMB__RU_____U2____U6____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda00000) { - // Instruction: 10: 10101101101xxxxxPPu00ttt0------- | memb (Rx ++ Mu) = Nt.new - hi->instruction = HEX_INS_MEMB__RX____MU____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xfa00000) { - // Instruction: 10: 10101111101xxxxxPPu00ttt0------- | memb (Rx ++ Mu:brev) = Nt.new - hi->instruction = HEX_INS_MEMB__RX____MU_BREV____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02000) { - // Instruction: 10: 10101011101xxxxxPP100ttt0iiii0vv | if (Pv) memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02004) { - // Instruction: 10: 10101011101xxxxxPP100ttt0iiii1vv | if !Pv memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02080) { - // Instruction: 10: 10101011101xxxxxPP100ttt1iiii0vv | if (Pv.new) memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02084) { - // Instruction: 10: 10101011101xxxxxPP100ttt1iiii1vv | if !Pv.new memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa00080) { - // Instruction: 10: 10101111101---iiPP000ttt1iiii0vv | if (Pv) memb (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMB___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa00084) { - // Instruction: 10: 10101111101---iiPP000ttt1iiii1vv | if !Pv memb (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMB___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa02080) { - // Instruction: 10: 10101111101---iiPP100ttt1iiii0vv | if (Pv.new) memb (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMB___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa02084) { - // Instruction: 10: 10101111101---iiPP100ttt1iiii1vv | if !Pv.new memb (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e01800) == 0x1a00800) { - // Instruction: 10: 10100ii1101sssssPPi01tttiiiiiiii | memh (Rs + #s11:1) = Nt.new - hi->instruction = HEX_INS_MEMH__RS____S11_1____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 11)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 11); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 1); - sprintf(hi->mnem, "memh (R%d + %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a00802) { - // Instruction: 10: 10101001101xxxxxPPu01ttt0-----1- | memh (Rx ++ I:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMH__RX____I_CIRC__MU_____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a00800) { - // Instruction: 10: 10101001101xxxxxPPu01ttt0iiii-0- | memh (Rx ++ #s4:1:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMH__RX_____S4_1_CIRC__MU_____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03880) == 0xba00880) { - // Instruction: 10: 10101011101eeeeePP001ttt1-IIIIII | memh (Re = #U6) = Nt.new - hi->instruction = HEX_INS_MEMH__RE____U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03882) == 0xba00800) { - // Instruction: 10: 10101011101xxxxxPP001ttt0iiii-0- | memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda00880) { - // Instruction: 10: 10101101101uuuuuPPi01ttt1iIIIIII | memh (Ru << #u2 + #U6) = Nt.new - hi->instruction = HEX_INS_MEMH__RU_____U2____U6____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memh (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda00800) { - // Instruction: 10: 10101101101xxxxxPPu01ttt0------- | memh (Rx ++ Mu) = Nt.new - hi->instruction = HEX_INS_MEMH__RX____MU____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xfa00800) { - // Instruction: 10: 10101111101xxxxxPPu01ttt0------- | memh (Rx ++ Mu:brev) = Nt.new - hi->instruction = HEX_INS_MEMH__RX____MU_BREV____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02800) { - // Instruction: 10: 10101011101xxxxxPP101ttt0iiii0vv | if (Pv) memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02804) { - // Instruction: 10: 10101011101xxxxxPP101ttt0iiii1vv | if !Pv memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02880) { - // Instruction: 10: 10101011101xxxxxPP101ttt1iiii0vv | if (Pv.new) memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02884) { - // Instruction: 10: 10101011101xxxxxPP101ttt1iiii1vv | if !Pv.new memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa00880) { - // Instruction: 10: 10101111101---iiPP001ttt1iiii0vv | if (Pv) memh (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMH___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa00884) { - // Instruction: 10: 10101111101---iiPP001ttt1iiii1vv | if !Pv memh (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMH___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa02880) { - // Instruction: 10: 10101111101---iiPP101ttt1iiii0vv | if (Pv.new) memh (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMH___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa02884) { - // Instruction: 10: 10101111101---iiPP101ttt1iiii1vv | if !Pv.new memh (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e01800) == 0x1a01000) { - // Instruction: 10: 10100ii1101sssssPPi10tttiiiiiiii | memw (Rs + #s11:2) = Nt.new - hi->instruction = HEX_INS_MEMW__RS____S11_2____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 12)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 12); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "memw (R%d + %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a01002) { - // Instruction: 10: 10101001101xxxxxPPu10ttt0-----1- | memw (Rx ++ I:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMW__RX____I_CIRC__MU_____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a01000) { - // Instruction: 10: 10101001101xxxxxPPu10ttt0iiii-0- | memw (Rx ++ #s4:2:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMW__RX_____S4_2_CIRC__MU_____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03880) == 0xba01080) { - // Instruction: 10: 10101011101eeeeePP010ttt1-IIIIII | memw (Re = #U6) = Nt.new - hi->instruction = HEX_INS_MEMW__RE____U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03882) == 0xba01000) { - // Instruction: 10: 10101011101xxxxxPP010ttt0iiii-0- | memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda01080) { - // Instruction: 10: 10101101101uuuuuPPi10ttt1iIIIIII | memw (Ru << #u2 + #U6) = Nt.new - hi->instruction = HEX_INS_MEMW__RU_____U2____U6____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memw (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda01000) { - // Instruction: 10: 10101101101xxxxxPPu10ttt0------- | memw (Rx ++ Mu) = Nt.new - hi->instruction = HEX_INS_MEMW__RX____MU____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xfa01000) { - // Instruction: 10: 10101111101xxxxxPPu10ttt0------- | memw (Rx ++ Mu:brev) = Nt.new - hi->instruction = HEX_INS_MEMW__RX____MU_BREV____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba03000) { - // Instruction: 10: 10101011101xxxxxPP110ttt0iiii0vv | if (Pv) memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba03004) { - // Instruction: 10: 10101011101xxxxxPP110ttt0iiii1vv | if !Pv memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba03080) { - // Instruction: 10: 10101011101xxxxxPP110ttt1iiii0vv | if (Pv.new) memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba03084) { - // Instruction: 10: 10101011101xxxxxPP110ttt1iiii1vv | if !Pv.new memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa01080) { - // Instruction: 10: 10101111101---iiPP010ttt1iiii0vv | if (Pv) memw (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMW___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if (P%d) memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa01084) { - // Instruction: 10: 10101111101---iiPP010ttt1iiii1vv | if !Pv memw (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMW___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if !P%d memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa03080) { - // Instruction: 10: 10101111101---iiPP110ttt1iiii0vv | if (Pv.new) memw (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMW___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if (P%d.new) memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa03084) { - // Instruction: 10: 10101111101---iiPP110ttt1iiii1vv | if !Pv.new memw (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if !P%d.new memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1c00000) { - // Instruction: 10: 10100ii1110sssssPPitttttiiiiiiii | memd (Rs + #s11:3) = Rtt - hi->instruction = HEX_INS_MEMD__RS____S11_3____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 13)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 13); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 3); - sprintf(hi->mnem, "memd (R%d + %d) = R%d:R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9c00002) { - // Instruction: 10: 10101001110xxxxxPPuttttt0-----1- | memd (Rx ++ I:circ (Mu)) = Rtt - hi->instruction = HEX_INS_MEMD__RX____I_CIRC__MU_____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ I:circ (R%d)) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9c00000) { - // Instruction: 10: 10101001110xxxxxPPuttttt0iiii-0- | memd (Rx ++ #s4:3:circ (Mu)) = Rtt - hi->instruction = HEX_INS_MEMD__RX_____S4_3_CIRC__MU_____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ %d:circ (R%d)) = R%d:R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xbc00080) { - // Instruction: 10: 10101011110eeeeePP0ttttt1-IIIIII | memd (Re = #U6) = Rtt - hi->instruction = HEX_INS_MEMD__RE____U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memd (R%d = 0x%x) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xbc00000) { - // Instruction: 10: 10101011110xxxxxPP0ttttt0iiii-0- | memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_MEMD__RX_____S4_3____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xdc00080) { - // Instruction: 10: 10101101110uuuuuPPittttt1iIIIIII | memd (Ru << #u2 + #U6) = Rtt - hi->instruction = HEX_INS_MEMD__RU_____U2____U6____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memd (R%d << 0x%x + 0x%x) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xdc00000) { - // Instruction: 10: 10101101110xxxxxPPuttttt0------- | memd (Rx ++ Mu) = Rtt - hi->instruction = HEX_INS_MEMD__RX____MU____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ R%d) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xfc00000) { - // Instruction: 10: 10101111110xxxxxPPuttttt0------- | memd (Rx ++ Mu:brev) = Rtt - hi->instruction = HEX_INS_MEMD__RX____MU_BREV____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ R%d:brev) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xbc02000) { - // Instruction: 10: 10101011110xxxxxPP1ttttt0iiii0vv | if (Pv) memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_IF__PV__MEMD__RX_____S4_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xbc02004) { - // Instruction: 10: 10101011110xxxxxPP1ttttt0iiii1vv | if !Pv memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_MEMD__RX_____S4_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xbc02080) { - // Instruction: 10: 10101011110xxxxxPP1ttttt1iiii0vv | if (Pv.new) memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_IF__PV_NEW__MEMD__RX_____S4_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xbc02084) { - // Instruction: 10: 10101011110xxxxxPP1ttttt1iiii1vv | if !Pv.new memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMD__RX_____S4_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xfc00080) { - // Instruction: 10: 10101111110---iiPP0ttttt1iiii0vv | if (Pv) memd (#u6) = Rtt - hi->instruction = HEX_INS_IF__PV__MEMD___U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memd (0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xfc00084) { - // Instruction: 10: 10101111110---iiPP0ttttt1iiii1vv | if !Pv memd (#u6) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_MEMD___U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memd (0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xfc02080) { - // Instruction: 10: 10101111110---iiPP1ttttt1iiii0vv | if (Pv.new) memd (#u6) = Rtt - hi->instruction = HEX_INS_IF__PV_NEW__MEMD___U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memd (0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xfc02084) { - // Instruction: 10: 10101111110---iiPP1ttttt1iiii1vv | if !Pv.new memd (#u6) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMD___U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memd (0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1000000) { - // Instruction: 10: 10100ii1000sssssPPitttttiiiiiiii | memb (Rs + #s11:0) = Rt - hi->instruction = HEX_INS_MEMB__RS____S11_0____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)); - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d + %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9000002) { - // Instruction: 10: 10101001000xxxxxPPuttttt0-----1- | memb (Rx ++ I:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMB__RX____I_CIRC__MU_____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9000000) { - // Instruction: 10: 10101001000xxxxxPPuttttt0iiii-0- | memb (Rx ++ #s4:0:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMB__RX_____S4_0_CIRC__MU_____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[1].op.imm & (1 << 3)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xb000080) { - // Instruction: 10: 10101011000eeeeePP0ttttt1-IIIIII | memb (Re = #U6) = Rt - hi->instruction = HEX_INS_MEMB__RE____U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xb000000) { - // Instruction: 10: 10101011000xxxxxPP0ttttt0iiii-0- | memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_MEMB__RX_____S4_0____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[1].op.imm & (1 << 3)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd000080) { - // Instruction: 10: 10101101000uuuuuPPittttt1iIIIIII | memb (Ru << #u2 + #U6) = Rt - hi->instruction = HEX_INS_MEMB__RU_____U2____U6____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd000000) { - // Instruction: 10: 10101101000xxxxxPPuttttt0------- | memb (Rx ++ Mu) = Rt - hi->instruction = HEX_INS_MEMB__RX____MU____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xf000000) { - // Instruction: 10: 10101111000xxxxxPPuttttt0------- | memb (Rx ++ Mu:brev) = Rt - hi->instruction = HEX_INS_MEMB__RX____MU_BREV____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb002000) { - // Instruction: 10: 10101011000xxxxxPP1ttttt0iiii0vv | if (Pv) memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_IF__PV__MEMB__RX_____S4_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb002004) { - // Instruction: 10: 10101011000xxxxxPP1ttttt0iiii1vv | if !Pv memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RX_____S4_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb002080) { - // Instruction: 10: 10101011000xxxxxPP1ttttt1iiii0vv | if (Pv.new) memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RX_____S4_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb002084) { - // Instruction: 10: 10101011000xxxxxPP1ttttt1iiii1vv | if !Pv.new memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RX_____S4_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf000080) { - // Instruction: 10: 10101111000---iiPP0ttttt1iiii0vv | if (Pv) memb (#u6) = Rt - hi->instruction = HEX_INS_IF__PV__MEMB___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf000084) { - // Instruction: 10: 10101111000---iiPP0ttttt1iiii1vv | if !Pv memb (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMB___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf002080) { - // Instruction: 10: 10101111000---iiPP1ttttt1iiii0vv | if (Pv.new) memb (#u6) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMB___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf002084) { - // Instruction: 10: 10101111000---iiPP1ttttt1iiii1vv | if !Pv.new memb (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1400000) { - // Instruction: 10: 10100ii1010sssssPPitttttiiiiiiii | memh (Rs + #s11:1) = Rt - hi->instruction = HEX_INS_MEMH__RS____S11_1____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 11)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 11); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 1); - sprintf(hi->mnem, "memh (R%d + %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1600000) { - // Instruction: 10: 10100ii1011sssssPPitttttiiiiiiii | memh (Rs + #s11:1) = Rt.H - hi->instruction = HEX_INS_MEMH__RS____S11_1____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 11)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 11); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + %d) = R%d.H", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9400002) { - // Instruction: 10: 10101001010xxxxxPPuttttt0-----1- | memh (Rx ++ I:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMH__RX____I_CIRC__MU_____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9400000) { - // Instruction: 10: 10101001010xxxxxPPuttttt0iiii-0- | memh (Rx ++ #s4:1:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMH__RX_____S4_1_CIRC__MU_____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9600002) { - // Instruction: 10: 10101001011xxxxxPPuttttt0-----1- | memh (Rx ++ I:circ (Mu)) = Rt.H - hi->instruction = HEX_INS_MEMH__RX____I_CIRC__MU_____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ I:circ (R%d)) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9600000) { - // Instruction: 10: 10101001011xxxxxPPuttttt0iiii-0- | memh (Rx ++ #s4:1:circ (Mu)) = Rt.H - hi->instruction = HEX_INS_MEMH__RX_____S4_1_CIRC__MU_____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d:circ (R%d)) = R%d.H", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xb400080) { - // Instruction: 10: 10101011010eeeeePP0ttttt1-IIIIII | memh (Re = #U6) = Rt - hi->instruction = HEX_INS_MEMH__RE____U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memh (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xb400000) { - // Instruction: 10: 10101011010xxxxxPP0ttttt0iiii-0- | memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_MEMH__RX_____S4_1____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xb600080) { - // Instruction: 10: 10101011011eeeeePP0ttttt1-IIIIII | memh (Re = #U6) = Rt.H - hi->instruction = HEX_INS_MEMH__RE____U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d = 0x%x) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xb600000) { - // Instruction: 10: 10101011011xxxxxPP0ttttt0iiii-0- | memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_MEMH__RX_____S4_1____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d) = R%d.H", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd400080) { - // Instruction: 10: 10101101010uuuuuPPittttt1iIIIIII | memh (Ru << #u2 + #U6) = Rt - hi->instruction = HEX_INS_MEMH__RU_____U2____U6____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memh (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd400000) { - // Instruction: 10: 10101101010xxxxxPPuttttt0------- | memh (Rx ++ Mu) = Rt - hi->instruction = HEX_INS_MEMH__RX____MU____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd600080) { - // Instruction: 10: 10101101011uuuuuPPittttt1iIIIIII | memh (Ru << #u2 + #U6) = Rt.H - hi->instruction = HEX_INS_MEMH__RU_____U2____U6____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d << 0x%x + 0x%x) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd600000) { - // Instruction: 10: 10101101011xxxxxPPuttttt0------- | memh (Rx ++ Mu) = Rt.H - hi->instruction = HEX_INS_MEMH__RX____MU____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xf400000) { - // Instruction: 10: 10101111010xxxxxPPuttttt0------- | memh (Rx ++ Mu:brev) = Rt - hi->instruction = HEX_INS_MEMH__RX____MU_BREV____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xf600000) { - // Instruction: 10: 10101111011xxxxxPPuttttt0------- | memh (Rx ++ Mu:brev) = Rt.H - hi->instruction = HEX_INS_MEMH__RX____MU_BREV____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d:brev) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb402000) { - // Instruction: 10: 10101011010xxxxxPP1ttttt0iiii0vv | if (Pv) memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_IF__PV__MEMH__RX_____S4_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb402004) { - // Instruction: 10: 10101011010xxxxxPP1ttttt0iiii1vv | if !Pv memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RX_____S4_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb402080) { - // Instruction: 10: 10101011010xxxxxPP1ttttt1iiii0vv | if (Pv.new) memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RX_____S4_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb402084) { - // Instruction: 10: 10101011010xxxxxPP1ttttt1iiii1vv | if !Pv.new memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RX_____S4_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb602000) { - // Instruction: 10: 10101011011xxxxxPP1ttttt0iiii0vv | if (Pv) memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_IF__PV__MEMH__RX_____S4_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d ++ %d) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb602004) { - // Instruction: 10: 10101011011xxxxxPP1ttttt0iiii1vv | if !Pv memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RX_____S4_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d ++ %d) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb602080) { - // Instruction: 10: 10101011011xxxxxPP1ttttt1iiii0vv | if (Pv.new) memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RX_____S4_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d ++ %d) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb602084) { - // Instruction: 10: 10101011011xxxxxPP1ttttt1iiii1vv | if !Pv.new memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RX_____S4_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d ++ %d) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf400080) { - // Instruction: 10: 10101111010---iiPP0ttttt1iiii0vv | if (Pv) memh (#u6) = Rt - hi->instruction = HEX_INS_IF__PV__MEMH___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf400084) { - // Instruction: 10: 10101111010---iiPP0ttttt1iiii1vv | if !Pv memh (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMH___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf402080) { - // Instruction: 10: 10101111010---iiPP1ttttt1iiii0vv | if (Pv.new) memh (#u6) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMH___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf402084) { - // Instruction: 10: 10101111010---iiPP1ttttt1iiii1vv | if !Pv.new memh (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf600080) { - // Instruction: 10: 10101111011---iiPP0ttttt1iiii0vv | if (Pv) memh (#u6) = Rt.H - hi->instruction = HEX_INS_IF__PV__MEMH___U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf600084) { - // Instruction: 10: 10101111011---iiPP0ttttt1iiii1vv | if !Pv memh (#u6) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_MEMH___U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf602080) { - // Instruction: 10: 10101111011---iiPP1ttttt1iiii0vv | if (Pv.new) memh (#u6) = Rt.H - hi->instruction = HEX_INS_IF__PV_NEW__MEMH___U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf602084) { - // Instruction: 10: 10101111011---iiPP1ttttt1iiii1vv | if !Pv.new memh (#u6) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH___U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1800000) { - // Instruction: 10: 10100ii1100sssssPPitttttiiiiiiii | memw (Rs + #s11:2) = Rt - hi->instruction = HEX_INS_MEMW__RS____S11_2____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 12)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 12); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "memw (R%d + %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9800002) { - // Instruction: 10: 10101001100xxxxxPPuttttt0-----1- | memw (Rx ++ I:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMW__RX____I_CIRC__MU_____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9800000) { - // Instruction: 10: 10101001100xxxxxPPuttttt0iiii-0- | memw (Rx ++ #s4:2:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMW__RX_____S4_2_CIRC__MU_____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xb800080) { - // Instruction: 10: 10101011100eeeeePP0ttttt1-IIIIII | memw (Re = #U6) = Rt - hi->instruction = HEX_INS_MEMW__RE____U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memw (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xb800000) { - // Instruction: 10: 10101011100xxxxxPP0ttttt0iiii-0- | memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_MEMW__RX_____S4_2____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd800080) { - // Instruction: 10: 10101101100uuuuuPPittttt1iIIIIII | memw (Ru << #u2 + #U6) = Rt - hi->instruction = HEX_INS_MEMW__RU_____U2____U6____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memw (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd800000) { - // Instruction: 10: 10101101100xxxxxPPuttttt0------- | memw (Rx ++ Mu) = Rt - hi->instruction = HEX_INS_MEMW__RX____MU____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xf800000) { - // Instruction: 10: 10101111100xxxxxPPuttttt0------- | memw (Rx ++ Mu:brev) = Rt - hi->instruction = HEX_INS_MEMW__RX____MU_BREV____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb802000) { - // Instruction: 10: 10101011100xxxxxPP1ttttt0iiii0vv | if (Pv) memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMW__RX_____S4_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb802004) { - // Instruction: 10: 10101011100xxxxxPP1ttttt0iiii1vv | if !Pv memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RX_____S4_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb802080) { - // Instruction: 10: 10101011100xxxxxPP1ttttt1iiii0vv | if (Pv.new) memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RX_____S4_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb802084) { - // Instruction: 10: 10101011100xxxxxPP1ttttt1iiii1vv | if !Pv.new memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RX_____S4_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf800080) { - // Instruction: 10: 10101111100---iiPP0ttttt1iiii0vv | if (Pv) memw (#u6) = Rt - hi->instruction = HEX_INS_IF__PV__MEMW___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if (P%d) memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf800084) { - // Instruction: 10: 10101111100---iiPP0ttttt1iiii1vv | if !Pv memw (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMW___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if !P%d memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf802080) { - // Instruction: 10: 10101111100---iiPP1ttttt1iiii0vv | if (Pv.new) memw (#u6) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMW___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if (P%d.new) memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf802084) { - // Instruction: 10: 10101111100---iiPP1ttttt1iiii1vv | if !Pv.new memw (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if !P%d.new memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfff3800) == 0x9d0000) { - // Instruction: 10: 1010000010011101PP000iiiiiiiiiii | allocframe (#u11:3) - hi->instruction = HEX_INS_ALLOCFRAME___U11_3_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32) & 0x7ff) >> 0) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "allocframe (0x%x)", hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2000000) { - // Instruction: 10: 10100010000-----PP-------------- | dckill - hi->instruction = HEX_INS_DCKILL; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dckill"); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2200000) { - // Instruction: 10: 10100010001sssssPP-------------- | dccleanidx (Rs) - hi->instruction = HEX_INS_DCCLEANIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dccleanidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2400000) { - // Instruction: 10: 10100010010sssssPP-------------- | dcinvidx (Rs) - hi->instruction = HEX_INS_DCINVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dcinvidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2600000) { - // Instruction: 10: 10100010011sssssPP-------------- | dccleaninvidx (Rs) - hi->instruction = HEX_INS_DCCLEANINVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dccleaninvidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4000000) { - // Instruction: 10: 10100100000sssssPP-ttttt-------- | dctagw (Rs, Rt) - hi->instruction = HEX_INS_DCTAGW__RS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dctagw (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4200000) { - // Instruction: 10: 10100100001sssssPP---------ddddd | Rd = dctagr (Rs) - hi->instruction = HEX_INS_RD___DCTAGR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = dctagr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6200000) { - // Instruction: 10: 10100110001sssssPP-------------- | l2cleanidx (Rs) - hi->instruction = HEX_INS_L2CLEANIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2cleanidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6400000) { - // Instruction: 10: 10100110010sssssPP-------------- | l2invidx (Rs) - hi->instruction = HEX_INS_L2INVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2invidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8600000) { - // Instruction: 10: 10101000011sssssPP-------------- | l2cleaninvidx (Rs) - hi->instruction = HEX_INS_L2CLEANINVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2cleaninvidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6a00000) { - // Instruction: 10: 10100110101-----PP-ttttt-------- | l2gclean (Rtt) - hi->instruction = HEX_INS_L2GCLEAN__RTT_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gclean (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6c00000) { - // Instruction: 10: 10100110110-----PP-ttttt-------- | l2gcleaninv (Rtt) - hi->instruction = HEX_INS_L2GCLEANINV__RTT_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gcleaninv (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe01c00) == 0x8200000) { - // Instruction: 10: 10101000001-----PP-000---------- | l2kill - hi->instruction = HEX_INS_L2KILL; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2kill"); - break; - } - if ((hi_u32 & 0xfe01c00) == 0x8200800) { - // Instruction: 10: 10101000001-----PP-010---------- | l2gunlock - hi->instruction = HEX_INS_L2GUNLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gunlock"); - break; - } - if ((hi_u32 & 0xfe01c00) == 0x8201000) { - // Instruction: 10: 10101000001-----PP-100---------- | l2gclean - hi->instruction = HEX_INS_L2GCLEAN; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gclean"); - break; - } - if ((hi_u32 & 0xfe01c00) == 0x8201800) { - // Instruction: 10: 10101000001-----PP-110---------- | l2gcleaninv - hi->instruction = HEX_INS_L2GCLEANINV; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gcleaninv"); - break; - } - if ((hi_u32 & 0xfe02000) == 0xe02000) { - // Instruction: 10: 10100000111sssssPP1-----------dd | Pd = l2locka (Rs) - hi->instruction = HEX_INS_PD___L2LOCKA__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = l2locka (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6600000) { - // Instruction: 10: 10100110011sssssPP-------------- | l2unlocka (Rs) - hi->instruction = HEX_INS_L2UNLOCKA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2unlocka (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x4400000) { - // Instruction: 10: 10100100010sssssPP0ttttt-------- | l2tagw (Rs, Rt) - hi->instruction = HEX_INS_L2TAGW__RS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2tagw (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4600000) { - // Instruction: 10: 10100100011sssssPP---------ddddd | Rd = l2tagr (Rs) - hi->instruction = HEX_INS_RD___L2TAGR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = l2tagr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa00000) { - // Instruction: 10: 10100000101sssssPP-ttttt------dd | memw_locked (Rs, Pd) = Rt - hi->instruction = HEX_INS_MEMW_LOCKED__RS__PD____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw_locked (R%d, P%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xe00000) { - // Instruction: 10: 10100000111sssssPP0ttttt------dd | memd_locked (Rs, Pd) = Rtt - hi->instruction = HEX_INS_MEMD_LOCKED__RS__PD____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd_locked (R%d, P%d) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xc00000) { - // Instruction: 10: 10100000110sssssPP0------------- | dczeroa (Rs) - hi->instruction = HEX_INS_DCZEROA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dczeroa (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8000000) { - // Instruction: 10: 10101000000-----PP-------------- | barrier - hi->instruction = HEX_INS_BARRIER; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "barrier"); - break; - } - if ((hi_u32 & 0xfe00000) == 0x0) { - // Instruction: 10: 10100000000sssssPP-------------- | dccleana (Rs) - hi->instruction = HEX_INS_DCCLEANA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dccleana (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x200000) { - // Instruction: 10: 10100000001sssssPP-------------- | dcinva (Rs) - hi->instruction = HEX_INS_DCINVA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dcinva (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x400000) { - // Instruction: 10: 10100000010sssssPP-------------- | dccleaninva (Rs) - hi->instruction = HEX_INS_DCCLEANINVA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dccleaninva (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6000000) { - // Instruction: 10: 10100110000sssssPP-ttttt-------- | l2fetch (Rs, Rt) - hi->instruction = HEX_INS_L2FETCH__RS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2fetch (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6800000) { - // Instruction: 10: 10100110100sssssPP-ttttt-------- | l2fetch (Rs, Rtt) - hi->instruction = HEX_INS_L2FETCH__RS__RTT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2fetch (R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8400000) { - // Instruction: 10: 10101000010-----PP-------------- | syncht - hi->instruction = HEX_INS_SYNCHT; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "syncht"); - break; - } - break; - } - case 0xb: { - if ((hi_u32 & 0x0) == 0x0) { - // Instruction: 11: 1011iiiiiiisssssPPiiiiiiiiiddddd | Rd = add (Rs, #s16) - hi->instruction = HEX_INS_RD___ADD__RS___S16_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xfe00000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 15)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 15); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = add (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - break; - } - case 0xc: { - if ((hi_u32 & 0xfe00000) == 0x2c00000) { - // Instruction: 12: 11000010110sssssPP-ttttt-xxddddd | Rdd = add (Rss, Rtt, Px) :carry - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT__PX___CARRY; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d, P%d) :carry", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2e00000) { - // Instruction: 12: 11000010111sssssPP-ttttt-xxddddd | Rdd = sub (Rss, Rtt, Px) :carry - hi->instruction = HEX_INS_RDD___SUB__RSS__RTT__PX___CARRY; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = sub (R%d:R%d, R%d:R%d, P%d) :carry", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xa800000) { - // Instruction: 12: 1100101010-sssssPP0ttttt000xxxxx | Rxx ^= xor (Rss, Rtt) - hi->instruction = HEX_INS_RXX____XOR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= xor (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6c00000) { - // Instruction: 12: 1100011011-sssssPP-ttttt00-ddddd | Rd = cround (Rs, Rt) - hi->instruction = HEX_INS_RD___CROUND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cround (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6c00080) { - // Instruction: 12: 1100011011-sssssPP-ttttt10-ddddd | Rd = round (Rs, Rt) - hi->instruction = HEX_INS_RD___ROUND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = round (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6c000c0) { - // Instruction: 12: 1100011011-sssssPP-ttttt11-ddddd | Rd = round (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___ROUND__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = round (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1400020) { - // Instruction: 12: 1100000101-sssssPP-ttttt001ddddd | Rd = vaddhub (Rss, Rtt) :sat - hi->instruction = HEX_INS_RD___VADDHUB__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vaddhub (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3c00040) { - // Instruction: 12: 1100001111-sssssPP-ttttt01-ddddd | Rdd = vcnegh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VCNEGH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vcnegh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2020e0) { - // Instruction: 12: 11001011001sssssPP1ttttt111xxxxx | Rxx += vrcnegh (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCNEGH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcnegh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb200020) { - // Instruction: 12: 11001011001sssssPP0xxxxx001uuuuu | Rxx = vrmaxh (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMAXH__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmaxh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb202020) { - // Instruction: 12: 11001011001sssssPP1xxxxx001uuuuu | Rxx = vrmaxuh (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMAXUH__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmaxuh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb200040) { - // Instruction: 12: 11001011001sssssPP0xxxxx010uuuuu | Rxx = vrmaxw (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMAXW__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmaxw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb202040) { - // Instruction: 12: 11001011001sssssPP1xxxxx010uuuuu | Rxx = vrmaxuw (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMAXUW__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmaxuw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2000a0) { - // Instruction: 12: 11001011001sssssPP0xxxxx101uuuuu | Rxx = vrminh (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMINH__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrminh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2020a0) { - // Instruction: 12: 11001011001sssssPP1xxxxx101uuuuu | Rxx = vrminuh (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMINUH__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrminuh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2000c0) { - // Instruction: 12: 11001011001sssssPP0xxxxx110uuuuu | Rxx = vrminw (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMINW__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrminw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2020c0) { - // Instruction: 12: 11001011001sssssPP1xxxxx110uuuuu | Rxx = vrminuw (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMINUW__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrminuw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1000000) { - // Instruction: 12: 1100000100-sssssPP-ttttt00-ddddd | Rdd = extractu (Rss, Rtt) - hi->instruction = HEX_INS_RDD___EXTRACTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = extractu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1c00080) { - // Instruction: 12: 1100000111-sssssPP-ttttt10-ddddd | Rdd = extract (Rss, Rtt) - hi->instruction = HEX_INS_RDD___EXTRACT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = extract (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x9000000) { - // Instruction: 12: 1100100100-sssssPP-ttttt00-ddddd | Rd = extractu (Rs, Rtt) - hi->instruction = HEX_INS_RD___EXTRACTU__RS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = extractu (R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x9000040) { - // Instruction: 12: 1100100100-sssssPP-ttttt01-ddddd | Rd = extract (Rs, Rtt) - hi->instruction = HEX_INS_RD___EXTRACT__RS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = extract (R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x8000000) { - // Instruction: 12: 11001000---sssssPP-ttttt---xxxxx | Rx = insert (Rs, Rtt) - hi->instruction = HEX_INS_RX___INSERT__RS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = insert (R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf802000) == 0xa000000) { - // Instruction: 12: 110010100--sssssPP0ttttt---xxxxx | Rxx = insert (Rss, Rtt) - hi->instruction = HEX_INS_RXX___INSERT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = insert (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x18000c0) { - // Instruction: 12: 1100000110-sssssPP-ttttt110ddddd | Rdd = lfs (Rss, Rtt) - hi->instruction = HEX_INS_RDD___LFS__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = lfs (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6800000) { - // Instruction: 12: 1100011010-sssssPP-ttttt00-ddddd | Rd = setbit (Rs, Rt) - hi->instruction = HEX_INS_RD___SETBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = setbit (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6800040) { - // Instruction: 12: 1100011010-sssssPP-ttttt01-ddddd | Rd = clrbit (Rs, Rt) - hi->instruction = HEX_INS_RD___CLRBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = clrbit (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6800080) { - // Instruction: 12: 1100011010-sssssPP-ttttt10-ddddd | Rd = togglebit (Rs, Rt) - hi->instruction = HEX_INS_RD___TOGGLEBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = togglebit (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1400080) { - // Instruction: 12: 1100000101-sssssPP-ttttt100ddddd | Rdd = vxaddsubh (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VXADDSUBH__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxaddsubh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x14000c0) { - // Instruction: 12: 1100000101-sssssPP-ttttt110ddddd | Rdd = vxsubaddh (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VXSUBADDH__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxsubaddh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1c00000) { - // Instruction: 12: 1100000111-sssssPP-ttttt00-ddddd | Rdd = vxaddsubh (Rss, Rtt) :rnd:>>1:sat - hi->instruction = HEX_INS_RDD___VXADDSUBH__RSS__RTT___RND___1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RSH1; // :>>1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxaddsubh (R%d:R%d, R%d:R%d) :rnd:>>1:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1c00040) { - // Instruction: 12: 1100000111-sssssPP-ttttt01-ddddd | Rdd = vxsubaddh (Rss, Rtt) :rnd:>>1:sat - hi->instruction = HEX_INS_RDD___VXSUBADDH__RSS__RTT___RND___1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RSH1; // :>>1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxsubaddh (R%d:R%d, R%d:R%d) :rnd:>>1:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1400000) { - // Instruction: 12: 1100000101-sssssPP-ttttt000ddddd | Rdd = vxaddsubw (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VXADDSUBW__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxaddsubw (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1400040) { - // Instruction: 12: 1100000101-sssssPP-ttttt010ddddd | Rdd = vxsubaddw (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VXSUBADDW__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxsubaddw (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x5000080) { - // Instruction: 12: 11000101---sssssPP-ttttt100ddddd | Rd = cmpyiwh (Rss, Rt) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___CMPYIWH__RSS__RT_____1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpyiwh (R%d:R%d, R%d) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x50000a0) { - // Instruction: 12: 11000101---sssssPP-ttttt101ddddd | Rd = cmpyiwh (Rss, Rt *) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___CMPYIWH__RSS__RT_______1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpyiwh (R%d:R%d, R%d *) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x50000c0) { - // Instruction: 12: 11000101---sssssPP-ttttt110ddddd | Rd = cmpyrwh (Rss, Rt) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___CMPYRWH__RSS__RT_____1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpyrwh (R%d:R%d, R%d) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x50000e0) { - // Instruction: 12: 11000101---sssssPP-ttttt111ddddd | Rd = cmpyrwh (Rss, Rt *) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___CMPYRWH__RSS__RT_______1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpyrwh (R%d:R%d, R%d *) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3c00000) { - // Instruction: 12: 1100001111-sssssPP-ttttt00-ddddd | Rdd = vcrotate (Rss, Rt) - hi->instruction = HEX_INS_RDD___VCROTATE__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vcrotate (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3c000c0) { - // Instruction: 12: 1100001111-sssssPPittttt11iddddd | Rdd = vrcrotate (Rss, Rt, #u2) - hi->instruction = HEX_INS_RDD___VRCROTATE__RSS__RT___U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x20) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcrotate (R%d:R%d, R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xba00000) { - // Instruction: 12: 11001011101sssssPPittttt--ixxxxx | Rxx += vrcrotate (Rss, Rt, #u2) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCROTATE__RSS__RT___U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x20) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcrotate (R%d:R%d, R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7e00000) { - // Instruction: 12: 11000111111sssssPP-ttttt000---dd | Pd = cmp.ge (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_GE__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.ge (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7e00020) { - // Instruction: 12: 11000111111sssssPP-ttttt001---dd | Pd = cmp.uo (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_UO__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.uo (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7e00060) { - // Instruction: 12: 11000111111sssssPP-ttttt011---dd | Pd = cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_EQ__RS__RT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7e00080) { - // Instruction: 12: 11000111111sssssPP-ttttt100---dd | Pd = cmp.gt (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_GT__RS__RT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1c000c0) { - // Instruction: 12: 1100000111-sssssPP-ttttt11-ddddd | Rdd = decbin (Rss, Rtt) - hi->instruction = HEX_INS_RDD___DECBIN__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = decbin (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0x0) { - // Instruction: 12: 110000000--sssssPP-tttttiiiddddd | Rdd = valignb (Rtt, Rss, #u3) - hi->instruction = HEX_INS_RDD___VALIGNB__RTT__RSS___U3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = valignb (R%d:R%d, R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0x2000000) { - // Instruction: 12: 110000100--sssssPP-ttttt-uuddddd | Rdd = valignb (Rtt, Rss, Pu) - hi->instruction = HEX_INS_RDD___VALIGNB__RTT__RSS__PU_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = valignb (R%d:R%d, R%d:R%d, P%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1000040) { - // Instruction: 12: 1100000100-sssssPP-ttttt01-ddddd | Rdd = shuffeb (Rss, Rtt) - hi->instruction = HEX_INS_RDD___SHUFFEB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = shuffeb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1000080) { - // Instruction: 12: 1100000100-sssssPP-ttttt10-ddddd | Rdd = shuffob (Rtt, Rss) - hi->instruction = HEX_INS_RDD___SHUFFOB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = shuffob (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x10000c0) { - // Instruction: 12: 1100000100-sssssPP-ttttt11-ddddd | Rdd = shuffeh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___SHUFFEH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = shuffeh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1800000) { - // Instruction: 12: 1100000110-sssssPP-ttttt000ddddd | Rdd = shuffoh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___SHUFFOH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = shuffoh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0x800000) { - // Instruction: 12: 110000001--sssssPP-tttttiiiddddd | Rdd = vspliceb (Rss, Rtt, #u3) - hi->instruction = HEX_INS_RDD___VSPLICEB__RSS__RTT___U3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vspliceb (R%d:R%d, R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2800000) { - // Instruction: 12: 11000010100sssssPP-ttttt-uuddddd | Rdd = vspliceb (Rss, Rtt, Pu) - hi->instruction = HEX_INS_RDD___VSPLICEB__RSS__RTT__PU_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vspliceb (R%d:R%d, R%d:R%d, P%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1800040) { - // Instruction: 12: 1100000110-sssssPP-ttttt010ddddd | Rdd = vtrunewh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VTRUNEWH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vtrunewh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1800060) { - // Instruction: 12: 1100000110-sssssPP-ttttt011ddddd | Rdd = vtrunehb (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VTRUNEHB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vtrunehb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1800080) { - // Instruction: 12: 1100000110-sssssPP-ttttt100ddddd | Rdd = vtrunowh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VTRUNOWH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vtrunowh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x18000a0) { - // Instruction: 12: 1100000110-sssssPP-ttttt101ddddd | Rdd = vtrunohb (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VTRUNOHB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vtrunohb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c00040) { - // Instruction: 12: 11000111110sssssPP-ttttt010---dd | Pd = cmpb.gt (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPB_GT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmpb.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c000c0) { - // Instruction: 12: 11000111110sssssPP-ttttt110---dd | Pd = cmpb.eq (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPB_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmpb.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c000e0) { - // Instruction: 12: 11000111110sssssPP-ttttt111---dd | Pd = cmpb.gtu (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPB_GTU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmpb.gtu (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c00060) { - // Instruction: 12: 11000111110sssssPP-ttttt011---dd | Pd = cmph.eq (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPH_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmph.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c00080) { - // Instruction: 12: 11000111110sssssPP-ttttt100---dd | Pd = cmph.gt (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPH_GT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmph.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c000a0) { - // Instruction: 12: 11000111110sssssPP-ttttt101---dd | Pd = cmph.gtu (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPH_GTU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmph.gtu (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7400000) { - // Instruction: 12: 11000111010sssssPP-ttttt------dd | Pd = bitsset (Rs, Rt) - hi->instruction = HEX_INS_PD___BITSSET__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = bitsset (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7600000) { - // Instruction: 12: 11000111011sssssPP-ttttt------dd | Pd = !bitsset (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_BITSSET__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !bitsset (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7800000) { - // Instruction: 12: 11000111100sssssPP-ttttt------dd | Pd = bitsclr (Rs, Rt) - hi->instruction = HEX_INS_PD___BITSCLR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = bitsclr (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7a00000) { - // Instruction: 12: 11000111101sssssPP-ttttt------dd | Pd = !bitsclr (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_BITSCLR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !bitsclr (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7000000) { - // Instruction: 12: 11000111000sssssPP-ttttt------dd | Pd = tstbit (Rs, Rt) - hi->instruction = HEX_INS_PD___TSTBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = tstbit (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7200000) { - // Instruction: 12: 11000111001sssssPP-ttttt------dd | Pd = !tstbit (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_TSTBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !tstbit (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x4000000) { - // Instruction: 12: 11000100000sssssPP0tttttiiiddddd | Rd = addasl (Rt, Rs, #u3) - hi->instruction = HEX_INS_RD___ADDASL__RT__RS___U3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32) & 0xe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = addasl (R%d, R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3800000) { - // Instruction: 12: 1100001110-sssssPP-ttttt00-ddddd | Rdd = asr (Rss, Rt) - hi->instruction = HEX_INS_RDD___ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3800040) { - // Instruction: 12: 1100001110-sssssPP-ttttt01-ddddd | Rdd = lsr (Rss, Rt) - hi->instruction = HEX_INS_RDD___LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3800080) { - // Instruction: 12: 1100001110-sssssPP-ttttt10-ddddd | Rdd = asl (Rss, Rt) - hi->instruction = HEX_INS_RDD___ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x38000c0) { - // Instruction: 12: 1100001110-sssssPP-ttttt11-ddddd | Rdd = lsl (Rss, Rt) - hi->instruction = HEX_INS_RDD___LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6400000) { - // Instruction: 12: 1100011001-sssssPP-ttttt00-ddddd | Rd = asr (Rs, Rt) - hi->instruction = HEX_INS_RD___ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6400040) { - // Instruction: 12: 1100011001-sssssPP-ttttt01-ddddd | Rd = lsr (Rs, Rt) - hi->instruction = HEX_INS_RD___LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6400080) { - // Instruction: 12: 1100011001-sssssPP-ttttt10-ddddd | Rd = asl (Rs, Rt) - hi->instruction = HEX_INS_RD___ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x64000c0) { - // Instruction: 12: 1100011001-sssssPP-ttttt11-ddddd | Rd = lsl (Rs, Rt) - hi->instruction = HEX_INS_RD___LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x68000c0) { - // Instruction: 12: 1100011010-iiiiiPP-ttttt11iddddd | Rd = lsl (#s6, Rt) - hi->instruction = HEX_INS_RD___LSL___S6__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x20) >> 5)); - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = lsl (%d, R%d)", hi->ops[0].op.reg, (st32) hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb800000) { - // Instruction: 12: 11001011100sssssPP-ttttt00-xxxxx | Rxx -= asr (Rss, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb800040) { - // Instruction: 12: 11001011100sssssPP-ttttt01-xxxxx | Rxx -= lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb800080) { - // Instruction: 12: 11001011100sssssPP-ttttt10-xxxxx | Rxx -= asl (Rss, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb8000c0) { - // Instruction: 12: 11001011100sssssPP-ttttt11-xxxxx | Rxx -= lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xbc00000) { - // Instruction: 12: 11001011110sssssPP-ttttt00-xxxxx | Rxx += asr (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xbc00040) { - // Instruction: 12: 11001011110sssssPP-ttttt01-xxxxx | Rxx += lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xbc00080) { - // Instruction: 12: 11001011110sssssPP-ttttt10-xxxxx | Rxx += asl (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xbc000c0) { - // Instruction: 12: 11001011110sssssPP-ttttt11-xxxxx | Rxx += lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800000) { - // Instruction: 12: 1100110010-sssssPP-ttttt00-xxxxx | Rx -= asr (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800040) { - // Instruction: 12: 1100110010-sssssPP-ttttt01-xxxxx | Rx -= lsr (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800080) { - // Instruction: 12: 1100110010-sssssPP-ttttt10-xxxxx | Rx -= asl (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc8000c0) { - // Instruction: 12: 1100110010-sssssPP-ttttt11-xxxxx | Rx -= lsl (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xcc00000) { - // Instruction: 12: 1100110011-sssssPP-ttttt00-xxxxx | Rx += asr (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xcc00040) { - // Instruction: 12: 1100110011-sssssPP-ttttt01-xxxxx | Rx += lsr (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xcc00080) { - // Instruction: 12: 1100110011-sssssPP-ttttt10-xxxxx | Rx += asl (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xcc000c0) { - // Instruction: 12: 1100110011-sssssPP-ttttt11-xxxxx | Rx += lsl (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb000000) { - // Instruction: 12: 11001011000sssssPP-ttttt00-xxxxx | Rxx |= asr (Rss, Rt) - hi->instruction = HEX_INS_RXX__OR_EQ__ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb000040) { - // Instruction: 12: 11001011000sssssPP-ttttt01-xxxxx | Rxx |= lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX__OR_EQ__LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb000080) { - // Instruction: 12: 11001011000sssssPP-ttttt10-xxxxx | Rxx |= asl (Rss, Rt) - hi->instruction = HEX_INS_RXX__OR_EQ__ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb0000c0) { - // Instruction: 12: 11001011000sssssPP-ttttt11-xxxxx | Rxx |= lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX__OR_EQ__LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb400000) { - // Instruction: 12: 11001011010sssssPP-ttttt00-xxxxx | Rxx &= asr (Rss, Rt) - hi->instruction = HEX_INS_RXX__AND_EQ__ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb400040) { - // Instruction: 12: 11001011010sssssPP-ttttt01-xxxxx | Rxx &= lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX__AND_EQ__LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb400080) { - // Instruction: 12: 11001011010sssssPP-ttttt10-xxxxx | Rxx &= asl (Rss, Rt) - hi->instruction = HEX_INS_RXX__AND_EQ__ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb4000c0) { - // Instruction: 12: 11001011010sssssPP-ttttt11-xxxxx | Rxx &= lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX__AND_EQ__LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb600000) { - // Instruction: 12: 11001011011sssssPP-ttttt00-xxxxx | Rxx ^= asr (Rss, Rt) - hi->instruction = HEX_INS_RXX____ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb600040) { - // Instruction: 12: 11001011011sssssPP-ttttt01-xxxxx | Rxx ^= lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX____LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb600080) { - // Instruction: 12: 11001011011sssssPP-ttttt10-xxxxx | Rxx ^= asl (Rss, Rt) - hi->instruction = HEX_INS_RXX____ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb6000c0) { - // Instruction: 12: 11001011011sssssPP-ttttt11-xxxxx | Rxx ^= lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX____LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc000000) { - // Instruction: 12: 1100110000-sssssPP-ttttt00-xxxxx | Rx |= asr (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc000040) { - // Instruction: 12: 1100110000-sssssPP-ttttt01-xxxxx | Rx |= lsr (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc000080) { - // Instruction: 12: 1100110000-sssssPP-ttttt10-xxxxx | Rx |= asl (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc0000c0) { - // Instruction: 12: 1100110000-sssssPP-ttttt11-xxxxx | Rx |= lsl (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc400000) { - // Instruction: 12: 1100110001-sssssPP-ttttt00-xxxxx | Rx &= asr (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc400040) { - // Instruction: 12: 1100110001-sssssPP-ttttt01-xxxxx | Rx &= lsr (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc400080) { - // Instruction: 12: 1100110001-sssssPP-ttttt10-xxxxx | Rx &= asl (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc4000c0) { - // Instruction: 12: 1100110001-sssssPP-ttttt11-xxxxx | Rx &= lsl (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6000000) { - // Instruction: 12: 1100011000-sssssPP-ttttt00-ddddd | Rd = asr (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___ASR__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = asr (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6000080) { - // Instruction: 12: 1100011000-sssssPP-ttttt10-ddddd | Rd = asl (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___ASL__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = asl (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3400000) { - // Instruction: 12: 1100001101-sssssPP-ttttt00-ddddd | Rdd = vasrh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VASRH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vasrh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3400040) { - // Instruction: 12: 1100001101-sssssPP-ttttt01-ddddd | Rdd = vlsrh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VLSRH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlsrh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3400080) { - // Instruction: 12: 1100001101-sssssPP-ttttt10-ddddd | Rdd = vaslh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VASLH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaslh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x34000c0) { - // Instruction: 12: 1100001101-sssssPP-ttttt11-ddddd | Rdd = vlslh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VLSLH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlslh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3000000) { - // Instruction: 12: 1100001100-sssssPP-ttttt00-ddddd | Rdd = vasrw (Rss, Rt) - hi->instruction = HEX_INS_RDD___VASRW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vasrw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3000040) { - // Instruction: 12: 1100001100-sssssPP-ttttt01-ddddd | Rdd = vlsrw (Rss, Rt) - hi->instruction = HEX_INS_RDD___VLSRW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlsrw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3000080) { - // Instruction: 12: 1100001100-sssssPP-ttttt10-ddddd | Rdd = vaslw (Rss, Rt) - hi->instruction = HEX_INS_RDD___VASLW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaslw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x30000c0) { - // Instruction: 12: 1100001100-sssssPP-ttttt11-ddddd | Rdd = vlslw (Rss, Rt) - hi->instruction = HEX_INS_RDD___VLSLW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlslw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x5000040) { - // Instruction: 12: 11000101---sssssPP-ttttt010ddddd | Rd = vasrw (Rss, Rt) - hi->instruction = HEX_INS_RD___VASRW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vasrw (R%d:R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - break; - } - case 0xd: { - if ((hi_u32 & 0xf800000) == 0xb000000) { - // Instruction: 13: 110110110iisssssPPidddddiiiuuuuu | Rd = add (Rs, add (Ru, #s6)) - hi->instruction = HEX_INS_RD___ADD__RS__ADD__RU___S6__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "R%d = add (R%d, add (R%d, %d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32) hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0xb800000) { - // Instruction: 13: 110110111iisssssPPidddddiiiuuuuu | Rd = add (Rs, sub (#s6, Ru)) - hi->instruction = HEX_INS_RD___ADD__RS__SUB___S6__RU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = add (R%d, sub (%d, R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x30000e0) { - // Instruction: 13: 11010011000sssssPP-ttttt111ddddd | Rdd = add (Rss, Rtt) - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x36000a0) { - // Instruction: 13: 11010011011sssssPP-ttttt101ddddd | Rdd = add (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x36000c0) { - // Instruction: 13: 11010011011sssssPP-ttttt110ddddd | Rdd = add (Rss, Rtt) :raw:lo - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT___RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d) :raw:lo", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x36000e0) { - // Instruction: 13: 11010011011sssssPP-ttttt111ddddd | Rdd = add (Rss, Rtt) :raw:hi - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT___RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d) :raw:hi", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5800000) { - // Instruction: 13: 11010101100sssssPP-ttttt0--ddddd | Rd = add (Rs, Rt) :sat:deprecated - hi->instruction = HEX_INS_RD___ADD__RS__RT___SAT_DEPRECATED; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_DEPRECATED; // :deprecated - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d, R%d) :sat:deprecated", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5000000) { - // Instruction: 13: 11010101000sssssPP-ttttt00-ddddd | Rd = add (Rt.L, Rs.L) - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_L_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.L)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5000040) { - // Instruction: 13: 11010101000sssssPP-ttttt01-ddddd | Rd = add (Rt.L, Rs.H) - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_H_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.H)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5000080) { - // Instruction: 13: 11010101000sssssPP-ttttt10-ddddd | Rd = add (Rt.L, Rs.L) :sat - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_L___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.L) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x50000c0) { - // Instruction: 13: 11010101000sssssPP-ttttt11-ddddd | Rd = add (Rt.L, Rs.H) :sat - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_H___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.H) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400000) { - // Instruction: 13: 11010101010sssssPP-ttttt000ddddd | Rd = add (Rt.L, Rs.L) :<<16 - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_L_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.L) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400020) { - // Instruction: 13: 11010101010sssssPP-ttttt001ddddd | Rd = add (Rt.L, Rs.H) :<<16 - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_H_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.H) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400040) { - // Instruction: 13: 11010101010sssssPP-ttttt010ddddd | Rd = add (Rt.H, Rs.L) :<<16 - hi->instruction = HEX_INS_RD___ADD__RT_H__RS_L_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = add (R%d.H, R%d.L) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400060) { - // Instruction: 13: 11010101010sssssPP-ttttt011ddddd | Rd = add (Rt.H, Rs.H) :<<16 - hi->instruction = HEX_INS_RD___ADD__RT_H__RS_H_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = add (R%d.H, R%d.H) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400080) { - // Instruction: 13: 11010101010sssssPP-ttttt100ddddd | Rd = add (Rt.L, Rs.L) :sat:<<16 - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_L___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.L) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x54000a0) { - // Instruction: 13: 11010101010sssssPP-ttttt101ddddd | Rd = add (Rt.L, Rs.H) :sat:<<16 - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_H___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.H) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x54000c0) { - // Instruction: 13: 11010101010sssssPP-ttttt110ddddd | Rd = add (Rt.H, Rs.L) :sat:<<16 - hi->instruction = HEX_INS_RD___ADD__RT_H__RS_L___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.H, R%d.L) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x54000e0) { - // Instruction: 13: 11010101010sssssPP-ttttt111ddddd | Rd = add (Rt.H, Rs.H) :sat:<<16 - hi->instruction = HEX_INS_RD___ADD__RT_H__RS_H___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.H, R%d.H) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00000) { - // Instruction: 13: 11010011111sssssPP-ttttt000ddddd | Rdd = and (Rss, Rtt) - hi->instruction = HEX_INS_RDD___AND__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = and (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00020) { - // Instruction: 13: 11010011111sssssPP-ttttt001ddddd | Rdd = and (Rtt, ~Rss) - hi->instruction = HEX_INS_RDD___AND__RTT___RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = and (R%d:R%d, ~R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00040) { - // Instruction: 13: 11010011111sssssPP-ttttt010ddddd | Rdd = or (Rss, Rtt) - hi->instruction = HEX_INS_RDD___OR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = or (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00060) { - // Instruction: 13: 11010011111sssssPP-ttttt011ddddd | Rdd = or (Rtt, ~Rss) - hi->instruction = HEX_INS_RDD___OR__RTT___RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = or (R%d:R%d, ~R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00080) { - // Instruction: 13: 11010011111sssssPP-ttttt100ddddd | Rdd = xor (Rss, Rtt) - hi->instruction = HEX_INS_RDD___XOR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = xor (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc00000) == 0xa000000) { - // Instruction: 13: 1101101000isssssPPiiiiiiiiixxxxx | Rx |= and (Rs, #s10) - hi->instruction = HEX_INS_RX__OR_EQ__AND__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= and (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0xa400000) { - // Instruction: 13: 1101101001ixxxxxPPiiiiiiiiiuuuuu | Rx = or (Ru, and (Rx, #s10)) - hi->instruction = HEX_INS_RX___OR__RU__AND__RX___S10__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = or (R%d, and (Rx, %d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0xa800000) { - // Instruction: 13: 1101101010isssssPPiiiiiiiiixxxxx | Rx |= or (Rs, #s10) - hi->instruction = HEX_INS_RX__OR_EQ__OR__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= or (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5c00000) { - // Instruction: 13: 11010101110sssssPP-ttttt0--ddddd | Rd = max (Rs, Rt) - hi->instruction = HEX_INS_RD___MAX__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = max (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5c00080) { - // Instruction: 13: 11010101110sssssPP-ttttt1--ddddd | Rd = maxu (Rs, Rt) - hi->instruction = HEX_INS_RD___MAXU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = maxu (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00080) { - // Instruction: 13: 11010011110sssssPP-ttttt100ddddd | Rdd = max (Rss, Rtt) - hi->instruction = HEX_INS_RDD___MAX__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = max (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c000a0) { - // Instruction: 13: 11010011110sssssPP-ttttt101ddddd | Rdd = maxu (Rss, Rtt) - hi->instruction = HEX_INS_RDD___MAXU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = maxu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5a00000) { - // Instruction: 13: 11010101101sssssPP-ttttt0--ddddd | Rd = min (Rt, Rs) - hi->instruction = HEX_INS_RD___MIN__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = min (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5a00080) { - // Instruction: 13: 11010101101sssssPP-ttttt1--ddddd | Rd = minu (Rt, Rs) - hi->instruction = HEX_INS_RD___MINU__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = minu (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a000c0) { - // Instruction: 13: 11010011101sssssPP-ttttt110ddddd | Rdd = min (Rtt, Rss) - hi->instruction = HEX_INS_RDD___MIN__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = min (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a000e0) { - // Instruction: 13: 11010011101sssssPP-ttttt111ddddd | Rdd = minu (Rtt, Rss) - hi->instruction = HEX_INS_RDD___MINU__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = minu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e000e0) { - // Instruction: 13: 11010011111sssssPP-ttttt111ddddd | Rd = modwrap (Rs, Rt) - hi->instruction = HEX_INS_RD___MODWRAP__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = modwrap (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x32000e0) { - // Instruction: 13: 11010011001sssssPP-ttttt111ddddd | Rdd = sub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___SUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = sub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5800080) { - // Instruction: 13: 11010101100sssssPP-ttttt1--ddddd | Rd = sub (Rt, Rs) :sat:deprecated - hi->instruction = HEX_INS_RD___SUB__RT__RS___SAT_DEPRECATED; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_DEPRECATED; // :deprecated - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d, R%d) :sat:deprecated", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5200000) { - // Instruction: 13: 11010101001sssssPP-ttttt00-ddddd | Rd = sub (Rt.L, Rs.L) - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_L_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.L)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5200040) { - // Instruction: 13: 11010101001sssssPP-ttttt01-ddddd | Rd = sub (Rt.L, Rs.H) - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_H_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.H)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5200080) { - // Instruction: 13: 11010101001sssssPP-ttttt10-ddddd | Rd = sub (Rt.L, Rs.L) :sat - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_L___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.L) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x52000c0) { - // Instruction: 13: 11010101001sssssPP-ttttt11-ddddd | Rd = sub (Rt.L, Rs.H) :sat - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_H___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.H) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600000) { - // Instruction: 13: 11010101011sssssPP-ttttt000ddddd | Rd = sub (Rt.L, Rs.L) :<<16 - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_L_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.L) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600020) { - // Instruction: 13: 11010101011sssssPP-ttttt001ddddd | Rd = sub (Rt.L, Rs.H) :<<16 - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_H_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.H) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600040) { - // Instruction: 13: 11010101011sssssPP-ttttt010ddddd | Rd = sub (Rt.H, Rs.L) :<<16 - hi->instruction = HEX_INS_RD___SUB__RT_H__RS_L_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = sub (R%d.H, R%d.L) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600060) { - // Instruction: 13: 11010101011sssssPP-ttttt011ddddd | Rd = sub (Rt.H, Rs.H) :<<16 - hi->instruction = HEX_INS_RD___SUB__RT_H__RS_H_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = sub (R%d.H, R%d.H) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600080) { - // Instruction: 13: 11010101011sssssPP-ttttt100ddddd | Rd = sub (Rt.L, Rs.L) :sat:<<16 - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_L___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.L) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x56000a0) { - // Instruction: 13: 11010101011sssssPP-ttttt101ddddd | Rd = sub (Rt.L, Rs.H) :sat:<<16 - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_H___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.H) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x56000c0) { - // Instruction: 13: 11010101011sssssPP-ttttt110ddddd | Rd = sub (Rt.H, Rs.L) :sat:<<16 - hi->instruction = HEX_INS_RD___SUB__RT_H__RS_L___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.H, R%d.L) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x56000e0) { - // Instruction: 13: 11010101011sssssPP-ttttt111ddddd | Rd = sub (Rt.H, Rs.H) :sat:<<16 - hi->instruction = HEX_INS_RD___SUB__RT_H__RS_H___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.H, R%d.H) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000040) { - // Instruction: 13: 11010011000sssssPP-ttttt010ddddd | Rdd = vaddh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VADDH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaddh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000060) { - // Instruction: 13: 11010011000sssssPP-ttttt011ddddd | Rdd = vaddh (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VADDH__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vaddh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000080) { - // Instruction: 13: 11010011000sssssPP-ttttt100ddddd | Rdd = vadduh (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VADDUH__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vadduh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000000) { - // Instruction: 13: 11010011000sssssPP-ttttt000ddddd | Rdd = vaddub (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VADDUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaddub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000020) { - // Instruction: 13: 11010011000sssssPP-ttttt001ddddd | Rdd = vaddub (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VADDUB__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vaddub (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x30000a0) { - // Instruction: 13: 11010011000sssssPP-ttttt101ddddd | Rdd = vaddw (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VADDW__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaddw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x30000c0) { - // Instruction: 13: 11010011000sssssPP-ttttt110ddddd | Rdd = vaddw (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VADDW__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vaddw (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400040) { - // Instruction: 13: 11010011010sssssPP-ttttt010ddddd | Rdd = vavgh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavgh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400060) { - // Instruction: 13: 11010011010sssssPP-ttttt011ddddd | Rdd = vavgh (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGH__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavgh (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400080) { - // Instruction: 13: 11010011010sssssPP-ttttt100ddddd | Rdd = vavgh (Rss, Rtt) :crnd - hi->instruction = HEX_INS_RDD___VAVGH__RSS__RTT___CRND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CRND; // :crnd - sprintf(hi->mnem, "R%d:R%d = vavgh (R%d:R%d, R%d:R%d) :crnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x34000a0) { - // Instruction: 13: 11010011010sssssPP-ttttt101ddddd | Rdd = vavguh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGUH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavguh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x34000c0) { - // Instruction: 13: 11010011010sssssPP-ttttt11-ddddd | Rdd = vavguh (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGUH__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavguh (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3800000) { - // Instruction: 13: 11010011100sssssPP-ttttt000ddddd | Rdd = vnavgh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VNAVGH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vnavgh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3800020) { - // Instruction: 13: 11010011100sssssPP-ttttt001ddddd | Rdd = vnavgh (Rtt, Rss) :rnd:sat - hi->instruction = HEX_INS_RDD___VNAVGH__RTT__RSS___RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vnavgh (R%d:R%d, R%d:R%d) :rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3800040) { - // Instruction: 13: 11010011100sssssPP-ttttt010ddddd | Rdd = vnavgh (Rtt, Rss) :crnd:sat - hi->instruction = HEX_INS_RDD___VNAVGH__RTT__RSS___CRND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CRND; // :crnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vnavgh (R%d:R%d, R%d:R%d) :crnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400000) { - // Instruction: 13: 11010011010sssssPP-ttttt000ddddd | Rdd = vavgub (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavgub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400020) { - // Instruction: 13: 11010011010sssssPP-ttttt001ddddd | Rdd = vavgub (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGUB__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavgub (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600000) { - // Instruction: 13: 11010011011sssssPP-ttttt000ddddd | Rdd = vavgw (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGW__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavgw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600020) { - // Instruction: 13: 11010011011sssssPP-ttttt001ddddd | Rdd = vavgw (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGW__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavgw (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600040) { - // Instruction: 13: 11010011011sssssPP-ttttt010ddddd | Rdd = vavgw (Rss, Rtt) :crnd - hi->instruction = HEX_INS_RDD___VAVGW__RSS__RTT___CRND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CRND; // :crnd - sprintf(hi->mnem, "R%d:R%d = vavgw (R%d:R%d, R%d:R%d) :crnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600060) { - // Instruction: 13: 11010011011sssssPP-ttttt011ddddd | Rdd = vavguw (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGUW__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavguw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600080) { - // Instruction: 13: 11010011011sssssPP-ttttt100ddddd | Rdd = vavguw (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGUW__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavguw (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3800060) { - // Instruction: 13: 11010011100sssssPP-ttttt011ddddd | Rdd = vnavgw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VNAVGW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vnavgw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x3800080) { - // Instruction: 13: 11010011100sssssPP-ttttt10-ddddd | Rdd = vnavgw (Rtt, Rss) :rnd:sat - hi->instruction = HEX_INS_RDD___VNAVGW__RTT__RSS___RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vnavgw (R%d:R%d, R%d:R%d) :rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x38000c0) { - // Instruction: 13: 11010011100sssssPP-ttttt11-ddddd | Rdd = vnavgw (Rtt, Rss) :crnd:sat - hi->instruction = HEX_INS_RDD___VNAVGW__RTT__RSS___CRND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CRND; // :crnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vnavgw (R%d:R%d, R%d:R%d) :crnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00000) { - // Instruction: 13: 11010011110sssssPP-ttttt000ddddd | Rdd = vmaxub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c000c0) { - // Instruction: 13: 11010011110sssssPP-ttttt110ddddd | Rdd = vmaxb (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00020) { - // Instruction: 13: 11010011110sssssPP-ttttt001ddddd | Rdd = vmaxh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00040) { - // Instruction: 13: 11010011110sssssPP-ttttt010ddddd | Rdd = vmaxuh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXUH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxuh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a000a0) { - // Instruction: 13: 11010011101sssssPP-ttttt101ddddd | Rdd = vmaxuw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXUW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxuw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00060) { - // Instruction: 13: 11010011110sssssPP-ttttt011ddddd | Rdd = vmaxw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00000) { - // Instruction: 13: 11010011101sssssPP-ttttt000ddddd | Rdd = vminub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c000e0) { - // Instruction: 13: 11010011110sssssPP-ttttt111ddddd | Rdd = vminb (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00020) { - // Instruction: 13: 11010011101sssssPP-ttttt001ddddd | Rdd = vminh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00040) { - // Instruction: 13: 11010011101sssssPP-ttttt010ddddd | Rdd = vminuh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINUH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminuh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00060) { - // Instruction: 13: 11010011101sssssPP-ttttt011ddddd | Rdd = vminw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00080) { - // Instruction: 13: 11010011101sssssPP-ttttt100ddddd | Rdd = vminuw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINUW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminuw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200040) { - // Instruction: 13: 11010011001sssssPP-ttttt010ddddd | Rdd = vsubh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VSUBH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsubh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200060) { - // Instruction: 13: 11010011001sssssPP-ttttt011ddddd | Rdd = vsubh (Rtt, Rss) :sat - hi->instruction = HEX_INS_RDD___VSUBH__RTT__RSS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vsubh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200080) { - // Instruction: 13: 11010011001sssssPP-ttttt100ddddd | Rdd = vsubuh (Rtt, Rss) :sat - hi->instruction = HEX_INS_RDD___VSUBUH__RTT__RSS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vsubuh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200000) { - // Instruction: 13: 11010011001sssssPP-ttttt000ddddd | Rdd = vsubub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VSUBUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsubub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200020) { - // Instruction: 13: 11010011001sssssPP-ttttt001ddddd | Rdd = vsubub (Rtt, Rss) :sat - hi->instruction = HEX_INS_RDD___VSUBUB__RTT__RSS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vsubub (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x32000a0) { - // Instruction: 13: 11010011001sssssPP-ttttt101ddddd | Rdd = vsubw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VSUBW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsubw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x32000c0) { - // Instruction: 13: 11010011001sssssPP-ttttt110ddddd | Rdd = vsubw (Rtt, Rss) :sat - hi->instruction = HEX_INS_RDD___VSUBW__RTT__RSS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vsubw (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x0) { - // Instruction: 13: 11010000---sssssPP-ttttt---ddddd | Rd = parity (Rss, Rtt) - hi->instruction = HEX_INS_RD___PARITY__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = parity (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5e00000) { - // Instruction: 13: 11010101111sssssPP-ttttt---ddddd | Rd = parity (Rs, Rt) - hi->instruction = HEX_INS_RD___PARITY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = parity (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf200000) == 0x4200000) { - // Instruction: 13: 11010100--1sssssPP-ttttt---ddddd | Rdd = bitsplit (Rs, Rt) - hi->instruction = HEX_INS_RDD___BITSPLIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = bitsplit (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01c18) == 0xc800010) { - // Instruction: 13: 11011100100sssssPP-000iiiii10-dd | Pd = dfclass (Rss, #u5) - hi->instruction = HEX_INS_PD___DFCLASS__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x3e0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = dfclass (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2e00000) { - // Instruction: 13: 11010010111sssssPP-ttttt000---dd | Pd = cmp.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_EQ__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2e00020) { - // Instruction: 13: 11010010111sssssPP-ttttt001---dd | Pd = cmp.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_GT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2e00040) { - // Instruction: 13: 11010010111sssssPP-ttttt010---dd | Pd = cmp.ge (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_GE__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.ge (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2e00060) { - // Instruction: 13: 11010010111sssssPP-ttttt011---dd | Pd = cmp.uo (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_UO__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.uo (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc00000) == 0x6000000) { - // Instruction: 13: 1101011000i-----PPiiiiiiiiiddddd | Rd = sfmake (#u10) :pos - hi->instruction = HEX_INS_RD___SFMAKE___U10___POS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_POS; // :pos - sprintf(hi->mnem, "R%d = sfmake (0x%x) :pos", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x6400000) { - // Instruction: 13: 1101011001i-----PPiiiiiiiiiddddd | Rd = sfmake (#u10) :neg - hi->instruction = HEX_INS_RD___SFMAKE___U10___NEG; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_NEG; // :neg - sprintf(hi->mnem, "R%d = sfmake (0x%x) :neg", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x9000000) { - // Instruction: 13: 1101100100i-----PPiiiiiiiiiddddd | Rdd = dfmake (#u10) :pos - hi->instruction = HEX_INS_RDD___DFMAKE___U10___POS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_POS; // :pos - sprintf(hi->mnem, "R%d:R%d = dfmake (0x%x) :pos", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x9400000) { - // Instruction: 13: 1101100101i-----PPiiiiiiiiiddddd | Rdd = dfmake (#u10) :neg - hi->instruction = HEX_INS_RDD___DFMAKE___U10___NEG; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_NEG; // :neg - sprintf(hi->mnem, "R%d:R%d = dfmake (0x%x) :neg", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0x7000000) { - // Instruction: 13: 110101110iisssssPPitttttiiiddddd | Rd = add (#u6, mpyi (Rs, Rt)) - hi->instruction = HEX_INS_RD___ADD___U6__MPYI__RS__RT__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (0x%x, mpyi (R%d, R%d))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x8000000) { - // Instruction: 13: 11011000IiisssssPPidddddiiiIIIII | Rd = add (#u6, mpyi (Rs, #U6)) - hi->instruction = HEX_INS_RD___ADD___U6__MPYI__RS___U6__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x800000) >> 18) | ((hi_u32 & 0x1f) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (0x%x, mpyi (R%d, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0xf000000) { - // Instruction: 13: 110111110iisssssPPidddddiiiuuuuu | Rd = add (Ru, mpyi (#u6:2, Rs)) - hi->instruction = HEX_INS_RD___ADD__RU__MPYI___U6_2__RS__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d, mpyi (0x%x, R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0xf800000) { - // Instruction: 13: 110111111iisssssPPidddddiiiuuuuu | Rd = add (Ru, mpyi (Rs, #u6)) - hi->instruction = HEX_INS_RD___ADD__RU__MPYI__RS___U6__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d, mpyi (R%d, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2002080) { - // Instruction: 13: 110100100--sssssPP1ttttt100---dd | Pd = boundscheck (Rss, Rtt) :raw:lo - hi->instruction = HEX_INS_PD___BOUNDSCHECK__RSS__RTT___RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "P%d = boundscheck (R%d:R%d, R%d:R%d) :raw:lo", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x20020a0) { - // Instruction: 13: 110100100--sssssPP1ttttt101---dd | Pd = boundscheck (Rss, Rtt) :raw:hi - hi->instruction = HEX_INS_PD___BOUNDSCHECK__RSS__RTT___RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "P%d = boundscheck (R%d:R%d, R%d:R%d) :raw:hi", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf600018) == 0xd000000) { - // Instruction: 13: 11011101-00sssssPP-iiiiiiii00-dd | Pd = cmpb.eq (Rs, #u8) - hi->instruction = HEX_INS_PD___CMPB_EQ__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmpb.eq (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf600018) == 0xd200000) { - // Instruction: 13: 11011101-01sssssPP-iiiiiiii00-dd | Pd = cmpb.gt (Rs, #s8) - hi->instruction = HEX_INS_PD___CMPB_GT__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmpb.gt (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf601018) == 0xd400000) { - // Instruction: 13: 11011101-10sssssPP-0iiiiiii00-dd | Pd = cmpb.gtu (Rs, #u7) - hi->instruction = HEX_INS_PD___CMPB_GTU__RS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmpb.gtu (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf600018) == 0xd000008) { - // Instruction: 13: 11011101-00sssssPP-iiiiiiii01-dd | Pd = cmph.eq (Rs, #s8) - hi->instruction = HEX_INS_PD___CMPH_EQ__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmph.eq (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf600018) == 0xd200008) { - // Instruction: 13: 11011101-01sssssPP-iiiiiiii01-dd | Pd = cmph.gt (Rs, #s8) - hi->instruction = HEX_INS_PD___CMPH_GT__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmph.gt (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf601018) == 0xd400008) { - // Instruction: 13: 11011101-10sssssPP-0iiiiiii01-dd | Pd = cmph.gtu (Rs, #u7) - hi->instruction = HEX_INS_PD___CMPH_GTU__RS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmph.gtu (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2800000) { - // Instruction: 13: 11010010100sssssPP-ttttt000---dd | Pd = cmp.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_EQ__RSS__RTT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2800040) { - // Instruction: 13: 11010010100sssssPP-ttttt010---dd | Pd = cmp.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_GT__RSS__RTT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2800080) { - // Instruction: 13: 11010010100sssssPP-ttttt100---dd | Pd = cmp.gtu (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_GTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gtu (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2002060) { - // Instruction: 13: 110100100--sssssPP1ttttt011---dd | Pd = tlbmatch (Rss, Rt) - hi->instruction = HEX_INS_PD___TLBMATCH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = tlbmatch (R%d:R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000060) { - // Instruction: 13: 110100100--sssssPP0ttttt011---dd | Pd = vcmph.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPH_EQ__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000080) { - // Instruction: 13: 110100100--sssssPP0ttttt100---dd | Pd = vcmph.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPH_GT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x20000a0) { - // Instruction: 13: 110100100--sssssPP0ttttt101---dd | Pd = vcmph.gtu (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPH_GTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.gtu (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc000008) { - // Instruction: 13: 11011100000sssssPP-iiiiiiii01-dd | Pd = vcmph.eq (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPH_EQ__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.eq (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc200008) { - // Instruction: 13: 11011100001sssssPP-iiiiiiii01-dd | Pd = vcmph.gt (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPH_GT__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.gt (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01018) == 0xc400008) { - // Instruction: 13: 11011100010sssssPP-0iiiiiii01-dd | Pd = vcmph.gtu (Rss, #u7) - hi->instruction = HEX_INS_PD___VCMPH_GTU__RSS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.gtu (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2002000) { - // Instruction: 13: 110100100--sssssPP1ttttt000---dd | Pd = any8 (vcmpb.eq (Rss, Rtt)) - hi->instruction = HEX_INS_PD___ANY8__VCMPB_EQ__RSS__RTT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = any8 (vcmpb.eq (R%d:R%d, R%d:R%d))", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x20000c0) { - // Instruction: 13: 110100100--sssssPP0ttttt110---dd | Pd = vcmpb.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPB_EQ__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x20000e0) { - // Instruction: 13: 110100100--sssssPP0ttttt111---dd | Pd = vcmpb.gtu (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPB_GTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.gtu (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2002040) { - // Instruction: 13: 110100100--sssssPP1ttttt010---dd | Pd = vcmpb.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPB_GT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc000000) { - // Instruction: 13: 11011100000sssssPP-iiiiiiii00-dd | Pd = vcmpb.eq (Rss, #u8) - hi->instruction = HEX_INS_PD___VCMPB_EQ__RSS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.eq (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc200000) { - // Instruction: 13: 11011100001sssssPP-iiiiiiii00-dd | Pd = vcmpb.gt (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPB_GT__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.gt (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01018) == 0xc400000) { - // Instruction: 13: 11011100010sssssPP-0iiiiiii00-dd | Pd = vcmpb.gtu (Rss, #u7) - hi->instruction = HEX_INS_PD___VCMPB_GTU__RSS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.gtu (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000000) { - // Instruction: 13: 110100100--sssssPP0ttttt000---dd | Pd = vcmpw.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPW_EQ__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000020) { - // Instruction: 13: 110100100--sssssPP0ttttt001---dd | Pd = vcmpw.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPW_GT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000040) { - // Instruction: 13: 110100100--sssssPP0ttttt010---dd | Pd = vcmpw.gtu (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPW_GTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.gtu (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc000010) { - // Instruction: 13: 11011100000sssssPP-iiiiiiii10-dd | Pd = vcmpw.eq (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPW_EQ__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.eq (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc200010) { - // Instruction: 13: 11011100001sssssPP-iiiiiiii10-dd | Pd = vcmpw.gt (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPW_GT__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.gt (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01018) == 0xc400010) { - // Instruction: 13: 11011100010sssssPP-0iiiiiii10-dd | Pd = vcmpw.gtu (Rss, #u7) - hi->instruction = HEX_INS_PD___VCMPW_GTU__RSS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.gtu (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x1000000) { - // Instruction: 13: 11010001---sssssPP-ttttt-uuddddd | Rdd = vmux (Pu, Rss, Rtt) - hi->instruction = HEX_INS_RDD___VMUX__PU__RSS__RTT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmux (P%d, R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000004) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii0i10- | Rx = add (#u8, asl (Rx, #U5)) - hi->instruction = HEX_INS_RX___ADD___U8__ASL__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = add (0x%x, asl (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000006) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii0i11- | Rx = sub (#u8, asl (Rx, #U5)) - hi->instruction = HEX_INS_RX___SUB___U8__ASL__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = sub (0x%x, asl (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000014) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii1i10- | Rx = add (#u8, lsr (Rx, #U5)) - hi->instruction = HEX_INS_RX___ADD___U8__LSR__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = add (0x%x, lsr (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000016) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii1i11- | Rx = sub (#u8, lsr (Rx, #U5)) - hi->instruction = HEX_INS_RX___SUB___U8__LSR__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = sub (0x%x, lsr (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000000) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii0i00- | Rx = and (#u8, asl (Rx, #U5)) - hi->instruction = HEX_INS_RX___AND___U8__ASL__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = and (0x%x, asl (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000002) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii0i01- | Rx = or (#u8, asl (Rx, #U5)) - hi->instruction = HEX_INS_RX___OR___U8__ASL__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = or (0x%x, asl (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000010) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii1i00- | Rx = and (#u8, lsr (Rx, #U5)) - hi->instruction = HEX_INS_RX___AND___U8__LSR__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = and (0x%x, lsr (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000012) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii1i01- | Rx = or (#u8, lsr (Rx, #U5)) - hi->instruction = HEX_INS_RX___OR___U8__LSR__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = or (0x%x, lsr (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - break; - } - case 0xe: { - if ((hi_u32 & 0xf802000) == 0x2000000) { - // Instruction: 14: 111000100--sssssPP0iiiiiiiixxxxx | Rx += add (Rs, #s8) - hi->instruction = HEX_INS_RX__PLUS_EQ__ADD__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d += add (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x2800000) { - // Instruction: 14: 111000101--sssssPP0iiiiiiiixxxxx | Rx -= add (Rs, #s8) - hi->instruction = HEX_INS_RX__MINUS_EQ__ADD__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d -= add (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32) hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf000020) { - // Instruction: 14: 11101111000sssssPP0ttttt001xxxxx | Rx += add (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__ADD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += add (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf800020) { - // Instruction: 14: 11101111100sssssPP0ttttt001xxxxx | Rx -= add (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__ADD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= add (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf200000) { - // Instruction: 14: 11101111001sssssPP0ttttt000xxxxx | Rx |= and (Rs, ~Rt) - hi->instruction = HEX_INS_RX__OR_EQ__AND__RS___RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= and (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf200020) { - // Instruction: 14: 11101111001sssssPP0ttttt001xxxxx | Rx &= and (Rs, ~Rt) - hi->instruction = HEX_INS_RX__AND_EQ__AND__RS___RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= and (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf200040) { - // Instruction: 14: 11101111001sssssPP0ttttt010xxxxx | Rx ^= and (Rs, ~Rt) - hi->instruction = HEX_INS_RX____AND__RS___RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= and (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf400000) { - // Instruction: 14: 11101111010sssssPP0ttttt000xxxxx | Rx &= and (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__AND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= and (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf400020) { - // Instruction: 14: 11101111010sssssPP0ttttt001xxxxx | Rx &= or (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__OR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= or (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf400040) { - // Instruction: 14: 11101111010sssssPP0ttttt010xxxxx | Rx &= xor (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__XOR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= xor (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf400060) { - // Instruction: 14: 11101111010sssssPP0ttttt011xxxxx | Rx |= and (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__AND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= and (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf800060) { - // Instruction: 14: 11101111100sssssPP0ttttt011xxxxx | Rx ^= xor (Rs, Rt) - hi->instruction = HEX_INS_RX____XOR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= xor (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xfc00000) { - // Instruction: 14: 11101111110sssssPP0ttttt000xxxxx | Rx |= or (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__OR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= or (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xfc00020) { - // Instruction: 14: 11101111110sssssPP0ttttt001xxxxx | Rx |= xor (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__XOR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= xor (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xfc00040) { - // Instruction: 14: 11101111110sssssPP0ttttt010xxxxx | Rx ^= and (Rs, Rt) - hi->instruction = HEX_INS_RX____AND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= and (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xfc00060) { - // Instruction: 14: 11101111110sssssPP0ttttt011xxxxx | Rx ^= or (Rs, Rt) - hi->instruction = HEX_INS_RX____OR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= or (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf000060) { - // Instruction: 14: 11101111000sssssPP0ttttt011xxxxx | Rx += sub (Rt, Rs) - hi->instruction = HEX_INS_RX__PLUS_EQ__SUB__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += sub (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8a00000) { - // Instruction: 14: 11101000101sssssPP0ttttt000ddddd | Rdd = vabsdiffub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VABSDIFFUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsdiffub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8e00000) { - // Instruction: 14: 11101000111sssssPP0ttttt000ddddd | Rdd = vabsdiffb (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VABSDIFFB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsdiffb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8600000) { - // Instruction: 14: 11101000011sssssPP0ttttt000ddddd | Rdd = vabsdiffh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VABSDIFFH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsdiffh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8200000) { - // Instruction: 14: 11101000001sssssPP0ttttt000ddddd | Rdd = vabsdiffw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VABSDIFFW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsdiffw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xaa00000) { - // Instruction: 14: 11101010101sssssPP0ttttt0eexxxxx | Rxx, Pe = vacsh (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PE___VACSH__RSS__RTT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d, P%d = vacsh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8400020) { - // Instruction: 14: 11101000010sssssPP0ttttt001ddddd | Rdd = vraddub (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRADDUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vraddub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa400020) { - // Instruction: 14: 11101010010sssssPP0ttttt001xxxxx | Rxx += vraddub (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRADDUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vraddub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf802060) == 0x9000020) { - // Instruction: 14: 111010010--sssssPP0ttttt-01ddddd | Rd = vradduh (Rss, Rtt) - hi->instruction = HEX_INS_RD___VRADDUH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vradduh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfa020e0) == 0x92000e0) { - // Instruction: 14: 111010010-1sssssPP0ttttt111ddddd | Rd = vraddh (Rss, Rtt) - hi->instruction = HEX_INS_RD___VRADDH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vraddh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xae00000) { - // Instruction: 14: 11101010111sssssPP0ttttt0eeddddd | Rdd, Pe = vminub (Rtt, Rss) - hi->instruction = HEX_INS_RDD__PE___VMINUB__RTT__RSS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d, P%d = vminub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8400040) { - // Instruction: 14: 11101000010sssssPP0ttttt010ddddd | Rdd = vrsadub (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRSADUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrsadub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa400040) { - // Instruction: 14: 11101010010sssssPP0ttttt010xxxxx | Rxx += vrsadub (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRSADUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrsadub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x50000c0) { - // Instruction: 14: 11100101N00sssssPP0ttttt110ddddd | Rdd = cmpy (Rs, Rt) [:<instruction = HEX_INS_RDD___CMPY__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = cmpy (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x54000c0) { - // Instruction: 14: 11100101N10sssssPP0ttttt110ddddd | Rdd = cmpy (Rs, Rt *) [:<instruction = HEX_INS_RDD___CMPY__RS__RT________N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = cmpy (R%d, R%d *) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x70000c0) { - // Instruction: 14: 11100111N00sssssPP0ttttt110xxxxx | Rxx += cmpy (Rs, Rt) [:<instruction = HEX_INS_RXX__PLUS_EQ__CMPY__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += cmpy (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x70000e0) { - // Instruction: 14: 11100111N00sssssPP0ttttt111xxxxx | Rxx -= cmpy (Rs, Rt) [:<instruction = HEX_INS_RXX__MINUS_EQ__CMPY__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d -= cmpy (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x74000c0) { - // Instruction: 14: 11100111N10sssssPP0ttttt110xxxxx | Rxx += cmpy (Rs, Rt *) [:<instruction = HEX_INS_RXX__PLUS_EQ__CMPY__RS__RT________N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += cmpy (R%d, R%d *) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x74000e0) { - // Instruction: 14: 11100111N10sssssPP0ttttt111xxxxx | Rxx -= cmpy (Rs, Rt *) [:<instruction = HEX_INS_RXX__MINUS_EQ__CMPY__RS__RT________N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d -= cmpy (R%d, R%d *) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5000020) { - // Instruction: 14: 11100101000sssssPP0ttttt001ddddd | Rdd = cmpyi (Rs, Rt) - hi->instruction = HEX_INS_RDD___CMPYI__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = cmpyi (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5000040) { - // Instruction: 14: 11100101000sssssPP0ttttt010ddddd | Rdd = cmpyr (Rs, Rt) - hi->instruction = HEX_INS_RDD___CMPYR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = cmpyr (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7000020) { - // Instruction: 14: 11100111000sssssPP0ttttt001xxxxx | Rxx += cmpyi (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__CMPYI__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += cmpyi (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7000040) { - // Instruction: 14: 11100111000sssssPP0ttttt010xxxxx | Rxx += cmpyr (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__CMPYR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += cmpyr (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xd2000c0) { - // Instruction: 14: 11101101N01sssssPP0ttttt110ddddd | Rd = cmpy (Rs, Rt) [:<instruction = HEX_INS_RD___CMPY__RS__RT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpy (R%d, R%d) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xd6000c0) { - // Instruction: 14: 11101101N11sssssPP0ttttt110ddddd | Rd = cmpy (Rs, Rt *) [:<instruction = HEX_INS_RD___CMPY__RS__RT________N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpy (R%d, R%d *) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x82000c0) { - // Instruction: 14: 11101000N01sssssPP0ttttt110ddddd | Rdd = vcmpyr (Rss, Rtt) [:<instruction = HEX_INS_RDD___VCMPYR__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vcmpyr (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x84000c0) { - // Instruction: 14: 11101000N10sssssPP0ttttt110ddddd | Rdd = vcmpyi (Rss, Rtt) [:<instruction = HEX_INS_RDD___VCMPYI__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vcmpyi (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa200080) { - // Instruction: 14: 11101010001sssssPP0ttttt100xxxxx | Rxx += vcmpyr (Rss, Rtt) :sat - hi->instruction = HEX_INS_RXX__PLUS_EQ__VCMPYR__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vcmpyr (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa400080) { - // Instruction: 14: 11101010010sssssPP0ttttt100xxxxx | Rxx += vcmpyi (Rss, Rtt) :sat - hi->instruction = HEX_INS_RXX__PLUS_EQ__VCMPYI__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vcmpyi (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8000000) { - // Instruction: 14: 11101000000sssssPP0ttttt000ddddd | Rdd = vrcmpyi (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRCMPYI__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcmpyi (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8000020) { - // Instruction: 14: 11101000000sssssPP0ttttt001ddddd | Rdd = vrcmpyr (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRCMPYR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcmpyr (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8400000) { - // Instruction: 14: 11101000010sssssPP0ttttt000ddddd | Rdd = vrcmpyi (Rss, Rtt *) - hi->instruction = HEX_INS_RDD___VRCMPYI__RSS__RTT___; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcmpyi (R%d:R%d, R%d:R%d *)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8600020) { - // Instruction: 14: 11101000011sssssPP0ttttt001ddddd | Rdd = vrcmpyr (Rss, Rtt *) - hi->instruction = HEX_INS_RDD___VRCMPYR__RSS__RTT___; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcmpyr (R%d:R%d, R%d:R%d *)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa000000) { - // Instruction: 14: 11101010000sssssPP0ttttt000xxxxx | Rxx += vrcmpyi (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYI__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcmpyi (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa000020) { - // Instruction: 14: 11101010000sssssPP0ttttt001xxxxx | Rxx += vrcmpyr (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcmpyr (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa400000) { - // Instruction: 14: 11101010010sssssPP0ttttt000xxxxx | Rxx += vrcmpyi (Rss, Rtt *) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYI__RSS__RTT___; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcmpyi (R%d:R%d, R%d:R%d *)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa600020) { - // Instruction: 14: 11101010011sssssPP0ttttt001xxxxx | Rxx += vrcmpyr (Rss, Rtt *) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYR__RSS__RTT___; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcmpyr (R%d:R%d, R%d:R%d *)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8a00080) { - // Instruction: 14: 11101000101sssssPP0ttttt100ddddd | Rdd = vrcmpys (Rss, Rtt) :<<1:sat:raw:hi - hi->instruction = HEX_INS_RDD___VRCMPYS__RSS__RTT_____1_SAT_RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vrcmpys (R%d:R%d, R%d:R%d) :<<1:sat:raw:hi", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8e00080) { - // Instruction: 14: 11101000111sssssPP0ttttt100ddddd | Rdd = vrcmpys (Rss, Rtt) :<<1:sat:raw:lo - hi->instruction = HEX_INS_RDD___VRCMPYS__RSS__RTT_____1_SAT_RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vrcmpys (R%d:R%d, R%d:R%d) :<<1:sat:raw:lo", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xaa00080) { - // Instruction: 14: 11101010101sssssPP0ttttt100xxxxx | Rxx += vrcmpys (Rss, Rtt) :<<1:sat:raw:hi - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYS__RSS__RTT_____1_SAT_RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vrcmpys (R%d:R%d, R%d:R%d) :<<1:sat:raw:hi", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xae00080) { - // Instruction: 14: 11101010111sssssPP0ttttt100xxxxx | Rxx += vrcmpys (Rss, Rtt) :<<1:sat:raw:lo - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYS__RSS__RTT_____1_SAT_RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vrcmpys (R%d:R%d, R%d:R%d) :<<1:sat:raw:lo", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfa020e0) == 0x9a000c0) { - // Instruction: 14: 111010011-1sssssPP0ttttt110ddddd | Rd = vrcmpys (Rss, Rtt) :<<1:rnd:sat:raw:hi - hi->instruction = HEX_INS_RD___VRCMPYS__RSS__RTT_____1_RND_SAT_RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vrcmpys (R%d:R%d, R%d:R%d) :<<1:rnd:sat:raw:hi", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfa020e0) == 0x9a000e0) { - // Instruction: 14: 111010011-1sssssPP0ttttt111ddddd | Rd = vrcmpys (Rss, Rtt) :<<1:rnd:sat:raw:lo - hi->instruction = HEX_INS_RD___VRCMPYS__RSS__RTT_____1_RND_SAT_RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vrcmpys (R%d:R%d, R%d:R%d) :<<1:rnd:sat:raw:lo", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb000000) { - // Instruction: 14: 11101011000sssssPP0ttttt000ddddd | Rd = sfadd (Rs, Rt) - hi->instruction = HEX_INS_RD___SFADD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfadd (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xbc00000) { - // Instruction: 14: 11101011110sssssPP0ttttt000ddddd | Rd = sffixupn (Rs, Rt) - hi->instruction = HEX_INS_RD___SFFIXUPN__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sffixupn (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xbc00020) { - // Instruction: 14: 11101011110sssssPP0ttttt001ddddd | Rd = sffixupd (Rs, Rt) - hi->instruction = HEX_INS_RD___SFFIXUPD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sffixupd (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf000080) { - // Instruction: 14: 11101111000sssssPP0ttttt100xxxxx | Rx += sfmpy (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__SFMPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += sfmpy (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf0000a0) { - // Instruction: 14: 11101111000sssssPP0ttttt101xxxxx | Rx -= sfmpy (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__SFMPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= sfmpy (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xf600080) { - // Instruction: 14: 11101111011sssssPP0ttttt1uuxxxxx | Rx += sfmpy (Rs, Rt, Pu) :scale - hi->instruction = HEX_INS_RX__PLUS_EQ__SFMPY__RS__RT__PU___SCALE; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32) & 0x60) >> 5); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SCALE; // :scale - sprintf(hi->mnem, "R%d += sfmpy (R%d, R%d, P%d) :scale", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf0000c0) { - // Instruction: 14: 11101111000sssssPP0ttttt110xxxxx | Rx += sfmpy (Rs, Rt) :lib - hi->instruction = HEX_INS_RX__PLUS_EQ__SFMPY__RS__RT___LIB; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += sfmpy (R%d, R%d) :lib", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf0000e0) { - // Instruction: 14: 11101111000sssssPP0ttttt111xxxxx | Rx -= sfmpy (Rs, Rt) :lib - hi->instruction = HEX_INS_RX__MINUS_EQ__SFMPY__RS__RT___LIB; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= sfmpy (R%d, R%d) :lib", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb800000) { - // Instruction: 14: 11101011100sssssPP0ttttt000ddddd | Rd = sfmax (Rs, Rt) - hi->instruction = HEX_INS_RD___SFMAX__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfmax (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb800020) { - // Instruction: 14: 11101011100sssssPP0ttttt001ddddd | Rd = sfmin (Rs, Rt) - hi->instruction = HEX_INS_RD___SFMIN__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfmin (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb400000) { - // Instruction: 14: 11101011010sssssPP0ttttt000ddddd | Rd = sfmpy (Rs, Rt) - hi->instruction = HEX_INS_RD___SFMPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfmpy (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xbe00080) { - // Instruction: 14: 11101011111sssssPP0ttttt1eeddddd | Rd, Pe = sfrecipa (Rs, Rt) - hi->instruction = HEX_INS_RD__PE___SFRECIPA__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d, P%d = sfrecipa (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb000020) { - // Instruction: 14: 11101011000sssssPP0ttttt001ddddd | Rd = sfsub (Rs, Rt) - hi->instruction = HEX_INS_RD___SFSUB__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfsub (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3000000) { - // Instruction: 14: 11100011000sssssPP-yyyyy---uuuuu | Ry = add (Ru, mpyi (Ry, Rs)) - hi->instruction = HEX_INS_RY___ADD__RU__MPYI__RY__RS__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f00) >> 8); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d, mpyi (Ry, R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf802000) == 0x0) { - // Instruction: 14: 111000000--sssssPP0iiiiiiiiddddd | Rd = + mpyi (Rs, #u8) - hi->instruction = HEX_INS_RD__EQ_PLUS__MPYI__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = + mpyi (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x800000) { - // Instruction: 14: 111000001--sssssPP0iiiiiiiiddddd | Rd = - mpyi (Rs, #u8) - hi->instruction = HEX_INS_RD__EQ_MINUS__MPYI__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = - mpyi (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x1000000) { - // Instruction: 14: 111000010--sssssPP0iiiiiiiixxxxx | Rx += mpyi (Rs, #u8) - hi->instruction = HEX_INS_RX__PLUS_EQ__MPYI__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyi (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x1800000) { - // Instruction: 14: 111000011--sssssPP0iiiiiiiixxxxx | Rx -= mpyi (Rs, #u8) - hi->instruction = HEX_INS_RX__MINUS_EQ__MPYI__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32) & 0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyi (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xd000000) { - // Instruction: 14: 11101101000sssssPP0ttttt000ddddd | Rd = mpyi (Rs, Rt) - hi->instruction = HEX_INS_RD___MPYI__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyi (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf000000) { - // Instruction: 14: 11101111000sssssPP0ttttt000xxxxx | Rx += mpyi (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__MPYI__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyi (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x80000a0) { - // Instruction: 14: 11101000N00sssssPP0ttttt101ddddd | Rdd = vmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWEH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyweh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x80000e0) { - // Instruction: 14: 11101000N00sssssPP0ttttt111ddddd | Rdd = vmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWOH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpywoh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x82000a0) { - // Instruction: 14: 11101000N01sssssPP0ttttt101ddddd | Rdd = vmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWEH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyweh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x82000e0) { - // Instruction: 14: 11101000N01sssssPP0ttttt111ddddd | Rdd = vmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWOH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpywoh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa0000a0) { - // Instruction: 14: 11101010N00sssssPP0ttttt101xxxxx | Rxx += vmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWEH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyweh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa0000e0) { - // Instruction: 14: 11101010N00sssssPP0ttttt111xxxxx | Rxx += vmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWOH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpywoh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa2000a0) { - // Instruction: 14: 11101010N01sssssPP0ttttt101xxxxx | Rxx += vmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWEH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyweh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa2000e0) { - // Instruction: 14: 11101010N01sssssPP0ttttt111xxxxx | Rxx += vmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWOH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpywoh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x84000a0) { - // Instruction: 14: 11101000N10sssssPP0ttttt101ddddd | Rdd = vmpyweuh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWEUH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyweuh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x84000e0) { - // Instruction: 14: 11101000N10sssssPP0ttttt111ddddd | Rdd = vmpywouh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWOUH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpywouh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x86000a0) { - // Instruction: 14: 11101000N11sssssPP0ttttt101ddddd | Rdd = vmpyweuh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWEUH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyweuh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x86000e0) { - // Instruction: 14: 11101000N11sssssPP0ttttt111ddddd | Rdd = vmpywouh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWOUH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpywouh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa4000a0) { - // Instruction: 14: 11101010N10sssssPP0ttttt101xxxxx | Rxx += vmpyweuh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWEUH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyweuh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa4000e0) { - // Instruction: 14: 11101010N10sssssPP0ttttt111xxxxx | Rxx += vmpywouh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWOUH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpywouh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa6000a0) { - // Instruction: 14: 11101010N11sssssPP0ttttt101xxxxx | Rxx += vmpyweuh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWEUH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyweuh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa6000e0) { - // Instruction: 14: 11101010N11sssssPP0ttttt111xxxxx | Rxx += vmpywouh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWOUH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpywouh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4000000) { - // Instruction: 14: 11100100N00sssssPP-ttttt-00ddddd | Rdd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RDD___MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4000020) { - // Instruction: 14: 11100100N00sssssPP-ttttt-01ddddd | Rdd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RDD___MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4000040) { - // Instruction: 14: 11100100N00sssssPP-ttttt-10ddddd | Rdd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RDD___MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4000060) { - // Instruction: 14: 11100100N00sssssPP-ttttt-11ddddd | Rdd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RDD___MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4200000) { - // Instruction: 14: 11100100N01sssssPP-ttttt-00ddddd | Rdd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RDD___MPY__RS_L__RT_L______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.L, R%d.L) %s:rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4200020) { - // Instruction: 14: 11100100N01sssssPP-ttttt-01ddddd | Rdd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RDD___MPY__RS_L__RT_H______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.L, R%d.H) %s:rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4200040) { - // Instruction: 14: 11100100N01sssssPP-ttttt-10ddddd | Rdd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RDD___MPY__RS_H__RT_L______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.H, R%d.L) %s:rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4200060) { - // Instruction: 14: 11100100N01sssssPP-ttttt-11ddddd | Rdd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RDD___MPY__RS_H__RT_H______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.H, R%d.H) %s:rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6000000) { - // Instruction: 14: 11100110N00sssssPP-ttttt000xxxxx | Rxx += mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6000020) { - // Instruction: 14: 11100110N00sssssPP-ttttt001xxxxx | Rxx += mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6000040) { - // Instruction: 14: 11100110N00sssssPP-ttttt010xxxxx | Rxx += mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6000060) { - // Instruction: 14: 11100110N00sssssPP-ttttt011xxxxx | Rxx += mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6200000) { - // Instruction: 14: 11100110N01sssssPP-ttttt000xxxxx | Rxx -= mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6200020) { - // Instruction: 14: 11100110N01sssssPP-ttttt001xxxxx | Rxx -= mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6200040) { - // Instruction: 14: 11100110N01sssssPP-ttttt010xxxxx | Rxx -= mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6200060) { - // Instruction: 14: 11100110N01sssssPP-ttttt011xxxxx | Rxx -= mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000000) { - // Instruction: 14: 11101100N00sssssPP-ttttt000ddddd | Rd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000020) { - // Instruction: 14: 11101100N00sssssPP-ttttt001ddddd | Rd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000040) { - // Instruction: 14: 11101100N00sssssPP-ttttt010ddddd | Rd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000060) { - // Instruction: 14: 11101100N00sssssPP-ttttt011ddddd | Rd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000080) { - // Instruction: 14: 11101100N00sssssPP-ttttt100ddddd | Rd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc0000a0) { - // Instruction: 14: 11101100N00sssssPP-ttttt101ddddd | Rd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc0000c0) { - // Instruction: 14: 11101100N00sssssPP-ttttt110ddddd | Rd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc0000e0) { - // Instruction: 14: 11101100N00sssssPP-ttttt111ddddd | Rd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200000) { - // Instruction: 14: 11101100N01sssssPP-ttttt000ddddd | Rd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_L______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.L) %s:rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200020) { - // Instruction: 14: 11101100N01sssssPP-ttttt001ddddd | Rd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_H______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.H) %s:rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200040) { - // Instruction: 14: 11101100N01sssssPP-ttttt010ddddd | Rd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_L______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.L) %s:rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200060) { - // Instruction: 14: 11101100N01sssssPP-ttttt011ddddd | Rd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_H______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.H) %s:rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200080) { - // Instruction: 14: 11101100N01sssssPP-ttttt100ddddd | Rd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_L______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.L) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc2000a0) { - // Instruction: 14: 11101100N01sssssPP-ttttt101ddddd | Rd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_H______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.H) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc2000c0) { - // Instruction: 14: 11101100N01sssssPP-ttttt110ddddd | Rd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_L______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.L) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc2000e0) { - // Instruction: 14: 11101100N01sssssPP-ttttt111ddddd | Rd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_H______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.H) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000000) { - // Instruction: 14: 11101110N00sssssPP-ttttt000xxxxx | Rx += mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000020) { - // Instruction: 14: 11101110N00sssssPP-ttttt001xxxxx | Rx += mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000040) { - // Instruction: 14: 11101110N00sssssPP-ttttt010xxxxx | Rx += mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000060) { - // Instruction: 14: 11101110N00sssssPP-ttttt011xxxxx | Rx += mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000080) { - // Instruction: 14: 11101110N00sssssPP-ttttt100xxxxx | Rx += mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_L__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d.L, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe0000a0) { - // Instruction: 14: 11101110N00sssssPP-ttttt101xxxxx | Rx += mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_L__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d.L, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe0000c0) { - // Instruction: 14: 11101110N00sssssPP-ttttt110xxxxx | Rx += mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_H__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d.H, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe0000e0) { - // Instruction: 14: 11101110N00sssssPP-ttttt111xxxxx | Rx += mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_H__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d.H, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200000) { - // Instruction: 14: 11101110N01sssssPP-ttttt000xxxxx | Rx -= mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200020) { - // Instruction: 14: 11101110N01sssssPP-ttttt001xxxxx | Rx -= mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200040) { - // Instruction: 14: 11101110N01sssssPP-ttttt010xxxxx | Rx -= mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200060) { - // Instruction: 14: 11101110N01sssssPP-ttttt011xxxxx | Rx -= mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200080) { - // Instruction: 14: 11101110N01sssssPP-ttttt100xxxxx | Rx -= mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_L__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d.L, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe2000a0) { - // Instruction: 14: 11101110N01sssssPP-ttttt101xxxxx | Rx -= mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_L__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d.L, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe2000c0) { - // Instruction: 14: 11101110N01sssssPP-ttttt110xxxxx | Rx -= mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_H__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d.H, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe2000e0) { - // Instruction: 14: 11101110N01sssssPP-ttttt111xxxxx | Rx -= mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_H__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d.H, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4400000) { - // Instruction: 14: 11100100N10sssssPP-ttttt-00ddddd | Rdd = mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RDD___MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4400020) { - // Instruction: 14: 11100100N10sssssPP-ttttt-01ddddd | Rdd = mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RDD___MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4400040) { - // Instruction: 14: 11100100N10sssssPP-ttttt-10ddddd | Rdd = mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RDD___MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4400060) { - // Instruction: 14: 11100100N10sssssPP-ttttt-11ddddd | Rdd = mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RDD___MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6400000) { - // Instruction: 14: 11100110N10sssssPP-ttttt000xxxxx | Rxx += mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6400020) { - // Instruction: 14: 11100110N10sssssPP-ttttt001xxxxx | Rxx += mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6400040) { - // Instruction: 14: 11100110N10sssssPP-ttttt010xxxxx | Rxx += mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6400060) { - // Instruction: 14: 11100110N10sssssPP-ttttt011xxxxx | Rxx += mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6600000) { - // Instruction: 14: 11100110N11sssssPP-ttttt000xxxxx | Rxx -= mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6600020) { - // Instruction: 14: 11100110N11sssssPP-ttttt001xxxxx | Rxx -= mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6600040) { - // Instruction: 14: 11100110N11sssssPP-ttttt010xxxxx | Rxx -= mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6600060) { - // Instruction: 14: 11100110N11sssssPP-ttttt011xxxxx | Rxx -= mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc400000) { - // Instruction: 14: 11101100N10sssssPP-ttttt000ddddd | Rd = mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc400020) { - // Instruction: 14: 11101100N10sssssPP-ttttt001ddddd | Rd = mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc400040) { - // Instruction: 14: 11101100N10sssssPP-ttttt010ddddd | Rd = mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc400060) { - // Instruction: 14: 11101100N10sssssPP-ttttt011ddddd | Rd = mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe400000) { - // Instruction: 14: 11101110N10sssssPP-ttttt000xxxxx | Rx += mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe400020) { - // Instruction: 14: 11101110N10sssssPP-ttttt001xxxxx | Rx += mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe400040) { - // Instruction: 14: 11101110N10sssssPP-ttttt010xxxxx | Rx += mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe400060) { - // Instruction: 14: 11101110N10sssssPP-ttttt011xxxxx | Rx += mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe600000) { - // Instruction: 14: 11101110N11sssssPP-ttttt000xxxxx | Rx -= mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe600020) { - // Instruction: 14: 11101110N11sssssPP-ttttt001xxxxx | Rx -= mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe600040) { - // Instruction: 14: 11101110N11sssssPP-ttttt010xxxxx | Rx -= mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe600060) { - // Instruction: 14: 11101110N11sssssPP-ttttt011xxxxx | Rx -= mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x54000e0) { - // Instruction: 14: 11100101010sssssPP0ttttt111ddddd | Rdd = pmpyw (Rs, Rt) - hi->instruction = HEX_INS_RDD___PMPYW__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = pmpyw (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x72000e0) { - // Instruction: 14: 11100111001sssssPP0ttttt111xxxxx | Rxx ^= pmpyw (Rs, Rt) - hi->instruction = HEX_INS_RXX____PMPYW__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= pmpyw (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x8200040) { - // Instruction: 14: 11101000N01sssssPP0ttttt010ddddd | Rdd = vrmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VRMPYWOH__RSS__RTT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpywoh (R%d:R%d, R%d:R%d) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x8400080) { - // Instruction: 14: 11101000N10sssssPP0ttttt100ddddd | Rdd = vrmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VRMPYWEH__RSS__RTT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpyweh (R%d:R%d, R%d:R%d) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa2000c0) { - // Instruction: 14: 11101010N01sssssPP0ttttt110xxxxx | Rxx += vrmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VRMPYWEH__RSS__RTT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpyweh (R%d:R%d, R%d:R%d) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa6000c0) { - // Instruction: 14: 11101010N11sssssPP0ttttt110xxxxx | Rxx += vrmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VRMPYWOH__RSS__RTT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpywoh (R%d:R%d, R%d:R%d) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xd200020) { - // Instruction: 14: 11101101001sssssPP0ttttt001ddddd | Rd = mpy (Rs, Rt) :rnd - hi->instruction = HEX_INS_RD___MPY__RS__RT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d, R%d) :rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xd400020) { - // Instruction: 14: 11101101010sssssPP0ttttt001ddddd | Rd = mpyu (Rs, Rt) - hi->instruction = HEX_INS_RD___MPYU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xd600020) { - // Instruction: 14: 11101101011sssssPP0ttttt001ddddd | Rd = mpysu (Rs, Rt) - hi->instruction = HEX_INS_RD___MPYSU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpysu (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xda00000) { - // Instruction: 14: 11101101101sssssPP0ttttt000ddddd | Rd = mpy (Rs, Rt.H) :<<1:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_H_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d.H) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xda00020) { - // Instruction: 14: 11101101101sssssPP0ttttt001ddddd | Rd = mpy (Rs, Rt.L) :<<1:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_L_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d.L) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xda00080) { - // Instruction: 14: 11101101101sssssPP0ttttt100ddddd | Rd = mpy (Rs, Rt.H) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_H_____1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d.H) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xde00000) { - // Instruction: 14: 11101101111sssssPP0ttttt000ddddd | Rd = mpy (Rs, Rt) :<<1:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xde00080) { - // Instruction: 14: 11101101111sssssPP0ttttt100ddddd | Rd = mpy (Rs, Rt.L) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_L_____1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d.L) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf402080) == 0xd000000) { - // Instruction: 14: 11101101N0NsssssPP0ttttt0NNddddd | Rd = mpy (Rs, Rt) [:<instruction = HEX_INS_RD___MPY__RS__RT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32 & 0x800000) >> 20) | ((hi_u32 & 0x200000) >> 19) | ((hi_u32 & 0x60) >> 5))) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d, R%d) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf600000) { - // Instruction: 14: 11101111011sssssPP0ttttt000xxxxx | Rx += mpy (Rs, Rt) :<<1:sat - hi->instruction = HEX_INS_RX__PLUS_EQ__MPY__RS__RT_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d, R%d) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf600020) { - // Instruction: 14: 11101111011sssssPP0ttttt001xxxxx | Rx -= mpy (Rs, Rt) :<<1:sat - hi->instruction = HEX_INS_RX__MINUS_EQ__MPY__RS__RT_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d, R%d) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5000000) { - // Instruction: 14: 11100101000sssssPP0ttttt000ddddd | Rdd = mpy (Rs, Rt) - hi->instruction = HEX_INS_RDD___MPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5400000) { - // Instruction: 14: 11100101010sssssPP0ttttt000ddddd | Rdd = mpyu (Rs, Rt) - hi->instruction = HEX_INS_RDD___MPYU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7000000) { - // Instruction: 14: 11100111000sssssPP0ttttt000xxxxx | Rxx += mpy (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7200000) { - // Instruction: 14: 11100111001sssssPP0ttttt000xxxxx | Rxx -= mpy (Rs, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7400000) { - // Instruction: 14: 11100111010sssssPP0ttttt000xxxxx | Rxx += mpyu (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7600000) { - // Instruction: 14: 11100111011sssssPP0ttttt000xxxxx | Rxx -= mpyu (Rs, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x8000080) { - // Instruction: 14: 11101000N00sssssPP0ttttt100ddddd | Rdd = vdmpy (Rss, Rtt) [:<instruction = HEX_INS_RDD___VDMPY__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vdmpy (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa000080) { - // Instruction: 14: 11101010N00sssssPP0ttttt100xxxxx | Rxx += vdmpy (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VDMPY__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vdmpy (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf002060) == 0x9000000) { - // Instruction: 14: 11101001N--sssssPP0ttttt-00ddddd | Rd = vdmpy (Rss, Rtt) [:<instruction = HEX_INS_RD___VDMPY__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vdmpy (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8800020) { - // Instruction: 14: 11101000100sssssPP0ttttt001ddddd | Rdd = vrmpybu (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRMPYBU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpybu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8c00020) { - // Instruction: 14: 11101000110sssssPP0ttttt001ddddd | Rdd = vrmpybsu (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRMPYBSU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpybsu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa800020) { - // Instruction: 14: 11101010100sssssPP0ttttt001xxxxx | Rxx += vrmpybu (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRMPYBU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpybu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xac00020) { - // Instruction: 14: 11101010110sssssPP0ttttt001xxxxx | Rxx += vrmpybsu (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRMPYBSU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpybsu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8a00020) { - // Instruction: 14: 11101000101sssssPP0ttttt001ddddd | Rdd = vdmpybsu (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VDMPYBSU__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vdmpybsu (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa200020) { - // Instruction: 14: 11101010001sssssPP0ttttt001xxxxx | Rxx += vdmpybsu (Rss, Rtt) :sat - hi->instruction = HEX_INS_RXX__PLUS_EQ__VDMPYBSU__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vdmpybsu (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x80000c0) { - // Instruction: 14: 11101000N00sssssPP0ttttt110ddddd | Rdd = vmpyeh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYEH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyeh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa200040) { - // Instruction: 14: 11101010001sssssPP0ttttt010xxxxx | Rxx += vmpyeh (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VMPYEH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vmpyeh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa0000c0) { - // Instruction: 14: 11101010N00sssssPP0ttttt110xxxxx | Rxx += vmpyeh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYEH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyeh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x50000a0) { - // Instruction: 14: 11100101N00sssssPP0ttttt101ddddd | Rdd = vmpyh (Rs, Rt) [:<instruction = HEX_INS_RDD___VMPYH__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyh (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7200020) { - // Instruction: 14: 11100111001sssssPP0ttttt001xxxxx | Rxx += vmpyh (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VMPYH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vmpyh (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x70000a0) { - // Instruction: 14: 11100111N00sssssPP0ttttt101xxxxx | Rxx += vmpyh (Rs, Rt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYH__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyh (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xd2000e0) { - // Instruction: 14: 11101101N01sssssPP0ttttt111ddddd | Rd = vmpyh (Rs, Rt) [:<instruction = HEX_INS_RD___VMPYH__RS__RT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vmpyh (R%d, R%d) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x50000e0) { - // Instruction: 14: 11100101N00sssssPP0ttttt111ddddd | Rdd = vmpyhsu (Rs, Rt) [:<instruction = HEX_INS_RDD___VMPYHSU__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyhsu (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x76000a0) { - // Instruction: 14: 11100111N11sssssPP0ttttt101xxxxx | Rxx += vmpyhsu (Rs, Rt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYHSU__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - if ((((hi_u32) & 0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyhsu (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8000040) { - // Instruction: 14: 11101000000sssssPP0ttttt010ddddd | Rdd = vrmpyh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRMPYH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpyh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa000040) { - // Instruction: 14: 11101010000sssssPP0ttttt010xxxxx | Rxx += vrmpyh (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRMPYH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpyh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5400020) { - // Instruction: 14: 11100101010sssssPP0ttttt001ddddd | Rdd = vmpybsu (Rs, Rt) - hi->instruction = HEX_INS_RDD___VMPYBSU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmpybsu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5800020) { - // Instruction: 14: 11100101100sssssPP0ttttt001ddddd | Rdd = vmpybu (Rs, Rt) - hi->instruction = HEX_INS_RDD___VMPYBU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmpybu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7800020) { - // Instruction: 14: 11100111100sssssPP0ttttt001xxxxx | Rxx += vmpybu (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VMPYBU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vmpybu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7c00020) { - // Instruction: 14: 11100111110sssssPP0ttttt001xxxxx | Rxx += vmpybsu (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VMPYBSU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vmpybsu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5c000e0) { - // Instruction: 14: 11100101110sssssPP0ttttt111ddddd | Rdd = vpmpyh (Rs, Rt) - hi->instruction = HEX_INS_RDD___VPMPYH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vpmpyh (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7a000e0) { - // Instruction: 14: 11100111101sssssPP0ttttt111xxxxx | Rxx ^= vpmpyh (Rs, Rt) - hi->instruction = HEX_INS_RXX____VPMPYH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= vpmpyh (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - break; - } - case 0xf: { - if ((hi_u32 & 0xfe00000) == 0x3000000) { - // Instruction: 15: 11110011000sssssPP-ttttt---ddddd | Rd = add (Rs, Rt) - hi->instruction = HEX_INS_RD___ADD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6400000) { - // Instruction: 15: 11110110010sssssPP-ttttt---ddddd | Rd = add (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___ADD__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1000000) { - // Instruction: 15: 11110001000sssssPP-ttttt---ddddd | Rd = and (Rs, Rt) - hi->instruction = HEX_INS_RD___AND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = and (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1200000) { - // Instruction: 15: 11110001001sssssPP-ttttt---ddddd | Rd = or (Rs, Rt) - hi->instruction = HEX_INS_RD___OR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = or (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1600000) { - // Instruction: 15: 11110001011sssssPP-ttttt---ddddd | Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_RD___XOR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = xor (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1800000) { - // Instruction: 15: 11110001100sssssPP-ttttt---ddddd | Rd = and (Rt, ~Rs) - hi->instruction = HEX_INS_RD___AND__RT___RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = and (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1a00000) { - // Instruction: 15: 11110001101sssssPP-ttttt---ddddd | Rd = or (Rt, ~Rs) - hi->instruction = HEX_INS_RD___OR__RT___RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = or (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3200000) { - // Instruction: 15: 11110011001sssssPP-ttttt---ddddd | Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_RD___SUB__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sub (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6c00000) { - // Instruction: 15: 11110110110sssssPP-ttttt---ddddd | Rd = sub (Rt, Rs) :sat - hi->instruction = HEX_INS_RD___SUB__RT__RS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6000000) { - // Instruction: 15: 11110110000sssssPP-ttttt---ddddd | Rd = vaddh (Rs, Rt) - hi->instruction = HEX_INS_RD___VADDH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vaddh (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6200000) { - // Instruction: 15: 11110110001sssssPP-ttttt---ddddd | Rd = vaddh (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___VADDH__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vaddh (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6600000) { - // Instruction: 15: 11110110011sssssPP-ttttt---ddddd | Rd = vadduh (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___VADDUH__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vadduh (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf600000) == 0x7000000) { - // Instruction: 15: 11110111-00sssssPP-ttttt---ddddd | Rd = vavgh (Rs, Rt) - hi->instruction = HEX_INS_RD___VAVGH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vavgh (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf600000) == 0x7200000) { - // Instruction: 15: 11110111-01sssssPP-ttttt---ddddd | Rd = vavgh (Rs, Rt) :rnd - hi->instruction = HEX_INS_RD___VAVGH__RS__RT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = vavgh (R%d, R%d) :rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf600000) == 0x7600000) { - // Instruction: 15: 11110111-11sssssPP-ttttt---ddddd | Rd = vnavgh (Rt, Rs) - hi->instruction = HEX_INS_RD___VNAVGH__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vnavgh (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6800000) { - // Instruction: 15: 11110110100sssssPP-ttttt---ddddd | Rd = vsubh (Rt, Rs) - hi->instruction = HEX_INS_RD___VSUBH__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsubh (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6a00000) { - // Instruction: 15: 11110110101sssssPP-ttttt---ddddd | Rd = vsubh (Rt, Rs) :sat - hi->instruction = HEX_INS_RD___VSUBH__RT__RS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vsubh (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6e00000) { - // Instruction: 15: 11110110111sssssPP-ttttt---ddddd | Rd = vsubuh (Rt, Rs) :sat - hi->instruction = HEX_INS_RD___VSUBUH__RT__RS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vsubuh (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3800000) { - // Instruction: 15: 11110011100sssssPP-ttttt---ddddd | Rd = combine (Rt.H, Rs.H) - hi->instruction = HEX_INS_RD___COMBINE__RT_H__RS_H_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = combine (R%d.H, R%d.H)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3a00000) { - // Instruction: 15: 11110011101sssssPP-ttttt---ddddd | Rd = combine (Rt.H, Rs.L) - hi->instruction = HEX_INS_RD___COMBINE__RT_H__RS_L_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = combine (R%d.H, R%d.L)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3c00000) { - // Instruction: 15: 11110011110sssssPP-ttttt---ddddd | Rd = combine (Rt.L, Rs.H) - hi->instruction = HEX_INS_RD___COMBINE__RT_L__RS_H_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = combine (R%d.L, R%d.H)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3e00000) { - // Instruction: 15: 11110011111sssssPP-ttttt---ddddd | Rd = combine (Rt.L, Rs.L) - hi->instruction = HEX_INS_RD___COMBINE__RT_L__RS_L_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = combine (R%d.L, R%d.L)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0x5000000) { - // Instruction: 15: 111101010--sssssPP-ttttt---ddddd | Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_RDD___COMBINE__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x4000000) { - // Instruction: 15: 11110100---sssssPP-ttttt-uuddddd | Rd = mux (Pu, Rs, Rt) - hi->instruction = HEX_INS_RD___MUX__PU__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mux (P%d, R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0x5800000) { - // Instruction: 15: 111101011--sssssPP-ttttt---ddddd | Rdd = packhl (Rs, Rt) - hi->instruction = HEX_INS_RDD___PACKHL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = packhl (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb000000) { - // Instruction: 15: 111110110-0sssssPP0ttttt0uuddddd | if (Pu) Rd = add (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RD___ADD__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = add (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb000080) { - // Instruction: 15: 111110110-0sssssPP0ttttt1uuddddd | if !Pu Rd = add (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ADD__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = add (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb002000) { - // Instruction: 15: 111110110-0sssssPP1ttttt0uuddddd | if (Pu.new) Rd = add (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ADD__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = add (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb002080) { - // Instruction: 15: 111110110-0sssssPP1ttttt1uuddddd | if !Pu.new Rd = add (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ADD__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = add (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf002080) == 0xd000000) { - // Instruction: 15: 11111101---sssssPP0ttttt0uuddddd | if (Pu) Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RDD___COMBINE__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf002080) == 0xd000080) { - // Instruction: 15: 11111101---sssssPP0ttttt1uuddddd | if !Pu Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RDD___COMBINE__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf002080) == 0xd002000) { - // Instruction: 15: 11111101---sssssPP1ttttt0uuddddd | if (Pu.new) Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RDD___COMBINE__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf002080) == 0xd002080) { - // Instruction: 15: 11111101---sssssPP1ttttt1uuddddd | if !Pu.new Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RDD___COMBINE__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9000000) { - // Instruction: 15: 11111001-00sssssPP0ttttt0uuddddd | if (Pu) Rd = and (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RD___AND__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = and (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9000080) { - // Instruction: 15: 11111001-00sssssPP0ttttt1uuddddd | if !Pu Rd = and (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RD___AND__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = and (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9002000) { - // Instruction: 15: 11111001-00sssssPP1ttttt0uuddddd | if (Pu.new) Rd = and (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RD___AND__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = and (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9002080) { - // Instruction: 15: 11111001-00sssssPP1ttttt1uuddddd | if !Pu.new Rd = and (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___AND__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = and (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9200000) { - // Instruction: 15: 11111001-01sssssPP0ttttt0uuddddd | if (Pu) Rd = or (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RD___OR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = or (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9200080) { - // Instruction: 15: 11111001-01sssssPP0ttttt1uuddddd | if !Pu Rd = or (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RD___OR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = or (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9202000) { - // Instruction: 15: 11111001-01sssssPP1ttttt0uuddddd | if (Pu.new) Rd = or (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RD___OR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = or (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9202080) { - // Instruction: 15: 11111001-01sssssPP1ttttt1uuddddd | if !Pu.new Rd = or (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___OR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = or (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9600000) { - // Instruction: 15: 11111001-11sssssPP0ttttt0uuddddd | if (Pu) Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RD___XOR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = xor (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9600080) { - // Instruction: 15: 11111001-11sssssPP0ttttt1uuddddd | if !Pu Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RD___XOR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = xor (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9602000) { - // Instruction: 15: 11111001-11sssssPP1ttttt0uuddddd | if (Pu.new) Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RD___XOR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = xor (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf602080) == 0x9602080) { - // Instruction: 15: 11111001-11sssssPP1ttttt1uuddddd | if !Pu.new Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___XOR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = xor (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb200000) { - // Instruction: 15: 111110110-1sssssPP0ttttt0uuddddd | if (Pu) Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_IF__PU__RD___SUB__RT__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = sub (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb200080) { - // Instruction: 15: 111110110-1sssssPP0ttttt1uuddddd | if !Pu Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___SUB__RT__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = sub (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb202000) { - // Instruction: 15: 111110110-1sssssPP1ttttt0uuddddd | if (Pu.new) Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___SUB__RT__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = sub (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb202080) { - // Instruction: 15: 111110110-1sssssPP1ttttt1uuddddd | if !Pu.new Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___SUB__RT__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = sub (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf60001c) == 0x2000000) { - // Instruction: 15: 11110010-00sssssPP-ttttt---000dd | Pd = cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf60001c) == 0x2000010) { - // Instruction: 15: 11110010-00sssssPP-ttttt---100dd | Pd = !cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_CMP_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !cmp.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf60001c) == 0x2400000) { - // Instruction: 15: 11110010-10sssssPP-ttttt---000dd | Pd = cmp.gt (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_GT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf60001c) == 0x2400010) { - // Instruction: 15: 11110010-10sssssPP-ttttt---100dd | Pd = !cmp.gt (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_CMP_GT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !cmp.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf60001c) == 0x2600000) { - // Instruction: 15: 11110010-11sssssPP-ttttt---000dd | Pd = cmp.gtu (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_GTU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gtu (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf60001c) == 0x2600010) { - // Instruction: 15: 11110010-11sssssPP-ttttt---100dd | Pd = !cmp.gtu (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_CMP_GTU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32) & 0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !cmp.gtu (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3400000) { - // Instruction: 15: 11110011010sssssPP-ttttt---ddddd | Rd = cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_RD___CMP_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cmp.eq (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3600000) { - // Instruction: 15: 11110011011sssssPP-ttttt---ddddd | Rd = !cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_RD____NOT_CMP_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32) & 0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32) & 0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32) & 0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = !cmp.eq (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - break; - } - } - } - return 4; -} diff --git a/rizin/hexagon_insn.h b/rizin/hexagon_insn.h deleted file mode 100644 index 73a3acff..00000000 --- a/rizin/hexagon_insn.h +++ /dev/null @@ -1,2812 +0,0 @@ -// THIS FILE IS AUTOGENERATED - SEE IMPORTER.PY FILE - -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov -// SPDX-License-Identifier: LGPL-3.0-only - -#ifndef HEXAGON_INSN_H -#define HEXAGON_INSN_H - -enum HEX_INS { - HEX_INS_UNKNOWN, - HEX_INS_IMMEXT, - HEX_INS_RD___ADD__RS___S16_, - HEX_INS_RD___ADD__RS__RT_, - HEX_INS_RD___ADD__RS__RT___SAT, - HEX_INS_RD___AND__RS___S10_, - HEX_INS_RD___OR__RS___S10_, - HEX_INS_RD___AND__RS__RT_, - HEX_INS_RD___OR__RS__RT_, - HEX_INS_RD___XOR__RS__RT_, - HEX_INS_RD___AND__RT___RS_, - HEX_INS_RD___OR__RT___RS_, - HEX_INS_NOP, - HEX_INS_RD___SUB___S10__RS_, - HEX_INS_RD___SUB__RT__RS_, - HEX_INS_RD___SUB__RT__RS___SAT, - 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HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RD___SXTB__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RS__RX_, - HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RX__RS_, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RD___SXTB__RU____P0___CMP_EQ__RS___U2_, - HEX_INS_DUPLEX_RD___SXTH__RS____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTH__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RD___SXTH__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RS__RX_, - HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RX__RS_, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RD___SXTH__RU____P0___CMP_EQ__RS___U2_, - HEX_INS_DUPLEX_RD___ZXTH__RS____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____JUMPR_LR, - HEX_INS_DUPLEX_RD___ZXTH__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RD___ZXTH__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RS__RX_, - HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RX__RS_, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RD___ZXTH__RU____P0___CMP_EQ__RS___U2_, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__DEALLOC_RETURN, - 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HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____P0___CMP_EQ__RS___U2_, -}; - -#endif diff --git a/rizin/librz/analysis/arch/hexagon/hexagon_analysis.c b/rizin/librz/analysis/arch/hexagon/hexagon_analysis.c new file mode 100644 index 00000000..d7e91b8c --- /dev/null +++ b/rizin/librz/analysis/arch/hexagon/hexagon_analysis.c @@ -0,0 +1,1039 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + +#include +#include +#include +#include +#include +#include +#include "hexagon.h" +#include "hexagon_insn.h" + +static inline bool is_endloop01_instr(const HexInsn *hi) { + return (hi->pkt_info.loop_attr & HEX_ENDS_LOOP_0) && (hi->pkt_info.loop_attr & HEX_ENDS_LOOP_1); +} + +static inline bool is_endloop0_instr(const HexInsn *hi) { + return (hi->pkt_info.loop_attr & HEX_ENDS_LOOP_0); +} + +static inline bool is_endloop1_instr(const HexInsn *hi) { + return (hi->pkt_info.loop_attr & HEX_ENDS_LOOP_1); +} + +static inline bool is_loop0_begin(const HexInsn *hi) { + return ((hi->pkt_info.loop_attr & HEX_LOOP_0) && !(hi->pkt_info.loop_attr & 0xc)); +} + +static inline bool is_loop1_begin(const HexInsn *hi) { + return ((hi->pkt_info.loop_attr & HEX_LOOP_1) && !(hi->pkt_info.loop_attr & 0xc)); +} + +int hexagon_analysis_instruction(HexInsn *hi, RzAnalysisOp *op) { + static ut32 hw_loop0_start = 0; + static ut32 hw_loop1_start = 0; + + switch (hi->instruction) { + default: + if (is_endloop01_instr(hi) && hi->pkt_info.last_insn) { + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->fail = hw_loop0_start; + op->jump = hw_loop1_start; + hw_loop1_start = 0; + hw_loop0_start = 0; + } else if (is_endloop0_instr(hi) && hi->pkt_info.last_insn) { + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = hw_loop0_start; + hw_loop0_start = 0; + } else if (is_endloop1_instr(hi) && hi->pkt_info.last_insn) { + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = hw_loop1_start; + hw_loop1_start = 0; + } + break; + case HEX_INS_J2_CALL: + // call Ii + op->type = RZ_ANALYSIS_OP_TYPE_CALL; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + break; + case HEX_INS_J2_CALLF: + // if (!Pu) call Ii + op->type = RZ_ANALYSIS_OP_TYPE_CCALL; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_CALLR: + // callr Rs + op->type = RZ_ANALYSIS_OP_TYPE_RCALL; + break; + case HEX_INS_J2_CALLRF: + // if (!Pu) callr Rs + op->type = RZ_ANALYSIS_OP_TYPE_UCCALL; + break; + case HEX_INS_J2_CALLRT: + // if (Pu) callr Rs + op->type = RZ_ANALYSIS_OP_TYPE_UCCALL; + break; + case HEX_INS_J2_CALLT: + // if (Pu) call Ii + op->type = RZ_ANALYSIS_OP_TYPE_CCALL; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMP: + // jump Ii + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + break; + case HEX_INS_J2_JUMPF: + // if (!Pu) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPFNEW: + // if (!Pu.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPFNEWPT: + // if (!Pu.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPFPT: + // if (!Pu) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPR: + // jumpr Rs + op->type = RZ_ANALYSIS_OP_TYPE_RJMP; + break; + case HEX_INS_J2_JUMPRF: + // if (!Pu) jumpr:nt Rs + op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; + break; + case HEX_INS_J2_JUMPRFNEW: + // if (!Pu.new) jumpr:nt Rs + op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; + break; + case HEX_INS_J2_JUMPRFNEWPT: + // if (!Pu.new) jumpr:t Rs + op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; + break; + case HEX_INS_J2_JUMPRFPT: + // if (!Pu) jumpr:t Rs + op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; + break; + case HEX_INS_J2_JUMPRGTEZ: + // if (Rs>=#0) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPRGTEZPT: + // if (Rs>=#0) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPRLTEZ: + // if (Rs<=#0) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPRLTEZPT: + // if (Rs<=#0) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPRNZ: + // if (Rs==#0) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPRNZPT: + // if (Rs==#0) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPRT: + // if (Pu) jumpr:nt Rs + op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; + break; + case HEX_INS_J2_JUMPRTNEW: + // if (Pu.new) jumpr:nt Rs + op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; + break; + case HEX_INS_J2_JUMPRTNEWPT: + // if (Pu.new) jumpr:t Rs + op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; + break; + case HEX_INS_J2_JUMPRTPT: + // if (Pu) jumpr:t Rs + op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; + break; + case HEX_INS_J2_JUMPRZ: + // if (Rs!=#0) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPRZPT: + // if (Rs!=#0) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPT: + // if (Pu) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPTNEW: + // if (Pu.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPTNEWPT: + // if (Pu.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_JUMPTPT: + // if (Pu) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J2_LOOP0I: + // loop0(Ii,#II) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J2_LOOP0R: + // loop0(Ii,Rs) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J2_LOOP1I: + // loop1(Ii,#II) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J2_LOOP1R: + // loop1(Ii,Rs) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J2_PLOOP1SI: + // p3 = sp1loop0(Ii,#II) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J2_PLOOP1SR: + // p3 = sp1loop0(Ii,Rs) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J2_PLOOP2SI: + // p3 = sp2loop0(Ii,#II) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J2_PLOOP2SR: + // p3 = sp2loop0(Ii,Rs) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J2_PLOOP3SI: + // p3 = sp3loop0(Ii,#II) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J2_PLOOP3SR: + // p3 = sp3loop0(Ii,Rs) + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[0].op.imm; + if (is_loop0_begin(hi)) { + hw_loop0_start = op->jump; + } else if (is_loop1_begin(hi)) { + hw_loop1_start = op->jump; + } + break; + case HEX_INS_J4_CMPEQ_F_JUMPNV_NT: + // if (!cmp.eq(Ns.new,Rt)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_F_JUMPNV_T: + // if (!cmp.eq(Ns.new,Rt)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_FP0_JUMP_NT: + // p0 = cmp.eq(Rs,Rt); if (!p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_FP0_JUMP_T: + // p0 = cmp.eq(Rs,Rt); if (!p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_FP1_JUMP_NT: + // p1 = cmp.eq(Rs,Rt); if (!p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_FP1_JUMP_T: + // p1 = cmp.eq(Rs,Rt); if (!p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_T_JUMPNV_NT: + // if (cmp.eq(Ns.new,Rt)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_T_JUMPNV_T: + // if (cmp.eq(Ns.new,Rt)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_TP0_JUMP_NT: + // p0 = cmp.eq(Rs,Rt); if (p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_TP0_JUMP_T: + // p0 = cmp.eq(Rs,Rt); if (p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_TP1_JUMP_NT: + // p1 = cmp.eq(Rs,Rt); if (p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQ_TP1_JUMP_T: + // p1 = cmp.eq(Rs,Rt); if (p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_F_JUMPNV_NT: + // if (!cmp.eq(Ns.new,#II)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_F_JUMPNV_T: + // if (!cmp.eq(Ns.new,#II)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_FP0_JUMP_NT: + // p0 = cmp.eq(Rs,#II); if (!p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_FP0_JUMP_T: + // p0 = cmp.eq(Rs,#II); if (!p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_FP1_JUMP_NT: + // p1 = cmp.eq(Rs,#II); if (!p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_FP1_JUMP_T: + // p1 = cmp.eq(Rs,#II); if (!p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_T_JUMPNV_NT: + // if (cmp.eq(Ns.new,#II)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_T_JUMPNV_T: + // if (cmp.eq(Ns.new,#II)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_TP0_JUMP_NT: + // p0 = cmp.eq(Rs,#II); if (p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_TP0_JUMP_T: + // p0 = cmp.eq(Rs,#II); if (p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_TP1_JUMP_NT: + // p1 = cmp.eq(Rs,#II); if (p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQI_TP1_JUMP_T: + // p1 = cmp.eq(Rs,#II); if (p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_F_JUMPNV_NT: + // if (!cmp.eq(Ns.new,#n1)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_F_JUMPNV_T: + // if (!cmp.eq(Ns.new,#n1)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_FP0_JUMP_NT: + // p0 = cmp.eq(Rs,#n1); if (!p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_FP0_JUMP_T: + // p0 = cmp.eq(Rs,#n1); if (!p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_FP1_JUMP_NT: + // p1 = cmp.eq(Rs,#n1); if (!p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_FP1_JUMP_T: + // p1 = cmp.eq(Rs,#n1); if (!p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_T_JUMPNV_NT: + // if (cmp.eq(Ns.new,#n1)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_T_JUMPNV_T: + // if (cmp.eq(Ns.new,#n1)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_TP0_JUMP_NT: + // p0 = cmp.eq(Rs,#n1); if (p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_TP0_JUMP_T: + // p0 = cmp.eq(Rs,#n1); if (p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_TP1_JUMP_NT: + // p1 = cmp.eq(Rs,#n1); if (p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPEQN1_TP1_JUMP_T: + // p1 = cmp.eq(Rs,#n1); if (p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_F_JUMPNV_NT: + // if (!cmp.gt(Ns.new,Rt)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_F_JUMPNV_T: + // if (!cmp.gt(Ns.new,Rt)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_FP0_JUMP_NT: + // p0 = cmp.gt(Rs,Rt); if (!p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_FP0_JUMP_T: + // p0 = cmp.gt(Rs,Rt); if (!p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_FP1_JUMP_NT: + // p1 = cmp.gt(Rs,Rt); if (!p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_FP1_JUMP_T: + // p1 = cmp.gt(Rs,Rt); if (!p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_T_JUMPNV_NT: + // if (cmp.gt(Ns.new,Rt)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_T_JUMPNV_T: + // if (cmp.gt(Ns.new,Rt)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_TP0_JUMP_NT: + // p0 = cmp.gt(Rs,Rt); if (p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_TP0_JUMP_T: + // p0 = cmp.gt(Rs,Rt); if (p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_TP1_JUMP_NT: + // p1 = cmp.gt(Rs,Rt); if (p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGT_TP1_JUMP_T: + // p1 = cmp.gt(Rs,Rt); if (p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_F_JUMPNV_NT: + // if (!cmp.gt(Ns.new,#II)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_F_JUMPNV_T: + // if (!cmp.gt(Ns.new,#II)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_FP0_JUMP_NT: + // p0 = cmp.gt(Rs,#II); if (!p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_FP0_JUMP_T: + // p0 = cmp.gt(Rs,#II); if (!p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_FP1_JUMP_NT: + // p1 = cmp.gt(Rs,#II); if (!p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_FP1_JUMP_T: + // p1 = cmp.gt(Rs,#II); if (!p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_T_JUMPNV_NT: + // if (cmp.gt(Ns.new,#II)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_T_JUMPNV_T: + // if (cmp.gt(Ns.new,#II)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_TP0_JUMP_NT: + // p0 = cmp.gt(Rs,#II); if (p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_TP0_JUMP_T: + // p0 = cmp.gt(Rs,#II); if (p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_TP1_JUMP_NT: + // p1 = cmp.gt(Rs,#II); if (p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTI_TP1_JUMP_T: + // p1 = cmp.gt(Rs,#II); if (p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_F_JUMPNV_NT: + // if (!cmp.gt(Ns.new,#n1)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_F_JUMPNV_T: + // if (!cmp.gt(Ns.new,#n1)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_FP0_JUMP_NT: + // p0 = cmp.gt(Rs,#n1); if (!p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_FP0_JUMP_T: + // p0 = cmp.gt(Rs,#n1); if (!p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_FP1_JUMP_NT: + // p1 = cmp.gt(Rs,#n1); if (!p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_FP1_JUMP_T: + // p1 = cmp.gt(Rs,#n1); if (!p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_T_JUMPNV_NT: + // if (cmp.gt(Ns.new,#n1)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_T_JUMPNV_T: + // if (cmp.gt(Ns.new,#n1)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_TP0_JUMP_NT: + // p0 = cmp.gt(Rs,#n1); if (p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_TP0_JUMP_T: + // p0 = cmp.gt(Rs,#n1); if (p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_TP1_JUMP_NT: + // p1 = cmp.gt(Rs,#n1); if (p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTN1_TP1_JUMP_T: + // p1 = cmp.gt(Rs,#n1); if (p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_F_JUMPNV_NT: + // if (!cmp.gtu(Ns.new,Rt)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_F_JUMPNV_T: + // if (!cmp.gtu(Ns.new,Rt)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_FP0_JUMP_NT: + // p0 = cmp.gtu(Rs,Rt); if (!p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_FP0_JUMP_T: + // p0 = cmp.gtu(Rs,Rt); if (!p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_FP1_JUMP_NT: + // p1 = cmp.gtu(Rs,Rt); if (!p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_FP1_JUMP_T: + // p1 = cmp.gtu(Rs,Rt); if (!p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_T_JUMPNV_NT: + // if (cmp.gtu(Ns.new,Rt)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_T_JUMPNV_T: + // if (cmp.gtu(Ns.new,Rt)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_TP0_JUMP_NT: + // p0 = cmp.gtu(Rs,Rt); if (p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_TP0_JUMP_T: + // p0 = cmp.gtu(Rs,Rt); if (p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_TP1_JUMP_NT: + // p1 = cmp.gtu(Rs,Rt); if (p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTU_TP1_JUMP_T: + // p1 = cmp.gtu(Rs,Rt); if (p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_F_JUMPNV_NT: + // if (!cmp.gtu(Ns.new,#II)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_F_JUMPNV_T: + // if (!cmp.gtu(Ns.new,#II)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_FP0_JUMP_NT: + // p0 = cmp.gtu(Rs,#II); if (!p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_FP0_JUMP_T: + // p0 = cmp.gtu(Rs,#II); if (!p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_FP1_JUMP_NT: + // p1 = cmp.gtu(Rs,#II); if (!p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_FP1_JUMP_T: + // p1 = cmp.gtu(Rs,#II); if (!p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_T_JUMPNV_NT: + // if (cmp.gtu(Ns.new,#II)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_T_JUMPNV_T: + // if (cmp.gtu(Ns.new,#II)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_TP0_JUMP_NT: + // p0 = cmp.gtu(Rs,#II); if (p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_TP0_JUMP_T: + // p0 = cmp.gtu(Rs,#II); if (p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_TP1_JUMP_NT: + // p1 = cmp.gtu(Rs,#II); if (p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPGTUI_TP1_JUMP_T: + // p1 = cmp.gtu(Rs,#II); if (p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPLT_F_JUMPNV_NT: + // if (!cmp.gt(Rt,Ns.new)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPLT_F_JUMPNV_T: + // if (!cmp.gt(Rt,Ns.new)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPLT_T_JUMPNV_NT: + // if (cmp.gt(Rt,Ns.new)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPLT_T_JUMPNV_T: + // if (cmp.gt(Rt,Ns.new)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPLTU_F_JUMPNV_NT: + // if (!cmp.gtu(Rt,Ns.new)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPLTU_F_JUMPNV_T: + // if (!cmp.gtu(Rt,Ns.new)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPLTU_T_JUMPNV_NT: + // if (cmp.gtu(Rt,Ns.new)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_CMPLTU_T_JUMPNV_T: + // if (cmp.gtu(Rt,Ns.new)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_HINTJUMPR: + // hintjr(Rs) + op->type = RZ_ANALYSIS_OP_TYPE_RJMP; + break; + case HEX_INS_J4_JUMPSETI: + // Rd = #II ; jump Ii + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + break; + case HEX_INS_J4_JUMPSETR: + // Rd = Rs ; jump Ii + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = op->addr + (st32)hi->ops[2].op.imm; + break; + case HEX_INS_J4_TSTBIT0_F_JUMPNV_NT: + // if (!tstbit(Ns.new,#0)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_F_JUMPNV_T: + // if (!tstbit(Ns.new,#0)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_FP0_JUMP_NT: + // p0 = tstbit(Rs,#0); if (!p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_FP0_JUMP_T: + // p0 = tstbit(Rs,#0); if (!p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_FP1_JUMP_NT: + // p1 = tstbit(Rs,#0); if (!p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_FP1_JUMP_T: + // p1 = tstbit(Rs,#0); if (!p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_T_JUMPNV_NT: + // if (tstbit(Ns.new,#0)) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_T_JUMPNV_T: + // if (tstbit(Ns.new,#0)) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_TP0_JUMP_NT: + // p0 = tstbit(Rs,#0); if (p0.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_TP0_JUMP_T: + // p0 = tstbit(Rs,#0); if (p0.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_TP1_JUMP_NT: + // p1 = tstbit(Rs,#0); if (p1.new) jump:nt Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + case HEX_INS_J4_TSTBIT0_TP1_JUMP_T: + // p1 = tstbit(Rs,#0); if (p1.new) jump:t Ii + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = op->addr + (st32)hi->ops[1].op.imm; + op->fail = op->addr + op->size; + break; + } + return op->size; +} \ No newline at end of file diff --git a/rizin/librz/analysis/arch/hexagon/hexagon_analysis.h b/rizin/librz/analysis/arch/hexagon/hexagon_analysis.h new file mode 100644 index 00000000..d93b0b44 --- /dev/null +++ b/rizin/librz/analysis/arch/hexagon/hexagon_analysis.h @@ -0,0 +1,10 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + +int hexagon_analysis_instruction(HexInsn *hi, RzAnalysisOp *op); diff --git a/rizin/librz/analysis/p/analysis_hexagon.c b/rizin/librz/analysis/p/analysis_hexagon.c new file mode 100644 index 00000000..c63de2a5 --- /dev/null +++ b/rizin/librz/analysis/p/analysis_hexagon.c @@ -0,0 +1,281 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + +#include +#include +#include +#include +#include +#include "hexagon.h" +#include "hexagon_insn.h" +#include "hexagon_analysis.h" + +static int hexagon_v6_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) { + HexInsn hi = { 0 }; + ; + ut32 data = 0; + memset(op, 0, sizeof(RzAnalysisOp)); + data = rz_read_le32(buf); + int size = hexagon_disasm_instruction(data, &hi, (ut32)addr); + op->size = size; + if (size <= 0) { + return size; + } + + op->addr = addr; + op->jump = op->fail = -1; + op->ptr = op->val = -1; + return hexagon_analysis_instruction(&hi, op); +} + +static bool set_reg_profile(RzAnalysis *analysis) { + const char *p = + + "=PC pc\n" + "=SP r29\n" + "=BP r30\n" + "=LR r31\n" + "=SR usr\n" + "=A0 r0\n" + "=A1 r1\n" + "=A2 r2\n" + "=A3 r3\n" + "=A4 r4\n" + "=A5 r5\n" + "=A6 r1:0\n" + "=A7 r3:2\n" + "=A8 r5:4\n" + "=R0 r0\n" + "=R1 r1\n" + "=R2 r1:0\n" + + "gpr lc0 .32 0 0\n" + "gpr sa0 .32 4 0\n" + "gpr lc1 .32 8 0\n" + "gpr sa1 .32 12 0\n" + "gpr p3:0 .32 16 0\n" + "gpr c5 .32 20 0\n" + "gpr pc .32 24 0\n" + "gpr ugp .32 28 0\n" + "gpr gp .32 32 0\n" + "gpr cs0 .32 36 0\n" + "gpr cs1 .32 40 0\n" + "gpr upcyclelo .32 44 0\n" + "gpr upcyclehi .32 48 0\n" + "gpr framelimit .32 52 0\n" + "gpr framekey .32 56 0\n" + "gpr pktcountlo .32 60 0\n" + "gpr pktcounthi .32 64 0\n" + "gpr utimerlo .32 68 0\n" + "gpr utimerhi .32 72 0\n" + "gpr m0 .32 76 0\n" + "gpr m1 .32 80 0\n" + "gpr usr .32 84 0\n" + + "gpr c1:0 .64 88 0\n" + "gpr c3:2 .64 96 0\n" + "gpr c5:4 .64 104 0\n" + "gpr c7:6 .64 112 0\n" + "gpr c9:8 .64 120 0\n" + "gpr c11:10 .64 128 0\n" + "gpr c13:12 .64 136 0\n" + "gpr c15:14 .64 144 0\n" + "gpr c17:16 .64 152 0\n" + "gpr c19:18 .64 160 0\n" + "gpr c31:30 .64 168 0\n" + + "gpr r1:0 .64 176 0\n" + "gpr r3:2 .64 184 0\n" + "gpr r5:4 .64 192 0\n" + "gpr r7:6 .64 200 0\n" + "gpr r9:8 .64 208 0\n" + "gpr r13:12 .64 216 0\n" + "gpr r15:14 .64 224 0\n" + "gpr r17:16 .64 232 0\n" + "gpr r19:18 .64 240 0\n" + "gpr r21:20 .64 248 0\n" + "gpr r23:22 .64 256 0\n" + "gpr r25:24 .64 264 0\n" + "gpr r27:26 .64 272 0\n" + "gpr r11:10 .64 280 0\n" + "gpr r29:28 .64 288 0\n" + "gpr r31:30 .64 296 0\n" + + "gpr gelr .32 304 0\n" + "gpr gsr .32 308 0\n" + "gpr gosp .32 312 0\n" + "gpr gbadva .32 316 0\n" + "gpr g4 .32 320 0\n" + "gpr g5 .32 324 0\n" + "gpr g6 .32 328 0\n" + "gpr g7 .32 332 0\n" + "gpr g8 .32 336 0\n" + "gpr g9 .32 340 0\n" + "gpr g10 .32 344 0\n" + "gpr g11 .32 348 0\n" + "gpr g12 .32 352 0\n" + "gpr g13 .32 356 0\n" + "gpr g14 .32 360 0\n" + "gpr g15 .32 364 0\n" + "gpr gpmucnt4 .32 368 0\n" + "gpr gpmucnt5 .32 372 0\n" + "gpr gpmucnt6 .32 376 0\n" + "gpr gpmucnt7 .32 380 0\n" + "gpr g20 .32 384 0\n" + "gpr g21 .32 388 0\n" + "gpr g22 .32 392 0\n" + "gpr g23 .32 396 0\n" + "gpr gpcyclelo .32 400 0\n" + "gpr gpcyclehi .32 404 0\n" + "gpr gpmucnt0 .32 408 0\n" + "gpr gpmucnt1 .32 412 0\n" + "gpr gpmucnt2 .32 416 0\n" + "gpr gpmucnt3 .32 420 0\n" + "gpr g30 .32 424 0\n" + "gpr g31 .32 428 0\n" + + "gpr g1:0 .64 432 0\n" + "gpr g3:2 .64 440 0\n" + "gpr g5:4 .64 448 0\n" + "gpr g7:6 .64 456 0\n" + "gpr g9:8 .64 464 0\n" + "gpr g11:10 .64 472 0\n" + "gpr g13:12 .64 480 0\n" + "gpr g15:14 .64 488 0\n" + "gpr g17:16 .64 496 0\n" + "gpr g19:18 .64 504 0\n" + "gpr g21:20 .64 512 0\n" + "gpr g23:22 .64 520 0\n" + "gpr g25:24 .64 528 0\n" + "gpr g27:26 .64 536 0\n" + "gpr g29:28 .64 544 0\n" + "gpr g31:30 .64 552 0\n" + + "gpr q0 .128 560 0\n" + "gpr q1 .128 576 0\n" + "gpr q2 .128 592 0\n" + "gpr q3 .128 608 0\n" + + "gpr v3:0 .4096 624 0\n" + "gpr v7:4 .4096 1136 0\n" + "gpr v11:8 .4096 1648 0\n" + "gpr v15:12 .4096 2160 0\n" + "gpr v19:16 .4096 2672 0\n" + "gpr v23:20 .4096 3184 0\n" + "gpr v27:24 .4096 3696 0\n" + "gpr v31:28 .4096 4208 0\n" + + "gpr v0 .1024 4720 0\n" + "gpr v1 .1024 4848 0\n" + "gpr v2 .1024 4976 0\n" + "gpr v3 .1024 5104 0\n" + "gpr v4 .1024 5232 0\n" + "gpr v5 .1024 5360 0\n" + "gpr v6 .1024 5488 0\n" + "gpr v7 .1024 5616 0\n" + "gpr v8 .1024 5744 0\n" + "gpr v9 .1024 5872 0\n" + "gpr v10 .1024 6000 0\n" + "gpr v11 .1024 6128 0\n" + "gpr v12 .1024 6256 0\n" + "gpr v13 .1024 6384 0\n" + "gpr v14 .1024 6512 0\n" + "gpr v15 .1024 6640 0\n" + "gpr v16 .1024 6768 0\n" + "gpr v17 .1024 6896 0\n" + "gpr v18 .1024 7024 0\n" + "gpr v19 .1024 7152 0\n" + "gpr v20 .1024 7280 0\n" + "gpr v21 .1024 7408 0\n" + "gpr v22 .1024 7536 0\n" + "gpr v23 .1024 7664 0\n" + "gpr v24 .1024 7792 0\n" + "gpr v25 .1024 7920 0\n" + "gpr v26 .1024 8048 0\n" + "gpr v27 .1024 8176 0\n" + "gpr v28 .1024 8304 0\n" + "gpr v29 .1024 8432 0\n" + "gpr v30 .1024 8560 0\n" + "gpr v31 .1024 8688 0\n" + + "gpr v1:0 .2048 8816 0\n" + "gpr v3:2 .2048 9072 0\n" + "gpr v5:4 .2048 9328 0\n" + "gpr v7:6 .2048 9584 0\n" + "gpr v9:8 .2048 9840 0\n" + "gpr v11:10 .2048 10096 0\n" + "gpr v13:12 .2048 10352 0\n" + "gpr v15:14 .2048 10608 0\n" + "gpr v17:16 .2048 10864 0\n" + "gpr v19:18 .2048 11120 0\n" + "gpr v21:20 .2048 11376 0\n" + "gpr v23:22 .2048 11632 0\n" + "gpr v25:24 .2048 11888 0\n" + "gpr v27:26 .2048 12144 0\n" + "gpr v29:28 .2048 12400 0\n" + "gpr v31:30 .2048 12656 0\n" + + "gpr r0 .32 12912 0\n" + "gpr r1 .32 12916 0\n" + "gpr r2 .32 12920 0\n" + "gpr r3 .32 12924 0\n" + "gpr r4 .32 12928 0\n" + "gpr r5 .32 12932 0\n" + "gpr r6 .32 12936 0\n" + "gpr r7 .32 12940 0\n" + "gpr r8 .32 12944 0\n" + "gpr r9 .32 12948 0\n" + "gpr r12 .32 12952 0\n" + "gpr r13 .32 12956 0\n" + "gpr r14 .32 12960 0\n" + "gpr r15 .32 12964 0\n" + "gpr r16 .32 12968 0\n" + "gpr r17 .32 12972 0\n" + "gpr r18 .32 12976 0\n" + "gpr r19 .32 12980 0\n" + "gpr r20 .32 12984 0\n" + "gpr r21 .32 12988 0\n" + "gpr r22 .32 12992 0\n" + "gpr r23 .32 12996 0\n" + "gpr r24 .32 13000 0\n" + "gpr r25 .32 13004 0\n" + "gpr r26 .32 13008 0\n" + "gpr r27 .32 13012 0\n" + "gpr r28 .32 13016 0\n" + "gpr r10 .32 13020 0\n" + "gpr r11 .32 13024 0\n" + "gpr r29 .32 13028 0\n" + "gpr r30 .32 13032 0\n" + "gpr r31 .32 13036 0\n" + + "gpr p0 .32 13040 0\n" + "gpr p1 .32 13044 0\n" + "gpr p2 .32 13048 0\n" + "gpr p3 .32 13052 0\n"; + return rz_reg_set_profile_string(analysis->reg, p); +} + +RzAnalysisPlugin rz_analysis_plugin_hexagon = { + .name = "hexagon", + .desc = "Qualcomm Hexagon (QDSP6) V6", + .license = "LGPL3", + .arch = "hexagon", + .bits = 32, + .op = hexagon_v6_op, + .esil = true, + .set_reg_profile = set_reg_profile, +}; + +#ifndef RZ_PLUGIN_INCORE +RZ_API RzLibStruct rizin_plugin = { + .type = RZ_LIB_TYPE_ANAL, + .data = &rz_analysis_plugin_hexagon_v6, + .version = RZ_VERSION +}; +#endif diff --git a/rizin/librz/asm/arch/hexagon/hexagon.c b/rizin/librz/asm/arch/hexagon/hexagon.c new file mode 100644 index 00000000..fb19cbfe --- /dev/null +++ b/rizin/librz/asm/arch/hexagon/hexagon.c @@ -0,0 +1,700 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + +#include +#include +#include +#include +#include +#include +#include +#include "hexagon.h" + +char *hex_get_ctr_regs(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_CTR_REGS_LC0: + return "LC0"; + case HEX_REG_CTR_REGS_SA0: + return "SA0"; + case HEX_REG_CTR_REGS_LC1: + return "LC1"; + case HEX_REG_CTR_REGS_SA1: + return "SA1"; + case HEX_REG_CTR_REGS_P3_0: + return "P3:0"; + case HEX_REG_CTR_REGS_C5: + return "C5"; + case HEX_REG_CTR_REGS_PC: + return "PC"; + case HEX_REG_CTR_REGS_UGP: + return "UGP"; + case HEX_REG_CTR_REGS_GP: + return "GP"; + case HEX_REG_CTR_REGS_CS0: + return "CS0"; + case HEX_REG_CTR_REGS_CS1: + return "CS1"; + case HEX_REG_CTR_REGS_UPCYCLELO: + return "UPCYCLELO"; + case HEX_REG_CTR_REGS_UPCYCLEHI: + return "UPCYCLEHI"; + case HEX_REG_CTR_REGS_FRAMELIMIT: + return "FRAMELIMIT"; + case HEX_REG_CTR_REGS_FRAMEKEY: + return "FRAMEKEY"; + case HEX_REG_CTR_REGS_PKTCOUNTLO: + return "PKTCOUNTLO"; + case HEX_REG_CTR_REGS_PKTCOUNTHI: + return "PKTCOUNTHI"; + case HEX_REG_CTR_REGS_UTIMERLO: + return "UTIMERLO"; + case HEX_REG_CTR_REGS_UTIMERHI: + return "UTIMERHI"; + case HEX_REG_CTR_REGS_M0: + return "M0"; + case HEX_REG_CTR_REGS_M1: + return "M1"; + case HEX_REG_CTR_REGS_USR: + return "USR"; + } +} + +char *hex_get_ctr_regs64(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_CTR_REGS64_C1_0: + return "C1:0"; + case HEX_REG_CTR_REGS64_C3_2: + return "C3:2"; + case HEX_REG_CTR_REGS64_C5_4: + return "C5:4"; + case HEX_REG_CTR_REGS64_C7_6: + return "C7:6"; + case HEX_REG_CTR_REGS64_C9_8: + return "C9:8"; + case HEX_REG_CTR_REGS64_C11_10: + return "C11:10"; + case HEX_REG_CTR_REGS64_CS: + return "C13:12"; + case HEX_REG_CTR_REGS64_UPCYCLE: + return "C15:14"; + case HEX_REG_CTR_REGS64_C17_16: + return "C17:16"; + case HEX_REG_CTR_REGS64_PKTCOUNT: + return "C19:18"; + case HEX_REG_CTR_REGS64_UTIMER: + return "C31:30"; + } +} + +char *hex_get_double_regs(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_DOUBLE_REGS_D0: + return "R1:0"; + case HEX_REG_DOUBLE_REGS_D1: + return "R3:2"; + case HEX_REG_DOUBLE_REGS_D2: + return "R5:4"; + case HEX_REG_DOUBLE_REGS_D3: + return "R7:6"; + case HEX_REG_DOUBLE_REGS_D4: + return "R9:8"; + case HEX_REG_DOUBLE_REGS_D6: + return "R13:12"; + case HEX_REG_DOUBLE_REGS_D7: + return "R15:14"; + case HEX_REG_DOUBLE_REGS_D8: + return "R17:16"; + case HEX_REG_DOUBLE_REGS_D9: + return "R19:18"; + case HEX_REG_DOUBLE_REGS_D10: + return "R21:20"; + case HEX_REG_DOUBLE_REGS_D11: + return "R23:22"; + case HEX_REG_DOUBLE_REGS_D12: + return "R25:24"; + case HEX_REG_DOUBLE_REGS_D13: + return "R27:26"; + case HEX_REG_DOUBLE_REGS_D5: + return "R11:10"; + case HEX_REG_DOUBLE_REGS_D14: + return "R29:28"; + case HEX_REG_DOUBLE_REGS_D15: + return "R31:30"; + } +} + +char *hex_get_general_double_low8_regs(int opcode_reg) { + opcode_reg = opcode_reg << 1; + if (opcode_reg > 6) { // HEX_REG_D3 == 6 + opcode_reg = (opcode_reg & 0x7) | 0x10; + } + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D11: + return "R23:22"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D10: + return "R21:20"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D9: + return "R19:18"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D8: + return "R17:16"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D3: + return "R7:6"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D2: + return "R5:4"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D1: + return "R3:2"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D0: + return "R1:0"; + } +} + +char *hex_get_general_sub_regs(int opcode_reg) { + if (opcode_reg > 7) { // HEX_REG_R7 == 7 + opcode_reg = (opcode_reg & 0x7) | 0x10; + } + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_GENERAL_SUB_REGS_R23: + return "R23"; + case HEX_REG_GENERAL_SUB_REGS_R22: + return "R22"; + case HEX_REG_GENERAL_SUB_REGS_R21: + return "R21"; + case HEX_REG_GENERAL_SUB_REGS_R20: + return "R20"; + case HEX_REG_GENERAL_SUB_REGS_R19: + return "R19"; + case HEX_REG_GENERAL_SUB_REGS_R18: + return "R18"; + case HEX_REG_GENERAL_SUB_REGS_R17: + return "R17"; + case HEX_REG_GENERAL_SUB_REGS_R16: + return "R16"; + case HEX_REG_GENERAL_SUB_REGS_R7: + return "R7"; + case HEX_REG_GENERAL_SUB_REGS_R6: + return "R6"; + case HEX_REG_GENERAL_SUB_REGS_R5: + return "R5"; + case HEX_REG_GENERAL_SUB_REGS_R4: + return "R4"; + case HEX_REG_GENERAL_SUB_REGS_R3: + return "R3"; + case HEX_REG_GENERAL_SUB_REGS_R2: + return "R2"; + case HEX_REG_GENERAL_SUB_REGS_R1: + return "R1"; + case HEX_REG_GENERAL_SUB_REGS_R0: + return "R0"; + } +} + +char *hex_get_guest_regs(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_GUEST_REGS_GELR: + return "GELR"; + case HEX_REG_GUEST_REGS_GSR: + return "GSR"; + case HEX_REG_GUEST_REGS_GOSP: + return "GOSP"; + case HEX_REG_GUEST_REGS_G3: + return "GBADVA"; + case HEX_REG_GUEST_REGS_G4: + return "G4"; + case HEX_REG_GUEST_REGS_G5: + return "G5"; + case HEX_REG_GUEST_REGS_G6: + return "G6"; + case HEX_REG_GUEST_REGS_G7: + return "G7"; + case HEX_REG_GUEST_REGS_G8: + return "G8"; + case HEX_REG_GUEST_REGS_G9: + return "G9"; + case HEX_REG_GUEST_REGS_G10: + return "G10"; + case HEX_REG_GUEST_REGS_G11: + return "G11"; + case HEX_REG_GUEST_REGS_G12: + return "G12"; + case HEX_REG_GUEST_REGS_G13: + return "G13"; + case HEX_REG_GUEST_REGS_G14: + return "G14"; + case HEX_REG_GUEST_REGS_G15: + return "G15"; + case HEX_REG_GUEST_REGS_GPMUCNT4: + return "GPMUCNT4"; + case HEX_REG_GUEST_REGS_GPMUCNT5: + return "GPMUCNT5"; + case HEX_REG_GUEST_REGS_GPMUCNT6: + return "GPMUCNT6"; + case HEX_REG_GUEST_REGS_GPMUCNT7: + return "GPMUCNT7"; + case HEX_REG_GUEST_REGS_G20: + return "G20"; + case HEX_REG_GUEST_REGS_G21: + return "G21"; + case HEX_REG_GUEST_REGS_G22: + return "G22"; + case HEX_REG_GUEST_REGS_G23: + return "G23"; + case HEX_REG_GUEST_REGS_GPCYCLELO: + return "GPCYCLELO"; + case HEX_REG_GUEST_REGS_GPCYCLEHI: + return "GPCYCLEHI"; + case HEX_REG_GUEST_REGS_GPMUCNT0: + return "GPMUCNT0"; + case HEX_REG_GUEST_REGS_GPMUCNT1: + return "GPMUCNT1"; + case HEX_REG_GUEST_REGS_GPMUCNT2: + return "GPMUCNT2"; + case HEX_REG_GUEST_REGS_GPMUCNT3: + return "GPMUCNT3"; + case HEX_REG_GUEST_REGS_G30: + return "G30"; + case HEX_REG_GUEST_REGS_G31: + return "G31"; + } +} + +char *hex_get_guest_regs64(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_GUEST_REGS64_G1_0: + return "G1:0"; + case HEX_REG_GUEST_REGS64_G3_2: + return "G3:2"; + case HEX_REG_GUEST_REGS64_G5_4: + return "G5:4"; + case HEX_REG_GUEST_REGS64_G7_6: + return "G7:6"; + case HEX_REG_GUEST_REGS64_G9_8: + return "G9:8"; + case HEX_REG_GUEST_REGS64_G11_10: + return "G11:10"; + case HEX_REG_GUEST_REGS64_G13_12: + return "G13:12"; + case HEX_REG_GUEST_REGS64_G15_14: + return "G15:14"; + case HEX_REG_GUEST_REGS64_G17_16: + return "G17:16"; + case HEX_REG_GUEST_REGS64_G19_18: + return "G19:18"; + case HEX_REG_GUEST_REGS64_G21_20: + return "G21:20"; + case HEX_REG_GUEST_REGS64_G23_22: + return "G23:22"; + case HEX_REG_GUEST_REGS64_G25_24: + return "G25:24"; + case HEX_REG_GUEST_REGS64_G27_26: + return "G27:26"; + case HEX_REG_GUEST_REGS64_G29_28: + return "G29:28"; + case HEX_REG_GUEST_REGS64_G31_30: + return "G31:30"; + } +} + +char *hex_get_hvx_qr(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_HVX_QR_Q0: + return "Q0"; + case HEX_REG_HVX_QR_Q1: + return "Q1"; + case HEX_REG_HVX_QR_Q2: + return "Q2"; + case HEX_REG_HVX_QR_Q3: + return "Q3"; + } +} + +char *hex_get_hvx_vqr(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_HVX_VQR_VQ0: + return "V3:0"; + case HEX_REG_HVX_VQR_VQ1: + return "V7:4"; + case HEX_REG_HVX_VQR_VQ2: + return "V11:8"; + case HEX_REG_HVX_VQR_VQ3: + return "V15:12"; + case HEX_REG_HVX_VQR_VQ4: + return "V19:16"; + case HEX_REG_HVX_VQR_VQ5: + return "V23:20"; + case HEX_REG_HVX_VQR_VQ6: + return "V27:24"; + case HEX_REG_HVX_VQR_VQ7: + return "V31:28"; + } +} + +char *hex_get_hvx_vr(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_HVX_VR_V0: + return "V0"; + case HEX_REG_HVX_VR_V1: + return "V1"; + case HEX_REG_HVX_VR_V2: + return "V2"; + case HEX_REG_HVX_VR_V3: + return "V3"; + case HEX_REG_HVX_VR_V4: + return "V4"; + case HEX_REG_HVX_VR_V5: + return "V5"; + case HEX_REG_HVX_VR_V6: + return "V6"; + case HEX_REG_HVX_VR_V7: + return "V7"; + case HEX_REG_HVX_VR_V8: + return "V8"; + case HEX_REG_HVX_VR_V9: + return "V9"; + case HEX_REG_HVX_VR_V10: + return "V10"; + case HEX_REG_HVX_VR_V11: + return "V11"; + case HEX_REG_HVX_VR_V12: + return "V12"; + case HEX_REG_HVX_VR_V13: + return "V13"; + case HEX_REG_HVX_VR_V14: + return "V14"; + case HEX_REG_HVX_VR_V15: + return "V15"; + case HEX_REG_HVX_VR_V16: + return "V16"; + case HEX_REG_HVX_VR_V17: + return "V17"; + case HEX_REG_HVX_VR_V18: + return "V18"; + case HEX_REG_HVX_VR_V19: + return "V19"; + case HEX_REG_HVX_VR_V20: + return "V20"; + case HEX_REG_HVX_VR_V21: + return "V21"; + case HEX_REG_HVX_VR_V22: + return "V22"; + case HEX_REG_HVX_VR_V23: + return "V23"; + case HEX_REG_HVX_VR_V24: + return "V24"; + case HEX_REG_HVX_VR_V25: + return "V25"; + case HEX_REG_HVX_VR_V26: + return "V26"; + case HEX_REG_HVX_VR_V27: + return "V27"; + case HEX_REG_HVX_VR_V28: + return "V28"; + case HEX_REG_HVX_VR_V29: + return "V29"; + case HEX_REG_HVX_VR_V30: + return "V30"; + case HEX_REG_HVX_VR_V31: + return "V31"; + } +} + +char *hex_get_hvx_wr(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_HVX_WR_W0: + return "V1:0"; + case HEX_REG_HVX_WR_W1: + return "V3:2"; + case HEX_REG_HVX_WR_W2: + return "V5:4"; + case HEX_REG_HVX_WR_W3: + return "V7:6"; + case HEX_REG_HVX_WR_W4: + return "V9:8"; + case HEX_REG_HVX_WR_W5: + return "V11:10"; + case HEX_REG_HVX_WR_W6: + return "V13:12"; + case HEX_REG_HVX_WR_W7: + return "V15:14"; + case HEX_REG_HVX_WR_W8: + return "V17:16"; + case HEX_REG_HVX_WR_W9: + return "V19:18"; + case HEX_REG_HVX_WR_W10: + return "V21:20"; + case HEX_REG_HVX_WR_W11: + return "V23:22"; + case HEX_REG_HVX_WR_W12: + return "V25:24"; + case HEX_REG_HVX_WR_W13: + return "V27:26"; + case HEX_REG_HVX_WR_W14: + return "V29:28"; + case HEX_REG_HVX_WR_W15: + return "V31:30"; + } +} + +char *hex_get_int_regs(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_INT_REGS_R0: + return "R0"; + case HEX_REG_INT_REGS_R1: + return "R1"; + case HEX_REG_INT_REGS_R2: + return "R2"; + case HEX_REG_INT_REGS_R3: + return "R3"; + case HEX_REG_INT_REGS_R4: + return "R4"; + case HEX_REG_INT_REGS_R5: + return "R5"; + case HEX_REG_INT_REGS_R6: + return "R6"; + case HEX_REG_INT_REGS_R7: + return "R7"; + case HEX_REG_INT_REGS_R8: + return "R8"; + case HEX_REG_INT_REGS_R9: + return "R9"; + case HEX_REG_INT_REGS_R12: + return "R12"; + case HEX_REG_INT_REGS_R13: + return "R13"; + case HEX_REG_INT_REGS_R14: + return "R14"; + case HEX_REG_INT_REGS_R15: + return "R15"; + case HEX_REG_INT_REGS_R16: + return "R16"; + case HEX_REG_INT_REGS_R17: + return "R17"; + case HEX_REG_INT_REGS_R18: + return "R18"; + case HEX_REG_INT_REGS_R19: + return "R19"; + case HEX_REG_INT_REGS_R20: + return "R20"; + case HEX_REG_INT_REGS_R21: + return "R21"; + case HEX_REG_INT_REGS_R22: + return "R22"; + case HEX_REG_INT_REGS_R23: + return "R23"; + case HEX_REG_INT_REGS_R24: + return "R24"; + case HEX_REG_INT_REGS_R25: + return "R25"; + case HEX_REG_INT_REGS_R26: + return "R26"; + case HEX_REG_INT_REGS_R27: + return "R27"; + case HEX_REG_INT_REGS_R28: + return "R28"; + case HEX_REG_INT_REGS_R10: + return "R10"; + case HEX_REG_INT_REGS_R11: + return "R11"; + case HEX_REG_INT_REGS_R29: + return "R29"; + case HEX_REG_INT_REGS_R30: + return "R30"; + case HEX_REG_INT_REGS_R31: + return "R31"; + } +} + +char *hex_get_int_regs_low8(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_INT_REGS_LOW8_R7: + return "R7"; + case HEX_REG_INT_REGS_LOW8_R6: + return "R6"; + case HEX_REG_INT_REGS_LOW8_R5: + return "R5"; + case HEX_REG_INT_REGS_LOW8_R4: + return "R4"; + case HEX_REG_INT_REGS_LOW8_R3: + return "R3"; + case HEX_REG_INT_REGS_LOW8_R2: + return "R2"; + case HEX_REG_INT_REGS_LOW8_R1: + return "R1"; + case HEX_REG_INT_REGS_LOW8_R0: + return "R0"; + } +} + +char *hex_get_mod_regs(int opcode_reg) { + opcode_reg |= 6; + + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_MOD_REGS_M0: + return "M0"; + case HEX_REG_MOD_REGS_M1: + return "M1"; + } +} + +char *hex_get_pred_regs(int opcode_reg) { + switch (opcode_reg) { + default: + rz_warn_if_reached(); + return ""; + case HEX_REG_PRED_REGS_P0: + return "P0"; + case HEX_REG_PRED_REGS_P1: + return "P1"; + case HEX_REG_PRED_REGS_P2: + return "P2"; + case HEX_REG_PRED_REGS_P3: + return "P3"; + } +} + +inline bool hex_if_duplex(uint32_t insn_word) { + if (((insn_word & 0xc000) >> 18) == 0) { + return true; + } + return false; +} + +static inline bool is_last_instr(const ut8 parse_bits) { + // Duplex instr. (parse bits = 0) are always the last. + return ((parse_bits == 0x3) || (parse_bits == 0x0)); +} + +static inline bool is_endloop0_pkt(const ut8 pi_0, const ut8 pi_1) { + return ((pi_0 == 0x2) && ((pi_1 == 0x1) || (pi_1 == 0x3))); +} + +static inline bool is_endloop1_pkt(const ut8 pi_0, const ut8 pi_1) { + return ((pi_0 == 0x1) && (pi_1 == 0x2)); +} + +static inline bool is_endloop01_pkt(const ut8 pi_0, const ut8 pi_1) { + return ((pi_0 == 0x2) && (pi_1 == 0x2)); +} + +void hex_set_pkt_info(HexPktInfo *i_pkt_info) { + static HexPkt pkt = { 0 }; // Current packet + static ut8 i = 0; // Index of the instruction in the current packet. + static ut8 p0 = 255; + static ut8 p1 = 255; + static bool new_pkt_starts = true; + + memcpy(&pkt.i_infos[i], i_pkt_info, sizeof(HexPktInfo)); + + // Parse instr. position in pkt + if (new_pkt_starts && is_last_instr(i_pkt_info->parse_bits)) { // Single instruction packet. + // TODO No indent in visual mode for "[" without spaces. + // Possible cause: 2 extra bytes in UTF-8 chars are printed as spaces? + strncpy(i_pkt_info->syntax_prefix, "[ ", 8); + i_pkt_info->first_insn = true; + i_pkt_info->last_insn = true; + new_pkt_starts = true; + i = 0; + } else if (new_pkt_starts) { + strncpy(i_pkt_info->syntax_prefix, "/", 8); // TODO Add utf8 option "┌" + i_pkt_info->first_insn = true; + new_pkt_starts = false; + // Just in case evil persons set the parsing bits incorrectly and pkts with more than 4 instr. occur. + i = (i + 1) % 4; + } else if (is_last_instr(i_pkt_info->parse_bits)) { + strncpy(i_pkt_info->syntax_prefix, "\\", 8); // TODO Add utf8 option "└" + i_pkt_info->last_insn = true; + new_pkt_starts = true; + + p0 = pkt.i_infos[0].parse_bits; + p1 = pkt.i_infos[1].parse_bits; + + if (is_endloop01_pkt(p0, p1)) { + strncpy(i_pkt_info->syntax_postfix, " < endloop01", 16); // TODO Add utf8 option "∎" + i_pkt_info->loop_attr |= (HEX_ENDS_LOOP_0 | HEX_ENDS_LOOP_1); + } else if (is_endloop0_pkt(p0, p1)) { + strncpy(i_pkt_info->syntax_postfix, " < endloop0", 16); + i_pkt_info->loop_attr |= HEX_ENDS_LOOP_0; + } else if (is_endloop1_pkt(p0, p1)) { + strncpy(i_pkt_info->syntax_postfix, " < endloop1", 16); + i_pkt_info->loop_attr |= HEX_ENDS_LOOP_1; + } + i = 0; + } else { + strncpy(i_pkt_info->syntax_prefix, "|", 8); // TODO Add utf8 option "│" + new_pkt_starts = false; + i = (i + 1) % 4; + } +} + +static inline bool imm_is_extendable(ut32 const_ext, ut8 type) { + return ((const_ext != 0) && (type == HEX_OP_TYPE_IMM)); +} + +static inline bool imm_is_scaled(HexOpAttr attr) { + return (attr & HEX_OP_IMM_SCALED); +} + +void hex_op_extend(RZ_INOUT HexOp *op, bool set_new_extender) { + // Constant extender value + static ut32 constant_extender = 0; + + if (set_new_extender) { + constant_extender = op->op.imm; + return; + } + + if (imm_is_extendable(constant_extender, op->type)) { + if (imm_is_scaled(op->attr)) { + op->op.imm = (op->op.imm >> op->shift); // Extended immediate values won't get scaled. Redo it. + } + op->op.imm = ((op->op.imm) & 0x3F) | (constant_extender); + } + constant_extender = 0; +} diff --git a/rizin/librz/asm/arch/hexagon/hexagon.h b/rizin/librz/asm/arch/hexagon/hexagon.h new file mode 100644 index 00000000..8781b109 --- /dev/null +++ b/rizin/librz/asm/arch/hexagon/hexagon.h @@ -0,0 +1,410 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + +#ifndef HEXAGON_H +#define HEXAGON_H + +// TODO NOT IN USE +// Predicates - declare the predicate state +typedef enum { + HEX_NOPRED, // no conditional execution + HEX_PRED_TRUE, // if (Pd) ... + HEX_PRED_FALSE, // if (!Pd) ... + HEX_PRED_TRUE_NEW, // if (Pd.new) ... + HEX_PRED_FALSE_NEW, // if (!Pd.new) ... +} HexPred; + +// TODO NOT IN USE +// Pre/post-fixes, different types +typedef enum { + HEX_PF_RND = 1, // :rnd + HEX_PF_CRND = 1 << 1, // :crnd + HEX_PF_RAW = 1 << 2, // :raw + HEX_PF_CHOP = 1 << 3, // :chop + HEX_PF_SAT = 1 << 4, // :sat + HEX_PF_HI = 1 << 5, // :hi + HEX_PF_LO = 1 << 6, // :lo + HEX_PF_LSH1 = 1 << 7, // :<<1 + HEX_PF_LSH16 = 1 << 8, // :<<16 + HEX_PF_RSH1 = 1 << 9, // :>>1 + HEX_PF_NEG = 1 << 10, // :neg + HEX_PF_POS = 1 << 11, // :pos + HEX_PF_SCALE = 1 << 12, // :scale, for FMA instructions + HEX_PF_DEPRECATED = 1 << 15, // :deprecated +} HexPf; + +typedef enum { + HEX_OP_TYPE_IMM, + HEX_OP_TYPE_REG, + // TODO It might be useful to differ between control, HVX, guest regs etc. Also see HexOp +} HexOpType; + +// Attributes - .H/.L, const extender +typedef enum { + HEX_OP_CONST_EXT = 1 << 0, // Constant extender marker for Immediate + HEX_OP_REG_HI = 1 << 1, // Rn.H marker + HEX_OP_REG_LO = 1 << 2, // Rn.L marker + HEX_OP_REG_PAIR = 1 << 3, // Is this a register pair? + HEX_OP_IMM_SCALED = 1 << 4 // Is the immediate shifted? +} HexOpAttr; + +typedef enum { + HEX_NO_LOOP = 0, + HEX_LOOP_0 = 1, // Is packet of loop0 + HEX_LOOP_1 = 1 << 1, // Is packet of loop1 + HEX_ENDS_LOOP_0 = 1 << 2, // Packet ends loop0? + HEX_ENDS_LOOP_1 = 1 << 3, // Packet ends loop1? +} HexLoopAttr; + +typedef struct { + bool first_insn; + bool last_insn; + char syntax_prefix[8]; // Package indicator + char syntax_postfix[16]; // for ":endloop" string. + unsigned int parse_bits; + HexLoopAttr loop_attr; +} HexPktInfo; + +typedef struct { + ut8 type; + union { + ut8 reg; // + additional Hi or Lo selector // + additional shift // + additional :brev // + ut32 imm; + } op; + ut8 attr; + ut8 shift; +} HexOp; + +typedef struct { + int instruction; + ut32 mask; + // TODO + // ut16 pf; // additional prefixes (bitmap) + // TODO + // HexPred pred; // Predicate type + bool duplex; // is part of duplex container? + bool compound; // is part of compound instruction? + int shift; // Optional shift left is it true? + HexPktInfo pkt_info; + ut8 op_count; + HexOp ops[6]; + char mnem[128]; // Instruction mnemonic +} HexInsn; + +typedef struct { + HexPktInfo i_infos[4]; +} HexPkt; + +// Instruction container (currently only 2 instructions) +// Can handle duplexes +typedef struct { + bool duplex; + HexInsn ins[2]; // Or make it pointer + size? +} HexInsnCont; + +typedef enum { + HEX_REG_CTR_REGS_SA0 = 0, // c0 + HEX_REG_CTR_REGS_LC0 = 1, // c1 + HEX_REG_CTR_REGS_SA1 = 2, // c2 + HEX_REG_CTR_REGS_LC1 = 3, // c3 + HEX_REG_CTR_REGS_P3_0 = 4, // c4 + HEX_REG_CTR_REGS_C5 = 5, // c5 + HEX_REG_CTR_REGS_M0 = 6, // c6 + HEX_REG_CTR_REGS_M1 = 7, // c7 + HEX_REG_CTR_REGS_USR = 8, // c8 + HEX_REG_CTR_REGS_PC = 9, // c9 + HEX_REG_CTR_REGS_UGP = 10, // c10 + HEX_REG_CTR_REGS_GP = 11, // c11 + HEX_REG_CTR_REGS_CS0 = 12, // c12 + HEX_REG_CTR_REGS_CS1 = 13, // c13 + HEX_REG_CTR_REGS_UPCYCLELO = 14, // c14 + HEX_REG_CTR_REGS_UPCYCLEHI = 15, // c15 + HEX_REG_CTR_REGS_FRAMELIMIT = 16, // c16 + HEX_REG_CTR_REGS_FRAMEKEY = 17, // c17 + HEX_REG_CTR_REGS_PKTCOUNTLO = 18, // c18 + HEX_REG_CTR_REGS_PKTCOUNTHI = 19, // c19 + HEX_REG_CTR_REGS_UTIMERLO = 30, // c30 + HEX_REG_CTR_REGS_UTIMERHI = 31, // c31 +} HEX_CTR_REGS; // CtrRegs + +typedef enum { + HEX_REG_CTR_REGS64_C1_0 = 0, // lc0:sa0 + HEX_REG_CTR_REGS64_C3_2 = 2, // lc1:sa1 + HEX_REG_CTR_REGS64_C5_4 = 4, + HEX_REG_CTR_REGS64_C7_6 = 6, // m1:0 + HEX_REG_CTR_REGS64_C9_8 = 8, + HEX_REG_CTR_REGS64_C11_10 = 10, + HEX_REG_CTR_REGS64_CS = 12, // cs1:0 + HEX_REG_CTR_REGS64_UPCYCLE = 14, // upcycle + HEX_REG_CTR_REGS64_C17_16 = 16, + HEX_REG_CTR_REGS64_PKTCOUNT = 18, // pktcount + HEX_REG_CTR_REGS64_UTIMER = 30, // utimer +} HEX_CTR_REGS64; // CtrRegs64 + +typedef enum { + HEX_REG_DOUBLE_REGS_D0 = 0, + HEX_REG_DOUBLE_REGS_D1 = 2, + HEX_REG_DOUBLE_REGS_D2 = 4, + HEX_REG_DOUBLE_REGS_D3 = 6, + HEX_REG_DOUBLE_REGS_D4 = 8, + HEX_REG_DOUBLE_REGS_D5 = 10, + HEX_REG_DOUBLE_REGS_D6 = 12, + HEX_REG_DOUBLE_REGS_D7 = 14, + HEX_REG_DOUBLE_REGS_D8 = 16, + HEX_REG_DOUBLE_REGS_D9 = 18, + HEX_REG_DOUBLE_REGS_D10 = 20, + HEX_REG_DOUBLE_REGS_D11 = 22, + HEX_REG_DOUBLE_REGS_D12 = 24, + HEX_REG_DOUBLE_REGS_D13 = 26, + HEX_REG_DOUBLE_REGS_D14 = 28, + HEX_REG_DOUBLE_REGS_D15 = 30, // lr:fp +} HEX_DOUBLE_REGS; // DoubleRegs + +typedef enum { + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D0 = 0, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D1 = 2, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D2 = 4, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D3 = 6, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D8 = 16, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D9 = 18, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D10 = 20, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D11 = 22, +} HEX_GENERAL_DOUBLE_LOW8_REGS; // GeneralDoubleLow8Regs + +typedef enum { + HEX_REG_GENERAL_SUB_REGS_R0 = 0, + HEX_REG_GENERAL_SUB_REGS_R1 = 1, + HEX_REG_GENERAL_SUB_REGS_R2 = 2, + HEX_REG_GENERAL_SUB_REGS_R3 = 3, + HEX_REG_GENERAL_SUB_REGS_R4 = 4, + HEX_REG_GENERAL_SUB_REGS_R5 = 5, + HEX_REG_GENERAL_SUB_REGS_R6 = 6, + HEX_REG_GENERAL_SUB_REGS_R7 = 7, + HEX_REG_GENERAL_SUB_REGS_R16 = 16, + HEX_REG_GENERAL_SUB_REGS_R17 = 17, + HEX_REG_GENERAL_SUB_REGS_R18 = 18, + HEX_REG_GENERAL_SUB_REGS_R19 = 19, + HEX_REG_GENERAL_SUB_REGS_R20 = 20, + HEX_REG_GENERAL_SUB_REGS_R21 = 21, + HEX_REG_GENERAL_SUB_REGS_R22 = 22, + HEX_REG_GENERAL_SUB_REGS_R23 = 23, +} HEX_GENERAL_SUB_REGS; // GeneralSubRegs + +typedef enum { + HEX_REG_GUEST_REGS_GELR = 0, // g0 + HEX_REG_GUEST_REGS_GSR = 1, // g1 + HEX_REG_GUEST_REGS_GOSP = 2, // g2 + HEX_REG_GUEST_REGS_G3 = 3, // g3 + HEX_REG_GUEST_REGS_G4 = 4, + HEX_REG_GUEST_REGS_G5 = 5, + HEX_REG_GUEST_REGS_G6 = 6, + HEX_REG_GUEST_REGS_G7 = 7, + HEX_REG_GUEST_REGS_G8 = 8, + HEX_REG_GUEST_REGS_G9 = 9, + HEX_REG_GUEST_REGS_G10 = 10, + HEX_REG_GUEST_REGS_G11 = 11, + HEX_REG_GUEST_REGS_G12 = 12, + HEX_REG_GUEST_REGS_G13 = 13, + HEX_REG_GUEST_REGS_G14 = 14, + HEX_REG_GUEST_REGS_G15 = 15, + HEX_REG_GUEST_REGS_GPMUCNT4 = 16, // g16 + HEX_REG_GUEST_REGS_GPMUCNT5 = 17, // g17 + HEX_REG_GUEST_REGS_GPMUCNT6 = 18, // g18 + HEX_REG_GUEST_REGS_GPMUCNT7 = 19, // g19 + HEX_REG_GUEST_REGS_G20 = 20, + HEX_REG_GUEST_REGS_G21 = 21, + HEX_REG_GUEST_REGS_G22 = 22, + HEX_REG_GUEST_REGS_G23 = 23, + HEX_REG_GUEST_REGS_GPCYCLELO = 24, // g24 + HEX_REG_GUEST_REGS_GPCYCLEHI = 25, // g25 + HEX_REG_GUEST_REGS_GPMUCNT0 = 26, // g26 + HEX_REG_GUEST_REGS_GPMUCNT1 = 27, // g27 + HEX_REG_GUEST_REGS_GPMUCNT2 = 28, // g28 + HEX_REG_GUEST_REGS_GPMUCNT3 = 29, // g29 + HEX_REG_GUEST_REGS_G30 = 30, + HEX_REG_GUEST_REGS_G31 = 31, +} HEX_GUEST_REGS; // GuestRegs + +typedef enum { + HEX_REG_GUEST_REGS64_G1_0 = 0, + HEX_REG_GUEST_REGS64_G3_2 = 2, + HEX_REG_GUEST_REGS64_G5_4 = 4, + HEX_REG_GUEST_REGS64_G7_6 = 6, + HEX_REG_GUEST_REGS64_G9_8 = 8, + HEX_REG_GUEST_REGS64_G11_10 = 10, + HEX_REG_GUEST_REGS64_G13_12 = 12, + HEX_REG_GUEST_REGS64_G15_14 = 14, + HEX_REG_GUEST_REGS64_G17_16 = 16, + HEX_REG_GUEST_REGS64_G19_18 = 18, + HEX_REG_GUEST_REGS64_G21_20 = 20, + HEX_REG_GUEST_REGS64_G23_22 = 22, + HEX_REG_GUEST_REGS64_G25_24 = 24, + HEX_REG_GUEST_REGS64_G27_26 = 26, + HEX_REG_GUEST_REGS64_G29_28 = 28, + HEX_REG_GUEST_REGS64_G31_30 = 30, +} HEX_GUEST_REGS64; // GuestRegs64 + +typedef enum { + HEX_REG_HVX_QR_Q0 = 0, + HEX_REG_HVX_QR_Q1 = 1, + HEX_REG_HVX_QR_Q2 = 2, + HEX_REG_HVX_QR_Q3 = 3, +} HEX_HVX_QR; // HvxQR + +typedef enum { + HEX_REG_HVX_VQR_VQ0 = 0, + HEX_REG_HVX_VQR_VQ1 = 4, + HEX_REG_HVX_VQR_VQ2 = 8, + HEX_REG_HVX_VQR_VQ3 = 12, + HEX_REG_HVX_VQR_VQ4 = 16, + HEX_REG_HVX_VQR_VQ5 = 20, + HEX_REG_HVX_VQR_VQ6 = 24, + HEX_REG_HVX_VQR_VQ7 = 28, +} HEX_HVX_VQR; // HvxVQR + +typedef enum { + HEX_REG_HVX_VR_V0 = 0, + HEX_REG_HVX_VR_V1 = 1, + HEX_REG_HVX_VR_V2 = 2, + HEX_REG_HVX_VR_V3 = 3, + HEX_REG_HVX_VR_V4 = 4, + HEX_REG_HVX_VR_V5 = 5, + HEX_REG_HVX_VR_V6 = 6, + HEX_REG_HVX_VR_V7 = 7, + HEX_REG_HVX_VR_V8 = 8, + HEX_REG_HVX_VR_V9 = 9, + HEX_REG_HVX_VR_V10 = 10, + HEX_REG_HVX_VR_V11 = 11, + HEX_REG_HVX_VR_V12 = 12, + HEX_REG_HVX_VR_V13 = 13, + HEX_REG_HVX_VR_V14 = 14, + HEX_REG_HVX_VR_V15 = 15, + HEX_REG_HVX_VR_V16 = 16, + HEX_REG_HVX_VR_V17 = 17, + HEX_REG_HVX_VR_V18 = 18, + HEX_REG_HVX_VR_V19 = 19, + HEX_REG_HVX_VR_V20 = 20, + HEX_REG_HVX_VR_V21 = 21, + HEX_REG_HVX_VR_V22 = 22, + HEX_REG_HVX_VR_V23 = 23, + HEX_REG_HVX_VR_V24 = 24, + HEX_REG_HVX_VR_V25 = 25, + HEX_REG_HVX_VR_V26 = 26, + HEX_REG_HVX_VR_V27 = 27, + HEX_REG_HVX_VR_V28 = 28, + HEX_REG_HVX_VR_V29 = 29, + HEX_REG_HVX_VR_V30 = 30, + HEX_REG_HVX_VR_V31 = 31, +} HEX_HVX_VR; // HvxVR + +typedef enum { + HEX_REG_HVX_WR_W0 = 0, + HEX_REG_HVX_WR_W1 = 2, + HEX_REG_HVX_WR_W2 = 4, + HEX_REG_HVX_WR_W3 = 6, + HEX_REG_HVX_WR_W4 = 8, + HEX_REG_HVX_WR_W5 = 10, + HEX_REG_HVX_WR_W6 = 12, + HEX_REG_HVX_WR_W7 = 14, + HEX_REG_HVX_WR_W8 = 16, + HEX_REG_HVX_WR_W9 = 18, + HEX_REG_HVX_WR_W10 = 20, + HEX_REG_HVX_WR_W11 = 22, + HEX_REG_HVX_WR_W12 = 24, + HEX_REG_HVX_WR_W13 = 26, + HEX_REG_HVX_WR_W14 = 28, + HEX_REG_HVX_WR_W15 = 30, +} HEX_HVX_WR; // HvxWR + +typedef enum { + HEX_REG_INT_REGS_R0 = 0, + HEX_REG_INT_REGS_R1 = 1, + HEX_REG_INT_REGS_R2 = 2, + HEX_REG_INT_REGS_R3 = 3, + HEX_REG_INT_REGS_R4 = 4, + HEX_REG_INT_REGS_R5 = 5, + HEX_REG_INT_REGS_R6 = 6, + HEX_REG_INT_REGS_R7 = 7, + HEX_REG_INT_REGS_R8 = 8, + HEX_REG_INT_REGS_R9 = 9, + HEX_REG_INT_REGS_R10 = 10, + HEX_REG_INT_REGS_R11 = 11, + HEX_REG_INT_REGS_R12 = 12, + HEX_REG_INT_REGS_R13 = 13, + HEX_REG_INT_REGS_R14 = 14, + HEX_REG_INT_REGS_R15 = 15, + HEX_REG_INT_REGS_R16 = 16, + HEX_REG_INT_REGS_R17 = 17, + HEX_REG_INT_REGS_R18 = 18, + HEX_REG_INT_REGS_R19 = 19, + HEX_REG_INT_REGS_R20 = 20, + HEX_REG_INT_REGS_R21 = 21, + HEX_REG_INT_REGS_R22 = 22, + HEX_REG_INT_REGS_R23 = 23, + HEX_REG_INT_REGS_R24 = 24, + HEX_REG_INT_REGS_R25 = 25, + HEX_REG_INT_REGS_R26 = 26, + HEX_REG_INT_REGS_R27 = 27, + HEX_REG_INT_REGS_R28 = 28, + HEX_REG_INT_REGS_R29 = 29, // sp + HEX_REG_INT_REGS_R30 = 30, // fp + HEX_REG_INT_REGS_R31 = 31, // lr +} HEX_INT_REGS; // IntRegs + +typedef enum { + HEX_REG_INT_REGS_LOW8_R0 = 0, + HEX_REG_INT_REGS_LOW8_R1 = 1, + HEX_REG_INT_REGS_LOW8_R2 = 2, + HEX_REG_INT_REGS_LOW8_R3 = 3, + HEX_REG_INT_REGS_LOW8_R4 = 4, + HEX_REG_INT_REGS_LOW8_R5 = 5, + HEX_REG_INT_REGS_LOW8_R6 = 6, + HEX_REG_INT_REGS_LOW8_R7 = 7, +} HEX_INT_REGS_LOW8; // IntRegsLow8 + +typedef enum { + HEX_REG_MOD_REGS_M0 = 6, // c6 + HEX_REG_MOD_REGS_M1 = 7, // c7 +} HEX_MOD_REGS; // ModRegs + +typedef enum { + HEX_REG_PRED_REGS_P0 = 0, + HEX_REG_PRED_REGS_P1 = 1, + HEX_REG_PRED_REGS_P2 = 2, + HEX_REG_PRED_REGS_P3 = 3, +} HEX_PRED_REGS; // PredRegs + +#define BIT_MASK(len) (BIT(len) - 1) +#define BF_MASK(start, len) (BIT_MASK(len) << (start)) +#define BF_PREP(x, start, len) (((x)&BIT_MASK(len)) << (start)) +#define BF_GET(y, start, len) (((y) >> (start)) & BIT_MASK(len)) +#define BF_GETB(y, start, end) (BF_GET((y), (start), (end) - (start) + 1) + +char *hex_get_ctr_regs(int opcode_reg); +char *hex_get_ctr_regs64(int opcode_reg); +char *hex_get_double_regs(int opcode_reg); +char *hex_get_general_double_low8_regs(int opcode_reg); +char *hex_get_general_sub_regs(int opcode_reg); +char *hex_get_guest_regs(int opcode_reg); +char *hex_get_guest_regs64(int opcode_reg); +char *hex_get_hvx_qr(int opcode_reg); +char *hex_get_hvx_vqr(int opcode_reg); +char *hex_get_hvx_vr(int opcode_reg); +char *hex_get_hvx_wr(int opcode_reg); +char *hex_get_int_regs(int opcode_reg); +char *hex_get_int_regs_low8(int opcode_reg); +char *hex_get_mod_regs(int opcode_reg); +char *hex_get_pred_regs(int opcode_reg); + +bool hex_if_duplex(ut32 insn_word); +void hex_op_extend(HexOp *op, bool set_new_extender); +void hex_set_pkt_info(RZ_INOUT HexPktInfo *pkt_info); +int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr); + +#endif \ No newline at end of file diff --git a/rizin/librz/asm/arch/hexagon/hexagon_disas.c b/rizin/librz/asm/arch/hexagon/hexagon_disas.c new file mode 100644 index 00000000..78a2d367 --- /dev/null +++ b/rizin/librz/asm/arch/hexagon/hexagon_disas.c @@ -0,0 +1,64400 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + +#include +#include +#include +#include +#include +#include "hexagon.h" +#include "hexagon_insn.h" + +extern ut32 constant_extender; + +int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) { + char signed_imm[16] = ""; + // DUPLEXES + if (((hi_u32 >> 14) & 0x3) == 0) { + switch ((((hi_u32 >> 29) & 0xF) << 1) | ((hi_u32 >> 13) & 1)) { + case 0x0: + if ((hi_u32 & 0xf000f000) == 0x0) { + // 0000IIIISSSSDDDDEE00iiiissssdddd | RD = memw(RS+#II) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f000) == 0x1000) { + // 0000IIIISSSSDDDDEE01iiiissssdddd | RD = memw(RS+#II) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f000) == 0x10001000) { + // 0001IIIISSSSDDDDEE01iiiissssdddd | RD = memub(RS+#II) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x1: + if ((hi_u32 & 0xf000ffff) == 0x3f00) { + // 0000iiiissssddddEE11111100000000 | Rd = memw(Rs+#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f00) { + // 0001iiiissssddddEE11111100000000 | Rd = memub(Rs+#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc0) { + // 0000iiiissssddddEE11111111000000 | Rd = memw(Rs+#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc0) { + // 0001iiiissssddddEE11111111000000 | Rd = memub(Rs+#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc5) { + // 0000iiiissssddddEE11111111000101 | Rd = memw(Rs+#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc5) { + // 0001iiiissssddddEE11111111000101 | Rd = memub(Rs+#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc7) { + // 0000iiiissssddddEE11111111000111 | Rd = memw(Rs+#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc7) { + // 0001iiiissssddddEE11111111000111 | Rd = memub(Rs+#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc4) { + // 0000iiiissssddddEE11111111000100 | Rd = memw(Rs+#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc4) { + // 0001iiiissssddddEE11111111000100 | Rd = memub(Rs+#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc6) { + // 0000iiiissssddddEE11111111000110 | Rd = memw(Rs+#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc6) { + // 0001iiiissssddddEE11111111000110 | Rd = memub(Rs+#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0x3000) { + // 0000IIIISSSSDDDDEE110iiissssdddd | RD = memw(RS+#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0x10003000) { + // 0001IIIISSSSDDDDEE110iiissssdddd | RD = memub(RS+#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0x3e00) { + // 0000IIIIssssDDDDEE111110iiiiiddd | RD = memw(Rs+#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0x10003e00) { + // 0001IIIIssssDDDDEE111110iiiiiddd | RD = memub(Rs+#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0x2000) { + // 0000IIIISSSSDDDDEE100iiissssdddd | RD = memw(RS+#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0x10002000) { + // 0001IIIISSSSDDDDEE100iiissssdddd | RD = memub(RS+#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0x3c00) { + // 0000IIIIssssDDDDEE11110iiiiidddd | RD = memw(Rs+#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0x10003c00) { + // 0001IIIIssssDDDDEE11110iiiiidddd | RD = memub(Rs+#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0x2800) { + // 0000IIIISSSSDDDDEE101iiissssdddd | RD = memw(RS+#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0x10002800) { + // 0001IIIISSSSDDDDEE101iiissssdddd | RD = memub(RS+#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3f40) { + // 0000iiiissssddddEE11111101000000 | Rd = memw(Rs+#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f40) { + // 0001iiiissssddddEE11111101000000 | Rd = memub(Rs+#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3f45) { + // 0000iiiissssddddEE11111101000101 | Rd = memw(Rs+#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f45) { + // 0001iiiissssddddEE11111101000101 | Rd = memub(Rs+#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3f47) { + // 0000iiiissssddddEE11111101000111 | Rd = memw(Rs+#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f47) { + // 0001iiiissssddddEE11111101000111 | Rd = memub(Rs+#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3f44) { + // 0000iiiissssddddEE11111101000100 | Rd = memw(Rs+#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f44) { + // 0001iiiissssddddEE11111101000100 | Rd = memub(Rs+#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x3f46) { + // 0000iiiissssddddEE11111101000110 | Rd = memw(Rs+#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f46) { + // 0001iiiissssddddEE11111101000110 | Rd = memub(Rs+#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x2: + if ((hi_u32 & 0xffffffff) == 0x3f001f00) { + // 0011111100000000EE01111100000000 | deallocframe ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; deallocframe %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f00) { + // 00110iiissssddddEE01111100000000 | Rd = memb(Rs+#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f00) { + // 00111110iiiiidddEE01111100000000 | Rdd = memd(r29+#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f00) { + // 00100iiissssddddEE01111100000000 | Rd = memh(Rs+#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f00) { + // 0011110iiiiiddddEE01111100000000 | Rd = memw(r29+#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f00) { + // 00101iiissssddddEE01111100000000 | Rd = memuh(Rs+#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc0) { + // 0011111100000000EE01111111000000 | deallocframe ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc0) { + // 00110iiissssddddEE01111111000000 | Rd = memb(Rs+#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc0) { + // 00111110iiiiidddEE01111111000000 | Rdd = memd(r29+#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc0) { + // 00100iiissssddddEE01111111000000 | Rd = memh(Rs+#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc0) { + // 0011110iiiiiddddEE01111111000000 | Rd = memw(r29+#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc0) { + // 00101iiissssddddEE01111111000000 | Rd = memuh(Rs+#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc0) { + // 0011111101000000EE01111111000000 | dealloc_return ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc0) { + // 0011111101000101EE01111111000000 | if (!p0) dealloc_return ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc0) { + // 0011111101000111EE01111111000000 | if (!p0.new) dealloc_return:nt ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc0) { + // 0011111101000100EE01111111000000 | if (p0) dealloc_return ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc0) { + // 0011111101000110EE01111111000000 | if (p0.new) dealloc_return:nt ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc5) { + // 0011111100000000EE01111111000101 | deallocframe ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc5) { + // 00110iiissssddddEE01111111000101 | Rd = memb(Rs+#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc5) { + // 00111110iiiiidddEE01111111000101 | Rdd = memd(r29+#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc5) { + // 00100iiissssddddEE01111111000101 | Rd = memh(Rs+#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc5) { + // 0011110iiiiiddddEE01111111000101 | Rd = memw(r29+#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc5) { + // 00101iiissssddddEE01111111000101 | Rd = memuh(Rs+#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc5) { + // 0011111101000000EE01111111000101 | dealloc_return ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc5) { + // 0011111101000101EE01111111000101 | if (!p0) dealloc_return ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc5) { + // 0011111101000111EE01111111000101 | if (!p0.new) dealloc_return:nt ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc5) { + // 0011111101000100EE01111111000101 | if (p0) dealloc_return ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc5) { + // 0011111101000110EE01111111000101 | if (p0.new) dealloc_return:nt ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc7) { + // 0011111100000000EE01111111000111 | deallocframe ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc7) { + // 00110iiissssddddEE01111111000111 | Rd = memb(Rs+#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc7) { + // 00111110iiiiidddEE01111111000111 | Rdd = memd(r29+#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc7) { + // 00100iiissssddddEE01111111000111 | Rd = memh(Rs+#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc7) { + // 0011110iiiiiddddEE01111111000111 | Rd = memw(r29+#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc7) { + // 00101iiissssddddEE01111111000111 | Rd = memuh(Rs+#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc7) { + // 0011111101000000EE01111111000111 | dealloc_return ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc7) { + // 0011111101000101EE01111111000111 | if (!p0) dealloc_return ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc7) { + // 0011111101000111EE01111111000111 | if (!p0.new) dealloc_return:nt ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc7) { + // 0011111101000100EE01111111000111 | if (p0) dealloc_return ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc7) { + // 0011111101000110EE01111111000111 | if (p0.new) dealloc_return:nt ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc4) { + // 0011111100000000EE01111111000100 | deallocframe ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc4) { + // 00110iiissssddddEE01111111000100 | Rd = memb(Rs+#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc4) { + // 00111110iiiiidddEE01111111000100 | Rdd = memd(r29+#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc4) { + // 00100iiissssddddEE01111111000100 | Rd = memh(Rs+#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc4) { + // 0011110iiiiiddddEE01111111000100 | Rd = memw(r29+#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc4) { + // 00101iiissssddddEE01111111000100 | Rd = memuh(Rs+#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc4) { + // 0011111101000000EE01111111000100 | dealloc_return ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc4) { + // 0011111101000101EE01111111000100 | if (!p0) dealloc_return ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc4) { + // 0011111101000111EE01111111000100 | if (!p0.new) dealloc_return:nt ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc4) { + // 0011111101000100EE01111111000100 | if (p0) dealloc_return ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc4) { + // 0011111101000110EE01111111000100 | if (p0.new) dealloc_return:nt ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc6) { + // 0011111100000000EE01111111000110 | deallocframe ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc6) { + // 00110iiissssddddEE01111111000110 | Rd = memb(Rs+#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc6) { + // 00111110iiiiidddEE01111111000110 | Rdd = memd(r29+#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc6) { + // 00100iiissssddddEE01111111000110 | Rd = memh(Rs+#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc6) { + // 0011110iiiiiddddEE01111111000110 | Rd = memw(r29+#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc6) { + // 00101iiissssddddEE01111111000110 | Rd = memuh(Rs+#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc6) { + // 0011111101000000EE01111111000110 | dealloc_return ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc6) { + // 0011111101000101EE01111111000110 | if (!p0) dealloc_return ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc6) { + // 0011111101000111EE01111111000110 | if (!p0.new) dealloc_return:nt ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc6) { + // 0011111101000100EE01111111000110 | if (p0) dealloc_return ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc6) { + // 0011111101000110EE01111111000110 | if (p0.new) dealloc_return:nt ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x30001000) { + // 00110IIISSSSDDDDEE010iiissssdddd | RD = memb(RS+#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x20001000) { + // 00100IIISSSSDDDDEE010iiissssdddd | RD = memh(RS+#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x28001000) { + // 00101IIISSSSDDDDEE010iiissssdddd | RD = memuh(RS+#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x30001e00) { + // 00110IIIssssDDDDEE011110iiiiiddd | RD = memb(Rs+#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x3e001e00) { + // 00111110IIIIIDDDEE011110iiiiiddd | RDD = memd(r29+#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x20001e00) { + // 00100IIIssssDDDDEE011110iiiiiddd | RD = memh(Rs+#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0x3c001e00) { + // 0011110IIIIIDDDDEE011110iiiiiddd | RD = memw(r29+#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x28001e00) { + // 00101IIIssssDDDDEE011110iiiiiddd | RD = memuh(Rs+#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x20000000) { + // 00100IIISSSSDDDDEE000iiissssdddd | RD = memh(RS+#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0x30001c00) { + // 00110IIIssssDDDDEE01110iiiiidddd | RD = memb(Rs+#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0x20001c00) { + // 00100IIIssssDDDDEE01110iiiiidddd | RD = memh(Rs+#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00fe00) == 0x3c001c00) { + // 0011110IIIIIDDDDEE01110iiiiidddd | RD = memw(r29+#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0x28001c00) { + // 00101IIIssssDDDDEE01110iiiiidddd | RD = memuh(Rs+#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x20000800) { + // 00100IIISSSSDDDDEE001iiissssdddd | RD = memh(RS+#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x28000800) { + // 00101IIISSSSDDDDEE001iiissssdddd | RD = memuh(RS+#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f40) { + // 0011111100000000EE01111101000000 | deallocframe ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; dealloc_return %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f40) { + // 00110iiissssddddEE01111101000000 | Rd = memb(Rs+#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f40) { + // 00111110iiiiidddEE01111101000000 | Rdd = memd(r29+#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f40) { + // 00100iiissssddddEE01111101000000 | Rd = memh(Rs+#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f40) { + // 0011110iiiiiddddEE01111101000000 | Rd = memw(r29+#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f40) { + // 00101iiissssddddEE01111101000000 | Rd = memuh(Rs+#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f40) { + // 0011111101000000EE01111101000000 | dealloc_return ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; dealloc_return %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f45) { + // 0011111100000000EE01111101000101 | deallocframe ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f45) { + // 00110iiissssddddEE01111101000101 | Rd = memb(Rs+#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f45) { + // 00111110iiiiidddEE01111101000101 | Rdd = memd(r29+#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f45) { + // 00100iiissssddddEE01111101000101 | Rd = memh(Rs+#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f45) { + // 0011110iiiiiddddEE01111101000101 | Rd = memw(r29+#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f45) { + // 00101iiissssddddEE01111101000101 | Rd = memuh(Rs+#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f45) { + // 0011111101000000EE01111101000101 | dealloc_return ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f451f45) { + // 0011111101000101EE01111101000101 | if (!p0) dealloc_return ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f441f45) { + // 0011111101000100EE01111101000101 | if (p0) dealloc_return ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f47) { + // 0011111100000000EE01111101000111 | deallocframe ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f47) { + // 00110iiissssddddEE01111101000111 | Rd = memb(Rs+#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f47) { + // 00111110iiiiidddEE01111101000111 | Rdd = memd(r29+#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f47) { + // 00100iiissssddddEE01111101000111 | Rd = memh(Rs+#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f47) { + // 0011110iiiiiddddEE01111101000111 | Rd = memw(r29+#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f47) { + // 00101iiissssddddEE01111101000111 | Rd = memuh(Rs+#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f47) { + // 0011111101000000EE01111101000111 | dealloc_return ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f451f47) { + // 0011111101000101EE01111101000111 | if (!p0) dealloc_return ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f471f47) { + // 0011111101000111EE01111101000111 | if (!p0.new) dealloc_return:nt ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f441f47) { + // 0011111101000100EE01111101000111 | if (p0) dealloc_return ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f461f47) { + // 0011111101000110EE01111101000111 | if (p0.new) dealloc_return:nt ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f44) { + // 0011111100000000EE01111101000100 | deallocframe ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f44) { + // 00110iiissssddddEE01111101000100 | Rd = memb(Rs+#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f44) { + // 00111110iiiiidddEE01111101000100 | Rdd = memd(r29+#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f44) { + // 00100iiissssddddEE01111101000100 | Rd = memh(Rs+#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f44) { + // 0011110iiiiiddddEE01111101000100 | Rd = memw(r29+#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f44) { + // 00101iiissssddddEE01111101000100 | Rd = memuh(Rs+#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f44) { + // 0011111101000000EE01111101000100 | dealloc_return ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f441f44) { + // 0011111101000100EE01111101000100 | if (p0) dealloc_return ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f46) { + // 0011111100000000EE01111101000110 | deallocframe ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s deallocframe ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f46) { + // 00110iiissssddddEE01111101000110 | Rd = memb(Rs+#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f46) { + // 00111110iiiiidddEE01111101000110 | Rdd = memd(r29+#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f46) { + // 00100iiissssddddEE01111101000110 | Rd = memh(Rs+#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f46) { + // 0011110iiiiiddddEE01111101000110 | Rd = memw(r29+#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f46) { + // 00101iiissssddddEE01111101000110 | Rd = memuh(Rs+#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f46) { + // 0011111101000000EE01111101000110 | dealloc_return ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s dealloc_return ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f451f46) { + // 0011111101000101EE01111101000110 | if (!p0) dealloc_return ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f441f46) { + // 0011111101000100EE01111101000110 | if (p0) dealloc_return ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffffff) == 0x3f461f46) { + // 0011111101000110EE01111101000110 | if (p0.new) dealloc_return:nt ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 0; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x3: + if ((hi_u32 & 0xf800ff00) == 0x20003800) { + // 00100iiiiiiiXXXXEE111000ssssxxxx | RX = add(RXin,#Ii) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RX16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // RX16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x38003800) { + // 00111000SSSSXXXXEE111000ssssxxxx | RX = add(RXin,RS) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RX16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // RX16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003800) { + // 001011iiiiiiddddEE111000ssssxxxx | Rd = add(r29,#Ii) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x32003800) { + // 00110010SSSSddddEE111000ssssxxxx | Rd = and(RS,#1) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x33003800) { + // 00110011SSSSddddEE111000ssssxxxx | Rd = add(RS,#n1) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x31003800) { + // 00110001SSSSddddEE111000ssssxxxx | Rd = add(RS,#1) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003800) { + // 001010iiiiiiddddEE111000ssssxxxx | Rd = #Ii ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x35003800) { + // 00110101SSSSddddEE111000ssssxxxx | Rd = sxtb(RS) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x34003800) { + // 00110100SSSSddddEE111000ssssxxxx | Rd = sxth(RS) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x30003800) { + // 00110000SSSSddddEE111000ssssxxxx | Rd = RS ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x37003800) { + // 00110111SSSSddddEE111000ssssxxxx | Rd = and(RS,#255) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x36003800) { + // 00110110SSSSddddEE111000ssssxxxx | Rd = zxth(RS) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ADDRX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = add(%sin,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fc00) == 0x20002c00) { + // 00100IIIIIIIxxxxEE1011iiiiiidddd | Rx = add(Rxin,#II) ; Rd = add(r29,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ADDSP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = add(R29,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fc00) == 0x2c002c00) { + // 001011IIIIIIDDDDEE1011iiiiiidddd | RD = add(r29,#II) ; Rd = add(r29,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ADDSP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = add(R29,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fc00) == 0x28002c00) { + // 001010IIIIIIDDDDEE1011iiiiiidddd | RD = #II ; Rd = add(r29,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ADDSP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = add(R29,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x20003200) { + // 00100iiiiiiixxxxEE110010ssssdddd | Rx = add(Rxin,#Ii) ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_AND1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = and(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003200) { + // 001011iiiiiiDDDDEE110010ssssdddd | RD = add(r29,#Ii) ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_AND1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = and(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x32003200) { + // 00110010SSSSDDDDEE110010ssssdddd | RD = and(RS,#1) ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_AND1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = and(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x31003200) { + // 00110001SSSSDDDDEE110010ssssdddd | RD = add(RS,#1) ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_AND1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = and(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003200) { + // 001010iiiiiiDDDDEE110010ssssdddd | RD = #Ii ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_AND1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = and(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x30003200) { + // 00110000SSSSDDDDEE110010ssssdddd | RD = RS ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_AND1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = and(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a70) { + // 00100iiiiiiixxxxEE1110100111dddd | Rx = add(Rxin,#Ii) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a70) { + // 00111000ssssxxxxEE1110100111dddd | Rx = add(Rxin,Rs) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a70) { + // 001011iiiiiiDDDDEE1110100111dddd | RD = add(r29,#Ii) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a70) { + // 00110010ssssDDDDEE1110100111dddd | RD = and(Rs,#1) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a703a70) { + // 001110100111DDDDEE1110100111dddd | if (!p0) RD = #0 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a503a70) { + // 001110100101DDDDEE1110100111dddd | if (!p0.new) RD = #0 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a603a70) { + // 001110100110DDDDEE1110100111dddd | if (p0) RD = #0 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a403a70) { + // 001110100100DDDDEE1110100111dddd | if (p0.new) RD = #0 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a70) { + // 00111001ssss00iiEE1110100111dddd | p0 = cmp.eq(Rs,#Ii) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a70) { + // 00110011ssssDDDDEE1110100111dddd | RD = add(Rs,#n1) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a70) { + // 00110001ssssDDDDEE1110100111dddd | RD = add(Rs,#1) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a70) { + // 001010iiiiiiDDDDEE1110100111dddd | RD = #Ii ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = ##0x%x ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a70) { + // 001110100000DDDDEE1110100111dddd | RD = #n1 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a70) { + // 00110101ssssDDDDEE1110100111dddd | RD = sxtb(Rs) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a70) { + // 00110100ssssDDDDEE1110100111dddd | RD = sxth(Rs) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a70) { + // 00110000ssssDDDDEE1110100111dddd | RD = Rs ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = %s ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a70) { + // 00110111ssssDDDDEE1110100111dddd | RD = and(Rs,#255) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a70) { + // 00110110ssssDDDDEE1110100111dddd | RD = zxth(Rs) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (!P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a50) { + // 00100iiiiiiixxxxEE1110100101dddd | Rx = add(Rxin,#Ii) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a50) { + // 00111000ssssxxxxEE1110100101dddd | Rx = add(Rxin,Rs) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a50) { + // 001011iiiiiiDDDDEE1110100101dddd | RD = add(r29,#Ii) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a50) { + // 00110010ssssDDDDEE1110100101dddd | RD = and(Rs,#1) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a503a50) { + // 001110100101DDDDEE1110100101dddd | if (!p0.new) RD = #0 ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a403a50) { + // 001110100100DDDDEE1110100101dddd | if (p0.new) RD = #0 ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a50) { + // 00111001ssss00iiEE1110100101dddd | p0 = cmp.eq(Rs,#Ii) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a50) { + // 00110011ssssDDDDEE1110100101dddd | RD = add(Rs,#n1) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a50) { + // 00110001ssssDDDDEE1110100101dddd | RD = add(Rs,#1) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a50) { + // 001010iiiiiiDDDDEE1110100101dddd | RD = #Ii ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = ##0x%x ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a50) { + // 001110100000DDDDEE1110100101dddd | RD = #n1 ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a50) { + // 00110101ssssDDDDEE1110100101dddd | RD = sxtb(Rs) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a50) { + // 00110100ssssDDDDEE1110100101dddd | RD = sxth(Rs) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a50) { + // 00110000ssssDDDDEE1110100101dddd | RD = Rs ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = %s ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a50) { + // 00110111ssssDDDDEE1110100101dddd | RD = and(Rs,#255) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a50) { + // 00110110ssssDDDDEE1110100101dddd | RD = zxth(Rs) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (!P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a60) { + // 00100iiiiiiixxxxEE1110100110dddd | Rx = add(Rxin,#Ii) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a60) { + // 00111000ssssxxxxEE1110100110dddd | Rx = add(Rxin,Rs) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a60) { + // 001011iiiiiiDDDDEE1110100110dddd | RD = add(r29,#Ii) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a60) { + // 00110010ssssDDDDEE1110100110dddd | RD = and(Rs,#1) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a503a60) { + // 001110100101DDDDEE1110100110dddd | if (!p0.new) RD = #0 ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a603a60) { + // 001110100110DDDDEE1110100110dddd | if (p0) RD = #0 ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a403a60) { + // 001110100100DDDDEE1110100110dddd | if (p0.new) RD = #0 ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a60) { + // 00111001ssss00iiEE1110100110dddd | p0 = cmp.eq(Rs,#Ii) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a60) { + // 00110011ssssDDDDEE1110100110dddd | RD = add(Rs,#n1) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a60) { + // 00110001ssssDDDDEE1110100110dddd | RD = add(Rs,#1) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a60) { + // 001010iiiiiiDDDDEE1110100110dddd | RD = #Ii ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = ##0x%x ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a60) { + // 001110100000DDDDEE1110100110dddd | RD = #n1 ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a60) { + // 00110101ssssDDDDEE1110100110dddd | RD = sxtb(Rs) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a60) { + // 00110100ssssDDDDEE1110100110dddd | RD = sxth(Rs) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a60) { + // 00110000ssssDDDDEE1110100110dddd | RD = Rs ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = %s ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a60) { + // 00110111ssssDDDDEE1110100110dddd | RD = and(Rs,#255) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a60) { + // 00110110ssssDDDDEE1110100110dddd | RD = zxth(Rs) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (P0) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a40) { + // 00100iiiiiiixxxxEE1110100100dddd | Rx = add(Rxin,#Ii) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a40) { + // 00111000ssssxxxxEE1110100100dddd | Rx = add(Rxin,Rs) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a40) { + // 001011iiiiiiDDDDEE1110100100dddd | RD = add(r29,#Ii) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a40) { + // 00110010ssssDDDDEE1110100100dddd | RD = and(Rs,#1) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a403a40) { + // 001110100100DDDDEE1110100100dddd | if (p0.new) RD = #0 ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a40) { + // 00111001ssss00iiEE1110100100dddd | p0 = cmp.eq(Rs,#Ii) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a40) { + // 00110011ssssDDDDEE1110100100dddd | RD = add(Rs,#n1) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a40) { + // 00110001ssssDDDDEE1110100100dddd | RD = add(Rs,#1) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a40) { + // 001010iiiiiiDDDDEE1110100100dddd | RD = #Ii ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = ##0x%x ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a40) { + // 001110100000DDDDEE1110100100dddd | RD = #n1 ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a40) { + // 00110101ssssDDDDEE1110100100dddd | RD = sxtb(Rs) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a40) { + // 00110100ssssDDDDEE1110100100dddd | RD = sxth(Rs) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a40) { + // 00110000ssssDDDDEE1110100100dddd | RD = Rs ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = %s ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a40) { + // 00110111ssssDDDDEE1110100100dddd | RD = and(Rs,#255) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a40) { + // 00110110ssssDDDDEE1110100100dddd | RD = zxth(Rs) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (P0.new) %s = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff0c) == 0x20003900) { + // 00100IIIIIIIxxxxEE111001ssss00ii | Rx = add(Rxin,#II) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff0c) == 0x38003900) { + // 00111000SSSSxxxxEE111001ssss00ii | Rx = add(Rxin,RS) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff0c) == 0x2c003900) { + // 001011IIIIIIddddEE111001ssss00ii | Rd = add(r29,#II) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff0c) == 0x32003900) { + // 00110010SSSSddddEE111001ssss00ii | Rd = and(RS,#1) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#1) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff0c) == 0x39003900) { + // 00111001SSSS00IIEE111001ssss00ii | p0 = cmp.eq(RS,#II) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff0c) == 0x33003900) { + // 00110011SSSSddddEE111001ssss00ii | Rd = add(RS,#n1) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff0c) == 0x31003900) { + // 00110001SSSSddddEE111001ssss00ii | Rd = add(RS,#1) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#1) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff0c) == 0x28003900) { + // 001010IIIIIIddddEE111001ssss00ii | Rd = #II ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = ##0x%x ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff0c) == 0x35003900) { + // 00110101SSSSddddEE111001ssss00ii | Rd = sxtb(RS) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = sxtb(%s) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff0c) == 0x34003900) { + // 00110100SSSSddddEE111001ssss00ii | Rd = sxth(RS) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = sxth(%s) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff0c) == 0x30003900) { + // 00110000SSSSddddEE111001ssss00ii | Rd = RS ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = %s ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff0c) == 0x37003900) { + // 00110111SSSSddddEE111001ssss00ii | Rd = and(RS,#255) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#255) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff0c) == 0x36003900) { + // 00110110SSSSddddEE111001ssss00ii | Rd = zxth(RS) ; p0 = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + sprintf(hi->mnem, "%s %s = zxth(%s) ; P0 = cmp.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff98) == 0x20003c00) { + // 00100IIIIIIIxxxxEE1111000ii00ddd | Rx = add(Rxin,#II) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x38003c00) { + // 00111000ssssxxxxEE1111000ii00ddd | Rx = add(Rxin,Rs) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff98) == 0x2c003c00) { + // 001011IIIIIIDDDDEE1111000ii00ddd | RD = add(r29,#II) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x32003c00) { + // 00110010ssssDDDDEE1111000ii00ddd | RD = and(Rs,#1) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a703c00) { + // 001110100111DDDDEE1111000ii00ddd | if (!p0) RD = #0 ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a503c00) { + // 001110100101DDDDEE1111000ii00ddd | if (!p0.new) RD = #0 ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a603c00) { + // 001110100110DDDDEE1111000ii00ddd | if (p0) RD = #0 ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a403c00) { + // 001110100100DDDDEE1111000ii00ddd | if (p0.new) RD = #0 ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff98) == 0x39003c00) { + // 00111001ssss00IIEE1111000ii00ddd | p0 = cmp.eq(Rs,#II) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c003c00) { + // 001111000II00DDDEE1111000ii00ddd | RDD = combine(#0,#II) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x33003c00) { + // 00110011ssssDDDDEE1111000ii00ddd | RD = add(Rs,#n1) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x31003c00) { + // 00110001ssssDDDDEE1111000ii00ddd | RD = add(Rs,#1) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c00) { + // 001010IIIIIIDDDDEE1111000ii00ddd | RD = #II ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a003c00) { + // 001110100000DDDDEE1111000ii00ddd | RD = #n1 ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = #-1 ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x35003c00) { + // 00110101ssssDDDDEE1111000ii00ddd | RD = sxtb(Rs) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x34003c00) { + // 00110100ssssDDDDEE1111000ii00ddd | RD = sxth(Rs) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x30003c00) { + // 00110000ssssDDDDEE1111000ii00ddd | RD = Rs ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = %s ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x37003c00) { + // 00110111ssssDDDDEE1111000ii00ddd | RD = and(Rs,#255) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x36003c00) { + // 00110110ssssDDDDEE1111000ii00ddd | RD = zxth(Rs) ; Rdd = combine(#0,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = combine(#0,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff98) == 0x20003c08) { + // 00100IIIIIIIxxxxEE1111000ii01ddd | Rx = add(Rxin,#II) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x38003c08) { + // 00111000ssssxxxxEE1111000ii01ddd | Rx = add(Rxin,Rs) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff98) == 0x2c003c08) { + // 001011IIIIIIDDDDEE1111000ii01ddd | RD = add(r29,#II) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x32003c08) { + // 00110010ssssDDDDEE1111000ii01ddd | RD = and(Rs,#1) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a703c08) { + // 001110100111DDDDEE1111000ii01ddd | if (!p0) RD = #0 ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a503c08) { + // 001110100101DDDDEE1111000ii01ddd | if (!p0.new) RD = #0 ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a603c08) { + // 001110100110DDDDEE1111000ii01ddd | if (p0) RD = #0 ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a403c08) { + // 001110100100DDDDEE1111000ii01ddd | if (p0.new) RD = #0 ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff98) == 0x39003c08) { + // 00111001ssss00IIEE1111000ii01ddd | p0 = cmp.eq(Rs,#II) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c003c08) { + // 001111000II00DDDEE1111000ii01ddd | RDD = combine(#0,#II) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c083c08) { + // 001111000II01DDDEE1111000ii01ddd | RDD = combine(#1,#II) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x33003c08) { + // 00110011ssssDDDDEE1111000ii01ddd | RD = add(Rs,#n1) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x31003c08) { + // 00110001ssssDDDDEE1111000ii01ddd | RD = add(Rs,#1) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c08) { + // 001010IIIIIIDDDDEE1111000ii01ddd | RD = #II ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a003c08) { + // 001110100000DDDDEE1111000ii01ddd | RD = #n1 ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = #-1 ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x35003c08) { + // 00110101ssssDDDDEE1111000ii01ddd | RD = sxtb(Rs) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x34003c08) { + // 00110100ssssDDDDEE1111000ii01ddd | RD = sxth(Rs) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x30003c08) { + // 00110000ssssDDDDEE1111000ii01ddd | RD = Rs ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = %s ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x37003c08) { + // 00110111ssssDDDDEE1111000ii01ddd | RD = and(Rs,#255) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x36003c08) { + // 00110110ssssDDDDEE1111000ii01ddd | RD = zxth(Rs) ; Rdd = combine(#1,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = combine(#1,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff98) == 0x20003c10) { + // 00100IIIIIIIxxxxEE1111000ii10ddd | Rx = add(Rxin,#II) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x38003c10) { + // 00111000ssssxxxxEE1111000ii10ddd | Rx = add(Rxin,Rs) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff98) == 0x2c003c10) { + // 001011IIIIIIDDDDEE1111000ii10ddd | RD = add(r29,#II) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x32003c10) { + // 00110010ssssDDDDEE1111000ii10ddd | RD = and(Rs,#1) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a703c10) { + // 001110100111DDDDEE1111000ii10ddd | if (!p0) RD = #0 ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a503c10) { + // 001110100101DDDDEE1111000ii10ddd | if (!p0.new) RD = #0 ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a603c10) { + // 001110100110DDDDEE1111000ii10ddd | if (p0) RD = #0 ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a403c10) { + // 001110100100DDDDEE1111000ii10ddd | if (p0.new) RD = #0 ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff98) == 0x39003c10) { + // 00111001ssss00IIEE1111000ii10ddd | p0 = cmp.eq(Rs,#II) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c003c10) { + // 001111000II00DDDEE1111000ii10ddd | RDD = combine(#0,#II) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c083c10) { + // 001111000II01DDDEE1111000ii10ddd | RDD = combine(#1,#II) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c103c10) { + // 001111000II10DDDEE1111000ii10ddd | RDD = combine(#2,#II) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x33003c10) { + // 00110011ssssDDDDEE1111000ii10ddd | RD = add(Rs,#n1) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x31003c10) { + // 00110001ssssDDDDEE1111000ii10ddd | RD = add(Rs,#1) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c10) { + // 001010IIIIIIDDDDEE1111000ii10ddd | RD = #II ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a003c10) { + // 001110100000DDDDEE1111000ii10ddd | RD = #n1 ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = #-1 ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x35003c10) { + // 00110101ssssDDDDEE1111000ii10ddd | RD = sxtb(Rs) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x34003c10) { + // 00110100ssssDDDDEE1111000ii10ddd | RD = sxth(Rs) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x30003c10) { + // 00110000ssssDDDDEE1111000ii10ddd | RD = Rs ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = %s ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x37003c10) { + // 00110111ssssDDDDEE1111000ii10ddd | RD = and(Rs,#255) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x36003c10) { + // 00110110ssssDDDDEE1111000ii10ddd | RD = zxth(Rs) ; Rdd = combine(#2,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE2I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = combine(#2,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff98) == 0x20003c18) { + // 00100IIIIIIIxxxxEE1111000ii11ddd | Rx = add(Rxin,#II) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x38003c18) { + // 00111000ssssxxxxEE1111000ii11ddd | Rx = add(Rxin,Rs) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff98) == 0x2c003c18) { + // 001011IIIIIIDDDDEE1111000ii11ddd | RD = add(r29,#II) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x32003c18) { + // 00110010ssssDDDDEE1111000ii11ddd | RD = and(Rs,#1) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a703c18) { + // 001110100111DDDDEE1111000ii11ddd | if (!p0) RD = #0 ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a503c18) { + // 001110100101DDDDEE1111000ii11ddd | if (!p0.new) RD = #0 ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a603c18) { + // 001110100110DDDDEE1111000ii11ddd | if (p0) RD = #0 ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a403c18) { + // 001110100100DDDDEE1111000ii11ddd | if (p0.new) RD = #0 ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff98) == 0x39003c18) { + // 00111001ssss00IIEE1111000ii11ddd | p0 = cmp.eq(Rs,#II) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c003c18) { + // 001111000II00DDDEE1111000ii11ddd | RDD = combine(#0,#II) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c083c18) { + // 001111000II01DDDEE1111000ii11ddd | RDD = combine(#1,#II) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c103c18) { + // 001111000II10DDDEE1111000ii11ddd | RDD = combine(#2,#II) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff98) == 0x3c183c18) { + // 001111000II11DDDEE1111000ii11ddd | RDD = combine(#3,#II) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x33003c18) { + // 00110011ssssDDDDEE1111000ii11ddd | RD = add(Rs,#n1) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x31003c18) { + // 00110001ssssDDDDEE1111000ii11ddd | RD = add(Rs,#1) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c18) { + // 001010IIIIIIDDDDEE1111000ii11ddd | RD = #II ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a003c18) { + // 001110100000DDDDEE1111000ii11ddd | RD = #n1 ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = #-1 ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x35003c18) { + // 00110101ssssDDDDEE1111000ii11ddd | RD = sxtb(Rs) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x34003c18) { + // 00110100ssssDDDDEE1111000ii11ddd | RD = sxth(Rs) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x30003c18) { + // 00110000ssssDDDDEE1111000ii11ddd | RD = Rs ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = %s ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x37003c18) { + // 00110111ssssDDDDEE1111000ii11ddd | RD = and(Rs,#255) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff98) == 0x36003c18) { + // 00110110ssssDDDDEE1111000ii11ddd | RD = zxth(Rs) ; Rdd = combine(#3,#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE3I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = combine(#3,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff08) == 0x20003d08) { + // 00100iiiiiiixxxxEE111101ssss1ddd | Rx = add(Rxin,#Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x38003d08) { + // 00111000SSSSxxxxEE111101ssss1ddd | Rx = add(Rxin,RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff08) == 0x2c003d08) { + // 001011iiiiiiDDDDEE111101ssss1ddd | RD = add(r29,#Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x32003d08) { + // 00110010SSSSDDDDEE111101ssss1ddd | RD = and(RS,#1) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a703d08) { + // 001110100111DDDDEE111101ssss1ddd | if (!p0) RD = #0 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a503d08) { + // 001110100101DDDDEE111101ssss1ddd | if (!p0.new) RD = #0 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a603d08) { + // 001110100110DDDDEE111101ssss1ddd | if (p0) RD = #0 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a403d08) { + // 001110100100DDDDEE111101ssss1ddd | if (p0.new) RD = #0 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff08) == 0x39003d08) { + // 00111001SSSS00iiEE111101ssss1ddd | p0 = cmp.eq(RS,#Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff08) == 0x3c003d08) { + // 001111000ii00DDDEE111101ssss1ddd | RDD = combine(#0,#Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff08) == 0x3c083d08) { + // 001111000ii01DDDEE111101ssss1ddd | RDD = combine(#1,#Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff08) == 0x3c103d08) { + // 001111000ii10DDDEE111101ssss1ddd | RDD = combine(#2,#Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff08) == 0x3c183d08) { + // 001111000ii11DDDEE111101ssss1ddd | RDD = combine(#3,#Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff08) == 0x3d083d08) { + // 00111101SSSS1DDDEE111101ssss1ddd | RDD = combine(RS,#0) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff08) == 0x3d003d08) { + // 00111101SSSS0DDDEE111101ssss1ddd | RDD = combine(#0,RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x33003d08) { + // 00110011SSSSDDDDEE111101ssss1ddd | RD = add(RS,#n1) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x31003d08) { + // 00110001SSSSDDDDEE111101ssss1ddd | RD = add(RS,#1) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff08) == 0x28003d08) { + // 001010iiiiiiDDDDEE111101ssss1ddd | RD = #Ii ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a003d08) { + // 001110100000DDDDEE111101ssss1ddd | RD = #n1 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = #-1 ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x35003d08) { + // 00110101SSSSDDDDEE111101ssss1ddd | RD = sxtb(RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x34003d08) { + // 00110100SSSSDDDDEE111101ssss1ddd | RD = sxth(RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x30003d08) { + // 00110000SSSSDDDDEE111101ssss1ddd | RD = RS ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x37003d08) { + // 00110111SSSSDDDDEE111101ssss1ddd | RD = and(RS,#255) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x36003d08) { + // 00110110SSSSDDDDEE111101ssss1ddd | RD = zxth(RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINERZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = combine(%s,#0) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff08) == 0x20003d00) { + // 00100iiiiiiixxxxEE111101ssss0ddd | Rx = add(Rxin,#Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x38003d00) { + // 00111000SSSSxxxxEE111101ssss0ddd | Rx = add(Rxin,RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff08) == 0x2c003d00) { + // 001011iiiiiiDDDDEE111101ssss0ddd | RD = add(r29,#Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x32003d00) { + // 00110010SSSSDDDDEE111101ssss0ddd | RD = and(RS,#1) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a703d00) { + // 001110100111DDDDEE111101ssss0ddd | if (!p0) RD = #0 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a503d00) { + // 001110100101DDDDEE111101ssss0ddd | if (!p0.new) RD = #0 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a603d00) { + // 001110100110DDDDEE111101ssss0ddd | if (p0) RD = #0 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a403d00) { + // 001110100100DDDDEE111101ssss0ddd | if (p0.new) RD = #0 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff08) == 0x39003d00) { + // 00111001SSSS00iiEE111101ssss0ddd | p0 = cmp.eq(RS,#Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff08) == 0x3c003d00) { + // 001111000ii00DDDEE111101ssss0ddd | RDD = combine(#0,#Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff08) == 0x3c083d00) { + // 001111000ii01DDDEE111101ssss0ddd | RDD = combine(#1,#Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff08) == 0x3c103d00) { + // 001111000ii10DDDEE111101ssss0ddd | RDD = combine(#2,#Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff08) == 0x3c183d00) { + // 001111000ii11DDDEE111101ssss0ddd | RDD = combine(#3,#Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff08) == 0x3d003d00) { + // 00111101SSSS0DDDEE111101ssss0ddd | RDD = combine(#0,RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x33003d00) { + // 00110011SSSSDDDDEE111101ssss0ddd | RD = add(RS,#n1) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x31003d00) { + // 00110001SSSSDDDDEE111101ssss0ddd | RD = add(RS,#1) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff08) == 0x28003d00) { + // 001010iiiiiiDDDDEE111101ssss0ddd | RD = #Ii ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a003d00) { + // 001110100000DDDDEE111101ssss0ddd | RD = #n1 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = #-1 ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x35003d00) { + // 00110101SSSSDDDDEE111101ssss0ddd | RD = sxtb(RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x34003d00) { + // 00110100SSSSDDDDEE111101ssss0ddd | RD = sxth(RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x30003d00) { + // 00110000SSSSDDDDEE111101ssss0ddd | RD = RS ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x37003d00) { + // 00110111SSSSDDDDEE111101ssss0ddd | RD = and(RS,#255) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff08) == 0x36003d00) { + // 00110110SSSSDDDDEE111101ssss0ddd | RD = zxth(RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINEZR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = combine(#0,%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x20003300) { + // 00100iiiiiiixxxxEE110011ssssdddd | Rx = add(Rxin,#Ii) ; Rd = add(Rs,#n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_DEC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = add(%s,#-1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003300) { + // 001011iiiiiiDDDDEE110011ssssdddd | RD = add(r29,#Ii) ; Rd = add(Rs,#n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_DEC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = add(%s,#-1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x32003300) { + // 00110010SSSSDDDDEE110011ssssdddd | RD = and(RS,#1) ; Rd = add(Rs,#n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_DEC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = add(%s,#-1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x33003300) { + // 00110011SSSSDDDDEE110011ssssdddd | RD = add(RS,#N1) ; Rd = add(Rs,#n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_DEC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = add(%s,#-1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x31003300) { + // 00110001SSSSDDDDEE110011ssssdddd | RD = add(RS,#1) ; Rd = add(Rs,#n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_DEC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = add(%s,#-1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003300) { + // 001010iiiiiiDDDDEE110011ssssdddd | RD = #Ii ; Rd = add(Rs,#n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_DEC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = add(%s,#-1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x30003300) { + // 00110000SSSSDDDDEE110011ssssdddd | RD = RS ; Rd = add(Rs,#n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_DEC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = add(%s,#-1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x20003100) { + // 00100iiiiiiixxxxEE110001ssssdddd | Rx = add(Rxin,#Ii) ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_INC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = add(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003100) { + // 001011iiiiiiDDDDEE110001ssssdddd | RD = add(r29,#Ii) ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_INC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = add(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x31003100) { + // 00110001SSSSDDDDEE110001ssssdddd | RD = add(RS,#1) ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_INC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = add(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003100) { + // 001010iiiiiiDDDDEE110001ssssdddd | RD = #Ii ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_INC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = add(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x30003100) { + // 00110000SSSSDDDDEE110001ssssdddd | RD = RS ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_INC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = add(%s,#1) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a00) { + // 00100iiiiiiixxxxEE1110100000dddd | Rx = add(Rxin,#Ii) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a00) { + // 00111000ssssxxxxEE1110100000dddd | Rx = add(Rxin,Rs) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a00) { + // 001011iiiiiiDDDDEE1110100000dddd | RD = add(r29,#Ii) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a00) { + // 00110010ssssDDDDEE1110100000dddd | RD = and(Rs,#1) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a00) { + // 00111001ssss00iiEE1110100000dddd | p0 = cmp.eq(Rs,#Ii) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a00) { + // 00110011ssssDDDDEE1110100000dddd | RD = add(Rs,#N1) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a00) { + // 00110001ssssDDDDEE1110100000dddd | RD = add(Rs,#1) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a00) { + // 001010iiiiiiDDDDEE1110100000dddd | RD = #Ii ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a00) { + // 001110100000DDDDEE1110100000dddd | RD = #N1 ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a00) { + // 00110101ssssDDDDEE1110100000dddd | RD = sxtb(Rs) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a00) { + // 00110100ssssDDDDEE1110100000dddd | RD = sxth(Rs) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a00) { + // 00110000ssssDDDDEE1110100000dddd | RD = Rs ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = %s ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a00) { + // 00110111ssssDDDDEE1110100000dddd | RD = and(Rs,#255) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a00) { + // 00110110ssssDDDDEE1110100000dddd | RD = zxth(Rs) ; Rd = #n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_SETIN1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = #-1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x20003500) { + // 00100iiiiiiixxxxEE110101ssssdddd | Rx = add(Rxin,#Ii) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003500) { + // 001011iiiiiiDDDDEE110101ssssdddd | RD = add(r29,#Ii) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x32003500) { + // 00110010SSSSDDDDEE110101ssssdddd | RD = and(RS,#1) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x33003500) { + // 00110011SSSSDDDDEE110101ssssdddd | RD = add(RS,#n1) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x31003500) { + // 00110001SSSSDDDDEE110101ssssdddd | RD = add(RS,#1) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003500) { + // 001010iiiiiiDDDDEE110101ssssdddd | RD = #Ii ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x35003500) { + // 00110101SSSSDDDDEE110101ssssdddd | RD = sxtb(RS) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x34003500) { + // 00110100SSSSDDDDEE110101ssssdddd | RD = sxth(RS) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x30003500) { + // 00110000SSSSDDDDEE110101ssssdddd | RD = RS ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x20003400) { + // 00100iiiiiiixxxxEE110100ssssdddd | Rx = add(Rxin,#Ii) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003400) { + // 001011iiiiiiDDDDEE110100ssssdddd | RD = add(r29,#Ii) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x32003400) { + // 00110010SSSSDDDDEE110100ssssdddd | RD = and(RS,#1) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x33003400) { + // 00110011SSSSDDDDEE110100ssssdddd | RD = add(RS,#n1) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x31003400) { + // 00110001SSSSDDDDEE110100ssssdddd | RD = add(RS,#1) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003400) { + // 001010iiiiiiDDDDEE110100ssssdddd | RD = #Ii ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x34003400) { + // 00110100SSSSDDDDEE110100ssssdddd | RD = sxth(RS) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x30003400) { + // 00110000SSSSDDDDEE110100ssssdddd | RD = RS ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x20003000) { + // 00100iiiiiiixxxxEE110000ssssdddd | Rx = add(Rxin,#Ii) ; Rd = Rs + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_TFR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003000) { + // 001011iiiiiiDDDDEE110000ssssdddd | RD = add(r29,#Ii) ; Rd = Rs + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_TFR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003000) { + // 001010iiiiiiDDDDEE110000ssssdddd | RD = #Ii ; Rd = Rs + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_TFR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x30003000) { + // 00110000SSSSDDDDEE110000ssssdddd | RD = RS ; Rd = Rs + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_TFR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x20003700) { + // 00100iiiiiiixxxxEE110111ssssdddd | Rx = add(Rxin,#Ii) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003700) { + // 001011iiiiiiDDDDEE110111ssssdddd | RD = add(r29,#Ii) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x32003700) { + // 00110010SSSSDDDDEE110111ssssdddd | RD = and(RS,#1) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x33003700) { + // 00110011SSSSDDDDEE110111ssssdddd | RD = add(RS,#n1) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x31003700) { + // 00110001SSSSDDDDEE110111ssssdddd | RD = add(RS,#1) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003700) { + // 001010iiiiiiDDDDEE110111ssssdddd | RD = #Ii ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x35003700) { + // 00110101SSSSDDDDEE110111ssssdddd | RD = sxtb(RS) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x34003700) { + // 00110100SSSSDDDDEE110111ssssdddd | RD = sxth(RS) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x30003700) { + // 00110000SSSSDDDDEE110111ssssdddd | RD = RS ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x37003700) { + // 00110111SSSSDDDDEE110111ssssdddd | RD = and(RS,#255) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x36003700) { + // 00110110SSSSDDDDEE110111ssssdddd | RD = zxth(RS) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ZXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = and(%s,#255) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x20003600) { + // 00100iiiiiiixxxxEE110110ssssdddd | Rx = add(Rxin,#Ii) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003600) { + // 001011iiiiiiDDDDEE110110ssssdddd | RD = add(r29,#Ii) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x32003600) { + // 00110010SSSSDDDDEE110110ssssdddd | RD = and(RS,#1) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x33003600) { + // 00110011SSSSDDDDEE110110ssssdddd | RD = add(RS,#n1) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x31003600) { + // 00110001SSSSDDDDEE110110ssssdddd | RD = add(RS,#1) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003600) { + // 001010iiiiiiDDDDEE110110ssssdddd | RD = #Ii ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x35003600) { + // 00110101SSSSDDDDEE110110ssssdddd | RD = sxtb(RS) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x34003600) { + // 00110100SSSSDDDDEE110110ssssdddd | RD = sxth(RS) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x30003600) { + // 00110000SSSSDDDDEE110110ssssdddd | RD = RS ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x36003600) { + // 00110110SSSSDDDDEE110110ssssdddd | RD = zxth(RS) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x4: + if ((hi_u32 & 0xf800f000) == 0x40000000) { + // 01000IIIIIIIxxxxEE00iiiissssdddd | Rx = add(Rxin,#II) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 2; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x58000000) { + // 01011000SSSSxxxxEE00iiiissssdddd | Rx = add(Rxin,RS) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 2; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f000) == 0x4c000000) { + // 010011IIIIIIDDDDEE00iiiissssdddd | RD = add(r29,#II) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x52000000) { + // 01010010SSSSDDDDEE00iiiissssdddd | RD = and(RS,#1) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a700000) { + // 010110100111DDDDEE00iiiissssdddd | if (!p0) RD = #0 ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a500000) { + // 010110100101DDDDEE00iiiissssdddd | if (!p0.new) RD = #0 ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a600000) { + // 010110100110DDDDEE00iiiissssdddd | if (p0) RD = #0 ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a400000) { + // 010110100100DDDDEE00iiiissssdddd | if (p0.new) RD = #0 ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cf000) == 0x59000000) { + // 01011001SSSS00IIEE00iiiissssdddd | p0 = cmp.eq(RS,#II) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x5c000000) { + // 010111000II00DDDEE00iiiissssdddd | RDD = combine(#0,#II) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x5c080000) { + // 010111000II01DDDEE00iiiissssdddd | RDD = combine(#1,#II) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x5c100000) { + // 010111000II10DDDEE00iiiissssdddd | RDD = combine(#2,#II) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x5c180000) { + // 010111000II11DDDEE00iiiissssdddd | RDD = combine(#3,#II) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f000) == 0x5d080000) { + // 01011101SSSS1DDDEE00iiiissssdddd | RDD = combine(RS,#0) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f000) == 0x5d000000) { + // 01011101SSSS0DDDEE00iiiissssdddd | RDD = combine(#0,RS) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x53000000) { + // 01010011SSSSDDDDEE00iiiissssdddd | RD = add(RS,#n1) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 2; + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x51000000) { + // 01010001SSSSDDDDEE00iiiissssdddd | RD = add(RS,#1) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f000) == 0x48000000) { + // 010010IIIIIIDDDDEE00iiiissssdddd | RD = #II ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a000000) { + // 010110100000DDDDEE00iiiissssdddd | RD = #n1 ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = #-1 ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x55000000) { + // 01010101SSSSDDDDEE00iiiissssdddd | RD = sxtb(RS) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x54000000) { + // 01010100SSSSDDDDEE00iiiissssdddd | RD = sxth(RS) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x50000000) { + // 01010000SSSSDDDDEE00iiiissssdddd | RD = RS ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = %s ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x57000000) { + // 01010111SSSSDDDDEE00iiiissssdddd | RD = and(RS,#255) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x56000000) { + // 01010110SSSSDDDDEE00iiiissssdddd | RD = zxth(RS) ; Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL1_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = memw(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f000) == 0x40001000) { + // 01000IIIIIIIxxxxEE01iiiissssdddd | Rx = add(Rxin,#II) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x58001000) { + // 01011000SSSSxxxxEE01iiiissssdddd | Rx = add(Rxin,RS) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f000) == 0x4c001000) { + // 010011IIIIIIDDDDEE01iiiissssdddd | RD = add(r29,#II) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x52001000) { + // 01010010SSSSDDDDEE01iiiissssdddd | RD = and(RS,#1) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a701000) { + // 010110100111DDDDEE01iiiissssdddd | if (!p0) RD = #0 ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a501000) { + // 010110100101DDDDEE01iiiissssdddd | if (!p0.new) RD = #0 ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a601000) { + // 010110100110DDDDEE01iiiissssdddd | if (p0) RD = #0 ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a401000) { + // 010110100100DDDDEE01iiiissssdddd | if (p0.new) RD = #0 ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cf000) == 0x59001000) { + // 01011001SSSS00IIEE01iiiissssdddd | p0 = cmp.eq(RS,#II) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x5c001000) { + // 010111000II00DDDEE01iiiissssdddd | RDD = combine(#0,#II) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x5c081000) { + // 010111000II01DDDEE01iiiissssdddd | RDD = combine(#1,#II) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x5c101000) { + // 010111000II10DDDEE01iiiissssdddd | RDD = combine(#2,#II) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x5c181000) { + // 010111000II11DDDEE01iiiissssdddd | RDD = combine(#3,#II) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f000) == 0x5d081000) { + // 01011101SSSS1DDDEE01iiiissssdddd | RDD = combine(RS,#0) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f000) == 0x5d001000) { + // 01011101SSSS0DDDEE01iiiissssdddd | RDD = combine(#0,RS) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x53001000) { + // 01010011SSSSDDDDEE01iiiissssdddd | RD = add(RS,#n1) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x51001000) { + // 01010001SSSSDDDDEE01iiiissssdddd | RD = add(RS,#1) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f000) == 0x48001000) { + // 010010IIIIIIDDDDEE01iiiissssdddd | RD = #II ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x5a001000) { + // 010110100000DDDDEE01iiiissssdddd | RD = #n1 ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = #-1 ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x55001000) { + // 01010101SSSSDDDDEE01iiiissssdddd | RD = sxtb(RS) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x54001000) { + // 01010100SSSSDDDDEE01iiiissssdddd | RD = sxth(RS) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x50001000) { + // 01010000SSSSDDDDEE01iiiissssdddd | RD = RS ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = %s ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x57001000) { + // 01010111SSSSDDDDEE01iiiissssdddd | RD = and(RS,#255) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x56001000) { + // 01010110SSSSDDDDEE01iiiissssdddd | RD = zxth(RS) ; Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL1_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = memub(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x5: + if ((hi_u32 & 0xf800ffff) == 0x40003f00) { + // 01000iiiiiiixxxxEE11111100000000 | Rx = add(Rxin,#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f00) { + // 01011000ssssxxxxEE11111100000000 | Rx = add(Rxin,Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f00) { + // 010011iiiiiiddddEE11111100000000 | Rd = add(r29,#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f00) { + // 01010010ssssddddEE11111100000000 | Rd = and(Rs,#1) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f00) { + // 010110100111ddddEE11111100000000 | if (!p0) Rd = #0 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f00) { + // 010110100101ddddEE11111100000000 | if (!p0.new) Rd = #0 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f00) { + // 010110100110ddddEE11111100000000 | if (p0) Rd = #0 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f00) { + // 010110100100ddddEE11111100000000 | if (p0.new) Rd = #0 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f00) { + // 01011001ssss00iiEE11111100000000 | p0 = cmp.eq(Rs,#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f00) { + // 010111000ii00dddEE11111100000000 | Rdd = combine(#0,#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f00) { + // 010111000ii01dddEE11111100000000 | Rdd = combine(#1,#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f00) { + // 010111000ii10dddEE11111100000000 | Rdd = combine(#2,#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f00) { + // 010111000ii11dddEE11111100000000 | Rdd = combine(#3,#Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f00) { + // 01011101ssss1dddEE11111100000000 | Rdd = combine(Rs,#0) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f00) { + // 01011101ssss0dddEE11111100000000 | Rdd = combine(#0,Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f00) { + // 01010011ssssddddEE11111100000000 | Rd = add(Rs,#n1) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f00) { + // 01010001ssssddddEE11111100000000 | Rd = add(Rs,#1) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f00) { + // 010010iiiiiiddddEE11111100000000 | Rd = #Ii ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f00) { + // 010110100000ddddEE11111100000000 | Rd = #n1 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f00) { + // 01010101ssssddddEE11111100000000 | Rd = sxtb(Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f00) { + // 01010100ssssddddEE11111100000000 | Rd = sxth(Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f00) { + // 01010000ssssddddEE11111100000000 | Rd = Rs ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f00) { + // 01010111ssssddddEE11111100000000 | Rd = and(Rs,#255) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f00) { + // 01010110ssssddddEE11111100000000 | Rd = zxth(Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; deallocframe %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc0) { + // 01000iiiiiiixxxxEE11111111000000 | Rx = add(Rxin,#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc0) { + // 01011000ssssxxxxEE11111111000000 | Rx = add(Rxin,Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc0) { + // 010011iiiiiiddddEE11111111000000 | Rd = add(r29,#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc0) { + // 01010010ssssddddEE11111111000000 | Rd = and(Rs,#1) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc0) { + // 010110100111ddddEE11111111000000 | if (!p0) Rd = #0 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc0) { + // 010110100101ddddEE11111111000000 | if (!p0.new) Rd = #0 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc0) { + // 010110100110ddddEE11111111000000 | if (p0) Rd = #0 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc0) { + // 010110100100ddddEE11111111000000 | if (p0.new) Rd = #0 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc0) { + // 01011001ssss00iiEE11111111000000 | p0 = cmp.eq(Rs,#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc0) { + // 010111000ii00dddEE11111111000000 | Rdd = combine(#0,#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc0) { + // 010111000ii01dddEE11111111000000 | Rdd = combine(#1,#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc0) { + // 010111000ii10dddEE11111111000000 | Rdd = combine(#2,#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc0) { + // 010111000ii11dddEE11111111000000 | Rdd = combine(#3,#Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc0) { + // 01011101ssss1dddEE11111111000000 | Rdd = combine(Rs,#0) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc0) { + // 01011101ssss0dddEE11111111000000 | Rdd = combine(#0,Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc0) { + // 01010011ssssddddEE11111111000000 | Rd = add(Rs,#n1) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc0) { + // 01010001ssssddddEE11111111000000 | Rd = add(Rs,#1) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc0) { + // 010010iiiiiiddddEE11111111000000 | Rd = #Ii ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc0) { + // 010110100000ddddEE11111111000000 | Rd = #n1 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc0) { + // 01010101ssssddddEE11111111000000 | Rd = sxtb(Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc0) { + // 01010100ssssddddEE11111111000000 | Rd = sxth(Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc0) { + // 01010000ssssddddEE11111111000000 | Rd = Rs ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc0) { + // 01010111ssssddddEE11111111000000 | Rd = and(Rs,#255) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc0) { + // 01010110ssssddddEE11111111000000 | Rd = zxth(Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc5) { + // 01000iiiiiiixxxxEE11111111000101 | Rx = add(Rxin,#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc5) { + // 01011000ssssxxxxEE11111111000101 | Rx = add(Rxin,Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc5) { + // 010011iiiiiiddddEE11111111000101 | Rd = add(r29,#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc5) { + // 01010010ssssddddEE11111111000101 | Rd = and(Rs,#1) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc5) { + // 010110100111ddddEE11111111000101 | if (!p0) Rd = #0 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc5) { + // 010110100101ddddEE11111111000101 | if (!p0.new) Rd = #0 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc5) { + // 010110100110ddddEE11111111000101 | if (p0) Rd = #0 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc5) { + // 010110100100ddddEE11111111000101 | if (p0.new) Rd = #0 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc5) { + // 01011001ssss00iiEE11111111000101 | p0 = cmp.eq(Rs,#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc5) { + // 010111000ii00dddEE11111111000101 | Rdd = combine(#0,#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc5) { + // 010111000ii01dddEE11111111000101 | Rdd = combine(#1,#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc5) { + // 010111000ii10dddEE11111111000101 | Rdd = combine(#2,#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc5) { + // 010111000ii11dddEE11111111000101 | Rdd = combine(#3,#Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc5) { + // 01011101ssss1dddEE11111111000101 | Rdd = combine(Rs,#0) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc5) { + // 01011101ssss0dddEE11111111000101 | Rdd = combine(#0,Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc5) { + // 01010011ssssddddEE11111111000101 | Rd = add(Rs,#n1) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc5) { + // 01010001ssssddddEE11111111000101 | Rd = add(Rs,#1) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc5) { + // 010010iiiiiiddddEE11111111000101 | Rd = #Ii ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc5) { + // 010110100000ddddEE11111111000101 | Rd = #n1 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc5) { + // 01010101ssssddddEE11111111000101 | Rd = sxtb(Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc5) { + // 01010100ssssddddEE11111111000101 | Rd = sxth(Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc5) { + // 01010000ssssddddEE11111111000101 | Rd = Rs ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc5) { + // 01010111ssssddddEE11111111000101 | Rd = and(Rs,#255) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc5) { + // 01010110ssssddddEE11111111000101 | Rd = zxth(Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (!P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc7) { + // 01000iiiiiiixxxxEE11111111000111 | Rx = add(Rxin,#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc7) { + // 01011000ssssxxxxEE11111111000111 | Rx = add(Rxin,Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc7) { + // 010011iiiiiiddddEE11111111000111 | Rd = add(r29,#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc7) { + // 01010010ssssddddEE11111111000111 | Rd = and(Rs,#1) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc7) { + // 010110100111ddddEE11111111000111 | if (!p0) Rd = #0 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc7) { + // 010110100101ddddEE11111111000111 | if (!p0.new) Rd = #0 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc7) { + // 010110100110ddddEE11111111000111 | if (p0) Rd = #0 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc7) { + // 010110100100ddddEE11111111000111 | if (p0.new) Rd = #0 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc7) { + // 01011001ssss00iiEE11111111000111 | p0 = cmp.eq(Rs,#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc7) { + // 010111000ii00dddEE11111111000111 | Rdd = combine(#0,#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc7) { + // 010111000ii01dddEE11111111000111 | Rdd = combine(#1,#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc7) { + // 010111000ii10dddEE11111111000111 | Rdd = combine(#2,#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc7) { + // 010111000ii11dddEE11111111000111 | Rdd = combine(#3,#Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc7) { + // 01011101ssss1dddEE11111111000111 | Rdd = combine(Rs,#0) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc7) { + // 01011101ssss0dddEE11111111000111 | Rdd = combine(#0,Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc7) { + // 01010011ssssddddEE11111111000111 | Rd = add(Rs,#n1) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc7) { + // 01010001ssssddddEE11111111000111 | Rd = add(Rs,#1) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc7) { + // 010010iiiiiiddddEE11111111000111 | Rd = #Ii ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc7) { + // 010110100000ddddEE11111111000111 | Rd = #n1 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc7) { + // 01010101ssssddddEE11111111000111 | Rd = sxtb(Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc7) { + // 01010100ssssddddEE11111111000111 | Rd = sxth(Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc7) { + // 01010000ssssddddEE11111111000111 | Rd = Rs ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc7) { + // 01010111ssssddddEE11111111000111 | Rd = and(Rs,#255) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc7) { + // 01010110ssssddddEE11111111000111 | Rd = zxth(Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (!P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc4) { + // 01000iiiiiiixxxxEE11111111000100 | Rx = add(Rxin,#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc4) { + // 01011000ssssxxxxEE11111111000100 | Rx = add(Rxin,Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc4) { + // 010011iiiiiiddddEE11111111000100 | Rd = add(r29,#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc4) { + // 01010010ssssddddEE11111111000100 | Rd = and(Rs,#1) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc4) { + // 010110100111ddddEE11111111000100 | if (!p0) Rd = #0 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc4) { + // 010110100101ddddEE11111111000100 | if (!p0.new) Rd = #0 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc4) { + // 010110100110ddddEE11111111000100 | if (p0) Rd = #0 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc4) { + // 010110100100ddddEE11111111000100 | if (p0.new) Rd = #0 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc4) { + // 01011001ssss00iiEE11111111000100 | p0 = cmp.eq(Rs,#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc4) { + // 010111000ii00dddEE11111111000100 | Rdd = combine(#0,#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc4) { + // 010111000ii01dddEE11111111000100 | Rdd = combine(#1,#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc4) { + // 010111000ii10dddEE11111111000100 | Rdd = combine(#2,#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc4) { + // 010111000ii11dddEE11111111000100 | Rdd = combine(#3,#Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc4) { + // 01011101ssss1dddEE11111111000100 | Rdd = combine(Rs,#0) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc4) { + // 01011101ssss0dddEE11111111000100 | Rdd = combine(#0,Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc4) { + // 01010011ssssddddEE11111111000100 | Rd = add(Rs,#n1) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc4) { + // 01010001ssssddddEE11111111000100 | Rd = add(Rs,#1) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc4) { + // 010010iiiiiiddddEE11111111000100 | Rd = #Ii ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc4) { + // 010110100000ddddEE11111111000100 | Rd = #n1 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc4) { + // 01010101ssssddddEE11111111000100 | Rd = sxtb(Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc4) { + // 01010100ssssddddEE11111111000100 | Rd = sxth(Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc4) { + // 01010000ssssddddEE11111111000100 | Rd = Rs ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc4) { + // 01010111ssssddddEE11111111000100 | Rd = and(Rs,#255) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc4) { + // 01010110ssssddddEE11111111000100 | Rd = zxth(Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (P0) jumpr R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc6) { + // 01000iiiiiiixxxxEE11111111000110 | Rx = add(Rxin,#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc6) { + // 01011000ssssxxxxEE11111111000110 | Rx = add(Rxin,Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc6) { + // 010011iiiiiiddddEE11111111000110 | Rd = add(r29,#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc6) { + // 01010010ssssddddEE11111111000110 | Rd = and(Rs,#1) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc6) { + // 010110100111ddddEE11111111000110 | if (!p0) Rd = #0 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc6) { + // 010110100101ddddEE11111111000110 | if (!p0.new) Rd = #0 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc6) { + // 010110100110ddddEE11111111000110 | if (p0) Rd = #0 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc6) { + // 010110100100ddddEE11111111000110 | if (p0.new) Rd = #0 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc6) { + // 01011001ssss00iiEE11111111000110 | p0 = cmp.eq(Rs,#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc6) { + // 010111000ii00dddEE11111111000110 | Rdd = combine(#0,#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc6) { + // 010111000ii01dddEE11111111000110 | Rdd = combine(#1,#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc6) { + // 010111000ii10dddEE11111111000110 | Rdd = combine(#2,#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc6) { + // 010111000ii11dddEE11111111000110 | Rdd = combine(#3,#Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc6) { + // 01011101ssss1dddEE11111111000110 | Rdd = combine(Rs,#0) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc6) { + // 01011101ssss0dddEE11111111000110 | Rdd = combine(#0,Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc6) { + // 01010011ssssddddEE11111111000110 | Rd = add(Rs,#n1) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc6) { + // 01010001ssssddddEE11111111000110 | Rd = add(Rs,#1) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc6) { + // 010010iiiiiiddddEE11111111000110 | Rd = #Ii ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc6) { + // 010110100000ddddEE11111111000110 | Rd = #n1 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc6) { + // 01010101ssssddddEE11111111000110 | Rd = sxtb(Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc6) { + // 01010100ssssddddEE11111111000110 | Rd = sxth(Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc6) { + // 01010000ssssddddEE11111111000110 | Rd = Rs ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc6) { + // 01010111ssssddddEE11111111000110 | Rd = and(Rs,#255) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc6) { + // 01010110ssssddddEE11111111000110 | Rd = zxth(Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (P0.new) jumpr:nt R31 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x40003000) { + // 01000IIIIIIIxxxxEE110iiissssdddd | Rx = add(Rxin,#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x58003000) { + // 01011000SSSSxxxxEE110iiissssdddd | Rx = add(Rxin,RS) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f800) == 0x4c003000) { + // 010011IIIIIIDDDDEE110iiissssdddd | RD = add(r29,#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x52003000) { + // 01010010SSSSDDDDEE110iiissssdddd | RD = and(RS,#1) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a703000) { + // 010110100111DDDDEE110iiissssdddd | if (!p0) RD = #0 ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a503000) { + // 010110100101DDDDEE110iiissssdddd | if (!p0.new) RD = #0 ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a603000) { + // 010110100110DDDDEE110iiissssdddd | if (p0) RD = #0 ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a403000) { + // 010110100100DDDDEE110iiissssdddd | if (p0.new) RD = #0 ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cf800) == 0x59003000) { + // 01011001SSSS00IIEE110iiissssdddd | p0 = cmp.eq(RS,#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c003000) { + // 010111000II00DDDEE110iiissssdddd | RDD = combine(#0,#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c083000) { + // 010111000II01DDDEE110iiissssdddd | RDD = combine(#1,#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c103000) { + // 010111000II10DDDEE110iiissssdddd | RDD = combine(#2,#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c183000) { + // 010111000II11DDDEE110iiissssdddd | RDD = combine(#3,#II) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f800) == 0x5d083000) { + // 01011101SSSS1DDDEE110iiissssdddd | RDD = combine(RS,#0) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f800) == 0x5d003000) { + // 01011101SSSS0DDDEE110iiissssdddd | RDD = combine(#0,RS) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x53003000) { + // 01010011SSSSDDDDEE110iiissssdddd | RD = add(RS,#n1) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x51003000) { + // 01010001SSSSDDDDEE110iiissssdddd | RD = add(RS,#1) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f800) == 0x48003000) { + // 010010IIIIIIDDDDEE110iiissssdddd | RD = #II ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a003000) { + // 010110100000DDDDEE110iiissssdddd | RD = #n1 ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = #-1 ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x55003000) { + // 01010101SSSSDDDDEE110iiissssdddd | RD = sxtb(RS) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x54003000) { + // 01010100SSSSDDDDEE110iiissssdddd | RD = sxth(RS) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x50003000) { + // 01010000SSSSDDDDEE110iiissssdddd | RD = RS ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = %s ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x57003000) { + // 01010111SSSSDDDDEE110iiissssdddd | RD = and(RS,#255) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x56003000) { + // 01010110SSSSDDDDEE110iiissssdddd | RD = zxth(RS) ; Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = memb(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x40003e00) { + // 01000IIIIIIIxxxxEE111110iiiiiddd | Rx = add(Rxin,#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x58003e00) { + // 01011000ssssxxxxEE111110iiiiiddd | Rx = add(Rxin,Rs) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x4c003e00) { + // 010011IIIIIIDDDDEE111110iiiiiddd | RD = add(r29,#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x52003e00) { + // 01010010ssssDDDDEE111110iiiiiddd | RD = and(Rs,#1) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a703e00) { + // 010110100111DDDDEE111110iiiiiddd | if (!p0) RD = #0 ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a503e00) { + // 010110100101DDDDEE111110iiiiiddd | if (!p0.new) RD = #0 ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a603e00) { + // 010110100110DDDDEE111110iiiiiddd | if (p0) RD = #0 ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a403e00) { + // 010110100100DDDDEE111110iiiiiddd | if (p0.new) RD = #0 ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff00) == 0x59003e00) { + // 01011001ssss00IIEE111110iiiiiddd | p0 = cmp.eq(Rs,#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x5c003e00) { + // 010111000II00DDDEE111110iiiiiddd | RDD = combine(#0,#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x5c083e00) { + // 010111000II01DDDEE111110iiiiiddd | RDD = combine(#1,#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x5c103e00) { + // 010111000II10DDDEE111110iiiiiddd | RDD = combine(#2,#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x5c183e00) { + // 010111000II11DDDEE111110iiiiiddd | RDD = combine(#3,#II) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x5d083e00) { + // 01011101ssss1DDDEE111110iiiiiddd | RDD = combine(Rs,#0) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x5d003e00) { + // 01011101ssss0DDDEE111110iiiiiddd | RDD = combine(#0,Rs) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x53003e00) { + // 01010011ssssDDDDEE111110iiiiiddd | RD = add(Rs,#n1) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x51003e00) { + // 01010001ssssDDDDEE111110iiiiiddd | RD = add(Rs,#1) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x48003e00) { + // 010010IIIIIIDDDDEE111110iiiiiddd | RD = #II ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a003e00) { + // 010110100000DDDDEE111110iiiiiddd | RD = #n1 ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = #-1 ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x55003e00) { + // 01010101ssssDDDDEE111110iiiiiddd | RD = sxtb(Rs) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x54003e00) { + // 01010100ssssDDDDEE111110iiiiiddd | RD = sxth(Rs) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x50003e00) { + // 01010000ssssDDDDEE111110iiiiiddd | RD = Rs ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = %s ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x57003e00) { + // 01010111ssssDDDDEE111110iiiiiddd | RD = and(Rs,#255) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x56003e00) { + // 01010110ssssDDDDEE111110iiiiiddd | RD = zxth(Rs) ; Rdd = memd(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRD_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = memd(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x40002000) { + // 01000IIIIIIIxxxxEE100iiissssdddd | Rx = add(Rxin,#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x58002000) { + // 01011000SSSSxxxxEE100iiissssdddd | Rx = add(Rxin,RS) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f800) == 0x4c002000) { + // 010011IIIIIIDDDDEE100iiissssdddd | RD = add(r29,#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x52002000) { + // 01010010SSSSDDDDEE100iiissssdddd | RD = and(RS,#1) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a702000) { + // 010110100111DDDDEE100iiissssdddd | if (!p0) RD = #0 ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a502000) { + // 010110100101DDDDEE100iiissssdddd | if (!p0.new) RD = #0 ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a602000) { + // 010110100110DDDDEE100iiissssdddd | if (p0) RD = #0 ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a402000) { + // 010110100100DDDDEE100iiissssdddd | if (p0.new) RD = #0 ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cf800) == 0x59002000) { + // 01011001SSSS00IIEE100iiissssdddd | p0 = cmp.eq(RS,#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c002000) { + // 010111000II00DDDEE100iiissssdddd | RDD = combine(#0,#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c082000) { + // 010111000II01DDDEE100iiissssdddd | RDD = combine(#1,#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c102000) { + // 010111000II10DDDEE100iiissssdddd | RDD = combine(#2,#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c182000) { + // 010111000II11DDDEE100iiissssdddd | RDD = combine(#3,#II) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f800) == 0x5d082000) { + // 01011101SSSS1DDDEE100iiissssdddd | RDD = combine(RS,#0) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f800) == 0x5d002000) { + // 01011101SSSS0DDDEE100iiissssdddd | RDD = combine(#0,RS) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x53002000) { + // 01010011SSSSDDDDEE100iiissssdddd | RD = add(RS,#n1) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x51002000) { + // 01010001SSSSDDDDEE100iiissssdddd | RD = add(RS,#1) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f800) == 0x48002000) { + // 010010IIIIIIDDDDEE100iiissssdddd | RD = #II ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a002000) { + // 010110100000DDDDEE100iiissssdddd | RD = #n1 ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = #-1 ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x55002000) { + // 01010101SSSSDDDDEE100iiissssdddd | RD = sxtb(RS) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x54002000) { + // 01010100SSSSDDDDEE100iiissssdddd | RD = sxth(RS) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x50002000) { + // 01010000SSSSDDDDEE100iiissssdddd | RD = RS ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = %s ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x57002000) { + // 01010111SSSSDDDDEE100iiissssdddd | RD = and(RS,#255) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x56002000) { + // 01010110SSSSDDDDEE100iiissssdddd | RD = zxth(RS) ; Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = memh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0x40003c00) { + // 01000IIIIIIIxxxxEE11110iiiiidddd | Rx = add(Rxin,#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x58003c00) { + // 01011000ssssxxxxEE11110iiiiidddd | Rx = add(Rxin,Rs) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fe00) == 0x4c003c00) { + // 010011IIIIIIDDDDEE11110iiiiidddd | RD = add(r29,#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x52003c00) { + // 01010010ssssDDDDEE11110iiiiidddd | RD = and(Rs,#1) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a703c00) { + // 010110100111DDDDEE11110iiiiidddd | if (!p0) RD = #0 ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a503c00) { + // 010110100101DDDDEE11110iiiiidddd | if (!p0.new) RD = #0 ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a603c00) { + // 010110100110DDDDEE11110iiiiidddd | if (p0) RD = #0 ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a403c00) { + // 010110100100DDDDEE11110iiiiidddd | if (p0.new) RD = #0 ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cfe00) == 0x59003c00) { + // 01011001ssss00IIEE11110iiiiidddd | p0 = cmp.eq(Rs,#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x5c003c00) { + // 010111000II00DDDEE11110iiiiidddd | RDD = combine(#0,#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x5c083c00) { + // 010111000II01DDDEE11110iiiiidddd | RDD = combine(#1,#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x5c103c00) { + // 010111000II10DDDEE11110iiiiidddd | RDD = combine(#2,#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x5c183c00) { + // 010111000II11DDDEE11110iiiiidddd | RDD = combine(#3,#II) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08fe00) == 0x5d083c00) { + // 01011101ssss1DDDEE11110iiiiidddd | RDD = combine(Rs,#0) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08fe00) == 0x5d003c00) { + // 01011101ssss0DDDEE11110iiiiidddd | RDD = combine(#0,Rs) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x53003c00) { + // 01010011ssssDDDDEE11110iiiiidddd | RD = add(Rs,#n1) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x51003c00) { + // 01010001ssssDDDDEE11110iiiiidddd | RD = add(Rs,#1) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fe00) == 0x48003c00) { + // 010010IIIIIIDDDDEE11110iiiiidddd | RD = #II ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a003c00) { + // 010110100000DDDDEE11110iiiiidddd | RD = #n1 ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = #-1 ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x55003c00) { + // 01010101ssssDDDDEE11110iiiiidddd | RD = sxtb(Rs) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x54003c00) { + // 01010100ssssDDDDEE11110iiiiidddd | RD = sxth(Rs) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x50003c00) { + // 01010000ssssDDDDEE11110iiiiidddd | RD = Rs ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = %s ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x57003c00) { + // 01010111ssssDDDDEE11110iiiiidddd | RD = and(Rs,#255) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x56003c00) { + // 01010110ssssDDDDEE11110iiiiidddd | RD = zxth(Rs) ; Rd = memw(r29+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRI_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = memw(R29+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x40002800) { + // 01000IIIIIIIxxxxEE101iiissssdddd | Rx = add(Rxin,#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x58002800) { + // 01011000SSSSxxxxEE101iiissssdddd | Rx = add(Rxin,RS) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f800) == 0x4c002800) { + // 010011IIIIIIDDDDEE101iiissssdddd | RD = add(r29,#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x52002800) { + // 01010010SSSSDDDDEE101iiissssdddd | RD = and(RS,#1) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = and(%s,#1) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a702800) { + // 010110100111DDDDEE101iiissssdddd | if (!p0) RD = #0 ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a502800) { + // 010110100101DDDDEE101iiissssdddd | if (!p0.new) RD = #0 ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a602800) { + // 010110100110DDDDEE101iiissssdddd | if (p0) RD = #0 ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + sprintf(hi->mnem, "%s if (P0) %s = #0 ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a402800) { + // 010110100100DDDDEE101iiissssdddd | if (p0.new) RD = #0 ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cf800) == 0x59002800) { + // 01011001SSSS00IIEE101iiissssdddd | p0 = cmp.eq(RS,#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c002800) { + // 010111000II00DDDEE101iiissssdddd | RDD = combine(#0,#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c082800) { + // 010111000II01DDDEE101iiissssdddd | RDD = combine(#1,#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c102800) { + // 010111000II10DDDEE101iiissssdddd | RDD = combine(#2,#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x5c182800) { + // 010111000II11DDDEE101iiissssdddd | RDD = combine(#3,#II) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f800) == 0x5d082800) { + // 01011101SSSS1DDDEE101iiissssdddd | RDD = combine(RS,#0) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f800) == 0x5d002800) { + // 01011101SSSS0DDDEE101iiissssdddd | RDD = combine(#0,RS) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x53002800) { + // 01010011SSSSDDDDEE101iiissssdddd | RD = add(RS,#n1) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hi->ops[5].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x51002800) { + // 01010001SSSSDDDDEE101iiissssdddd | RD = add(RS,#1) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = add(%s,#1) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f800) == 0x48002800) { + // 010010IIIIIIDDDDEE101iiissssdddd | RD = #II ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = ##0x%x ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x5a002800) { + // 010110100000DDDDEE101iiissssdddd | RD = #n1 ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = #-1 ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x55002800) { + // 01010101SSSSDDDDEE101iiissssdddd | RD = sxtb(RS) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = sxtb(%s) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x54002800) { + // 01010100SSSSDDDDEE101iiissssdddd | RD = sxth(RS) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = sxth(%s) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x50002800) { + // 01010000SSSSDDDDEE101iiissssdddd | RD = RS ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = %s ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x57002800) { + // 01010111SSSSDDDDEE101iiissssdddd | RD = and(RS,#255) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = and(%s,#255) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x56002800) { + // 01010110SSSSDDDDEE101iiissssdddd | RD = zxth(RS) ; Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + sprintf(hi->mnem, "%s %s = zxth(%s) ; %s = memuh(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f40) { + // 01000iiiiiiixxxxEE11111101000000 | Rx = add(Rxin,#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f40) { + // 01011000ssssxxxxEE11111101000000 | Rx = add(Rxin,Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f40) { + // 010011iiiiiiddddEE11111101000000 | Rd = add(r29,#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f40) { + // 01010010ssssddddEE11111101000000 | Rd = and(Rs,#1) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f40) { + // 010110100111ddddEE11111101000000 | if (!p0) Rd = #0 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f40) { + // 010110100101ddddEE11111101000000 | if (!p0.new) Rd = #0 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f40) { + // 010110100110ddddEE11111101000000 | if (p0) Rd = #0 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f40) { + // 010110100100ddddEE11111101000000 | if (p0.new) Rd = #0 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f40) { + // 01011001ssss00iiEE11111101000000 | p0 = cmp.eq(Rs,#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f40) { + // 010111000ii00dddEE11111101000000 | Rdd = combine(#0,#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f40) { + // 010111000ii01dddEE11111101000000 | Rdd = combine(#1,#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f40) { + // 010111000ii10dddEE11111101000000 | Rdd = combine(#2,#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f40) { + // 010111000ii11dddEE11111101000000 | Rdd = combine(#3,#Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f40) { + // 01011101ssss1dddEE11111101000000 | Rdd = combine(Rs,#0) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f40) { + // 01011101ssss0dddEE11111101000000 | Rdd = combine(#0,Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f40) { + // 01010011ssssddddEE11111101000000 | Rd = add(Rs,#n1) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f40) { + // 01010001ssssddddEE11111101000000 | Rd = add(Rs,#1) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f40) { + // 010010iiiiiiddddEE11111101000000 | Rd = #Ii ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f40) { + // 010110100000ddddEE11111101000000 | Rd = #n1 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f40) { + // 01010101ssssddddEE11111101000000 | Rd = sxtb(Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f40) { + // 01010100ssssddddEE11111101000000 | Rd = sxth(Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f40) { + // 01010000ssssddddEE11111101000000 | Rd = Rs ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f40) { + // 01010111ssssddddEE11111101000000 | Rd = and(Rs,#255) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f40) { + // 01010110ssssddddEE11111101000000 | Rd = zxth(Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f45) { + // 01000iiiiiiixxxxEE11111101000101 | Rx = add(Rxin,#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f45) { + // 01011000ssssxxxxEE11111101000101 | Rx = add(Rxin,Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f45) { + // 010011iiiiiiddddEE11111101000101 | Rd = add(r29,#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f45) { + // 01010010ssssddddEE11111101000101 | Rd = and(Rs,#1) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f45) { + // 010110100111ddddEE11111101000101 | if (!p0) Rd = #0 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f45) { + // 010110100101ddddEE11111101000101 | if (!p0.new) Rd = #0 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f45) { + // 010110100110ddddEE11111101000101 | if (p0) Rd = #0 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f45) { + // 010110100100ddddEE11111101000101 | if (p0.new) Rd = #0 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f45) { + // 01011001ssss00iiEE11111101000101 | p0 = cmp.eq(Rs,#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f45) { + // 010111000ii00dddEE11111101000101 | Rdd = combine(#0,#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f45) { + // 010111000ii01dddEE11111101000101 | Rdd = combine(#1,#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f45) { + // 010111000ii10dddEE11111101000101 | Rdd = combine(#2,#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f45) { + // 010111000ii11dddEE11111101000101 | Rdd = combine(#3,#Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f45) { + // 01011101ssss1dddEE11111101000101 | Rdd = combine(Rs,#0) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f45) { + // 01011101ssss0dddEE11111101000101 | Rdd = combine(#0,Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f45) { + // 01010011ssssddddEE11111101000101 | Rd = add(Rs,#n1) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f45) { + // 01010001ssssddddEE11111101000101 | Rd = add(Rs,#1) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f45) { + // 010010iiiiiiddddEE11111101000101 | Rd = #Ii ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f45) { + // 010110100000ddddEE11111101000101 | Rd = #n1 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f45) { + // 01010101ssssddddEE11111101000101 | Rd = sxtb(Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f45) { + // 01010100ssssddddEE11111101000101 | Rd = sxth(Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f45) { + // 01010000ssssddddEE11111101000101 | Rd = Rs ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f45) { + // 01010111ssssddddEE11111101000101 | Rd = and(Rs,#255) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f45) { + // 01010110ssssddddEE11111101000101 | Rd = zxth(Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (!P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f47) { + // 01000iiiiiiixxxxEE11111101000111 | Rx = add(Rxin,#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f47) { + // 01011000ssssxxxxEE11111101000111 | Rx = add(Rxin,Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f47) { + // 010011iiiiiiddddEE11111101000111 | Rd = add(r29,#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f47) { + // 01010010ssssddddEE11111101000111 | Rd = and(Rs,#1) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f47) { + // 010110100111ddddEE11111101000111 | if (!p0) Rd = #0 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f47) { + // 010110100101ddddEE11111101000111 | if (!p0.new) Rd = #0 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f47) { + // 010110100110ddddEE11111101000111 | if (p0) Rd = #0 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f47) { + // 010110100100ddddEE11111101000111 | if (p0.new) Rd = #0 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f47) { + // 01011001ssss00iiEE11111101000111 | p0 = cmp.eq(Rs,#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f47) { + // 010111000ii00dddEE11111101000111 | Rdd = combine(#0,#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f47) { + // 010111000ii01dddEE11111101000111 | Rdd = combine(#1,#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f47) { + // 010111000ii10dddEE11111101000111 | Rdd = combine(#2,#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f47) { + // 010111000ii11dddEE11111101000111 | Rdd = combine(#3,#Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f47) { + // 01011101ssss1dddEE11111101000111 | Rdd = combine(Rs,#0) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f47) { + // 01011101ssss0dddEE11111101000111 | Rdd = combine(#0,Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f47) { + // 01010011ssssddddEE11111101000111 | Rd = add(Rs,#n1) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f47) { + // 01010001ssssddddEE11111101000111 | Rd = add(Rs,#1) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f47) { + // 010010iiiiiiddddEE11111101000111 | Rd = #Ii ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f47) { + // 010110100000ddddEE11111101000111 | Rd = #n1 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f47) { + // 01010101ssssddddEE11111101000111 | Rd = sxtb(Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f47) { + // 01010100ssssddddEE11111101000111 | Rd = sxth(Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f47) { + // 01010000ssssddddEE11111101000111 | Rd = Rs ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f47) { + // 01010111ssssddddEE11111101000111 | Rd = and(Rs,#255) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f47) { + // 01010110ssssddddEE11111101000111 | Rd = zxth(Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_FNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (!P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f44) { + // 01000iiiiiiixxxxEE11111101000100 | Rx = add(Rxin,#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f44) { + // 01011000ssssxxxxEE11111101000100 | Rx = add(Rxin,Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f44) { + // 010011iiiiiiddddEE11111101000100 | Rd = add(r29,#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f44) { + // 01010010ssssddddEE11111101000100 | Rd = and(Rs,#1) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f44) { + // 010110100111ddddEE11111101000100 | if (!p0) Rd = #0 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f44) { + // 010110100101ddddEE11111101000100 | if (!p0.new) Rd = #0 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f44) { + // 010110100110ddddEE11111101000100 | if (p0) Rd = #0 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f44) { + // 010110100100ddddEE11111101000100 | if (p0.new) Rd = #0 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f44) { + // 01011001ssss00iiEE11111101000100 | p0 = cmp.eq(Rs,#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f44) { + // 010111000ii00dddEE11111101000100 | Rdd = combine(#0,#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f44) { + // 010111000ii01dddEE11111101000100 | Rdd = combine(#1,#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f44) { + // 010111000ii10dddEE11111101000100 | Rdd = combine(#2,#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f44) { + // 010111000ii11dddEE11111101000100 | Rdd = combine(#3,#Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f44) { + // 01011101ssss1dddEE11111101000100 | Rdd = combine(Rs,#0) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f44) { + // 01011101ssss0dddEE11111101000100 | Rdd = combine(#0,Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f44) { + // 01010011ssssddddEE11111101000100 | Rd = add(Rs,#n1) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f44) { + // 01010001ssssddddEE11111101000100 | Rd = add(Rs,#1) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f44) { + // 010010iiiiiiddddEE11111101000100 | Rd = #Ii ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f44) { + // 010110100000ddddEE11111101000100 | Rd = #n1 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f44) { + // 01010101ssssddddEE11111101000100 | Rd = sxtb(Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f44) { + // 01010100ssssddddEE11111101000100 | Rd = sxth(Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f44) { + // 01010000ssssddddEE11111101000100 | Rd = Rs ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f44) { + // 01010111ssssddddEE11111101000100 | Rd = and(Rs,#255) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f44) { + // 01010110ssssddddEE11111101000100 | Rd = zxth(Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (P0) dealloc_return %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f46) { + // 01000iiiiiiixxxxEE11111101000110 | Rx = add(Rxin,#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f46) { + // 01011000ssssxxxxEE11111101000110 | Rx = add(Rxin,Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f46) { + // 010011iiiiiiddddEE11111101000110 | Rd = add(r29,#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f46) { + // 01010010ssssddddEE11111101000110 | Rd = and(Rs,#1) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f46) { + // 010110100111ddddEE11111101000110 | if (!p0) Rd = #0 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f46) { + // 010110100101ddddEE11111101000110 | if (!p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f46) { + // 010110100110ddddEE11111101000110 | if (p0) Rd = #0 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f46) { + // 010110100100ddddEE11111101000110 | if (p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f46) { + // 01011001ssss00iiEE11111101000110 | p0 = cmp.eq(Rs,#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f46) { + // 010111000ii00dddEE11111101000110 | Rdd = combine(#0,#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f46) { + // 010111000ii01dddEE11111101000110 | Rdd = combine(#1,#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f46) { + // 010111000ii10dddEE11111101000110 | Rdd = combine(#2,#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f46) { + // 010111000ii11dddEE11111101000110 | Rdd = combine(#3,#Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f46) { + // 01011101ssss1dddEE11111101000110 | Rdd = combine(Rs,#0) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f46) { + // 01011101ssss0dddEE11111101000110 | Rdd = combine(#0,Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f46) { + // 01010011ssssddddEE11111101000110 | Rd = add(Rs,#n1) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f46) { + // 01010001ssssddddEE11111101000110 | Rd = add(Rs,#1) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f46) { + // 010010iiiiiiddddEE11111101000110 | Rd = #Ii ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = ##0x%x ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f46) { + // 010110100000ddddEE11111101000110 | Rd = #n1 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + sprintf(hi->mnem, "%s %s = #-1 ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f46) { + // 01010101ssssddddEE11111101000110 | Rd = sxtb(Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f46) { + // 01010100ssssddddEE11111101000110 | Rd = sxth(Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f46) { + // 01010000ssssddddEE11111101000110 | Rd = Rs ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = %s ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f46) { + // 01010111ssssddddEE11111101000110 | Rd = and(Rs,#255) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f46) { + // 01010110ssssddddEE11111101000110 | Rd = zxth(Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_TNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; if (P0.new) dealloc_return:nt %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x6: + if ((hi_u32 & 0xf800f000) == 0x60001000) { + // 01100IIIIIIIxxxxEE01iiiisssstttt | Rx = add(Rxin,#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x78001000) { + // 01111000SSSSxxxxEE01iiiisssstttt | Rx = add(Rxin,RS) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f000) == 0x6c001000) { + // 011011IIIIIIddddEE01iiiisssstttt | Rd = add(r29,#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x72001000) { + // 01110010SSSSddddEE01iiiisssstttt | Rd = and(RS,#1) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a701000) { + // 011110100111ddddEE01iiiisssstttt | if (!p0) Rd = #0 ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a501000) { + // 011110100101ddddEE01iiiisssstttt | if (!p0.new) Rd = #0 ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a601000) { + // 011110100110ddddEE01iiiisssstttt | if (p0) Rd = #0 ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a401000) { + // 011110100100ddddEE01iiiisssstttt | if (p0.new) Rd = #0 ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cf000) == 0x79001000) { + // 01111001SSSS00IIEE01iiiisssstttt | p0 = cmp.eq(RS,#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x7c001000) { + // 011111000II00dddEE01iiiisssstttt | Rdd = combine(#0,#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x7c081000) { + // 011111000II01dddEE01iiiisssstttt | Rdd = combine(#1,#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x7c101000) { + // 011111000II10dddEE01iiiisssstttt | Rdd = combine(#2,#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x7c181000) { + // 011111000II11dddEE01iiiisssstttt | Rdd = combine(#3,#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f000) == 0x7d081000) { + // 01111101SSSS1dddEE01iiiisssstttt | Rdd = combine(RS,#0) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f000) == 0x7d001000) { + // 01111101SSSS0dddEE01iiiisssstttt | Rdd = combine(#0,RS) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x73001000) { + // 01110011SSSSddddEE01iiiisssstttt | Rd = add(RS,#n1) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x71001000) { + // 01110001SSSSddddEE01iiiisssstttt | Rd = add(RS,#1) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f000) == 0x68001000) { + // 011010IIIIIIddddEE01iiiisssstttt | Rd = #II ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = ##0x%x ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a001000) { + // 011110100000ddddEE01iiiisssstttt | Rd = #n1 ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = #-1 ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x75001000) { + // 01110101SSSSddddEE01iiiisssstttt | Rd = sxtb(RS) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x74001000) { + // 01110100SSSSddddEE01iiiisssstttt | Rd = sxth(RS) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x70001000) { + // 01110000SSSSddddEE01iiiisssstttt | Rd = RS ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = %s ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x77001000) { + // 01110111SSSSddddEE01iiiisssstttt | Rd = and(RS,#255) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x76001000) { + // 01110110SSSSddddEE01iiiisssstttt | Rd = zxth(RS) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f000) == 0x60000000) { + // 01100IIIIIIIxxxxEE00iiiisssstttt | Rx = add(Rxin,#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x78000000) { + // 01111000SSSSxxxxEE00iiiisssstttt | Rx = add(Rxin,RS) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f000) == 0x6c000000) { + // 011011IIIIIIddddEE00iiiisssstttt | Rd = add(r29,#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x72000000) { + // 01110010SSSSddddEE00iiiisssstttt | Rd = and(RS,#1) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a700000) { + // 011110100111ddddEE00iiiisssstttt | if (!p0) Rd = #0 ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a500000) { + // 011110100101ddddEE00iiiisssstttt | if (!p0.new) Rd = #0 ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a600000) { + // 011110100110ddddEE00iiiisssstttt | if (p0) Rd = #0 ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a400000) { + // 011110100100ddddEE00iiiisssstttt | if (p0.new) Rd = #0 ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cf000) == 0x79000000) { + // 01111001SSSS00IIEE00iiiisssstttt | p0 = cmp.eq(RS,#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x7c000000) { + // 011111000II00dddEE00iiiisssstttt | Rdd = combine(#0,#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x7c080000) { + // 011111000II01dddEE00iiiisssstttt | Rdd = combine(#1,#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x7c100000) { + // 011111000II10dddEE00iiiisssstttt | Rdd = combine(#2,#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f000) == 0x7c180000) { + // 011111000II11dddEE00iiiisssstttt | Rdd = combine(#3,#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f000) == 0x7d080000) { + // 01111101SSSS1dddEE00iiiisssstttt | Rdd = combine(RS,#0) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f000) == 0x7d000000) { + // 01111101SSSS0dddEE00iiiisssstttt | Rdd = combine(#0,RS) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x73000000) { + // 01110011SSSSddddEE00iiiisssstttt | Rd = add(RS,#n1) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x71000000) { + // 01110001SSSSddddEE00iiiisssstttt | Rd = add(RS,#1) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f000) == 0x68000000) { + // 011010IIIIIIddddEE00iiiisssstttt | Rd = #II ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = ##0x%x ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f000) == 0x7a000000) { + // 011110100000ddddEE00iiiisssstttt | Rd = #n1 ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = #-1 ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x75000000) { + // 01110101SSSSddddEE00iiiisssstttt | Rd = sxtb(RS) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x74000000) { + // 01110100SSSSddddEE00iiiisssstttt | Rd = sxth(RS) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x70000000) { + // 01110000SSSSddddEE00iiiisssstttt | Rd = RS ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = %s ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x77000000) { + // 01110111SSSSddddEE00iiiisssstttt | Rd = and(RS,#255) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x76000000) { + // 01110110SSSSddddEE00iiiisssstttt | Rd = zxth(RS) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x7: + if ((hi_u32 & 0xf800fe0f) == 0x60003c00) { + // 01100IIIIIIIxxxxEE11110iiiii0000 | Rx = add(Rxin,#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0x78003c00) { + // 01111000ssssxxxxEE11110iiiii0000 | Rx = add(Rxin,Rs) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fe0f) == 0x6c003c00) { + // 011011IIIIIIddddEE11110iiiii0000 | Rd = add(r29,#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0x72003c00) { + // 01110010ssssddddEE11110iiiii0000 | Rd = and(Rs,#1) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = and(%s,#1) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a703c00) { + // 011110100111ddddEE11110iiiii0000 | if (!p0) Rd = #0 ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a503c00) { + // 011110100101ddddEE11110iiiii0000 | if (!p0.new) Rd = #0 ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a603c00) { + // 011110100110ddddEE11110iiiii0000 | if (p0) Rd = #0 ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s if (P0) %s = #0 ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a403c00) { + // 011110100100ddddEE11110iiiii0000 | if (p0.new) Rd = #0 ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cfe0f) == 0x79003c00) { + // 01111001ssss00IIEE11110iiiii0000 | p0 = cmp.eq(Rs,#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe0f) == 0x7c003c00) { + // 011111000II00dddEE11110iiiii0000 | Rdd = combine(#0,#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe0f) == 0x7c083c00) { + // 011111000II01dddEE11110iiiii0000 | Rdd = combine(#1,#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe0f) == 0x7c103c00) { + // 011111000II10dddEE11110iiiii0000 | Rdd = combine(#2,#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe0f) == 0x7c183c00) { + // 011111000II11dddEE11110iiiii0000 | Rdd = combine(#3,#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08fe0f) == 0x7d083c00) { + // 01111101ssss1dddEE11110iiiii0000 | Rdd = combine(Rs,#0) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08fe0f) == 0x7d003c00) { + // 01111101ssss0dddEE11110iiiii0000 | Rdd = combine(#0,Rs) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0x73003c00) { + // 01110011ssssddddEE11110iiiii0000 | Rd = add(Rs,#n1) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0x71003c00) { + // 01110001ssssddddEE11110iiiii0000 | Rd = add(Rs,#1) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = add(%s,#1) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fe0f) == 0x68003c00) { + // 011010IIIIIIddddEE11110iiiii0000 | Rd = #II ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = ##0x%x ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a003c00) { + // 011110100000ddddEE11110iiiii0000 | Rd = #n1 ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = #-1 ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0x75003c00) { + // 01110101ssssddddEE11110iiiii0000 | Rd = sxtb(Rs) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = sxtb(%s) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0x74003c00) { + // 01110100ssssddddEE11110iiiii0000 | Rd = sxth(Rs) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = sxth(%s) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0x70003c00) { + // 01110000ssssddddEE11110iiiii0000 | Rd = Rs ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = %s ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0x77003c00) { + // 01110111ssssddddEE11110iiiii0000 | Rd = and(Rs,#255) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = and(%s,#255) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0x76003c00) { + // 01110110ssssddddEE11110iiiii0000 | Rd = zxth(Rs) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = zxth(%s) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x60003200) { + // 01100IIIIIIIxxxxEE110010ssssiiii | Rx = add(Rxin,#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x78003200) { + // 01111000SSSSxxxxEE110010ssssiiii | Rx = add(Rxin,RS) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x6c003200) { + // 011011IIIIIIddddEE110010ssssiiii | Rd = add(r29,#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x72003200) { + // 01110010SSSSddddEE110010ssssiiii | Rd = and(RS,#1) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#1) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a703200) { + // 011110100111ddddEE110010ssssiiii | if (!p0) Rd = #0 ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a503200) { + // 011110100101ddddEE110010ssssiiii | if (!p0.new) Rd = #0 ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a603200) { + // 011110100110ddddEE110010ssssiiii | if (p0) Rd = #0 ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (P0) %s = #0 ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a403200) { + // 011110100100ddddEE110010ssssiiii | if (p0.new) Rd = #0 ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff00) == 0x79003200) { + // 01111001SSSS00IIEE110010ssssiiii | p0 = cmp.eq(RS,#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c003200) { + // 011111000II00dddEE110010ssssiiii | Rdd = combine(#0,#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c083200) { + // 011111000II01dddEE110010ssssiiii | Rdd = combine(#1,#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c103200) { + // 011111000II10dddEE110010ssssiiii | Rdd = combine(#2,#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c183200) { + // 011111000II11dddEE110010ssssiiii | Rdd = combine(#3,#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x7d083200) { + // 01111101SSSS1dddEE110010ssssiiii | Rdd = combine(RS,#0) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x7d003200) { + // 01111101SSSS0dddEE110010ssssiiii | Rdd = combine(#0,RS) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x73003200) { + // 01110011SSSSddddEE110010ssssiiii | Rd = add(RS,#n1) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x71003200) { + // 01110001SSSSddddEE110010ssssiiii | Rd = add(RS,#1) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#1) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003200) { + // 011010IIIIIIddddEE110010ssssiiii | Rd = #II ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = ##0x%x ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a003200) { + // 011110100000ddddEE110010ssssiiii | Rd = #n1 ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = #-1 ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x75003200) { + // 01110101SSSSddddEE110010ssssiiii | Rd = sxtb(RS) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = sxtb(%s) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x74003200) { + // 01110100SSSSddddEE110010ssssiiii | Rd = sxth(RS) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = sxth(%s) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x70003200) { + // 01110000SSSSddddEE110010ssssiiii | Rd = RS ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = %s ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x77003200) { + // 01110111SSSSddddEE110010ssssiiii | Rd = and(RS,#255) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#255) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x76003200) { + // 01110110SSSSddddEE110010ssssiiii | Rd = zxth(RS) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = zxth(%s) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x60003300) { + // 01100IIIIIIIxxxxEE110011ssssiiii | Rx = add(Rxin,#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x78003300) { + // 01111000SSSSxxxxEE110011ssssiiii | Rx = add(Rxin,RS) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x6c003300) { + // 011011IIIIIIddddEE110011ssssiiii | Rd = add(r29,#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x72003300) { + // 01110010SSSSddddEE110011ssssiiii | Rd = and(RS,#1) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#1) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a703300) { + // 011110100111ddddEE110011ssssiiii | if (!p0) Rd = #0 ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a503300) { + // 011110100101ddddEE110011ssssiiii | if (!p0.new) Rd = #0 ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a603300) { + // 011110100110ddddEE110011ssssiiii | if (p0) Rd = #0 ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (P0) %s = #0 ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a403300) { + // 011110100100ddddEE110011ssssiiii | if (p0.new) Rd = #0 ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff00) == 0x79003300) { + // 01111001SSSS00IIEE110011ssssiiii | p0 = cmp.eq(RS,#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c003300) { + // 011111000II00dddEE110011ssssiiii | Rdd = combine(#0,#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c083300) { + // 011111000II01dddEE110011ssssiiii | Rdd = combine(#1,#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c103300) { + // 011111000II10dddEE110011ssssiiii | Rdd = combine(#2,#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c183300) { + // 011111000II11dddEE110011ssssiiii | Rdd = combine(#3,#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x7d083300) { + // 01111101SSSS1dddEE110011ssssiiii | Rdd = combine(RS,#0) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x7d003300) { + // 01111101SSSS0dddEE110011ssssiiii | Rdd = combine(#0,RS) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x73003300) { + // 01110011SSSSddddEE110011ssssiiii | Rd = add(RS,#n1) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x71003300) { + // 01110001SSSSddddEE110011ssssiiii | Rd = add(RS,#1) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = add(%s,#1) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003300) { + // 011010IIIIIIddddEE110011ssssiiii | Rd = #II ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = ##0x%x ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a003300) { + // 011110100000ddddEE110011ssssiiii | Rd = #n1 ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = #-1 ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x75003300) { + // 01110101SSSSddddEE110011ssssiiii | Rd = sxtb(RS) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = sxtb(%s) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x74003300) { + // 01110100SSSSddddEE110011ssssiiii | Rd = sxth(RS) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = sxth(%s) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x70003300) { + // 01110000SSSSddddEE110011ssssiiii | Rd = RS ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = %s ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x77003300) { + // 01110111SSSSddddEE110011ssssiiii | Rd = and(RS,#255) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = and(%s,#255) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x76003300) { + // 01110110SSSSddddEE110011ssssiiii | Rd = zxth(RS) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = zxth(%s) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0x60002a00) { + // 01100IIIIIIIxxxxEE10101iiiiiittt | Rx = add(Rxin,#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x78002a00) { + // 01111000ssssxxxxEE10101iiiiiittt | Rx = add(Rxin,Rs) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fe00) == 0x6c002a00) { + // 011011IIIIIIddddEE10101iiiiiittt | Rd = add(r29,#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x72002a00) { + // 01110010ssssddddEE10101iiiiiittt | Rd = and(Rs,#1) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a702a00) { + // 011110100111ddddEE10101iiiiiittt | if (!p0) Rd = #0 ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 8)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a502a00) { + // 011110100101ddddEE10101iiiiiittt | if (!p0.new) Rd = #0 ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 8)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a602a00) { + // 011110100110ddddEE10101iiiiiittt | if (p0) Rd = #0 ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 8)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a402a00) { + // 011110100100ddddEE10101iiiiiittt | if (p0.new) Rd = #0 ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 8)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cfe00) == 0x79002a00) { + // 01111001ssss00IIEE10101iiiiiittt | p0 = cmp.eq(Rs,#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x7c002a00) { + // 011111000II00dddEE10101iiiiiittt | Rdd = combine(#0,#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x7c082a00) { + // 011111000II01dddEE10101iiiiiittt | Rdd = combine(#1,#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x7c102a00) { + // 011111000II10dddEE10101iiiiiittt | Rdd = combine(#2,#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x7c182a00) { + // 011111000II11dddEE10101iiiiiittt | Rdd = combine(#3,#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08fe00) == 0x7d082a00) { + // 01111101ssss1dddEE10101iiiiiittt | Rdd = combine(Rs,#0) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08fe00) == 0x7d002a00) { + // 01111101ssss0dddEE10101iiiiiittt | Rdd = combine(#0,Rs) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x73002a00) { + // 01110011ssssddddEE10101iiiiiittt | Rd = add(Rs,#n1) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x71002a00) { + // 01110001ssssddddEE10101iiiiiittt | Rd = add(Rs,#1) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fe00) == 0x68002a00) { + // 011010IIIIIIddddEE10101iiiiiittt | Rd = #II ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = ##0x%x ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a002a00) { + // 011110100000ddddEE10101iiiiiittt | Rd = #n1 ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = #-1 ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x75002a00) { + // 01110101ssssddddEE10101iiiiiittt | Rd = sxtb(Rs) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x74002a00) { + // 01110100ssssddddEE10101iiiiiittt | Rd = sxth(Rs) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = sxth(%s) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x70002a00) { + // 01110000ssssddddEE10101iiiiiittt | Rd = Rs ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = %s ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x77002a00) { + // 01110111ssssddddEE10101iiiiiittt | Rd = and(Rs,#255) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x76002a00) { + // 01110110ssssddddEE10101iiiiiittt | Rd = zxth(Rs) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = zxth(%s) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0x60002000) { + // 01100IIIIIIIxxxxEE100iiisssstttt | Rx = add(Rxin,#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x78002000) { + // 01111000SSSSxxxxEE100iiisssstttt | Rx = add(Rxin,RS) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f800) == 0x6c002000) { + // 011011IIIIIIddddEE100iiisssstttt | Rd = add(r29,#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x72002000) { + // 01110010SSSSddddEE100iiisssstttt | Rd = and(RS,#1) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x7a702000) { + // 011110100111ddddEE100iiisssstttt | if (!p0) Rd = #0 ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x7a502000) { + // 011110100101ddddEE100iiisssstttt | if (!p0.new) Rd = #0 ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x7a602000) { + // 011110100110ddddEE100iiisssstttt | if (p0) Rd = #0 ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x7a402000) { + // 011110100100ddddEE100iiisssstttt | if (p0.new) Rd = #0 ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cf800) == 0x79002000) { + // 01111001SSSS00IIEE100iiisssstttt | p0 = cmp.eq(RS,#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x7c002000) { + // 011111000II00dddEE100iiisssstttt | Rdd = combine(#0,#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x7c082000) { + // 011111000II01dddEE100iiisssstttt | Rdd = combine(#1,#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x7c102000) { + // 011111000II10dddEE100iiisssstttt | Rdd = combine(#2,#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98f800) == 0x7c182000) { + // 011111000II11dddEE100iiisssstttt | Rdd = combine(#3,#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f800) == 0x7d082000) { + // 01111101SSSS1dddEE100iiisssstttt | Rdd = combine(RS,#0) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08f800) == 0x7d002000) { + // 01111101SSSS0dddEE100iiisssstttt | Rdd = combine(#0,RS) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x73002000) { + // 01110011SSSSddddEE100iiisssstttt | Rd = add(RS,#n1) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x71002000) { + // 01110001SSSSddddEE100iiisssstttt | Rd = add(RS,#1) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00f800) == 0x68002000) { + // 011010IIIIIIddddEE100iiisssstttt | Rd = #II ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = ##0x%x ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0f800) == 0x7a002000) { + // 011110100000ddddEE100iiisssstttt | Rd = #n1 ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = #-1 ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x75002000) { + // 01110101SSSSddddEE100iiisssstttt | Rd = sxtb(RS) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x74002000) { + // 01110100SSSSddddEE100iiisssstttt | Rd = sxth(RS) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x70002000) { + // 01110000SSSSddddEE100iiisssstttt | Rd = RS ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = %s ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x77002000) { + // 01110111SSSSddddEE100iiisssstttt | Rd = and(RS,#255) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0x76002000) { + // 01110110SSSSddddEE100iiisssstttt | Rd = zxth(RS) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0x60002800) { + // 01100IIIIIIIxxxxEE10100iiiiitttt | Rx = add(Rxin,#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x78002800) { + // 01111000ssssxxxxEE10100iiiiitttt | Rx = add(Rxin,Rs) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fe00) == 0x6c002800) { + // 011011IIIIIIddddEE10100iiiiitttt | Rd = add(r29,#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x72002800) { + // 01110010ssssddddEE10100iiiiitttt | Rd = and(Rs,#1) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = and(%s,#1) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a702800) { + // 011110100111ddddEE10100iiiiitttt | if (!p0) Rd = #0 ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a502800) { + // 011110100101ddddEE10100iiiiitttt | if (!p0.new) Rd = #0 ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a602800) { + // 011110100110ddddEE10100iiiiitttt | if (p0) Rd = #0 ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0) %s = #0 ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a402800) { + // 011110100100ddddEE10100iiiiitttt | if (p0.new) Rd = #0 ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cfe00) == 0x79002800) { + // 01111001ssss00IIEE10100iiiiitttt | p0 = cmp.eq(Rs,#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x7c002800) { + // 011111000II00dddEE10100iiiiitttt | Rdd = combine(#0,#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x7c082800) { + // 011111000II01dddEE10100iiiiitttt | Rdd = combine(#1,#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x7c102800) { + // 011111000II10dddEE10100iiiiitttt | Rdd = combine(#2,#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98fe00) == 0x7c182800) { + // 011111000II11dddEE10100iiiiitttt | Rdd = combine(#3,#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08fe00) == 0x7d082800) { + // 01111101ssss1dddEE10100iiiiitttt | Rdd = combine(Rs,#0) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08fe00) == 0x7d002800) { + // 01111101ssss0dddEE10100iiiiitttt | Rdd = combine(#0,Rs) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x73002800) { + // 01110011ssssddddEE10100iiiiitttt | Rd = add(Rs,#n1) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x71002800) { + // 01110001ssssddddEE10100iiiiitttt | Rd = add(Rs,#1) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = add(%s,#1) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00fe00) == 0x68002800) { + // 011010IIIIIIddddEE10100iiiiitttt | Rd = #II ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = ##0x%x ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a002800) { + // 011110100000ddddEE10100iiiiitttt | Rd = #n1 ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = #-1 ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x75002800) { + // 01110101ssssddddEE10100iiiiitttt | Rd = sxtb(Rs) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = sxtb(%s) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x74002800) { + // 01110100ssssddddEE10100iiiiitttt | Rd = sxth(Rs) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = sxth(%s) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x70002800) { + // 01110000ssssddddEE10100iiiiitttt | Rd = Rs ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = %s ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x77002800) { + // 01110111ssssddddEE10100iiiiitttt | Rd = and(Rs,#255) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = and(%s,#255) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0x76002800) { + // 01110110ssssddddEE10100iiiiitttt | Rd = zxth(Rs) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = zxth(%s) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x60003000) { + // 01100IIIIIIIxxxxEE110000ssssiiii | Rx = add(Rxin,#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x78003000) { + // 01111000SSSSxxxxEE110000ssssiiii | Rx = add(Rxin,RS) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x6c003000) { + // 011011IIIIIIddddEE110000ssssiiii | Rd = add(r29,#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x72003000) { + // 01110010SSSSddddEE110000ssssiiii | Rd = and(RS,#1) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = and(%s,#1) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a703000) { + // 011110100111ddddEE110000ssssiiii | if (!p0) Rd = #0 ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a503000) { + // 011110100101ddddEE110000ssssiiii | if (!p0.new) Rd = #0 ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a603000) { + // 011110100110ddddEE110000ssssiiii | if (p0) Rd = #0 ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (P0) %s = #0 ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a403000) { + // 011110100100ddddEE110000ssssiiii | if (p0.new) Rd = #0 ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff00) == 0x79003000) { + // 01111001SSSS00IIEE110000ssssiiii | p0 = cmp.eq(RS,#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c003000) { + // 011111000II00dddEE110000ssssiiii | Rdd = combine(#0,#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c083000) { + // 011111000II01dddEE110000ssssiiii | Rdd = combine(#1,#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c103000) { + // 011111000II10dddEE110000ssssiiii | Rdd = combine(#2,#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c183000) { + // 011111000II11dddEE110000ssssiiii | Rdd = combine(#3,#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x7d083000) { + // 01111101SSSS1dddEE110000ssssiiii | Rdd = combine(RS,#0) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x7d003000) { + // 01111101SSSS0dddEE110000ssssiiii | Rdd = combine(#0,RS) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x73003000) { + // 01110011SSSSddddEE110000ssssiiii | Rd = add(RS,#n1) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x71003000) { + // 01110001SSSSddddEE110000ssssiiii | Rd = add(RS,#1) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = add(%s,#1) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003000) { + // 011010IIIIIIddddEE110000ssssiiii | Rd = #II ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = ##0x%x ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a003000) { + // 011110100000ddddEE110000ssssiiii | Rd = #n1 ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = #-1 ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x75003000) { + // 01110101SSSSddddEE110000ssssiiii | Rd = sxtb(RS) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = sxtb(%s) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x74003000) { + // 01110100SSSSddddEE110000ssssiiii | Rd = sxth(RS) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = sxth(%s) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x70003000) { + // 01110000SSSSddddEE110000ssssiiii | Rd = RS ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = %s ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x77003000) { + // 01110111SSSSddddEE110000ssssiiii | Rd = and(RS,#255) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = and(%s,#255) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x76003000) { + // 01110110SSSSddddEE110000ssssiiii | Rd = zxth(RS) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = zxth(%s) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0x60003100) { + // 01100IIIIIIIxxxxEE110001ssssiiii | Rx = add(Rxin,#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x78003100) { + // 01111000SSSSxxxxEE110001ssssiiii | Rx = add(Rxin,RS) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%sin,%s) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x6c003100) { + // 011011IIIIIIddddEE110001ssssiiii | Rd = add(r29,#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = add(R29,#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x72003100) { + // 01110010SSSSddddEE110001ssssiiii | Rd = and(RS,#1) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = and(%s,#1) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a703100) { + // 011110100111ddddEE110001ssssiiii | if (!p0) Rd = #0 ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (!P0) %s = #0 ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a503100) { + // 011110100101ddddEE110001ssssiiii | if (!p0.new) Rd = #0 ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (!P0.new) %s = #0 ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a603100) { + // 011110100110ddddEE110001ssssiiii | if (p0) Rd = #0 ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (P0) %s = #0 ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a403100) { + // 011110100100ddddEE110001ssssiiii | if (p0.new) Rd = #0 ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + sprintf(hi->mnem, "%s if (P0.new) %s = #0 ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0cff00) == 0x79003100) { + // 01111001SSSS00IIEE110001ssssiiii | p0 = cmp.eq(RS,#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c003100) { + // 011111000II00dddEE110001ssssiiii | Rdd = combine(#0,#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#0,#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c083100) { + // 011111000II01dddEE110001ssssiiii | Rdd = combine(#1,#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#1,#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c103100) { + // 011111000II10dddEE110001ssssiiii | Rdd = combine(#2,#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#2,#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff98ff00) == 0x7c183100) { + // 011111000II11dddEE110001ssssiiii | Rdd = combine(#3,#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#3,#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x7d083100) { + // 01111101SSSS1dddEE110001ssssiiii | Rdd = combine(RS,#0) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(%s,#0) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff08ff00) == 0x7d003100) { + // 01111101SSSS0dddEE110001ssssiiii | Rdd = combine(#0,RS) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = combine(#0,%s) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x73003100) { + // 01110011SSSSddddEE110001ssssiiii | Rd = add(RS,#n1) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = add(%s,#-1) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x71003100) { + // 01110001SSSSddddEE110001ssssiiii | Rd = add(RS,#1) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = add(%s,#1) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003100) { + // 011010IIIIIIddddEE110001ssssiiii | Rd = #II ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = ##0x%x ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a003100) { + // 011110100000ddddEE110001ssssiiii | Rd = #n1 ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = #-1 ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x75003100) { + // 01110101SSSSddddEE110001ssssiiii | Rd = sxtb(RS) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = sxtb(%s) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x74003100) { + // 01110100SSSSddddEE110001ssssiiii | Rd = sxth(RS) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = sxth(%s) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x70003100) { + // 01110000SSSSddddEE110001ssssiiii | Rd = RS ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = %s ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x77003100) { + // 01110111SSSSddddEE110001ssssiiii | Rd = and(RS,#255) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = and(%s,#255) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0x76003100) { + // 01110110SSSSddddEE110001ssssiiii | Rd = zxth(RS) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = zxth(%s) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x8: + if ((hi_u32 & 0xf000f000) == 0x80001000) { + // 1000IIIISSSSddddEE01iiiisssstttt | Rd = memw(RS+#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f000) == 0x90001000) { + // 1001IIIISSSSddddEE01iiiisssstttt | Rd = memub(RS+#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f000) == 0x80000000) { + // 1000IIIISSSSddddEE00iiiisssstttt | Rd = memw(RS+#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f000) == 0x90000000) { + // 1001IIIISSSSddddEE00iiiisssstttt | Rd = memub(RS+#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x9: + if ((hi_u32 & 0xfffff000) == 0x9f003000) { + // 1001111100000000EE11iiiisssstttt | deallocframe ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s deallocframe ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f000) == 0x90003000) { + // 10010IIISSSSddddEE11iiiisssstttt | Rd = memb(RS+#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x9e003000) { + // 10011110IIIIIdddEE11iiiisssstttt | Rdd = memd(r29+#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f000) == 0x80003000) { + // 10000IIISSSSddddEE11iiiisssstttt | Rd = memh(RS+#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00f000) == 0x9c003000) { + // 1001110IIIIIddddEE11iiiisssstttt | Rd = memw(r29+#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f000) == 0x88003000) { + // 10001IIISSSSddddEE11iiiisssstttt | Rd = memuh(RS+#II) ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f403000) { + // 1001111101000000EE11iiiisssstttt | dealloc_return ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s dealloc_return ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f453000) { + // 1001111101000101EE11iiiisssstttt | if (!p0) dealloc_return ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f473000) { + // 1001111101000111EE11iiiisssstttt | if (!p0.new) dealloc_return:nt ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f443000) { + // 1001111101000100EE11iiiisssstttt | if (p0) dealloc_return ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0) dealloc_return ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f463000) { + // 1001111101000110EE11iiiisssstttt | if (p0.new) dealloc_return:nt ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f002000) { + // 1001111100000000EE10iiiisssstttt | deallocframe ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s deallocframe ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f000) == 0x90002000) { + // 10010IIISSSSddddEE10iiiisssstttt | Rd = memb(RS+#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f000) == 0x9e002000) { + // 10011110IIIIIdddEE10iiiisssstttt | Rdd = memd(r29+#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f000) == 0x80002000) { + // 10000IIISSSSddddEE10iiiisssstttt | Rd = memh(RS+#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00f000) == 0x9c002000) { + // 1001110IIIIIddddEE10iiiisssstttt | Rd = memw(r29+#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f000) == 0x88002000) { + // 10001IIISSSSddddEE10iiiisssstttt | Rd = memuh(RS+#II) ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f402000) { + // 1001111101000000EE10iiiisssstttt | dealloc_return ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s dealloc_return ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f452000) { + // 1001111101000101EE10iiiisssstttt | if (!p0) dealloc_return ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f472000) { + // 1001111101000111EE10iiiisssstttt | if (!p0.new) dealloc_return:nt ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f442000) { + // 1001111101000100EE10iiiisssstttt | if (p0) dealloc_return ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0) dealloc_return ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff000) == 0x9f462000) { + // 1001111101000110EE10iiiisssstttt | if (p0.new) dealloc_return:nt ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xa: + if ((hi_u32 & 0xf000f000) == 0xb0001000) { + // 1011IIIISSSSTTTTEE01iiiisssstttt | memb(RS+#II) = RT ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f000) == 0xa0001000) { + // 1010IIIISSSSTTTTEE01iiiisssstttt | memw(RS+#II) = RT ; memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS1_STOREB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f000) == 0xa0000000) { + // 1010IIIISSSSTTTTEE00iiiisssstttt | memw(RS+#II) = RT ; memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS1_STOREW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xb: + if ((hi_u32 & 0xf000fe0f) == 0xb0003c00) { + // 1011IIIIssssttttEE11110iiiii0000 | memb(Rs+#II) = Rt ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe0f) == 0xa0003c00) { + // 1010IIIIssssttttEE11110iiiii0000 | memw(Rs+#II) = Rt ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xb0003200) { + // 1011IIIISSSSttttEE110010ssssiiii | memb(RS+#II) = Rt ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xa0003200) { + // 1010IIIISSSSttttEE110010ssssiiii | memw(RS+#II) = Rt ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xb0003300) { + // 1011IIIISSSSttttEE110011ssssiiii | memb(RS+#II) = Rt ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xa0003300) { + // 1010IIIISSSSttttEE110011ssssiiii | memw(RS+#II) = Rt ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0xb0002a00) { + // 1011IIIIssssTTTTEE10101iiiiiittt | memb(Rs+#II) = RT ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0xa0002a00) { + // 1010IIIIssssTTTTEE10101iiiiiittt | memw(Rs+#II) = RT ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0xb0002000) { + // 1011IIIISSSSTTTTEE100iiisssstttt | memb(RS+#II) = RT ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0xa0002000) { + // 1010IIIISSSSTTTTEE100iiisssstttt | memw(RS+#II) = RT ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0xb0002800) { + // 1011IIIIssssTTTTEE10100iiiiitttt | memb(Rs+#II) = RT ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0xa0002800) { + // 1010IIIIssssTTTTEE10100iiiiitttt | memw(Rs+#II) = RT ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xb0003000) { + // 1011IIIISSSSttttEE110000ssssiiii | memb(RS+#II) = Rt ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xa0003000) { + // 1010IIIISSSSttttEE110000ssssiiii | memw(RS+#II) = Rt ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xb0003100) { + // 1011IIIISSSSttttEE110001ssssiiii | memb(RS+#II) = Rt ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xa0003100) { + // 1010IIIISSSSttttEE110001ssssiiii | memw(RS+#II) = Rt ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xc: + if ((hi_u32 & 0xf000fe0f) == 0xc0001c00) { + // 1100IIIIssssddddEE01110iiiii0000 | Rd = memw(Rs+#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe0f) == 0xd0001c00) { + // 1101IIIIssssddddEE01110iiiii0000 | Rd = memub(Rs+#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xc0001200) { + // 1100IIIISSSSddddEE010010ssssiiii | Rd = memw(RS+#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xd0001200) { + // 1101IIIISSSSddddEE010010ssssiiii | Rd = memub(RS+#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xc0001300) { + // 1100IIIISSSSddddEE010011ssssiiii | Rd = memw(RS+#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xd0001300) { + // 1101IIIISSSSddddEE010011ssssiiii | Rd = memub(RS+#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0xc0000a00) { + // 1100IIIIssssddddEE00101iiiiiittt | Rd = memw(Rs+#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0xd0000a00) { + // 1101IIIIssssddddEE00101iiiiiittt | Rd = memub(Rs+#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0xc0000000) { + // 1100IIIISSSSddddEE000iiisssstttt | Rd = memw(RS+#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000f800) == 0xd0000000) { + // 1101IIIISSSSddddEE000iiisssstttt | Rd = memub(RS+#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0xc0000800) { + // 1100IIIIssssddddEE00100iiiiitttt | Rd = memw(Rs+#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000fe00) == 0xd0000800) { + // 1101IIIIssssddddEE00100iiiiitttt | Rd = memub(Rs+#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xc0001000) { + // 1100IIIISSSSddddEE010000ssssiiii | Rd = memw(RS+#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xd0001000) { + // 1101IIIISSSSddddEE010000ssssiiii | Rd = memub(RS+#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xc0001100) { + // 1100IIIISSSSddddEE010001ssssiiii | Rd = memw(RS+#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memw(%s+#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf000ff00) == 0xd0001100) { + // 1101IIIISSSSddddEE010001ssssiiii | Rd = memub(RS+#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memub(%s+#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xd: + if ((hi_u32 & 0xfffffe0f) == 0xdf003c00) { + // 1101111100000000EE11110iiiii0000 | deallocframe ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + sprintf(hi->mnem, "%s deallocframe ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe0f) == 0xd0003c00) { + // 11010IIIssssddddEE11110iiiii0000 | Rd = memb(Rs+#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0xde003c00) { + // 11011110IIIIIdddEE11110iiiii0000 | Rdd = memd(r29+#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe0f) == 0xc0003c00) { + // 11000IIIssssddddEE11110iiiii0000 | Rd = memh(Rs+#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00fe0f) == 0xdc003c00) { + // 1101110IIIIIddddEE11110iiiii0000 | Rd = memw(r29+#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe0f) == 0xc8003c00) { + // 11001IIIssssddddEE11110iiiii0000 | Rd = memuh(Rs+#II) ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf403c00) { + // 1101111101000000EE11110iiiii0000 | dealloc_return ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + sprintf(hi->mnem, "%s dealloc_return ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf453c00) { + // 1101111101000101EE11110iiiii0000 | if (!p0) dealloc_return ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf473c00) { + // 1101111101000111EE11110iiiii0000 | if (!p0.new) dealloc_return:nt ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf443c00) { + // 1101111101000100EE11110iiiii0000 | if (p0) dealloc_return ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf463c00) { + // 1101111101000110EE11110iiiii0000 | if (p0.new) dealloc_return:nt ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf003200) { + // 1101111100000000EE110010ssssiiii | deallocframe ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s deallocframe ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xd0003200) { + // 11010IIISSSSddddEE110010ssssiiii | Rd = memb(RS+#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xde003200) { + // 11011110IIIIIdddEE110010ssssiiii | Rdd = memd(r29+#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xc0003200) { + // 11000IIISSSSddddEE110010ssssiiii | Rd = memh(RS+#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xdc003200) { + // 1101110IIIIIddddEE110010ssssiiii | Rd = memw(r29+#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xc8003200) { + // 11001IIISSSSddddEE110010ssssiiii | Rd = memuh(RS+#II) ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf403200) { + // 1101111101000000EE110010ssssiiii | dealloc_return ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s dealloc_return ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf453200) { + // 1101111101000101EE110010ssssiiii | if (!p0) dealloc_return ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf473200) { + // 1101111101000111EE110010ssssiiii | if (!p0.new) dealloc_return:nt ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf443200) { + // 1101111101000100EE110010ssssiiii | if (p0) dealloc_return ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (P0) dealloc_return ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf463200) { + // 1101111101000110EE110010ssssiiii | if (p0.new) dealloc_return:nt ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf003300) { + // 1101111100000000EE110011ssssiiii | deallocframe ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s deallocframe ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xd0003300) { + // 11010IIISSSSddddEE110011ssssiiii | Rd = memb(RS+#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xde003300) { + // 11011110IIIIIdddEE110011ssssiiii | Rdd = memd(r29+#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xc0003300) { + // 11000IIISSSSddddEE110011ssssiiii | Rd = memh(RS+#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xdc003300) { + // 1101110IIIIIddddEE110011ssssiiii | Rd = memw(r29+#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xc8003300) { + // 11001IIISSSSddddEE110011ssssiiii | Rd = memuh(RS+#II) ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf403300) { + // 1101111101000000EE110011ssssiiii | dealloc_return ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s dealloc_return ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf453300) { + // 1101111101000101EE110011ssssiiii | if (!p0) dealloc_return ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf473300) { + // 1101111101000111EE110011ssssiiii | if (!p0.new) dealloc_return:nt ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf443300) { + // 1101111101000100EE110011ssssiiii | if (p0) dealloc_return ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (P0) dealloc_return ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf463300) { + // 1101111101000110EE110011ssssiiii | if (p0.new) dealloc_return:nt ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf002a00) { + // 1101111100000000EE10101iiiiiittt | deallocframe ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s deallocframe ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0xd0002a00) { + // 11010IIIssssddddEE10101iiiiiittt | Rd = memb(Rs+#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0xde002a00) { + // 11011110IIIIIdddEE10101iiiiiittt | Rdd = memd(r29+#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0xc0002a00) { + // 11000IIIssssddddEE10101iiiiiittt | Rd = memh(Rs+#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00fe00) == 0xdc002a00) { + // 1101110IIIIIddddEE10101iiiiiittt | Rd = memw(r29+#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0xc8002a00) { + // 11001IIIssssddddEE10101iiiiiittt | Rd = memuh(Rs+#II) ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf402a00) { + // 1101111101000000EE10101iiiiiittt | dealloc_return ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s dealloc_return ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf452a00) { + // 1101111101000101EE10101iiiiiittt | if (!p0) dealloc_return ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf472a00) { + // 1101111101000111EE10101iiiiiittt | if (!p0.new) dealloc_return:nt ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf442a00) { + // 1101111101000100EE10101iiiiiittt | if (p0) dealloc_return ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s if (P0) dealloc_return ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf462a00) { + // 1101111101000110EE10101iiiiiittt | if (p0.new) dealloc_return:nt ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff800) == 0xdf002000) { + // 1101111100000000EE100iiisssstttt | deallocframe ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s deallocframe ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0xd0002000) { + // 11010IIISSSSddddEE100iiisssstttt | Rd = memb(RS+#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00f800) == 0xde002000) { + // 11011110IIIIIdddEE100iiisssstttt | Rdd = memd(r29+#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0xc0002000) { + // 11000IIISSSSddddEE100iiisssstttt | Rd = memh(RS+#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00f800) == 0xdc002000) { + // 1101110IIIIIddddEE100iiisssstttt | Rd = memw(r29+#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0xc8002000) { + // 11001IIISSSSddddEE100iiisssstttt | Rd = memuh(RS+#II) ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff800) == 0xdf402000) { + // 1101111101000000EE100iiisssstttt | dealloc_return ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s dealloc_return ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff800) == 0xdf452000) { + // 1101111101000101EE100iiisssstttt | if (!p0) dealloc_return ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff800) == 0xdf472000) { + // 1101111101000111EE100iiisssstttt | if (!p0.new) dealloc_return:nt ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff800) == 0xdf442000) { + // 1101111101000100EE100iiisssstttt | if (p0) dealloc_return ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0) dealloc_return ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffff800) == 0xdf462000) { + // 1101111101000110EE100iiisssstttt | if (p0.new) dealloc_return:nt ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf002800) { + // 1101111100000000EE10100iiiiitttt | deallocframe ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s deallocframe ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0xd0002800) { + // 11010IIIssssddddEE10100iiiiitttt | Rd = memb(Rs+#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe00) == 0xde002800) { + // 11011110IIIIIdddEE10100iiiiitttt | Rdd = memd(r29+#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0xc0002800) { + // 11000IIIssssddddEE10100iiiiitttt | Rd = memh(Rs+#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00fe00) == 0xdc002800) { + // 1101110IIIIIddddEE10100iiiiitttt | Rd = memw(r29+#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0xc8002800) { + // 11001IIIssssddddEE10100iiiiitttt | Rd = memuh(Rs+#II) ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf402800) { + // 1101111101000000EE10100iiiiitttt | dealloc_return ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s dealloc_return ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf452800) { + // 1101111101000101EE10100iiiiitttt | if (!p0) dealloc_return ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf472800) { + // 1101111101000111EE10100iiiiitttt | if (!p0.new) dealloc_return:nt ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf442800) { + // 1101111101000100EE10100iiiiitttt | if (p0) dealloc_return ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0) dealloc_return ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffffe00) == 0xdf462800) { + // 1101111101000110EE10100iiiiitttt | if (p0.new) dealloc_return:nt ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf003000) { + // 1101111100000000EE110000ssssiiii | deallocframe ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s deallocframe ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xd0003000) { + // 11010IIISSSSddddEE110000ssssiiii | Rd = memb(RS+#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xde003000) { + // 11011110IIIIIdddEE110000ssssiiii | Rdd = memd(r29+#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xc0003000) { + // 11000IIISSSSddddEE110000ssssiiii | Rd = memh(RS+#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xdc003000) { + // 1101110IIIIIddddEE110000ssssiiii | Rd = memw(r29+#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xc8003000) { + // 11001IIISSSSddddEE110000ssssiiii | Rd = memuh(RS+#II) ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf403000) { + // 1101111101000000EE110000ssssiiii | dealloc_return ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s dealloc_return ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf453000) { + // 1101111101000101EE110000ssssiiii | if (!p0) dealloc_return ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf473000) { + // 1101111101000111EE110000ssssiiii | if (!p0.new) dealloc_return:nt ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf443000) { + // 1101111101000100EE110000ssssiiii | if (p0) dealloc_return ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf463000) { + // 1101111101000110EE110000ssssiiii | if (p0.new) dealloc_return:nt ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf003100) { + // 1101111100000000EE110001ssssiiii | deallocframe ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s deallocframe ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xd0003100) { + // 11010IIISSSSddddEE110001ssssiiii | Rd = memb(RS+#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memb(%s+#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xde003100) { + // 11011110IIIIIdddEE110001ssssiiii | Rdd = memd(r29+#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = memd(R29+#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_double_low8_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xc0003100) { + // 11000IIISSSSddddEE110001ssssiiii | Rd = memh(RS+#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memh(%s+#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xdc003100) { + // 1101110IIIIIddddEE110001ssssiiii | Rd = memw(r29+#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s %s = memw(R29+#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xc8003100) { + // 11001IIISSSSddddEE110001ssssiiii | Rd = memuh(RS+#II) ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s %s = memuh(%s+#0x%x) ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf403100) { + // 1101111101000000EE110001ssssiiii | dealloc_return ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s dealloc_return ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf453100) { + // 1101111101000101EE110001ssssiiii | if (!p0) dealloc_return ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s if (!P0) dealloc_return ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf473100) { + // 1101111101000111EE110001ssssiiii | if (!p0.new) dealloc_return:nt ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s if (!P0.new) dealloc_return:nt ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf443100) { + // 1101111101000100EE110001ssssiiii | if (p0) dealloc_return ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s if (P0) dealloc_return ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffffff00) == 0xdf463100) { + // 1101111101000110EE110001ssssiiii | if (p0.new) dealloc_return:nt ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s if (P0.new) dealloc_return:nt ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xe: + if ((hi_u32 & 0xff00fe0f) == 0xf2001c00) { + // 11110010ssssIIIIEE01110iiiii0000 | memb(Rs+#II) = #0 ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s memb(%s+#0x%x) = #0 ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0xf3001c00) { + // 11110011ssssIIIIEE01110iiiii0000 | memb(Rs+#II) = #1 ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI1_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s memb(%s+#0x%x) = #1 ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00fe0f) == 0xea001c00) { + // 1110101IIIIIItttEE01110iiiii0000 | memd(r29+#II) = Rtt ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s memd(R29+%s) = %s ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe0f) == 0xe0001c00) { + // 11100IIIssssttttEE01110iiiii0000 | memh(Rs+#II) = Rt ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + sprintf(hi->mnem, "%s memh(%s+#0x%x) = %s ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00fe0f) == 0xe8001c00) { + // 1110100IIIIIttttEE01110iiiii0000 | memw(r29+#II) = Rt ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s memw(R29+#0x%x) = %s ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0xf0001c00) { + // 11110000ssssIIIIEE01110iiiii0000 | memw(Rs+#II) = #0 ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s memw(%s+#0x%x) = #0 ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00fe0f) == 0xf1001c00) { + // 11110001ssssIIIIEE01110iiiii0000 | memw(Rs+#II) = #1 ; allocframe(#Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + sprintf(hi->mnem, "%s memw(%s+#0x%x) = #1 ; allocframe(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf2001200) { + // 11110010SSSSIIIIEE010010ssssiiii | memb(RS+#II) = #0 ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memb(%s+#0x%x) = #0 ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xea001200) { + // 1110101IIIIIItttEE010010ssssiiii | memd(r29+#II) = Rtt ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memd(R29+%s) = %s ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xe0001200) { + // 11100IIISSSSttttEE010010ssssiiii | memh(RS+#II) = Rt ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memh(%s+#0x%x) = %s ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xe8001200) { + // 1110100IIIIIttttEE010010ssssiiii | memw(r29+#II) = Rt ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memw(R29+#0x%x) = %s ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf0001200) { + // 11110000SSSSIIIIEE010010ssssiiii | memw(RS+#II) = #0 ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memw(%s+#0x%x) = #0 ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf1001200) { + // 11110001SSSSIIIIEE010010ssssiiii | memw(RS+#II) = #1 ; memb(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREBI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memw(%s+#0x%x) = #1 ; memb(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf2001300) { + // 11110010SSSSIIIIEE010011ssssiiii | memb(RS+#II) = #0 ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memb(%s+#0x%x) = #0 ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf3001300) { + // 11110011SSSSIIIIEE010011ssssiiii | memb(RS+#II) = #1 ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI1_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memb(%s+#0x%x) = #1 ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xea001300) { + // 1110101IIIIIItttEE010011ssssiiii | memd(r29+#II) = Rtt ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memd(R29+%s) = %s ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xe0001300) { + // 11100IIISSSSttttEE010011ssssiiii | memh(RS+#II) = Rt ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memh(%s+#0x%x) = %s ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xe8001300) { + // 1110100IIIIIttttEE010011ssssiiii | memw(r29+#II) = Rt ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memw(R29+#0x%x) = %s ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf0001300) { + // 11110000SSSSIIIIEE010011ssssiiii | memw(RS+#II) = #0 ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memw(%s+#0x%x) = #0 ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf1001300) { + // 11110001SSSSIIIIEE010011ssssiiii | memw(RS+#II) = #1 ; memb(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREBI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + sprintf(hi->mnem, "%s memw(%s+#0x%x) = #1 ; memb(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00fe00) == 0xea000a00) { + // 1110101IIIIIITTTEE00101iiiiiittt | memd(r29+#II) = RTT ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // RTT8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s memd(R29+%s) = %s ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0xe0000a00) { + // 11100IIIssssTTTTEE00101iiiiiittt | memh(Rs+#II) = RT ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s memh(%s+#0x%x) = %s ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00fe00) == 0xe8000a00) { + // 1110100IIIIITTTTEE00101iiiiiittt | memw(r29+#II) = RT ; memd(r29+#Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STORED_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + sprintf(hi->mnem, "%s memw(R29+#0x%x) = %s ; memd(R29+%s) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800f800) == 0xe0000000) { + // 11100IIISSSSTTTTEE000iiisssstttt | memh(RS+#II) = RT ; memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memh(%s+#0x%x) = %s ; memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800fe00) == 0xe0000800) { + // 11100IIIssssTTTTEE00100iiiiitttt | memh(Rs+#II) = RT ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memh(%s+#0x%x) = %s ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00fe00) == 0xe8000800) { + // 1110100IIIIITTTTEE00100iiiiitttt | memw(r29+#II) = RT ; memw(r29+#Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREW_SP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + sprintf(hi->mnem, "%s memw(R29+#0x%x) = %s ; memw(R29+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xea001000) { + // 1110101IIIIIItttEE010000ssssiiii | memd(r29+#II) = Rtt ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s memd(R29+%s) = %s ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xe0001000) { + // 11100IIISSSSttttEE010000ssssiiii | memh(RS+#II) = Rt ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s memh(%s+#0x%x) = %s ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xe8001000) { + // 1110100IIIIIttttEE010000ssssiiii | memw(r29+#II) = Rt ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s memw(R29+#0x%x) = %s ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf0001000) { + // 11110000SSSSIIIIEE010000ssssiiii | memw(RS+#II) = #0 ; memw(Rs+#Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREWI0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s memw(%s+#0x%x) = #0 ; memw(%s+#0x%x) = #0 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xea001100) { + // 1110101IIIIIItttEE010001ssssiiii | memd(r29+#II) = Rtt ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + if (((st32)hi->ops[0].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[0].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s memd(R29+%s) = %s ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, signed_imm, hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf800ff00) == 0xe0001100) { + // 11100IIISSSSttttEE010001ssssiiii | memh(RS+#II) = Rt ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + sprintf(hi->mnem, "%s memh(%s+#0x%x) = %s ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe00ff00) == 0xe8001100) { + // 1110100IIIIIttttEE010001ssssiiii | memw(r29+#II) = Rt ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s memw(R29+#0x%x) = %s ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf0001100) { + // 11110000SSSSIIIIEE010001ssssiiii | memw(RS+#II) = #0 ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s memw(%s+#0x%x) = #0 ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff00ff00) == 0xf1001100) { + // 11110001SSSSIIIIEE010001ssssiiii | memw(RS+#II) = #1 ; memw(Rs+#Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREWI1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + sprintf(hi->mnem, "%s memw(%s+#0x%x) = #1 ; memw(%s+#0x%x) = #1 %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + break; + } + } else { + switch ((hi_u32 >> 28) & 0xF) { + case 0x0: + if ((hi_u32 & 0xf0000000) == 0x0) { + // 0000iiiiiiiiiiiiPPiiiiiiiiiiiiii | immext(#Ii) + hi->instruction = HEX_INS_A4_EXT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0xfff0000) >> 2) | (((hi_u32)&0x3fff) >> 0)) << 6; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 6; + sprintf(hi->mnem, "%s immext(##0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + hex_op_extend(&(hi->ops[0]), true); + break; + } + if ((hi_u32 & 0xffff3fff) == 0x0) { + // 0000000000000000PP00000000000000 | + hi->instruction = HEX_INS_INVALID_DECODE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x1: + if ((hi_u32 & 0xffc03001) == 0x14400000) { + // 0001010001iissssPP00ttttiiiiiii0 | p0 = cmp.eq(Rs,Rt); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_FP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,%s); if (!P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14402000) { + // 0001010001iissssPP10ttttiiiiiii0 | p0 = cmp.eq(Rs,Rt); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_FP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,%s); if (!P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14401000) { + // 0001010001iissssPP01ttttiiiiiii0 | p1 = cmp.eq(Rs,Rt); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_FP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,%s); if (!P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14403000) { + // 0001010001iissssPP11ttttiiiiiii0 | p1 = cmp.eq(Rs,Rt); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_FP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,%s); if (!P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14000000) { + // 0001010000iissssPP00ttttiiiiiii0 | p0 = cmp.eq(Rs,Rt); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_TP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,%s); if (P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14002000) { + // 0001010000iissssPP10ttttiiiiiii0 | p0 = cmp.eq(Rs,Rt); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_TP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,%s); if (P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14001000) { + // 0001010000iissssPP01ttttiiiiiii0 | p1 = cmp.eq(Rs,Rt); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_TP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,%s); if (P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14003000) { + // 0001010000iissssPP11ttttiiiiiii0 | p1 = cmp.eq(Rs,Rt); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_TP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,%s); if (P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x10400000) { + // 0001000001iissssPP0IIIIIiiiiiii0 | p0 = cmp.eq(Rs,#II); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_FP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x); if (!P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x10402000) { + // 0001000001iissssPP1IIIIIiiiiiii0 | p0 = cmp.eq(Rs,#II); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_FP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x); if (!P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x12400000) { + // 0001001001iissssPP0IIIIIiiiiiii0 | p1 = cmp.eq(Rs,#II); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_FP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,#0x%x); if (!P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x12402000) { + // 0001001001iissssPP1IIIIIiiiiiii0 | p1 = cmp.eq(Rs,#II); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_FP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,#0x%x); if (!P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x10000000) { + // 0001000000iissssPP0IIIIIiiiiiii0 | p0 = cmp.eq(Rs,#II); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_TP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x); if (P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x10002000) { + // 0001000000iissssPP1IIIIIiiiiiii0 | p0 = cmp.eq(Rs,#II); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_TP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#0x%x); if (P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x12000000) { + // 0001001000iissssPP0IIIIIiiiiiii0 | p1 = cmp.eq(Rs,#II); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_TP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,#0x%x); if (P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x12002000) { + // 0001001000iissssPP1IIIIIiiiiiii0 | p1 = cmp.eq(Rs,#II); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_TP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,#0x%x); if (P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11c00000) { + // 0001000111iissssPP000000iiiiiii0 | p0 = cmp.eq(Rs,#n1); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_FP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#-1); if (!P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11c02000) { + // 0001000111iissssPP100000iiiiiii0 | p0 = cmp.eq(Rs,#n1); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_FP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#-1); if (!P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13c00000) { + // 0001001111iissssPP000000iiiiiii0 | p1 = cmp.eq(Rs,#n1); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_FP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,#-1); if (!P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13c02000) { + // 0001001111iissssPP100000iiiiiii0 | p1 = cmp.eq(Rs,#n1); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_FP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,#-1); if (!P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11800000) { + // 0001000110iissssPP000000iiiiiii0 | p0 = cmp.eq(Rs,#n1); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_TP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#-1); if (P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11802000) { + // 0001000110iissssPP100000iiiiiii0 | p0 = cmp.eq(Rs,#n1); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_TP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.eq(%s,#-1); if (P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13800000) { + // 0001001110iissssPP000000iiiiiii0 | p1 = cmp.eq(Rs,#n1); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_TP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,#-1); if (P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13802000) { + // 0001001110iissssPP100000iiiiiii0 | p1 = cmp.eq(Rs,#n1); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_TP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.eq(%s,#-1); if (P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14c00000) { + // 0001010011iissssPP00ttttiiiiiii0 | p0 = cmp.gt(Rs,Rt); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_FP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,%s); if (!P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14c02000) { + // 0001010011iissssPP10ttttiiiiiii0 | p0 = cmp.gt(Rs,Rt); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_FP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,%s); if (!P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14c01000) { + // 0001010011iissssPP01ttttiiiiiii0 | p1 = cmp.gt(Rs,Rt); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_FP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,%s); if (!P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14c03000) { + // 0001010011iissssPP11ttttiiiiiii0 | p1 = cmp.gt(Rs,Rt); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_FP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,%s); if (!P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14800000) { + // 0001010010iissssPP00ttttiiiiiii0 | p0 = cmp.gt(Rs,Rt); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_TP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,%s); if (P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14802000) { + // 0001010010iissssPP10ttttiiiiiii0 | p0 = cmp.gt(Rs,Rt); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_TP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,%s); if (P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14801000) { + // 0001010010iissssPP01ttttiiiiiii0 | p1 = cmp.gt(Rs,Rt); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_TP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,%s); if (P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x14803000) { + // 0001010010iissssPP11ttttiiiiiii0 | p1 = cmp.gt(Rs,Rt); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_TP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,%s); if (P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x10c00000) { + // 0001000011iissssPP0IIIIIiiiiiii0 | p0 = cmp.gt(Rs,#II); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_FP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,#0x%x); if (!P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x10c02000) { + // 0001000011iissssPP1IIIIIiiiiiii0 | p0 = cmp.gt(Rs,#II); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_FP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,#0x%x); if (!P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x12c00000) { + // 0001001011iissssPP0IIIIIiiiiiii0 | p1 = cmp.gt(Rs,#II); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_FP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,#0x%x); if (!P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x12c02000) { + // 0001001011iissssPP1IIIIIiiiiiii0 | p1 = cmp.gt(Rs,#II); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_FP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,#0x%x); if (!P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x10800000) { + // 0001000010iissssPP0IIIIIiiiiiii0 | p0 = cmp.gt(Rs,#II); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_TP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,#0x%x); if (P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x10802000) { + // 0001000010iissssPP1IIIIIiiiiiii0 | p0 = cmp.gt(Rs,#II); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_TP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,#0x%x); if (P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x12800000) { + // 0001001010iissssPP0IIIIIiiiiiii0 | p1 = cmp.gt(Rs,#II); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_TP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,#0x%x); if (P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x12802000) { + // 0001001010iissssPP1IIIIIiiiiiii0 | p1 = cmp.gt(Rs,#II); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_TP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,#0x%x); if (P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11c00100) { + // 0001000111iissssPP000001iiiiiii0 | p0 = cmp.gt(Rs,#n1); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_FP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,#-1); if (!P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11c02100) { + // 0001000111iissssPP100001iiiiiii0 | p0 = cmp.gt(Rs,#n1); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_FP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,#-1); if (!P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13c00100) { + // 0001001111iissssPP000001iiiiiii0 | p1 = cmp.gt(Rs,#n1); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_FP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,#-1); if (!P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13c02100) { + // 0001001111iissssPP100001iiiiiii0 | p1 = cmp.gt(Rs,#n1); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_FP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,#-1); if (!P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11800100) { + // 0001000110iissssPP000001iiiiiii0 | p0 = cmp.gt(Rs,#n1); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_TP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,#-1); if (P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11802100) { + // 0001000110iissssPP100001iiiiiii0 | p0 = cmp.gt(Rs,#n1); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_TP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gt(%s,#-1); if (P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13800100) { + // 0001001110iissssPP000001iiiiiii0 | p1 = cmp.gt(Rs,#n1); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_TP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,#-1); if (P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13802100) { + // 0001001110iissssPP100001iiiiiii0 | p1 = cmp.gt(Rs,#n1); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_TP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gt(%s,#-1); if (P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x15400000) { + // 0001010101iissssPP00ttttiiiiiii0 | p0 = cmp.gtu(Rs,Rt); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_FP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gtu(%s,%s); if (!P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x15402000) { + // 0001010101iissssPP10ttttiiiiiii0 | p0 = cmp.gtu(Rs,Rt); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_FP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gtu(%s,%s); if (!P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x15401000) { + // 0001010101iissssPP01ttttiiiiiii0 | p1 = cmp.gtu(Rs,Rt); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_FP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gtu(%s,%s); if (!P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x15403000) { + // 0001010101iissssPP11ttttiiiiiii0 | p1 = cmp.gtu(Rs,Rt); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_FP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gtu(%s,%s); if (!P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x15000000) { + // 0001010100iissssPP00ttttiiiiiii0 | p0 = cmp.gtu(Rs,Rt); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_TP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gtu(%s,%s); if (P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x15002000) { + // 0001010100iissssPP10ttttiiiiiii0 | p0 = cmp.gtu(Rs,Rt); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_TP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gtu(%s,%s); if (P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x15001000) { + // 0001010100iissssPP01ttttiiiiiii0 | p1 = cmp.gtu(Rs,Rt); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_TP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gtu(%s,%s); if (P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x15003000) { + // 0001010100iissssPP11ttttiiiiiii0 | p1 = cmp.gtu(Rs,Rt); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_TP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gtu(%s,%s); if (P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x11400000) { + // 0001000101iissssPP0IIIIIiiiiiii0 | p0 = cmp.gtu(Rs,#II); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_FP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gtu(%s,#0x%x); if (!P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x11402000) { + // 0001000101iissssPP1IIIIIiiiiiii0 | p0 = cmp.gtu(Rs,#II); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_FP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gtu(%s,#0x%x); if (!P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x13400000) { + // 0001001101iissssPP0IIIIIiiiiiii0 | p1 = cmp.gtu(Rs,#II); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_FP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gtu(%s,#0x%x); if (!P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x13402000) { + // 0001001101iissssPP1IIIIIiiiiiii0 | p1 = cmp.gtu(Rs,#II); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_FP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gtu(%s,#0x%x); if (!P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x11000000) { + // 0001000100iissssPP0IIIIIiiiiiii0 | p0 = cmp.gtu(Rs,#II); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_TP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gtu(%s,#0x%x); if (P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x11002000) { + // 0001000100iissssPP1IIIIIiiiiiii0 | p0 = cmp.gtu(Rs,#II); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_TP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = cmp.gtu(%s,#0x%x); if (P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x13000000) { + // 0001001100iissssPP0IIIIIiiiiiii0 | p1 = cmp.gtu(Rs,#II); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_TP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gtu(%s,#0x%x); if (P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc02001) == 0x13002000) { + // 0001001100iissssPP1IIIIIiiiiiii0 | p1 = cmp.gtu(Rs,#II); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_TP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = cmp.gtu(%s,#0x%x); if (P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00001) == 0x16000000) { + // 0001011000iiddddPPIIIIIIiiiiiii0 | Rd = #II ; jump Ii + hi->instruction = HEX_INS_J4_JUMPSETI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = #0x%x ; jump 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03001) == 0x17000000) { + // 0001011100iissssPP00ddddiiiiiii0 | Rd = Rs ; jump Ii + hi->instruction = HEX_INS_J4_JUMPSETR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00) >> 8); // Rd16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = %s ; jump 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11c00300) { + // 0001000111iissssPP000011iiiiiii0 | p0 = tstbit(Rs,#0); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_FP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = tstbit(%s,#0); if (!P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11c02300) { + // 0001000111iissssPP100011iiiiiii0 | p0 = tstbit(Rs,#0); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_FP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = tstbit(%s,#0); if (!P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13c00300) { + // 0001001111iissssPP000011iiiiiii0 | p1 = tstbit(Rs,#0); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_FP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = tstbit(%s,#0); if (!P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13c02300) { + // 0001001111iissssPP100011iiiiiii0 | p1 = tstbit(Rs,#0); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_FP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = tstbit(%s,#0); if (!P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11800300) { + // 0001000110iissssPP000011iiiiiii0 | p0 = tstbit(Rs,#0); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_TP0_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = tstbit(%s,#0); if (P0.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x11802300) { + // 0001000110iissssPP100011iiiiiii0 | p0 = tstbit(Rs,#0); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_TP0_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s P0 = tstbit(%s,#0); if (P0.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13800300) { + // 0001001110iissssPP000011iiiiiii0 | p1 = tstbit(Rs,#0); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_TP1_JUMP_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = tstbit(%s,#0); if (P1.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc03f01) == 0x13802300) { + // 0001001110iissssPP100011iiiiiii0 | p1 = tstbit(Rs,#0); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_TP1_JUMP_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s P1 = tstbit(%s,#0); if (P1.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_general_sub_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x19c00040) { + // 00011001110tttttPP000000010ddddd | Vd.b = vsplat(Rt) + hi->instruction = HEX_INS_V6_LVSPLATB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.b = vsplat(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x19c00020) { + // 00011001110tttttPP000000001ddddd | Vd.h = vsplat(Rt) + hi->instruction = HEX_INS_V6_LVSPLATH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vsplat(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x19a00020) { + // 00011001101tttttPP000000001ddddd | Vd = vsplat(Rt) + hi->instruction = HEX_INS_V6_LVSPLATW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s = vsplat(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030000) { + // 00011110tt000011PP0000ss000000dd | Qd = and(Qs,Qt) + hi->instruction = HEX_INS_V6_PRED_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + sprintf(hi->mnem, "%s %s = and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030014) { + // 00011110tt000011PP0000ss000101dd | Qd = and(Qs,!Qt) + hi->instruction = HEX_INS_V6_PRED_AND_N; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + sprintf(hi->mnem, "%s %s = and(%s,!%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3cfc) == 0x1e030008) { + // 0001111000000011PP0000ss000010dd | Qd = not(Qs) + hi->instruction = HEX_INS_V6_PRED_NOT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + sprintf(hi->mnem, "%s %s = not(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030004) { + // 00011110tt000011PP0000ss000001dd | Qd = or(Qs,Qt) + hi->instruction = HEX_INS_V6_PRED_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + sprintf(hi->mnem, "%s %s = or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030010) { + // 00011110tt000011PP0000ss000100dd | Qd = or(Qs,!Qt) + hi->instruction = HEX_INS_V6_PRED_OR_N; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + sprintf(hi->mnem, "%s %s = or(%s,!%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ffc) == 0x19a00044) { + // 00011001101tttttPP000000010001dd | Qd = vsetq(Rt) + hi->instruction = HEX_INS_V6_PRED_SCALAR2; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s = vsetq(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ffc) == 0x19a0004c) { + // 00011001101tttttPP000000010011dd | Qd = vsetq2(Rt) + hi->instruction = HEX_INS_V6_PRED_SCALAR2V2; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s = vsetq2(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e03000c) { + // 00011110tt000011PP0000ss000011dd | Qd = xor(Qs,Qt) + hi->instruction = HEX_INS_V6_PRED_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + sprintf(hi->mnem, "%s %s = xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030018) { + // 00011110tt000011PP0000ss000110dd | Qd.b = vshuffe(Qs.h,Qt.h) + hi->instruction = HEX_INS_V6_SHUFFEQH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + sprintf(hi->mnem, "%s %s.b = vshuffe(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e03001c) { + // 00011110tt000011PP0000ss000111dd | Qd.h = vshuffe(Qs.w,Qt.w) + hi->instruction = HEX_INS_V6_SHUFFEQW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + sprintf(hi->mnem, "%s %s.h = vshuffe(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1f402080) { + // 00011111010vvvvvPP1uuuuu1iiddddd | Vdd.w = v6mpy(Vuu.ub,Vvv.b,#Ii):h + hi->instruction = HEX_INS_V6_V6MPYHUBS10; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s.w = V6mpy(%s.ub,%s.b,#0x%x):h %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1f202080) { + // 00011111001vvvvvPP1uuuuu1iixxxxx | Vxx.w += v6mpy(Vuu.ub,Vvv.b,#Ii):h + hi->instruction = HEX_INS_V6_V6MPYHUBS10_VXX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s.w += V6mpy(%s.ub,%s.b,#0x%x):h %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1f402000) { + // 00011111010vvvvvPP1uuuuu0iiddddd | Vdd.w = v6mpy(Vuu.ub,Vvv.b,#Ii):v + hi->instruction = HEX_INS_V6_V6MPYVUBS10; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s.w = V6mpy(%s.ub,%s.b,#0x%x):v %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1f202000) { + // 00011111001vvvvvPP1uuuuu0iixxxxx | Vxx.w += v6mpy(Vuu.ub,Vvv.b,#Ii):v + hi->instruction = HEX_INS_V6_V6MPYVUBS10_VXX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + sprintf(hi->mnem, "%s %s.w += V6mpy(%s.ub,%s.b,#0x%x):v %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010080) { + // 0001111000000001PP0uuuuu100ddddd | Vd.b = vabs(Vu.b) + hi->instruction = HEX_INS_V6_VABSB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.b = vabs(%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0100a0) { + // 0001111000000001PP0uuuuu101ddddd | Vd.b = vabs(Vu.b):sat + hi->instruction = HEX_INS_V6_VABSB_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.b = vabs(%s.b):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00020) { + // 00011100110vvvvvPP0uuuuu001ddddd | Vd.uh = vabsdiff(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VABSDIFFH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vabsdiff(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00000) { + // 00011100110vvvvvPP0uuuuu000ddddd | Vd.ub = vabsdiff(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VABSDIFFUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vabsdiff(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00040) { + // 00011100110vvvvvPP0uuuuu010ddddd | Vd.uh = vabsdiff(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VABSDIFFUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vabsdiff(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00060) { + // 00011100110vvvvvPP0uuuuu011ddddd | Vd.uw = vabsdiff(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VABSDIFFW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw = vabsdiff(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000000) { + // 0001111000000000PP0uuuuu000ddddd | Vd.h = vabs(Vu.h) + hi->instruction = HEX_INS_V6_VABSH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.h = vabs(%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000020) { + // 0001111000000000PP0uuuuu001ddddd | Vd.h = vabs(Vu.h):sat + hi->instruction = HEX_INS_V6_VABSH_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.h = vabs(%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000040) { + // 0001111000000000PP0uuuuu010ddddd | Vd.w = vabs(Vu.w) + hi->instruction = HEX_INS_V6_VABSW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vabs(%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000060) { + // 0001111000000000PP0uuuuu011ddddd | Vd.w = vabs(Vu.w):sat + hi->instruction = HEX_INS_V6_VABSW_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vabs(%s.w):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa000c0) { + // 00011111101vvvvvPP0uuuuu110ddddd | Vd.b = vadd(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VADDB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vadd(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600080) { + // 00011100011vvvvvPP0uuuuu100ddddd | Vdd.b = vadd(Vuu.b,Vvv.b) + hi->instruction = HEX_INS_V6_VADDB_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.b = vadd(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012060) { + // 00011110vv000001PP1uuuuu011xxxxx | if (!Qv) Vx.b += Vu.b + hi->instruction = HEX_INS_V6_VADDBNQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (!%s) %s.b += %s.b %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012000) { + // 00011110vv000001PP1uuuuu000xxxxx | if (Qv) Vx.b += Vu.b + hi->instruction = HEX_INS_V6_VADDBQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (%s) %s.b += %s.b %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000000) { + // 00011111000vvvvvPP0uuuuu000ddddd | Vd.b = vadd(Vu.b,Vv.b):sat + hi->instruction = HEX_INS_V6_VADDBSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vadd(%s.b,%s.b):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00000) { + // 00011110101vvvvvPP0uuuuu000ddddd | Vdd.b = vadd(Vuu.b,Vvv.b):sat + hi->instruction = HEX_INS_V6_VADDBSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.b = vadd(%s.b,%s.b):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1ca02000) { + // 00011100101vvvvvPP1uuuuu0xxddddd | Vd.w = vadd(Vu.w,Vv.w,Qx):carry + hi->instruction = HEX_INS_V6_VADDCARRY; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vadd(%s.w,%s.w,%s):carry %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[3].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1da02000) { + // 00011101101vvvvvPP1uuuuu0eeddddd | Vd.w,Qe = vadd(Vu.w,Vv.w):carry + hi->instruction = HEX_INS_V6_VADDCARRYO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Qe4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w,%s = vadd(%s.w,%s.w):carry %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1d802000) { + // 00011101100vvvvvPP1uuuuu0ssddddd | Vd.w = vadd(Vu.w,Vv.w,Qs):carry:sat + hi->instruction = HEX_INS_V6_VADDCARRYSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + sprintf(hi->mnem, "%s %s.w = vadd(%s.w,%s.w,%s):carry:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_qr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002000) { + // 00011111000vvvvvPP1uuuuu000ddddd | Vd.h = vadd(vclb(Vu.h),Vv.h) + hi->instruction = HEX_INS_V6_VADDCLBH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vadd(vclb(%s.h),%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002020) { + // 00011111000vvvvvPP1uuuuu001ddddd | Vd.w = vadd(vclb(Vu.w),Vv.w) + hi->instruction = HEX_INS_V6_VADDCLBW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vadd(vclb(%s.w),%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa000e0) { + // 00011111101vvvvvPP0uuuuu111ddddd | Vd.h = vadd(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VADDH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vadd(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c6000a0) { + // 00011100011vvvvvPP0uuuuu101ddddd | Vdd.h = vadd(Vuu.h,Vvv.h) + hi->instruction = HEX_INS_V6_VADDH_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.h = vadd(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012080) { + // 00011110vv000001PP1uuuuu100xxxxx | if (!Qv) Vx.h += Vu.h + hi->instruction = HEX_INS_V6_VADDHNQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (!%s) %s.h += %s.h %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012020) { + // 00011110vv000001PP1uuuuu001xxxxx | if (Qv) Vx.h += Vu.h + hi->instruction = HEX_INS_V6_VADDHQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (%s) %s.h += %s.h %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400060) { + // 00011100010vvvvvPP0uuuuu011ddddd | Vd.h = vadd(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VADDHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vadd(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800020) { + // 00011100100vvvvvPP0uuuuu001ddddd | Vdd.h = vadd(Vuu.h,Vvv.h):sat + hi->instruction = HEX_INS_V6_VADDHSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.h = vadd(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00080) { + // 00011100101vvvvvPP0uuuuu100ddddd | Vdd.w = vadd(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VADDHW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vadd(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202040) { + // 00011100001vvvvvPP1uuuuu010xxxxx | Vxx.w += vadd(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VADDHW_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vadd(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00040) { + // 00011100101vvvvvPP0uuuuu010ddddd | Vdd.h = vadd(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VADDUBH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vadd(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c4020a0) { + // 00011100010vvvvvPP1uuuuu101xxxxx | Vxx.h += vadd(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VADDUBH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h += vadd(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400020) { + // 00011100010vvvvvPP0uuuuu001ddddd | Vd.ub = vadd(Vu.ub,Vv.ub):sat + hi->instruction = HEX_INS_V6_VADDUBSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vadd(%s.ub,%s.ub):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c6000e0) { + // 00011100011vvvvvPP0uuuuu111ddddd | Vdd.ub = vadd(Vuu.ub,Vvv.ub):sat + hi->instruction = HEX_INS_V6_VADDUBSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.ub = vadd(%s.ub,%s.ub):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00080) { + // 00011110101vvvvvPP0uuuuu100ddddd | Vd.ub = vadd(Vu.ub,Vv.b):sat + hi->instruction = HEX_INS_V6_VADDUBUBB_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vadd(%s.ub,%s.b):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400040) { + // 00011100010vvvvvPP0uuuuu010ddddd | Vd.uh = vadd(Vu.uh,Vv.uh):sat + hi->instruction = HEX_INS_V6_VADDUHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vadd(%s.uh,%s.uh):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800000) { + // 00011100100vvvvvPP0uuuuu000ddddd | Vdd.uh = vadd(Vuu.uh,Vvv.uh):sat + hi->instruction = HEX_INS_V6_VADDUHSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.uh = vadd(%s.uh,%s.uh):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00060) { + // 00011100101vvvvvPP0uuuuu011ddddd | Vdd.w = vadd(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VADDUHW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vadd(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c402080) { + // 00011100010vvvvvPP1uuuuu100xxxxx | Vxx.w += vadd(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VADDUHW_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vadd(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600020) { + // 00011111011vvvvvPP0uuuuu001ddddd | Vd.uw = vadd(Vu.uw,Vv.uw):sat + hi->instruction = HEX_INS_V6_VADDUWSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw = vadd(%s.uw,%s.uw):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00040) { + // 00011110101vvvvvPP0uuuuu010ddddd | Vdd.uw = vadd(Vuu.uw,Vvv.uw):sat + hi->instruction = HEX_INS_V6_VADDUWSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.uw = vadd(%s.uw,%s.uw):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400000) { + // 00011100010vvvvvPP0uuuuu000ddddd | Vd.w = vadd(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VADDW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vadd(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c6000c0) { + // 00011100011vvvvvPP0uuuuu110ddddd | Vdd.w = vadd(Vuu.w,Vvv.w) + hi->instruction = HEX_INS_V6_VADDW_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.w = vadd(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e0120a0) { + // 00011110vv000001PP1uuuuu101xxxxx | if (!Qv) Vx.w += Vu.w + hi->instruction = HEX_INS_V6_VADDWNQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (!%s) %s.w += %s.w %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012040) { + // 00011110vv000001PP1uuuuu010xxxxx | if (Qv) Vx.w += Vu.w + hi->instruction = HEX_INS_V6_VADDWQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (%s) %s.w += %s.w %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400080) { + // 00011100010vvvvvPP0uuuuu100ddddd | Vd.w = vadd(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VADDWSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vadd(%s.w,%s.w):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800040) { + // 00011100100vvvvvPP0uuuuu010ddddd | Vdd.w = vadd(Vuu.w,Vvv.w):sat + hi->instruction = HEX_INS_V6_VADDWSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.w = vadd(%s.w,%s.w):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000000) { + // 00011011vvvvvtttPP0uuuuu000ddddd | Vd = valign(Vu,Vv,Rt) + hi->instruction = HEX_INS_V6_VALIGNB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s = valign(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x1e202000) { + // 00011110001vvvvvPP1uuuuuiiiddddd | Vd = valign(Vu,Vv,#Ii) + hi->instruction = HEX_INS_V6_VALIGNBI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = valign(%s,%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2000a0) { + // 00011100001vvvvvPP0uuuuu101ddddd | Vd = vand(Vu,Vv) + hi->instruction = HEX_INS_V6_VAND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vand(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x19a004a0) { + // 00011001101tttttPP0001uu101ddddd | Vd = vand(!Qu,Rt) + hi->instruction = HEX_INS_V6_VANDNQRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s = vand(!%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x19602460) { + // 00011001011tttttPP1001uu011xxxxx | Vx |= vand(!Qu,Rt) + hi->instruction = HEX_INS_V6_VANDNQRT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s |= vand(!%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x19a000a0) { + // 00011001101tttttPP0000uu101ddddd | Vd = vand(Qu,Rt) + hi->instruction = HEX_INS_V6_VANDQRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s = vand(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x19602060) { + // 00011001011tttttPP1000uu011xxxxx | Vx |= vand(Qu,Rt) + hi->instruction = HEX_INS_V6_VANDQRT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s |= vand(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e032020) { + // 00011110vv000011PP1uuuuu001ddddd | Vd = vand(!Qv,Vu) + hi->instruction = HEX_INS_V6_VANDVNQV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s = vand(!%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e032000) { + // 00011110vv000011PP1uuuuu000ddddd | Vd = vand(Qv,Vu) + hi->instruction = HEX_INS_V6_VANDVQV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s = vand(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x19a00048) { + // 00011001101tttttPP0uuuuu010010dd | Qd = vand(Vu,Rt) + hi->instruction = HEX_INS_V6_VANDVRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s = vand(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x19602080) { + // 00011001011tttttPP1uuuuu100000xx | Qx |= vand(Vu,Rt) + hi->instruction = HEX_INS_V6_VANDVRT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s |= vand(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19800000) { + // 00011001100tttttPP0uuuuu000ddddd | Vd.h = vasl(Vu.h,Rt) + hi->instruction = HEX_INS_V6_VASLH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vasl(%s.h,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19a020a0) { + // 00011001101tttttPP1uuuuu101xxxxx | Vx.h += vasl(Vu.h,Rt) + hi->instruction = HEX_INS_V6_VASLH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += vasl(%s.h,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa000a0) { + // 00011111101vvvvvPP0uuuuu101ddddd | Vd.h = vasl(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VASLHV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vasl(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x196000e0) { + // 00011001011tttttPP0uuuuu111ddddd | Vd.w = vasl(Vu.w,Rt) + hi->instruction = HEX_INS_V6_VASLW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vasl(%s.w,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19602040) { + // 00011001011tttttPP1uuuuu010xxxxx | Vx.w += vasl(Vu.w,Rt) + hi->instruction = HEX_INS_V6_VASLW_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vasl(%s.w,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00080) { + // 00011111101vvvvvPP0uuuuu100ddddd | Vd.w = vasl(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VASLWV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vasl(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1aa020e0) { + // 00011010101vvvvvPP1uuuuu111xxxxx | Vxx.w = vasrinto(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VASR_INTO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vasrinto(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x196000c0) { + // 00011001011tttttPP0uuuuu110ddddd | Vd.h = vasr(Vu.h,Rt) + hi->instruction = HEX_INS_V6_VASRH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vasr(%s.h,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x198020e0) { + // 00011001100tttttPP1uuuuu111xxxxx | Vx.h += vasr(Vu.h,Rt) + hi->instruction = HEX_INS_V6_VASRH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += vasr(%s.h,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b002000) { + // 00011011vvvvvtttPP1uuuuu000ddddd | Vd.b = vasr(Vu.h,Vv.h,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRHBRNDSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.b = vasr(%s.h,%s.h,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x18000000) { + // 00011000vvvvvtttPP0uuuuu000ddddd | Vd.b = vasr(Vu.h,Vv.h,Rt):sat + hi->instruction = HEX_INS_V6_VASRHBSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.b = vasr(%s.h,%s.h,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0000e0) { + // 00011011vvvvvtttPP0uuuuu111ddddd | Vd.ub = vasr(Vu.h,Vv.h,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRHUBRNDSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.ub = vasr(%s.h,%s.h,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0000c0) { + // 00011011vvvvvtttPP0uuuuu110ddddd | Vd.ub = vasr(Vu.h,Vv.h,Rt):sat + hi->instruction = HEX_INS_V6_VASRHUBSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.ub = vasr(%s.h,%s.h,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00060) { + // 00011111101vvvvvPP0uuuuu011ddddd | Vd.h = vasr(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VASRHV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vasr(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x180000e0) { + // 00011000vvvvvtttPP0uuuuu111ddddd | Vd.ub = vasr(Vu.uh,Vv.uh,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRUHUBRNDSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.ub = vasr(%s.uh,%s.uh,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x180020a0) { + // 00011000vvvvvtttPP1uuuuu101ddddd | Vd.ub = vasr(Vu.uh,Vv.uh,Rt):sat + hi->instruction = HEX_INS_V6_VASRUHUBSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.ub = vasr(%s.uh,%s.uh,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x18000020) { + // 00011000vvvvvtttPP0uuuuu001ddddd | Vd.uh = vasr(Vu.uw,Vv.uw,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRUWUHRNDSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.uh = vasr(%s.uw,%s.uw,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x18002080) { + // 00011000vvvvvtttPP1uuuuu100ddddd | Vd.uh = vasr(Vu.uw,Vv.uw,Rt):sat + hi->instruction = HEX_INS_V6_VASRUWUHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.uh = vasr(%s.uw,%s.uw,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x196000a0) { + // 00011001011tttttPP0uuuuu101ddddd | Vd.w = vasr(Vu.w,Rt) + hi->instruction = HEX_INS_V6_VASRW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vasr(%s.w,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x196020a0) { + // 00011001011tttttPP1uuuuu101xxxxx | Vx.w += vasr(Vu.w,Rt) + hi->instruction = HEX_INS_V6_VASRW_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vasr(%s.w,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000040) { + // 00011011vvvvvtttPP0uuuuu010ddddd | Vd.h = vasr(Vu.w,Vv.w,Rt) + hi->instruction = HEX_INS_V6_VASRWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.h = vasr(%s.w,%s.w,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000080) { + // 00011011vvvvvtttPP0uuuuu100ddddd | Vd.h = vasr(Vu.w,Vv.w,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRWHRNDSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.h = vasr(%s.w,%s.w,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000060) { + // 00011011vvvvvtttPP0uuuuu011ddddd | Vd.h = vasr(Vu.w,Vv.w,Rt):sat + hi->instruction = HEX_INS_V6_VASRWHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.h = vasr(%s.w,%s.w,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x18000040) { + // 00011000vvvvvtttPP0uuuuu010ddddd | Vd.uh = vasr(Vu.w,Vv.w,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRWUHRNDSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.uh = vasr(%s.w,%s.w,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0000a0) { + // 00011011vvvvvtttPP0uuuuu101ddddd | Vd.uh = vasr(Vu.w,Vv.w,Rt):sat + hi->instruction = HEX_INS_V6_VASRWUHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.uh = vasr(%s.w,%s.w,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00000) { + // 00011111101vvvvvPP0uuuuu000ddddd | Vd.w = vasr(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VASRWV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vasr(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0320e0) { + // 0001111000000011PP1uuuuu111ddddd | Vd = Vu + hi->instruction = HEX_INS_V6_VASSIGN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002080) { + // 00011111000vvvvvPP1uuuuu100ddddd | Vd.b = vavg(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VAVGB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vavg(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0020a0) { + // 00011111000vvvvvPP1uuuuu101ddddd | Vd.b = vavg(Vu.b,Vv.b):rnd + hi->instruction = HEX_INS_V6_VAVGBRND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vavg(%s.b,%s.b):rnd %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc000c0) { + // 00011100110vvvvvPP0uuuuu110ddddd | Vd.h = vavg(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VAVGH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vavg(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce000a0) { + // 00011100111vvvvvPP0uuuuu101ddddd | Vd.h = vavg(Vu.h,Vv.h):rnd + hi->instruction = HEX_INS_V6_VAVGHRND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vavg(%s.h,%s.h):rnd %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00080) { + // 00011100110vvvvvPP0uuuuu100ddddd | Vd.ub = vavg(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VAVGUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vavg(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00060) { + // 00011100111vvvvvPP0uuuuu011ddddd | Vd.ub = vavg(Vu.ub,Vv.ub):rnd + hi->instruction = HEX_INS_V6_VAVGUBRND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vavg(%s.ub,%s.ub):rnd %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc000a0) { + // 00011100110vvvvvPP0uuuuu101ddddd | Vd.uh = vavg(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VAVGUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vavg(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00080) { + // 00011100111vvvvvPP0uuuuu100ddddd | Vd.uh = vavg(Vu.uh,Vv.uh):rnd + hi->instruction = HEX_INS_V6_VAVGUHRND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vavg(%s.uh,%s.uh):rnd %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002040) { + // 00011111000vvvvvPP1uuuuu010ddddd | Vd.uw = vavg(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VAVGUW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw = vavg(%s.uw,%s.uw) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002060) { + // 00011111000vvvvvPP1uuuuu011ddddd | Vd.uw = vavg(Vu.uw,Vv.uw):rnd + hi->instruction = HEX_INS_V6_VAVGUWRND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw = vavg(%s.uw,%s.uw):rnd %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc000e0) { + // 00011100110vvvvvPP0uuuuu111ddddd | Vd.w = vavg(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VAVGW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vavg(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce000c0) { + // 00011100111vvvvvPP0uuuuu110ddddd | Vd.w = vavg(Vu.w,Vv.w):rnd + hi->instruction = HEX_INS_V6_VAVGWRND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vavg(%s.w,%s.w):rnd %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1a600000) { + // 00011010011vvvvvPP0uuuuu0ssddddd | if (Ps) Vdd = vcombine(Vu,Vv) + hi->instruction = HEX_INS_V6_VCCOMBINE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s if (%s) %s = vcombine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0200e0) { + // 0001111000000010PP0uuuuu111ddddd | Vd.uh = vcl0(Vu.uh) + hi->instruction = HEX_INS_V6_VCL0H; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.uh = vcl0(%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0200a0) { + // 0001111000000010PP0uuuuu101ddddd | Vd.uw = vcl0(Vu.uw) + hi->instruction = HEX_INS_V6_VCL0W; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.uw = vcl0(%s.uw) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff2080) == 0x1a000000) { + // 0001101000000000PP0uuuuu0ssddddd | if (Ps) Vd = Vu + hi->instruction = HEX_INS_V6_VCMOV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (%s) %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f4000e0) { + // 00011111010vvvvvPP0uuuuu111ddddd | Vdd = vcombine(Vu,Vv) + hi->instruction = HEX_INS_V6_VCOMBINE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcombine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19e02040) { + // 00011001111tttttPP1yyyyy010xxxxx | vdeal(Vy,Vx,Rt) + hi->instruction = HEX_INS_V6_VDEAL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Vy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s vdeal(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0000e0) { + // 0001111000000000PP0uuuuu111ddddd | Vd.b = vdeal(Vu.b) + hi->instruction = HEX_INS_V6_VDEALB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.b = vdeal(%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f2000e0) { + // 00011111001vvvvvPP0uuuuu111ddddd | Vd.b = vdeale(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VDEALB4W; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vdeale(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0000c0) { + // 0001111000000000PP0uuuuu110ddddd | Vd.h = vdeal(Vu.h) + hi->instruction = HEX_INS_V6_VDEALH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.h = vdeal(%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b002080) { + // 00011011vvvvvtttPP1uuuuu100ddddd | Vdd = vdeal(Vu,Vv,Rt) + hi->instruction = HEX_INS_V6_VDEALVDD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s = vdeal(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200020) { + // 00011111001vvvvvPP0uuuuu001ddddd | Vd = vdelta(Vu,Vv) + hi->instruction = HEX_INS_V6_VDELTA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vdelta(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x190000c0) { + // 00011001000tttttPP0uuuuu110ddddd | Vd.h = vdmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYBUS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vdmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x190020c0) { + // 00011001000tttttPP1uuuuu110xxxxx | Vx.h += vdmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYBUS_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += vdmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x190000e0) { + // 00011001000tttttPP0uuuuu111ddddd | Vdd.h = vdmpy(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYBUS_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vdmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x190020e0) { + // 00011001000tttttPP1uuuuu111xxxxx | Vxx.h += vdmpy(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYBUS_DV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += vdmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19000040) { + // 00011001000tttttPP0uuuuu010ddddd | Vd.w = vdmpy(Vu.h,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vdmpy(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19002060) { + // 00011001000tttttPP1uuuuu011xxxxx | Vx.w += vdmpy(Vu.h,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYHB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vdmpy(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19200080) { + // 00011001001tttttPP0uuuuu100ddddd | Vdd.w = vdmpy(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYHB_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vdmpy(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19202080) { + // 00011001001tttttPP1uuuuu100xxxxx | Vxx.w += vdmpy(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYHB_DV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vdmpy(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19200060) { + // 00011001001tttttPP0uuuuu011ddddd | Vd.w = vdmpy(Vuu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VDMPYHISAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vdmpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19202040) { + // 00011001001tttttPP1uuuuu010xxxxx | Vx.w += vdmpy(Vuu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VDMPYHISAT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vdmpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19200040) { + // 00011001001tttttPP0uuuuu010ddddd | Vd.w = vdmpy(Vu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VDMPYHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vdmpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19202060) { + // 00011001001tttttPP1uuuuu011xxxxx | Vx.w += vdmpy(Vu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VDMPYHSAT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vdmpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19200020) { + // 00011001001tttttPP0uuuuu001ddddd | Vd.w = vdmpy(Vuu.h,Rt.uh,#1):sat + hi->instruction = HEX_INS_V6_VDMPYHSUISAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vdmpy(%s.h,%s.uh,#1):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19202020) { + // 00011001001tttttPP1uuuuu001xxxxx | Vx.w += vdmpy(Vuu.h,Rt.uh,#1):sat + hi->instruction = HEX_INS_V6_VDMPYHSUISAT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vdmpy(%s.h,%s.uh,#1):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19200000) { + // 00011001001tttttPP0uuuuu000ddddd | Vd.w = vdmpy(Vu.h,Rt.uh):sat + hi->instruction = HEX_INS_V6_VDMPYHSUSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vdmpy(%s.h,%s.uh):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19202000) { + // 00011001001tttttPP1uuuuu000xxxxx | Vx.w += vdmpy(Vu.h,Rt.uh):sat + hi->instruction = HEX_INS_V6_VDMPYHSUSAT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vdmpy(%s.h,%s.uh):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000060) { + // 00011100000vvvvvPP0uuuuu011ddddd | Vd.w = vdmpy(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VDMPYHVSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vdmpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002060) { + // 00011100000vvvvvPP1uuuuu011xxxxx | Vx.w += vdmpy(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VDMPYHVSAT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vdmpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x190000a0) { + // 00011001000tttttPP0uuuuu101ddddd | Vdd.uw = vdsad(Vuu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VDSADUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uw = vdsad(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19602000) { + // 00011001011tttttPP1uuuuu000xxxxx | Vxx.uw += vdsad(Vuu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VDSADUH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uw += vdsad(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800000) { + // 00011111100vvvvvPP0uuuuu000000dd | Qd = vcmp.eq(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VEQB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcmp.eq(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802000) { + // 00011100100vvvvvPP1uuuuu000000xx | Qx &= vcmp.eq(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VEQB_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s &= vcmp.eq(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802040) { + // 00011100100vvvvvPP1uuuuu010000xx | Qx |= vcmp.eq(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VEQB_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s |= vcmp.eq(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802080) { + // 00011100100vvvvvPP1uuuuu100000xx | Qx ^= vcmp.eq(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VEQB_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s ^= vcmp.eq(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800004) { + // 00011111100vvvvvPP0uuuuu000001dd | Qd = vcmp.eq(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VEQH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcmp.eq(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802004) { + // 00011100100vvvvvPP1uuuuu000001xx | Qx &= vcmp.eq(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VEQH_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s &= vcmp.eq(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802044) { + // 00011100100vvvvvPP1uuuuu010001xx | Qx |= vcmp.eq(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VEQH_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s |= vcmp.eq(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802084) { + // 00011100100vvvvvPP1uuuuu100001xx | Qx ^= vcmp.eq(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VEQH_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s ^= vcmp.eq(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800008) { + // 00011111100vvvvvPP0uuuuu000010dd | Qd = vcmp.eq(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VEQW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcmp.eq(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802008) { + // 00011100100vvvvvPP1uuuuu000010xx | Qx &= vcmp.eq(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VEQW_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s &= vcmp.eq(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802048) { + // 00011100100vvvvvPP1uuuuu010010xx | Qx |= vcmp.eq(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VEQW_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s |= vcmp.eq(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802088) { + // 00011100100vvvvvPP1uuuuu100010xx | Qx ^= vcmp.eq(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VEQW_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s ^= vcmp.eq(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800010) { + // 00011111100vvvvvPP0uuuuu000100dd | Qd = vcmp.gt(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VGTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcmp.gt(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802010) { + // 00011100100vvvvvPP1uuuuu000100xx | Qx &= vcmp.gt(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VGTB_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s &= vcmp.gt(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802050) { + // 00011100100vvvvvPP1uuuuu010100xx | Qx |= vcmp.gt(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VGTB_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s |= vcmp.gt(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802090) { + // 00011100100vvvvvPP1uuuuu100100xx | Qx ^= vcmp.gt(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VGTB_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s ^= vcmp.gt(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800014) { + // 00011111100vvvvvPP0uuuuu000101dd | Qd = vcmp.gt(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VGTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcmp.gt(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802014) { + // 00011100100vvvvvPP1uuuuu000101xx | Qx &= vcmp.gt(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VGTH_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s &= vcmp.gt(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802054) { + // 00011100100vvvvvPP1uuuuu010101xx | Qx |= vcmp.gt(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VGTH_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s |= vcmp.gt(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802094) { + // 00011100100vvvvvPP1uuuuu100101xx | Qx ^= vcmp.gt(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VGTH_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s ^= vcmp.gt(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800020) { + // 00011111100vvvvvPP0uuuuu001000dd | Qd = vcmp.gt(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VGTUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcmp.gt(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802020) { + // 00011100100vvvvvPP1uuuuu001000xx | Qx &= vcmp.gt(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VGTUB_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s &= vcmp.gt(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802060) { + // 00011100100vvvvvPP1uuuuu011000xx | Qx |= vcmp.gt(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VGTUB_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s |= vcmp.gt(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c8020a0) { + // 00011100100vvvvvPP1uuuuu101000xx | Qx ^= vcmp.gt(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VGTUB_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s ^= vcmp.gt(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800024) { + // 00011111100vvvvvPP0uuuuu001001dd | Qd = vcmp.gt(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VGTUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcmp.gt(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802024) { + // 00011100100vvvvvPP1uuuuu001001xx | Qx &= vcmp.gt(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VGTUH_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s &= vcmp.gt(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802064) { + // 00011100100vvvvvPP1uuuuu011001xx | Qx |= vcmp.gt(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VGTUH_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s |= vcmp.gt(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c8020a4) { + // 00011100100vvvvvPP1uuuuu101001xx | Qx ^= vcmp.gt(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VGTUH_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s ^= vcmp.gt(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800028) { + // 00011111100vvvvvPP0uuuuu001010dd | Qd = vcmp.gt(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VGTUW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcmp.gt(%s.uw,%s.uw) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802028) { + // 00011100100vvvvvPP1uuuuu001010xx | Qx &= vcmp.gt(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VGTUW_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s &= vcmp.gt(%s.uw,%s.uw) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802068) { + // 00011100100vvvvvPP1uuuuu011010xx | Qx |= vcmp.gt(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VGTUW_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s |= vcmp.gt(%s.uw,%s.uw) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c8020a8) { + // 00011100100vvvvvPP1uuuuu101010xx | Qx ^= vcmp.gt(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VGTUW_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s ^= vcmp.gt(%s.uw,%s.uw) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800018) { + // 00011111100vvvvvPP0uuuuu000110dd | Qd = vcmp.gt(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VGTW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vcmp.gt(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802018) { + // 00011100100vvvvvPP1uuuuu000110xx | Qx &= vcmp.gt(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VGTW_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s &= vcmp.gt(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802058) { + // 00011100100vvvvvPP1uuuuu010110xx | Qx |= vcmp.gt(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VGTW_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s |= vcmp.gt(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802098) { + // 00011100100vvvvvPP1uuuuu100110xx | Qx ^= vcmp.gt(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VGTW_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s ^= vcmp.gt(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fff) == 0x1e002080) { + // 0001111000000000PP10000010000000 | vhist + hi->instruction = HEX_INS_V6_VHIST; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s vhist %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3fff) == 0x1e022080) { + // 00011110vv000010PP10000010000000 | vhist(Qv) + hi->instruction = HEX_INS_V6_VHISTQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + sprintf(hi->mnem, "%s vhist(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x19a02020) { + // 00011001101tttttPP100000001xxxxx | Vx.w = vinsert(Rt) + hi->instruction = HEX_INS_V6_VINSERTWR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vinsert(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000020) { + // 00011011vvvvvtttPP0uuuuu001ddddd | Vd = vlalign(Vu,Vv,Rt) + hi->instruction = HEX_INS_V6_VLALIGNB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s = vlalign(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x1e602000) { + // 00011110011vvvvvPP1uuuuuiiiddddd | Vd = vlalign(Vu,Vv,#Ii) + hi->instruction = HEX_INS_V6_VLALIGNBI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = vlalign(%s,%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19800060) { + // 00011001100tttttPP0uuuuu011ddddd | Vd.ub = vlsr(Vu.ub,Rt) + hi->instruction = HEX_INS_V6_VLSRB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.ub = vlsr(%s.ub,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19800040) { + // 00011001100tttttPP0uuuuu010ddddd | Vd.uh = vlsr(Vu.uh,Rt) + hi->instruction = HEX_INS_V6_VLSRH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uh = vlsr(%s.uh,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00040) { + // 00011111101vvvvvPP0uuuuu010ddddd | Vd.h = vlsr(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VLSRHV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vlsr(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19800020) { + // 00011001100tttttPP0uuuuu001ddddd | Vd.uw = vlsr(Vu.uw,Rt) + hi->instruction = HEX_INS_V6_VLSRW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uw = vlsr(%s.uw,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00020) { + // 00011111101vvvvvPP0uuuuu001ddddd | Vd.w = vlsr(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VLSRWV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vlsr(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19600080) { + // 00011001011tttttPP0uuuuu100ddddd | Vd.h = vlut4(Vu.uh,Rtt.h) + hi->instruction = HEX_INS_V6_VLUT4; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + sprintf(hi->mnem, "%s %s.h = vlut4(%s.uh,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b002020) { + // 00011011vvvvvtttPP1uuuuu001ddddd | Vd.b = vlut32(Vu.b,Vv.b,Rt) + hi->instruction = HEX_INS_V6_VLUTVVB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.b = vlut32(%s.b,%s.b,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x18000060) { + // 00011000vvvvvtttPP0uuuuu011ddddd | Vd.b = vlut32(Vu.b,Vv.b,Rt):nomatch + hi->instruction = HEX_INS_V6_VLUTVVB_NM; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.b = vlut32(%s.b,%s.b,%s):nomatch %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0020a0) { + // 00011011vvvvvtttPP1uuuuu101xxxxx | Vx.b |= vlut32(Vu.b,Vv.b,Rt) + hi->instruction = HEX_INS_V6_VLUTVVB_ORACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.b |= vlut32(%s.b,%s.b,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x1cc02000) { + // 00011100110vvvvvPP1uuuuuiiixxxxx | Vx.b |= vlut32(Vu.b,Vv.b,#Ii) + hi->instruction = HEX_INS_V6_VLUTVVB_ORACCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s.b |= vlut32(%s.b,%s.b,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x1e200000) { + // 00011110001vvvvvPP0uuuuuiiiddddd | Vd.b = vlut32(Vu.b,Vv.b,#Ii) + hi->instruction = HEX_INS_V6_VLUTVVBI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s.b = vlut32(%s.b,%s.b,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0020c0) { + // 00011011vvvvvtttPP1uuuuu110ddddd | Vdd.h = vlut16(Vu.b,Vv.h,Rt) + hi->instruction = HEX_INS_V6_VLUTVWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.h = vlut16(%s.b,%s.h,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x18000080) { + // 00011000vvvvvtttPP0uuuuu100ddddd | Vdd.h = vlut16(Vu.b,Vv.h,Rt):nomatch + hi->instruction = HEX_INS_V6_VLUTVWH_NM; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.h = vlut16(%s.b,%s.h,%s):nomatch %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0020e0) { + // 00011011vvvvvtttPP1uuuuu111xxxxx | Vxx.h |= vlut16(Vu.b,Vv.h,Rt) + hi->instruction = HEX_INS_V6_VLUTVWH_ORACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.h |= vlut16(%s.b,%s.h,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x1ce02000) { + // 00011100111vvvvvPP1uuuuuiiixxxxx | Vxx.h |= vlut16(Vu.b,Vv.h,#Ii) + hi->instruction = HEX_INS_V6_VLUTVWH_ORACCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s.h |= vlut16(%s.b,%s.h,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x1e600000) { + // 00011110011vvvvvPP0uuuuuiiiddddd | Vdd.h = vlut16(Vu.b,Vv.h,#Ii) + hi->instruction = HEX_INS_V6_VLUTVWHI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s.h = vlut16(%s.b,%s.h,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f2000a0) { + // 00011111001vvvvvPP0uuuuu101ddddd | Vd.b = vmax(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VMAXB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vmax(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0000e0) { + // 00011111000vvvvvPP0uuuuu111ddddd | Vd.h = vmax(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMAXH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vmax(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0000a0) { + // 00011111000vvvvvPP0uuuuu101ddddd | Vd.ub = vmax(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VMAXUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vmax(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0000c0) { + // 00011111000vvvvvPP0uuuuu110ddddd | Vd.uh = vmax(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VMAXUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vmax(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200000) { + // 00011111001vvvvvPP0uuuuu000ddddd | Vd.w = vmax(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VMAXW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmax(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200080) { + // 00011111001vvvvvPP0uuuuu100ddddd | Vd.b = vmin(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VMINB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vmin(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000060) { + // 00011111000vvvvvPP0uuuuu011ddddd | Vd.h = vmin(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMINH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vmin(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000020) { + // 00011111000vvvvvPP0uuuuu001ddddd | Vd.ub = vmin(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VMINUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vmin(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000040) { + // 00011111000vvvvvPP0uuuuu010ddddd | Vd.uh = vmin(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VMINUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vmin(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000080) { + // 00011111000vvvvvPP0uuuuu100ddddd | Vd.w = vmin(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VMINW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmin(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x192000c0) { + // 00011001001tttttPP0uuuuu110ddddd | Vdd.h = vmpa(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VMPABUS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vmpa(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x192020c0) { + // 00011001001tttttPP1uuuuu110xxxxx | Vxx.h += vmpa(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VMPABUS_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += vmpa(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200060) { + // 00011100001vvvvvPP0uuuuu011ddddd | Vdd.h = vmpa(Vuu.ub,Vvv.b) + hi->instruction = HEX_INS_V6_VMPABUSV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.h = vmpa(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19600060) { + // 00011001011tttttPP0uuuuu011ddddd | Vdd.h = vmpa(Vuu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VMPABUU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vmpa(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19a02080) { + // 00011001101tttttPP1uuuuu100xxxxx | Vxx.h += vmpa(Vuu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VMPABUU_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += vmpa(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce000e0) { + // 00011100111vvvvvPP0uuuuu111ddddd | Vdd.h = vmpa(Vuu.ub,Vvv.ub) + hi->instruction = HEX_INS_V6_VMPABUUV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.h = vmpa(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x192000e0) { + // 00011001001tttttPP0uuuuu111ddddd | Vdd.w = vmpa(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VMPAHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vmpa(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x192020e0) { + // 00011001001tttttPP1uuuuu111xxxxx | Vxx.w += vmpa(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VMPAHB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vmpa(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19802080) { + // 00011001100tttttPP1uuuuu100xxxxx | Vx.h = vmpa(Vxin.h,Vu.h,Rtt.h):sat + hi->instruction = HEX_INS_V6_VMPAHHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + sprintf(hi->mnem, "%s %s.h = vmpa(%sin.h,%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x198000a0) { + // 00011001100tttttPP0uuuuu101ddddd | Vdd.w = vmpa(Vuu.uh,Rt.b) + hi->instruction = HEX_INS_V6_VMPAUHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vmpa(%s.uh,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19802040) { + // 00011001100tttttPP1uuuuu010xxxxx | Vxx.w += vmpa(Vuu.uh,Rt.b) + hi->instruction = HEX_INS_V6_VMPAUHB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vmpa(%s.uh,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x198020a0) { + // 00011001100tttttPP1uuuuu101xxxxx | Vx.h = vmpa(Vxin.h,Vu.uh,Rtt.uh):sat + hi->instruction = HEX_INS_V6_VMPAUHUHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + sprintf(hi->mnem, "%s %s.h = vmpa(%sin.h,%s.uh,%s.uh):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x198020c0) { + // 00011001100tttttPP1uuuuu110xxxxx | Vx.h = vmps(Vxin.h,Vu.uh,Rtt.uh):sat + hi->instruction = HEX_INS_V6_VMPSUHUHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32in + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + sprintf(hi->mnem, "%s %s.h = vmps(%sin.h,%s.uh,%s.uh):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x192000a0) { + // 00011001001tttttPP0uuuuu101ddddd | Vdd.h = vmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VMPYBUS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x192020a0) { + // 00011001001tttttPP1uuuuu101xxxxx | Vxx.h += vmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VMPYBUS_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += vmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0000c0) { + // 00011100000vvvvvPP0uuuuu110ddddd | Vdd.h = vmpy(Vu.ub,Vv.b) + hi->instruction = HEX_INS_V6_VMPYBUSV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0020c0) { + // 00011100000vvvvvPP1uuuuu110xxxxx | Vxx.h += vmpy(Vu.ub,Vv.b) + hi->instruction = HEX_INS_V6_VMPYBUSV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h += vmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000080) { + // 00011100000vvvvvPP0uuuuu100ddddd | Vdd.h = vmpy(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VMPYBV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vmpy(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002080) { + // 00011100000vvvvvPP1uuuuu100xxxxx | Vxx.h += vmpy(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VMPYBV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h += vmpy(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe000a0) { + // 00011111111vvvvvPP0uuuuu101ddddd | Vd.w = vmpye(Vu.w,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYEWUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmpye(%s.w,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea000c0) { + // 00011110101vvvvvPP0uuuuu110ddddd | Vdd = vmpye(Vu.w,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYEWUH_64; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vmpye(%s.w,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19400000) { + // 00011001010tttttPP0uuuuu000ddddd | Vdd.w = vmpy(Vu.h,Rt.h) + hi->instruction = HEX_INS_V6_VMPYH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vmpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19a020c0) { + // 00011001101tttttPP1uuuuu110xxxxx | Vxx.w += vmpy(Vu.h,Rt.h) + hi->instruction = HEX_INS_V6_VMPYH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vmpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19402000) { + // 00011001010tttttPP1uuuuu000xxxxx | Vxx.w += vmpy(Vu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VMPYHSAT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vmpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19400040) { + // 00011001010tttttPP0uuuuu010ddddd | Vd.h = vmpy(Vu.h,Rt.h):<<1:rnd:sat + hi->instruction = HEX_INS_V6_VMPYHSRS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vmpy(%s.h,%s.h):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19400020) { + // 00011001010tttttPP0uuuuu001ddddd | Vd.h = vmpy(Vu.h,Rt.h):<<1:sat + hi->instruction = HEX_INS_V6_VMPYHSS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vmpy(%s.h,%s.h):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200040) { + // 00011100001vvvvvPP0uuuuu010ddddd | Vdd.w = vmpy(Vu.h,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYHUS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmpy(%s.h,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202020) { + // 00011100001vvvvvPP1uuuuu001xxxxx | Vxx.w += vmpy(Vu.h,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYHUS_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vmpy(%s.h,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0000e0) { + // 00011100000vvvvvPP0uuuuu111ddddd | Vdd.w = vmpy(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYHV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0020e0) { + // 00011100000vvvvvPP1uuuuu111xxxxx | Vxx.w += vmpy(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYHV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vmpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200020) { + // 00011100001vvvvvPP0uuuuu001ddddd | Vd.h = vmpy(Vu.h,Vv.h):<<1:rnd:sat + hi->instruction = HEX_INS_V6_VMPYHVSRS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vmpy(%s.h,%s.h):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600000) { + // 00011111011vvvvvPP0uuuuu000ddddd | Vd.w = vmpyieo(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIEOH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmpyieo(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c402000) { + // 00011100010vvvvvPP1uuuuu000xxxxx | Vx.w += vmpyie(Vu.w,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIEWH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vmpyie(%s.w,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00000) { + // 00011111110vvvvvPP0uuuuu000ddddd | Vd.w = vmpyie(Vu.w,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYIEWUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmpyie(%s.w,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2020a0) { + // 00011100001vvvvvPP1uuuuu101xxxxx | Vx.w += vmpyie(Vu.w,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYIEWUH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vmpyie(%s.w,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200080) { + // 00011100001vvvvvPP0uuuuu100ddddd | Vd.h = vmpyi(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vmpyi(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202080) { + // 00011100001vvvvvPP1uuuuu100xxxxx | Vx.h += vmpyi(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h += vmpyi(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19600000) { + // 00011001011tttttPP0uuuuu000ddddd | Vd.h = vmpyi(Vu.h,Rt.b) + hi->instruction = HEX_INS_V6_VMPYIHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = vmpyi(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19602020) { + // 00011001011tttttPP1uuuuu001xxxxx | Vx.h += vmpyi(Vu.h,Rt.b) + hi->instruction = HEX_INS_V6_VMPYIHB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += vmpyi(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00020) { + // 00011111110vvvvvPP0uuuuu001ddddd | Vd.w = vmpyio(Vu.w,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIOWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmpyio(%s.w,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19a00000) { + // 00011001101tttttPP0uuuuu000ddddd | Vd.w = vmpyi(Vu.w,Rt.b) + hi->instruction = HEX_INS_V6_VMPYIWB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vmpyi(%s.w,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19402040) { + // 00011001010tttttPP1uuuuu010xxxxx | Vx.w += vmpyi(Vu.w,Rt.b) + hi->instruction = HEX_INS_V6_VMPYIWB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vmpyi(%s.w,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x198000e0) { + // 00011001100tttttPP0uuuuu111ddddd | Vd.w = vmpyi(Vu.w,Rt.h) + hi->instruction = HEX_INS_V6_VMPYIWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vmpyi(%s.w,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19402060) { + // 00011001010tttttPP1uuuuu011xxxxx | Vx.w += vmpyi(Vu.w,Rt.h) + hi->instruction = HEX_INS_V6_VMPYIWH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vmpyi(%s.w,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x198000c0) { + // 00011001100tttttPP0uuuuu110ddddd | Vd.w = vmpyi(Vu.w,Rt.ub) + hi->instruction = HEX_INS_V6_VMPYIWUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vmpyi(%s.w,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19802020) { + // 00011001100tttttPP1uuuuu001xxxxx | Vx.w += vmpyi(Vu.w,Rt.ub) + hi->instruction = HEX_INS_V6_VMPYIWUB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vmpyi(%s.w,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe000e0) { + // 00011111111vvvvvPP0uuuuu111ddddd | Vd.w = vmpyo(Vu.w,Vv.h):<<1:sat + hi->instruction = HEX_INS_V6_VMPYOWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmpyo(%s.w,%s.h):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202060) { + // 00011100001vvvvvPP1uuuuu011xxxxx | Vxx += vmpyo(Vu.w,Vv.h) + hi->instruction = HEX_INS_V6_VMPYOWH_64_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s += vmpyo(%s.w,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400000) { + // 00011111010vvvvvPP0uuuuu000ddddd | Vd.w = vmpyo(Vu.w,Vv.h):<<1:rnd:sat + hi->instruction = HEX_INS_V6_VMPYOWH_RND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vmpyo(%s.w,%s.h):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2020e0) { + // 00011100001vvvvvPP1uuuuu111xxxxx | Vx.w += vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift + hi->instruction = HEX_INS_V6_VMPYOWH_RND_SACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vmpyo(%s.w,%s.h):<<1:rnd:sat:shift %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2020c0) { + // 00011100001vvvvvPP1uuuuu110xxxxx | Vx.w += vmpyo(Vu.w,Vv.h):<<1:sat:shift + hi->instruction = HEX_INS_V6_VMPYOWH_SACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vmpyo(%s.w,%s.h):<<1:sat:shift %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19c00000) { + // 00011001110tttttPP0uuuuu000ddddd | Vdd.uh = vmpy(Vu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VMPYUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uh = vmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19802000) { + // 00011001100tttttPP1uuuuu000xxxxx | Vxx.uh += vmpy(Vu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VMPYUB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uh += vmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0000a0) { + // 00011100000vvvvvPP0uuuuu101ddddd | Vdd.uh = vmpy(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VMPYUBV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0020a0) { + // 00011100000vvvvvPP1uuuuu101xxxxx | Vxx.uh += vmpy(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VMPYUBV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh += vmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19400060) { + // 00011001010tttttPP0uuuuu011ddddd | Vdd.uw = vmpy(Vu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VMPYUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uw = vmpy(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19402020) { + // 00011001010tttttPP1uuuuu001xxxxx | Vxx.uw += vmpy(Vu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VMPYUH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uw += vmpy(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19600040) { + // 00011001011tttttPP0uuuuu010ddddd | Vd.uw = vmpye(Vu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VMPYUHE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uw = vmpye(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19802060) { + // 00011001100tttttPP1uuuuu011xxxxx | Vx.uw += vmpye(Vu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VMPYUHE_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uw += vmpye(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200000) { + // 00011100001vvvvvPP0uuuuu000ddddd | Vdd.uw = vmpy(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYUHV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw = vmpy(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202000) { + // 00011100001vvvvvPP1uuuuu000xxxxx | Vxx.uw += vmpy(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYUHV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw += vmpy(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1ee02000) { + // 00011110111vvvvvPP1uuuuu0ttddddd | Vd = vmux(Qt,Vu,Vv) + hi->instruction = HEX_INS_V6_VMUX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Qt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vmux(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0020c0) { + // 00011111000vvvvvPP1uuuuu110ddddd | Vd.b = vnavg(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VNAVGB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vnavg(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00020) { + // 00011100111vvvvvPP0uuuuu001ddddd | Vd.h = vnavg(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VNAVGH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vnavg(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00000) { + // 00011100111vvvvvPP0uuuuu000ddddd | Vd.b = vnavg(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VNAVGUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vnavg(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00040) { + // 00011100111vvvvvPP0uuuuu010ddddd | Vd.w = vnavg(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VNAVGW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vnavg(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1a400000) { + // 00011010010vvvvvPP0uuuuu0ssddddd | if (!Ps) Vdd = vcombine(Vu,Vv) + hi->instruction = HEX_INS_V6_VNCCOMBINE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s if (!%s) %s = vcombine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff2080) == 0x1a200000) { + // 0001101000100000PP0uuuuu0ssddddd | if (!Ps) Vd = Vu + hi->instruction = HEX_INS_V6_VNCMOV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (!%s) %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0300a0) { + // 0001111000000011PP0uuuuu101ddddd | Vd.h = vnormamt(Vu.h) + hi->instruction = HEX_INS_V6_VNORMAMTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.h = vnormamt(%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e030080) { + // 0001111000000011PP0uuuuu100ddddd | Vd.w = vnormamt(Vu.w) + hi->instruction = HEX_INS_V6_VNORMAMTW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vnormamt(%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000080) { + // 0001111000000000PP0uuuuu100ddddd | Vd = vnot(Vu) + hi->instruction = HEX_INS_V6_VNOT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s = vnot(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2000c0) { + // 00011100001vvvvvPP0uuuuu110ddddd | Vd = vor(Vu,Vv) + hi->instruction = HEX_INS_V6_VOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00040) { + // 00011111110vvvvvPP0uuuuu010ddddd | Vd.b = vpacke(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VPACKEB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vpacke(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00060) { + // 00011111110vvvvvPP0uuuuu011ddddd | Vd.h = vpacke(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VPACKEH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vpacke(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc000c0) { + // 00011111110vvvvvPP0uuuuu110ddddd | Vd.b = vpack(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VPACKHB_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vpack(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc000a0) { + // 00011111110vvvvvPP0uuuuu101ddddd | Vd.ub = vpack(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VPACKHUB_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vpack(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00020) { + // 00011111111vvvvvPP0uuuuu001ddddd | Vd.b = vpacko(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VPACKOB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vpacko(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00040) { + // 00011111111vvvvvPP0uuuuu010ddddd | Vd.h = vpacko(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VPACKOH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vpacko(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00000) { + // 00011111111vvvvvPP0uuuuu000ddddd | Vd.h = vpack(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VPACKWH_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vpack(%s.w,%s.w):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc000e0) { + // 00011111110vvvvvPP0uuuuu111ddddd | Vd.uh = vpack(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VPACKWUH_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vpack(%s.w,%s.w):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0200c0) { + // 0001111000000010PP0uuuuu110ddddd | Vd.h = vpopcount(Vu.h) + hi->instruction = HEX_INS_V6_VPOPCOUNTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.h = vpopcount(%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3fe0) == 0x1e032040) { + // 00011110vv000011PP100000010ddddd | Vd.b = prefixsum(Qv) + hi->instruction = HEX_INS_V6_VPREFIXQB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + sprintf(hi->mnem, "%s %s.b = prefixsum(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3fe0) == 0x1e032140) { + // 00011110vv000011PP100001010ddddd | Vd.h = prefixsum(Qv) + hi->instruction = HEX_INS_V6_VPREFIXQH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + sprintf(hi->mnem, "%s %s.h = prefixsum(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3fe0) == 0x1e032240) { + // 00011110vv000011PP100010010ddddd | Vd.w = prefixsum(Qv) + hi->instruction = HEX_INS_V6_VPREFIXQW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + sprintf(hi->mnem, "%s %s.w = prefixsum(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200060) { + // 00011111001vvvvvPP0uuuuu011ddddd | Vd = vrdelta(Vu,Vv) + hi->instruction = HEX_INS_V6_VRDELTA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vrdelta(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19c000a0) { + // 00011001110tttttPP0uuuuu101ddddd | Vdd.w = vrmpy(Vu.b,Rtt.ub) + hi->instruction = HEX_INS_V6_VRMPYBUB_RTT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + sprintf(hi->mnem, "%s %s.w = vrmpy(%s.b,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19a02000) { + // 00011001101tttttPP1uuuuu000xxxxx | Vxx.w += vrmpy(Vu.b,Rtt.ub) + hi->instruction = HEX_INS_V6_VRMPYBUB_RTT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + sprintf(hi->mnem, "%s %s.w += vrmpy(%s.b,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19000080) { + // 00011001000tttttPP0uuuuu100ddddd | Vd.w = vrmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYBUS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = vrmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x190020a0) { + // 00011001000tttttPP1uuuuu101xxxxx | Vx.w += vrmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYBUS_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += vrmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0x19400080) { + // 00011001010tttttPP0uuuuu10iddddd | Vdd.w = vrmpy(Vuu.ub,Rt.b,#Ii) + hi->instruction = HEX_INS_V6_VRMPYBUSI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + sprintf(hi->mnem, "%s %s.w = vrmpy(%s.ub,%s.b,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0x19402080) { + // 00011001010tttttPP1uuuuu10ixxxxx | Vxx.w += vrmpy(Vuu.ub,Rt.b,#Ii) + hi->instruction = HEX_INS_V6_VRMPYBUSI_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + sprintf(hi->mnem, "%s %s.w += vrmpy(%s.ub,%s.b,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000040) { + // 00011100000vvvvvPP0uuuuu010ddddd | Vd.w = vrmpy(Vu.ub,Vv.b) + hi->instruction = HEX_INS_V6_VRMPYBUSV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vrmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002040) { + // 00011100000vvvvvPP1uuuuu010xxxxx | Vx.w += vrmpy(Vu.ub,Vv.b) + hi->instruction = HEX_INS_V6_VRMPYBUSV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vrmpy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000020) { + // 00011100000vvvvvPP0uuuuu001ddddd | Vd.w = vrmpy(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VRMPYBV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vrmpy(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002020) { + // 00011100000vvvvvPP1uuuuu001xxxxx | Vx.w += vrmpy(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VRMPYBV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w += vrmpy(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19000060) { + // 00011001000tttttPP0uuuuu011ddddd | Vd.uw = vrmpy(Vu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VRMPYUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uw = vrmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19002080) { + // 00011001000tttttPP1uuuuu100xxxxx | Vx.uw += vrmpy(Vu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VRMPYUB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.uw += vrmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19c00080) { + // 00011001110tttttPP0uuuuu100ddddd | Vdd.uw = vrmpy(Vu.ub,Rtt.ub) + hi->instruction = HEX_INS_V6_VRMPYUB_RTT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + sprintf(hi->mnem, "%s %s.uw = vrmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19a020e0) { + // 00011001101tttttPP1uuuuu111xxxxx | Vxx.uw += vrmpy(Vu.ub,Rtt.ub) + hi->instruction = HEX_INS_V6_VRMPYUB_RTT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + sprintf(hi->mnem, "%s %s.uw += vrmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0x19a000c0) { + // 00011001101tttttPP0uuuuu11iddddd | Vdd.uw = vrmpy(Vuu.ub,Rt.ub,#Ii) + hi->instruction = HEX_INS_V6_VRMPYUBI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + sprintf(hi->mnem, "%s %s.uw = vrmpy(%s.ub,%s.ub,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0x196020c0) { + // 00011001011tttttPP1uuuuu11ixxxxx | Vxx.uw += vrmpy(Vuu.ub,Rt.ub,#Ii) + hi->instruction = HEX_INS_V6_VRMPYUBI_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + sprintf(hi->mnem, "%s %s.uw += vrmpy(%s.ub,%s.ub,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000000) { + // 00011100000vvvvvPP0uuuuu000ddddd | Vd.uw = vrmpy(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VRMPYUBV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw = vrmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002000) { + // 00011100000vvvvvPP1uuuuu000xxxxx | Vx.uw += vrmpy(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VRMPYUBV_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw += vrmpy(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19e80000) { + // 0001100111101tttPP0uuuuu000ddddd | Vdddd.w = vrmpyz(Vu.b,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZBB_RT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w = vrmpyz(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19c02040) { + // 0001100111000tttPP1uuuuu010yyyyy | Vyyyy.w += vrmpyz(Vu.b,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZBB_RT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w += vrmpyz(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19e00000) { + // 0001100111100xxxPP0uuuuu000ddddd | Vdddd.w = vrmpyz(Vu.b,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZBB_RX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vrmpyz(%s.b,%s.b++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19c82040) { + // 0001100111001xxxPP1uuuuu010yyyyy | Vyyyy.w += vrmpyz(Vu.b,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZBB_RX_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w += vrmpyz(%s.b,%s.b++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19f80040) { + // 0001100111111tttPP0uuuuu010ddddd | Vdddd.w = vrmpyz(Vu.b,Rt.ub) + hi->instruction = HEX_INS_V6_VRMPYZBUB_RT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w = vrmpyz(%s.b,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19d02020) { + // 0001100111010tttPP1uuuuu001yyyyy | Vyyyy.w += vrmpyz(Vu.b,Rt.ub) + hi->instruction = HEX_INS_V6_VRMPYZBUB_RT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w += vrmpyz(%s.b,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19f00040) { + // 0001100111110xxxPP0uuuuu010ddddd | Vdddd.w = vrmpyz(Vu.b,Rx.ub++) + hi->instruction = HEX_INS_V6_VRMPYZBUB_RX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vrmpyz(%s.b,%s.ub++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19d82020) { + // 0001100111011xxxPP1uuuuu001yyyyy | Vyyyy.w += vrmpyz(Vu.b,Rx.ub++) + hi->instruction = HEX_INS_V6_VRMPYZBUB_RX_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w += vrmpyz(%s.b,%s.ub++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19e80020) { + // 0001100111101tttPP0uuuuu001ddddd | Vdddd.w = vr16mpyz(Vu.c,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZCB_RT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w = vr16mpyz(%s.c,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19c02060) { + // 0001100111000tttPP1uuuuu011yyyyy | Vyyyy.w += vr16mpyz(Vu.c,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZCB_RT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w += vr16mpyz(%s.c,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19e00020) { + // 0001100111100xxxPP0uuuuu001ddddd | Vdddd.w = vr16mpyz(Vu.c,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZCB_RX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vr16mpyz(%s.c,%s.b++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19c82060) { + // 0001100111001xxxPP1uuuuu011yyyyy | Vyyyy.w += vr16mpyz(Vu.c,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZCB_RX_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w += vr16mpyz(%s.c,%s.b++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19e80040) { + // 0001100111101tttPP0uuuuu010ddddd | Vdddd.w = vr16mpyzs(Vu.c,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZCBS_RT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w = vr16mpyzs(%s.c,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19c02020) { + // 0001100111000tttPP1uuuuu001yyyyy | Vyyyy.w += vr16mpyzs(Vu.c,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZCBS_RT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w += vr16mpyzs(%s.c,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19e00040) { + // 0001100111100xxxPP0uuuuu010ddddd | Vdddd.w = vr16mpyzs(Vu.c,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZCBS_RX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vr16mpyzs(%s.c,%s.b++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19c82020) { + // 0001100111001xxxPP1uuuuu001yyyyy | Vyyyy.w += vr16mpyzs(Vu.c,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZCBS_RX_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w += vr16mpyzs(%s.c,%s.b++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19f80000) { + // 0001100111111tttPP0uuuuu000ddddd | Vdddd.w = vr8mpyz(Vu.n,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZNB_RT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w = vr8mpyz(%s.n,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19d02040) { + // 0001100111010tttPP1uuuuu010yyyyy | Vyyyy.w += vr8mpyz(Vu.n,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZNB_RT_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s.w += vr8mpyz(%s.n,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19f00000) { + // 0001100111110xxxPP0uuuuu000ddddd | Vdddd.w = vr8mpyz(Vu.n,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZNB_RX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vr8mpyz(%s.n,%s.b++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfff820e0) == 0x19d82040) { + // 0001100111011xxxPP1uuuuu010yyyyy | Vyyyy.w += vr8mpyz(Vu.n,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZNB_RX_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w += vr8mpyz(%s.n,%s.b++) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19600020) { + // 00011001011tttttPP0uuuuu001ddddd | Vd = vror(Vu,Rt) + hi->instruction = HEX_INS_V6_VROR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s = vror(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1a8020e0) { + // 00011010100vvvvvPP1uuuuu111ddddd | Vd.uw = vrotr(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VROTR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw = vrotr(%s.uw,%s.uw) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f6000c0) { + // 00011111011vvvvvPP0uuuuu110ddddd | Vd.b = vround(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VROUNDHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vround(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f6000e0) { + // 00011111011vvvvvPP0uuuuu111ddddd | Vd.ub = vround(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VROUNDHUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vround(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00060) { + // 00011111111vvvvvPP0uuuuu011ddddd | Vd.ub = vround(Vu.uh,Vv.uh):sat + hi->instruction = HEX_INS_V6_VROUNDUHUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vround(%s.uh,%s.uh):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00080) { + // 00011111111vvvvvPP0uuuuu100ddddd | Vd.uh = vround(Vu.uw,Vv.uw):sat + hi->instruction = HEX_INS_V6_VROUNDUWUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vround(%s.uw,%s.uw):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600080) { + // 00011111011vvvvvPP0uuuuu100ddddd | Vd.h = vround(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VROUNDWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vround(%s.w,%s.w):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f6000a0) { + // 00011111011vvvvvPP0uuuuu101ddddd | Vd.uh = vround(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VROUNDWUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vround(%s.w,%s.w):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0x194000c0) { + // 00011001010tttttPP0uuuuu11iddddd | Vdd.uw = vrsad(Vuu.ub,Rt.ub,#Ii) + hi->instruction = HEX_INS_V6_VRSADUBI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + sprintf(hi->mnem, "%s %s.uw = vrsad(%s.ub,%s.ub,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0x194020c0) { + // 00011001010tttttPP1uuuuu11ixxxxx | Vxx.uw += vrsad(Vuu.ub,Rt.ub,#Ii) + hi->instruction = HEX_INS_V6_VRSADUBI_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + sprintf(hi->mnem, "%s %s.uw += vrsad(%s.ub,%s.ub,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1d8020e0) { + // 00011101100vvvvvPP1uuuuu111ddddd | Vd.w = vsatdw(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VSATDW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vsatdw(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600040) { + // 00011111011vvvvvPP0uuuuu010ddddd | Vd.ub = vsat(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSATHUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vsat(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f2000c0) { + // 00011111001vvvvvPP0uuuuu110ddddd | Vd.uh = vsat(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VSATUWUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vsat(%s.uw,%s.uw) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600060) { + // 00011111011vvvvvPP0uuuuu011ddddd | Vd.h = vsat(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VSATWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vsat(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020060) { + // 0001111000000010PP0uuuuu011ddddd | Vdd.h = vsxt(Vu.b) + hi->instruction = HEX_INS_V6_VSB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.h = vsxt(%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020080) { + // 0001111000000010PP0uuuuu100ddddd | Vdd.w = vsxt(Vu.h) + hi->instruction = HEX_INS_V6_VSH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vsxt(%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400060) { + // 00011111010vvvvvPP0uuuuu011ddddd | Vd.h = vshuffe(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSHUFEH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vshuffe(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19e02020) { + // 00011001111tttttPP1yyyyy001xxxxx | vshuff(Vy,Vx,Rt) + hi->instruction = HEX_INS_V6_VSHUFF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Vy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s vshuff(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020000) { + // 0001111000000010PP0uuuuu000ddddd | Vd.b = vshuff(Vu.b) + hi->instruction = HEX_INS_V6_VSHUFFB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.b = vshuff(%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400020) { + // 00011111010vvvvvPP0uuuuu001ddddd | Vd.b = vshuffe(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VSHUFFEB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vshuffe(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0100e0) { + // 0001111000000001PP0uuuuu111ddddd | Vd.h = vshuff(Vu.h) + hi->instruction = HEX_INS_V6_VSHUFFH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.h = vshuff(%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400040) { + // 00011111010vvvvvPP0uuuuu010ddddd | Vd.b = vshuffo(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VSHUFFOB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vshuffo(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff0020e0) == 0x1b002060) { + // 00011011vvvvvtttPP1uuuuu011ddddd | Vdd = vshuff(Vu,Vv,Rt) + hi->instruction = HEX_INS_V6_VSHUFFVDD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + sprintf(hi->mnem, "%s %s = vshuff(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f4000c0) { + // 00011111010vvvvvPP0uuuuu110ddddd | Vdd.b = vshuffoe(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VSHUFOEB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vshuffoe(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f4000a0) { + // 00011111010vvvvvPP0uuuuu101ddddd | Vdd.h = vshuffoe(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSHUFOEH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vshuffoe(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400080) { + // 00011111010vvvvvPP0uuuuu100ddddd | Vd.h = vshuffo(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSHUFOH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vshuffo(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c4000a0) { + // 00011100010vvvvvPP0uuuuu101ddddd | Vd.b = vsub(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VSUBB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vsub(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800060) { + // 00011100100vvvvvPP0uuuuu011ddddd | Vdd.b = vsub(Vuu.b,Vvv.b) + hi->instruction = HEX_INS_V6_VSUBB_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.b = vsub(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e022020) { + // 00011110vv000010PP1uuuuu001xxxxx | if (!Qv) Vx.b -= Vu.b + hi->instruction = HEX_INS_V6_VSUBBNQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (!%s) %s.b -= %s.b %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e0120c0) { + // 00011110vv000001PP1uuuuu110xxxxx | if (Qv) Vx.b -= Vu.b + hi->instruction = HEX_INS_V6_VSUBBQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (%s) %s.b -= %s.b %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200040) { + // 00011111001vvvvvPP0uuuuu010ddddd | Vd.b = vsub(Vu.b,Vv.b):sat + hi->instruction = HEX_INS_V6_VSUBBSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.b = vsub(%s.b,%s.b):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00020) { + // 00011110101vvvvvPP0uuuuu001ddddd | Vdd.b = vsub(Vuu.b,Vvv.b):sat + hi->instruction = HEX_INS_V6_VSUBBSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.b = vsub(%s.b,%s.b):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1ca02080) { + // 00011100101vvvvvPP1uuuuu1xxddddd | Vd.w = vsub(Vu.w,Vv.w,Qx):carry + hi->instruction = HEX_INS_V6_VSUBCARRY; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Qx4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vsub(%s.w,%s.w,%s):carry %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[3].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1da02080) { + // 00011101101vvvvvPP1uuuuu1eeddddd | Vd.w,Qe = vsub(Vu.w,Vv.w):carry + hi->instruction = HEX_INS_V6_VSUBCARRYO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Qe4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w,%s = vsub(%s.w,%s.w):carry %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c4000c0) { + // 00011100010vvvvvPP0uuuuu110ddddd | Vd.h = vsub(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSUBH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vsub(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800080) { + // 00011100100vvvvvPP0uuuuu100ddddd | Vdd.h = vsub(Vuu.h,Vvv.h) + hi->instruction = HEX_INS_V6_VSUBH_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.h = vsub(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e022040) { + // 00011110vv000010PP1uuuuu010xxxxx | if (!Qv) Vx.h -= Vu.h + hi->instruction = HEX_INS_V6_VSUBHNQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (!%s) %s.h -= %s.h %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e0120e0) { + // 00011110vv000001PP1uuuuu111xxxxx | if (Qv) Vx.h -= Vu.h + hi->instruction = HEX_INS_V6_VSUBHQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (%s) %s.h -= %s.h %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600040) { + // 00011100011vvvvvPP0uuuuu010ddddd | Vd.h = vsub(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VSUBHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vsub(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00000) { + // 00011100101vvvvvPP0uuuuu000ddddd | Vdd.h = vsub(Vuu.h,Vvv.h):sat + hi->instruction = HEX_INS_V6_VSUBHSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.h = vsub(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca000e0) { + // 00011100101vvvvvPP0uuuuu111ddddd | Vdd.w = vsub(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSUBHW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vsub(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca000a0) { + // 00011100101vvvvvPP0uuuuu101ddddd | Vdd.h = vsub(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VSUBUBH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.h = vsub(%s.ub,%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600000) { + // 00011100011vvvvvPP0uuuuu000ddddd | Vd.ub = vsub(Vu.ub,Vv.ub):sat + hi->instruction = HEX_INS_V6_VSUBUBSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vsub(%s.ub,%s.ub):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c8000c0) { + // 00011100100vvvvvPP0uuuuu110ddddd | Vdd.ub = vsub(Vuu.ub,Vvv.ub):sat + hi->instruction = HEX_INS_V6_VSUBUBSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.ub = vsub(%s.ub,%s.ub):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea000a0) { + // 00011110101vvvvvPP0uuuuu101ddddd | Vd.ub = vsub(Vu.ub,Vv.b):sat + hi->instruction = HEX_INS_V6_VSUBUBUBB_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.ub = vsub(%s.ub,%s.b):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600020) { + // 00011100011vvvvvPP0uuuuu001ddddd | Vd.uh = vsub(Vu.uh,Vv.uh):sat + hi->instruction = HEX_INS_V6_VSUBUHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uh = vsub(%s.uh,%s.uh):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c8000e0) { + // 00011100100vvvvvPP0uuuuu111ddddd | Vdd.uh = vsub(Vuu.uh,Vvv.uh):sat + hi->instruction = HEX_INS_V6_VSUBUHSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.uh = vsub(%s.uh,%s.uh):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca000c0) { + // 00011100101vvvvvPP0uuuuu110ddddd | Vdd.w = vsub(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VSUBUHW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vsub(%s.uh,%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00080) { + // 00011111110vvvvvPP0uuuuu100ddddd | Vd.uw = vsub(Vu.uw,Vv.uw):sat + hi->instruction = HEX_INS_V6_VSUBUWSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.uw = vsub(%s.uw,%s.uw):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00060) { + // 00011110101vvvvvPP0uuuuu011ddddd | Vdd.uw = vsub(Vuu.uw,Vvv.uw):sat + hi->instruction = HEX_INS_V6_VSUBUWSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.uw = vsub(%s.uw,%s.uw):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c4000e0) { + // 00011100010vvvvvPP0uuuuu111ddddd | Vd.w = vsub(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VSUBW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vsub(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c8000a0) { + // 00011100100vvvvvPP0uuuuu101ddddd | Vdd.w = vsub(Vuu.w,Vvv.w) + hi->instruction = HEX_INS_V6_VSUBW_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.w = vsub(%s.w,%s.w) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e022060) { + // 00011110vv000010PP1uuuuu011xxxxx | if (!Qv) Vx.w -= Vu.w + hi->instruction = HEX_INS_V6_VSUBWNQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (!%s) %s.w -= %s.w %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e022000) { + // 00011110vv000010PP1uuuuu000xxxxx | if (Qv) Vx.w -= Vu.w + hi->instruction = HEX_INS_V6_VSUBWQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s if (%s) %s.w -= %s.w %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600060) { + // 00011100011vvvvvPP0uuuuu011ddddd | Vd.w = vsub(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VSUBWSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s.w = vsub(%s.w,%s.w):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00020) { + // 00011100101vvvvvPP0uuuuu001ddddd | Vdd.w = vsub(Vuu.w,Vvv.w):sat + hi->instruction = HEX_INS_V6_VSUBWSAT_DV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + sprintf(hi->mnem, "%s %s.w = vsub(%s.w,%s.w):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0x1ea02000) { + // 00011110101vvvvvPP1uuuuu0ttddddd | Vdd = vswap(Qt,Vu,Vv) + hi->instruction = HEX_INS_V6_VSWAP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Qt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vswap(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19000000) { + // 00011001000tttttPP0uuuuu000ddddd | Vdd.h = vtmpy(Vuu.b,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = VTMPy(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19002000) { + // 00011001000tttttPP1uuuuu000xxxxx | Vxx.h += vtmpy(Vuu.b,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += VTMPy(%s.b,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19000020) { + // 00011001000tttttPP0uuuuu001ddddd | Vdd.h = vtmpy(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYBUS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h = VTMPy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19002020) { + // 00011001000tttttPP1uuuuu001xxxxx | Vxx.h += vtmpy(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYBUS_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.h += VTMPy(%s.ub,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19a00080) { + // 00011001101tttttPP0uuuuu100ddddd | Vdd.w = vtmpy(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w = VTMPy(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x19002040) { + // 00011001000tttttPP1uuuuu010xxxxx | Vxx.w += vtmpy(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYHB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s.w += VTMPy(%s.h,%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010040) { + // 0001111000000001PP0uuuuu010ddddd | Vdd.h = vunpack(Vu.b) + hi->instruction = HEX_INS_V6_VUNPACKB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.h = vunpack(%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010060) { + // 0001111000000001PP0uuuuu011ddddd | Vdd.w = vunpack(Vu.h) + hi->instruction = HEX_INS_V6_VUNPACKH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w = vunpack(%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e002000) { + // 0001111000000000PP1uuuuu000xxxxx | Vxx.h |= vunpacko(Vu.b) + hi->instruction = HEX_INS_V6_VUNPACKOB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.h |= vunpacko(%s.b) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e002020) { + // 0001111000000000PP1uuuuu001xxxxx | Vxx.w |= vunpacko(Vu.h) + hi->instruction = HEX_INS_V6_VUNPACKOH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.w |= vunpacko(%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010000) { + // 0001111000000001PP0uuuuu000ddddd | Vdd.uh = vunpack(Vu.ub) + hi->instruction = HEX_INS_V6_VUNPACKUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.uh = vunpack(%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010020) { + // 0001111000000001PP0uuuuu001ddddd | Vdd.uw = vunpack(Vu.uh) + hi->instruction = HEX_INS_V6_VUNPACKUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.uw = vunpack(%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fff) == 0x1e002480) { + // 0001111000000000PP10010010000000 | vwhist128 + hi->instruction = HEX_INS_V6_VWHIST128; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s vwhist128 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3eff) == 0x1e002680) { + // 0001111000000000PP10011i10000000 | vwhist128(#Ii) + hi->instruction = HEX_INS_V6_VWHIST128M; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x100) >> 8); // Ii + sprintf(hi->mnem, "%s vwhist128(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3fff) == 0x1e022480) { + // 00011110vv000010PP10010010000000 | vwhist128(Qv) + hi->instruction = HEX_INS_V6_VWHIST128Q; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + sprintf(hi->mnem, "%s vwhist128(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3eff) == 0x1e022680) { + // 00011110vv000010PP10011i10000000 | vwhist128(Qv,#Ii) + hi->instruction = HEX_INS_V6_VWHIST128QM; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x100) >> 8); // Ii + sprintf(hi->mnem, "%s vwhist128(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fff) == 0x1e002280) { + // 0001111000000000PP10001010000000 | vwhist256 + hi->instruction = HEX_INS_V6_VWHIST256; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s vwhist256 %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fff) == 0x1e002380) { + // 0001111000000000PP10001110000000 | vwhist256:sat + hi->instruction = HEX_INS_V6_VWHIST256_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s vwhist256:sat %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3fff) == 0x1e022280) { + // 00011110vv000010PP10001010000000 | vwhist256(Qv) + hi->instruction = HEX_INS_V6_VWHIST256Q; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + sprintf(hi->mnem, "%s vwhist256(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff3f3fff) == 0x1e022380) { + // 00011110vv000010PP10001110000000 | vwhist256(Qv):sat + hi->instruction = HEX_INS_V6_VWHIST256Q_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + sprintf(hi->mnem, "%s vwhist256(%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2000e0) { + // 00011100001vvvvvPP0uuuuu111ddddd | Vd = vxor(Vu,Vv) + hi->instruction = HEX_INS_V6_VXOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + sprintf(hi->mnem, "%s %s = vxor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020020) { + // 0001111000000010PP0uuuuu001ddddd | Vdd.uh = vzxt(Vu.ub) + hi->instruction = HEX_INS_V6_VZB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.uh = vzxt(%s.ub) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020040) { + // 0001111000000010PP0uuuuu010ddddd | Vdd.uw = vzxt(Vu.uh) + hi->instruction = HEX_INS_V6_VZH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + sprintf(hi->mnem, "%s %s.uw = vzxt(%s.uh) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x19a00120) { + // 00011001101tttttPP000001001ddddd | Vd = zextract(Rt) + hi->instruction = HEX_INS_V6_ZEXTRACT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + sprintf(hi->mnem, "%s %s = zextract(%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x2: + if ((hi_u32 & 0xffc82001) == 0x20400000) { + // 0010000001ii0sssPP0tttttiiiiiii0 | if (!cmp.eq(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.eq(%s.new,%s)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x20402000) { + // 0010000001ii0sssPP1tttttiiiiiii0 | if (!cmp.eq(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.eq(%s.new,%s)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x20000000) { + // 0010000000ii0sssPP0tttttiiiiiii0 | if (cmp.eq(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.eq(%s.new,%s)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x20002000) { + // 0010000000ii0sssPP1tttttiiiiiii0 | if (cmp.eq(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.eq(%s.new,%s)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x24400000) { + // 0010010001ii0sssPP0IIIIIiiiiiii0 | if (!cmp.eq(Ns.new,#II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.eq(%s.new,#0x%x)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x24402000) { + // 0010010001ii0sssPP1IIIIIiiiiiii0 | if (!cmp.eq(Ns.new,#II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.eq(%s.new,#0x%x)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x24000000) { + // 0010010000ii0sssPP0IIIIIiiiiiii0 | if (cmp.eq(Ns.new,#II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.eq(%s.new,#0x%x)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x24002000) { + // 0010010000ii0sssPP1IIIIIiiiiiii0 | if (cmp.eq(Ns.new,#II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.eq(%s.new,#0x%x)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x26400000) { + // 0010011001ii0sssPP000000iiiiiii0 | if (!cmp.eq(Ns.new,#n1)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.eq(%s.new,#-1)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x26402000) { + // 0010011001ii0sssPP100000iiiiiii0 | if (!cmp.eq(Ns.new,#n1)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.eq(%s.new,#-1)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x26000000) { + // 0010011000ii0sssPP000000iiiiiii0 | if (cmp.eq(Ns.new,#n1)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.eq(%s.new,#-1)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x26002000) { + // 0010011000ii0sssPP100000iiiiiii0 | if (cmp.eq(Ns.new,#n1)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.eq(%s.new,#-1)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x20c00000) { + // 0010000011ii0sssPP0tttttiiiiiii0 | if (!cmp.gt(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gt(%s.new,%s)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x20c02000) { + // 0010000011ii0sssPP1tttttiiiiiii0 | if (!cmp.gt(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gt(%s.new,%s)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x20800000) { + // 0010000010ii0sssPP0tttttiiiiiii0 | if (cmp.gt(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gt(%s.new,%s)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x20802000) { + // 0010000010ii0sssPP1tttttiiiiiii0 | if (cmp.gt(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gt(%s.new,%s)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x24c00000) { + // 0010010011ii0sssPP0IIIIIiiiiiii0 | if (!cmp.gt(Ns.new,#II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gt(%s.new,#0x%x)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x24c02000) { + // 0010010011ii0sssPP1IIIIIiiiiiii0 | if (!cmp.gt(Ns.new,#II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gt(%s.new,#0x%x)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x24800000) { + // 0010010010ii0sssPP0IIIIIiiiiiii0 | if (cmp.gt(Ns.new,#II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gt(%s.new,#0x%x)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x24802000) { + // 0010010010ii0sssPP1IIIIIiiiiiii0 | if (cmp.gt(Ns.new,#II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gt(%s.new,#0x%x)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x26c00000) { + // 0010011011ii0sssPP000000iiiiiii0 | if (!cmp.gt(Ns.new,#n1)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gt(%s.new,#-1)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x26c02000) { + // 0010011011ii0sssPP100000iiiiiii0 | if (!cmp.gt(Ns.new,#n1)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gt(%s.new,#-1)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x26800000) { + // 0010011010ii0sssPP000000iiiiiii0 | if (cmp.gt(Ns.new,#n1)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gt(%s.new,#-1)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x26802000) { + // 0010011010ii0sssPP100000iiiiiii0 | if (cmp.gt(Ns.new,#n1)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gt(%s.new,#-1)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x21400000) { + // 0010000101ii0sssPP0tttttiiiiiii0 | if (!cmp.gtu(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gtu(%s.new,%s)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x21402000) { + // 0010000101ii0sssPP1tttttiiiiiii0 | if (!cmp.gtu(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gtu(%s.new,%s)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x21000000) { + // 0010000100ii0sssPP0tttttiiiiiii0 | if (cmp.gtu(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gtu(%s.new,%s)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x21002000) { + // 0010000100ii0sssPP1tttttiiiiiii0 | if (cmp.gtu(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gtu(%s.new,%s)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x25400000) { + // 0010010101ii0sssPP0IIIIIiiiiiii0 | if (!cmp.gtu(Ns.new,#II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gtu(%s.new,#0x%x)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x25402000) { + // 0010010101ii0sssPP1IIIIIiiiiiii0 | if (!cmp.gtu(Ns.new,#II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gtu(%s.new,#0x%x)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x25000000) { + // 0010010100ii0sssPP0IIIIIiiiiiii0 | if (cmp.gtu(Ns.new,#II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gtu(%s.new,#0x%x)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x25002000) { + // 0010010100ii0sssPP1IIIIIiiiiiii0 | if (cmp.gtu(Ns.new,#II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gtu(%s.new,#0x%x)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x21c00000) { + // 0010000111ii0sssPP0tttttiiiiiii0 | if (!cmp.gt(Rt,Ns.new)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPLT_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gt(%s,%s.new)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x21c02000) { + // 0010000111ii0sssPP1tttttiiiiiii0 | if (!cmp.gt(Rt,Ns.new)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPLT_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gt(%s,%s.new)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x21800000) { + // 0010000110ii0sssPP0tttttiiiiiii0 | if (cmp.gt(Rt,Ns.new)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPLT_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gt(%s,%s.new)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x21802000) { + // 0010000110ii0sssPP1tttttiiiiiii0 | if (cmp.gt(Rt,Ns.new)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPLT_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gt(%s,%s.new)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x22400000) { + // 0010001001ii0sssPP0tttttiiiiiii0 | if (!cmp.gtu(Rt,Ns.new)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPLTU_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gtu(%s,%s.new)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x22402000) { + // 0010001001ii0sssPP1tttttiiiiiii0 | if (!cmp.gtu(Rt,Ns.new)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPLTU_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!cmp.gtu(%s,%s.new)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x22000000) { + // 0010001000ii0sssPP0tttttiiiiiii0 | if (cmp.gtu(Rt,Ns.new)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPLTU_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gtu(%s,%s.new)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc82001) == 0x22002000) { + // 0010001000ii0sssPP1tttttiiiiiii0 | if (cmp.gtu(Rt,Ns.new)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPLTU_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (cmp.gtu(%s,%s.new)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), addr + (st32)hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x25c00000) { + // 0010010111ii0sssPP000000iiiiiii0 | if (!tstbit(Ns.new,#0)) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_F_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (!tstbit(%s.new,#0)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x25c02000) { + // 0010010111ii0sssPP100000iiiiiii0 | if (!tstbit(Ns.new,#0)) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_F_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (!tstbit(%s.new,#0)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x25800000) { + // 0010010110ii0sssPP000000iiiiiii0 | if (tstbit(Ns.new,#0)) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_T_JUMPNV_NT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (tstbit(%s.new,#0)) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc83f01) == 0x25802000) { + // 0010010110ii0sssPP100000iiiiiii0 | if (tstbit(Ns.new,#0)) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_T_JUMPNV_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (tstbit(%s.new,#0)) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x280000e0) { + // 00101000000tttttPPi00iii111ddddd | Vd = vmemu(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32UB_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vmemu(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x290000e0) { + // 00101001000xxxxxPP000iii111ddddd | Vd = vmemu(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32UB_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vmemu(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b0000e0) { + // 00101011000xxxxxPPu00000111ddddd | Vd = vmemu(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32UB_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = vmemu(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x28000000) { + // 00101000000tttttPPi00iii000ddddd | Vd = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32B_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x28000020) { + // 00101000000tttttPPi00iii001ddddd | Vd.cur = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s.cur = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x288000a0) { + // 00101000100tttttPPivviii101ddddd | if (!Pv) Vd.cur = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s.cur = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x298000a0) { + // 00101001100xxxxxPP0vviii101ddddd | if (!Pv) Vd.cur = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s.cur = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2b8000a0) { + // 00101011100xxxxxPPuvv000101ddddd | if (!Pv) Vd.cur = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_CUR_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (!%s) %s.cur = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x29000020) { + // 00101001000xxxxxPP000iii001ddddd | Vd.cur = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s.cur = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b000020) { + // 00101011000xxxxxPPu00000001ddddd | Vd.cur = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_CUR_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s.cur = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28800080) { + // 00101000100tttttPPivviii100ddddd | if (Pv) Vd.cur = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s.cur = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29800080) { + // 00101001100xxxxxPP0vviii100ddddd | if (Pv) Vd.cur = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s.cur = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800080) { + // 00101011100xxxxxPPuvv000100ddddd | if (Pv) Vd.cur = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_CUR_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (%s) %s.cur = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28800060) { + // 00101000100tttttPPivviii011ddddd | if (!Pv) Vd = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32B_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29800060) { + // 00101001100xxxxxPP0vviii011ddddd | if (!Pv) Vd = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32B_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800060) { + // 00101011100xxxxxPPuvv000011ddddd | if (!Pv) Vd = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (!%s) %s = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x28400000) { + // 00101000010tttttPPi00iii000ddddd | Vd = vmem(Rt+#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vmem(%s+%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x28400020) { + // 00101000010tttttPPi00iii001ddddd | Vd.cur = vmem(Rt+#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s.cur = vmem(%s+%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28c000a0) { + // 00101000110tttttPPivviii101ddddd | if (!Pv) Vd.cur = vmem(Rt+#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s.cur = vmem(%s+%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29c000a0) { + // 00101001110xxxxxPP0vviii101ddddd | if (!Pv) Vd.cur = vmem(Rx++#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s.cur = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc000a0) { + // 00101011110xxxxxPPuvv000101ddddd | if (!Pv) Vd.cur = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (!%s) %s.cur = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x29400020) { + // 00101001010xxxxxPP000iii001ddddd | Vd.cur = vmem(Rx++#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s.cur = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b400020) { + // 00101011010xxxxxPPu00000001ddddd | Vd.cur = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s.cur = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00080) { + // 00101000110tttttPPivviii100ddddd | if (Pv) Vd.cur = vmem(Rt+#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s.cur = vmem(%s+%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00080) { + // 00101001110xxxxxPP0vviii100ddddd | if (Pv) Vd.cur = vmem(Rx++#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s.cur = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00080) { + // 00101011110xxxxxPPuvv000100ddddd | if (Pv) Vd.cur = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (%s) %s.cur = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00060) { + // 00101000110tttttPPivviii011ddddd | if (!Pv) Vd = vmem(Rt+#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = vmem(%s+%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00060) { + // 00101001110xxxxxPP0vviii011ddddd | if (!Pv) Vd = vmem(Rx++#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00060) { + // 00101011110xxxxxPPuvv000011ddddd | if (!Pv) Vd = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (!%s) %s = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x29400000) { + // 00101001010xxxxxPP000iii000ddddd | Vd = vmem(Rx++#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b400000) { + // 00101011010xxxxxPPu00000000ddddd | Vd = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00040) { + // 00101000110tttttPPivviii010ddddd | if (Pv) Vd = vmem(Rt+#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = vmem(%s+%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00040) { + // 00101001110xxxxxPP0vviii010ddddd | if (Pv) Vd = vmem(Rx++#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00040) { + // 00101011110xxxxxPPuvv000010ddddd | if (Pv) Vd = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (%s) %s = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x28400040) { + // 00101000010tttttPPi00iii010ddddd | Vd.tmp = vmem(Rt+#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s.tmp = vmem(%s+%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28c000e0) { + // 00101000110tttttPPivviii111ddddd | if (!Pv) Vd.tmp = vmem(Rt+#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s.tmp = vmem(%s+%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29c000e0) { + // 00101001110xxxxxPP0vviii111ddddd | if (!Pv) Vd.tmp = vmem(Rx++#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s.tmp = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc000e0) { + // 00101011110xxxxxPPuvv000111ddddd | if (!Pv) Vd.tmp = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (!%s) %s.tmp = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x29400040) { + // 00101001010xxxxxPP000iii010ddddd | Vd.tmp = vmem(Rx++#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s.tmp = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b400040) { + // 00101011010xxxxxPPu00000010ddddd | Vd.tmp = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s.tmp = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28c000c0) { + // 00101000110tttttPPivviii110ddddd | if (Pv) Vd.tmp = vmem(Rt+#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s.tmp = vmem(%s+%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29c000c0) { + // 00101001110xxxxxPP0vviii110ddddd | if (Pv) Vd.tmp = vmem(Rx++#Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s.tmp = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc000c0) { + // 00101011110xxxxxPPuvv000110ddddd | if (Pv) Vd.tmp = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (%s) %s.tmp = vmem(%s++%s):nt %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x29000000) { + // 00101001000xxxxxPP000iii000ddddd | Vd = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32B_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b000000) { + // 00101011000xxxxxPPu00000000ddddd | Vd = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28800040) { + // 00101000100tttttPPivviii010ddddd | if (Pv) Vd = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32B_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29800040) { + // 00101001100xxxxxPP0vviii010ddddd | if (Pv) Vd = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32B_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800040) { + // 00101011100xxxxxPPuvv000010ddddd | if (Pv) Vd = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (%s) %s = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x28000040) { + // 00101000000tttttPPi00iii010ddddd | Vd.tmp = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s.tmp = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x288000e0) { + // 00101000100tttttPPivviii111ddddd | if (!Pv) Vd.tmp = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s.tmp = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x298000e0) { + // 00101001100xxxxxPP0vviii111ddddd | if (!Pv) Vd.tmp = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s.tmp = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2b8000e0) { + // 00101011100xxxxxPPuvv000111ddddd | if (!Pv) Vd.tmp = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_TMP_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (!%s) %s.tmp = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x29000040) { + // 00101001000xxxxxPP000iii010ddddd | Vd.tmp = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s.tmp = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b000040) { + // 00101011000xxxxxPPu00000010ddddd | Vd.tmp = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_TMP_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s.tmp = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x288000c0) { + // 00101000100tttttPPivviii110ddddd | if (Pv) Vd.tmp = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s.tmp = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x298000c0) { + // 00101001100xxxxxPP0vviii110ddddd | if (Pv) Vd.tmp = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s.tmp = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2b8000c0) { + // 00101011100xxxxxPPuvv000110ddddd | if (Pv) Vd.tmp = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_TMP_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (%s) %s.tmp = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x282000e0) { + // 00101000001tttttPPi00iii111sssss | vmemu(Rt+#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s vmemu(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28a000e0) { + // 00101000101tttttPPivviii111sssss | if (!Pv) vmemu(Rt+#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmemu(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29a000e0) { + // 00101001101xxxxxPP0vviii111sssss | if (!Pv) vmemu(Rx++#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmemu(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2ba000e0) { + // 00101011101xxxxxPPuvv000111sssss | if (!Pv) vmemu(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32UB_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmemu(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x292000e0) { + // 00101001001xxxxxPP000iii111sssss | vmemu(Rx++#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s vmemu(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b2000e0) { + // 00101011001xxxxxPPu00000111sssss | vmemu(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s vmemu(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28a000c0) { + // 00101000101tttttPPivviii110sssss | if (Pv) vmemu(Rt+#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmemu(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29a000c0) { + // 00101001101xxxxxPP0vviii110sssss | if (Pv) vmemu(Rx++#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmemu(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2ba000c0) { + // 00101011101xxxxxPPuvv000110sssss | if (Pv) vmemu(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmemu(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x28200000) { + // 00101000001tttttPPi00iii000sssss | vmem(Rt+#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s vmem(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018f8) == 0x28200020) { + // 00101000001tttttPPi00iii00100sss | vmem(Rt+#Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s vmem(%s+%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000f8) == 0x28a00068) { + // 00101000101tttttPPivviii01101sss | if (!Pv) vmem(Rt+#Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (!%s) vmem(%s+%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020f8) == 0x29a00068) { + // 00101001101xxxxxPP0vviii01101sss | if (!Pv) vmem(Rx++#Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007f8) == 0x2ba00068) { + // 00101011101xxxxxPPuvv00001101sss | if (!Pv) vmem(Rx++Mu) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038f8) == 0x29200020) { + // 00101001001xxxxxPP000iii00100sss | vmem(Rx++#Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s vmem(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01ff8) == 0x2b200020) { + // 00101011001xxxxxPPu0000000100sss | vmem(Rx++Mu) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s vmem(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000f8) == 0x28a00040) { + // 00101000101tttttPPivviii01000sss | if (Pv) vmem(Rt+#Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (%s) vmem(%s+%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020f8) == 0x29a00040) { + // 00101001101xxxxxPP0vviii01000sss | if (Pv) vmem(Rx++#Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007f8) == 0x2ba00040) { + // 00101011101xxxxxPPuvv00001000sss | if (Pv) vmem(Rx++Mu) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28a00020) { + // 00101000101tttttPPivviii001sssss | if (!Pv) vmem(Rt+#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29a00020) { + // 00101001101xxxxxPP0vviii001sssss | if (!Pv) vmem(Rx++#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2ba00020) { + // 00101011101xxxxxPPuvv000001sssss | if (!Pv) vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28800020) { + // 00101000100tttttPPivviii001sssss | if (!Qv) vmem(Rt+#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_NQPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29800020) { + // 00101001100xxxxxPP0vviii001sssss | if (!Qv) vmem(Rx++#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_NQPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800020) { + // 00101011100xxxxxPPuvv000001sssss | if (!Qv) vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_NQPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018e0) == 0x28600000) { + // 00101000011tttttPPi00iii000sssss | vmem(Rt+#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s vmem(%s+%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018f8) == 0x28600020) { + // 00101000011tttttPPi00iii00100sss | vmem(Rt+#Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s vmem(%s+%s):nt = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000f8) == 0x28e00078) { + // 00101000111tttttPPivviii01111sss | if (!Pv) vmem(Rt+#Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (!%s) vmem(%s+%s):nt = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020f8) == 0x29e00078) { + // 00101001111xxxxxPP0vviii01111sss | if (!Pv) vmem(Rx++#Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s):nt = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007f8) == 0x2be00078) { + // 00101011111xxxxxPPuvv00001111sss | if (!Pv) vmem(Rx++Mu):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s):nt = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038f8) == 0x29600020) { + // 00101001011xxxxxPP000iii00100sss | vmem(Rx++#Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s vmem(%s++%s):nt = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01ff8) == 0x2b600020) { + // 00101011011xxxxxPPu0000000100sss | vmem(Rx++Mu):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s vmem(%s++%s):nt = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000f8) == 0x28e00050) { + // 00101000111tttttPPivviii01010sss | if (Pv) vmem(Rt+#Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (%s) vmem(%s+%s):nt = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020f8) == 0x29e00050) { + // 00101001111xxxxxPP0vviii01010sss | if (Pv) vmem(Rx++#Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s):nt = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007f8) == 0x2be00050) { + // 00101011111xxxxxPPuvv00001010sss | if (Pv) vmem(Rx++Mu):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s):nt = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28e00020) { + // 00101000111tttttPPivviii001sssss | if (!Pv) vmem(Rt+#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s+%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29e00020) { + // 00101001111xxxxxPP0vviii001sssss | if (!Pv) vmem(Rx++#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2be00020) { + // 00101011111xxxxxPPuvv000001sssss | if (!Pv) vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00020) { + // 00101000110tttttPPivviii001sssss | if (!Qv) vmem(Rt+#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NQPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s+%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00020) { + // 00101001110xxxxxPP0vviii001sssss | if (!Qv) vmem(Rx++#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NQPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00020) { + // 00101011110xxxxxPPuvv000001sssss | if (!Qv) vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NQPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (!%s) vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x29600000) { + // 00101001011xxxxxPP000iii000sssss | vmem(Rx++#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b600000) { + // 00101011011xxxxxPPu00000000sssss | vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28e00000) { + // 00101000111tttttPPivviii000sssss | if (Pv) vmem(Rt+#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s+%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29e00000) { + // 00101001111xxxxxPP0vviii000sssss | if (Pv) vmem(Rx++#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2be00000) { + // 00101011111xxxxxPPuvv000000sssss | if (Pv) vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00000) { + // 00101000110tttttPPivviii000sssss | if (Qv) vmem(Rt+#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_QPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s+%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00000) { + // 00101001110xxxxxPP0vviii000sssss | if (Qv) vmem(Rx++#Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_QPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00000) { + // 00101011110xxxxxPPuvv000000sssss | if (Qv) vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_QPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s):nt = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x29200000) { + // 00101001001xxxxxPP000iii000sssss | vmem(Rx++#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b200000) { + // 00101011001xxxxxPPu00000000sssss | vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28a00000) { + // 00101000101tttttPPivviii000sssss | if (Pv) vmem(Rt+#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29a00000) { + // 00101001101xxxxxPP0vviii000sssss | if (Pv) vmem(Rx++#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2ba00000) { + // 00101011101xxxxxPPuvv000000sssss | if (Pv) vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x28800000) { + // 00101000100tttttPPivviii000sssss | if (Qv) vmem(Rt+#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_QPRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x29800000) { + // 00101001100xxxxxPP0vviii000sssss | if (Qv) vmem(Rx++#Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_QPRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), signed_imm, hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800000) { + // 00101011100xxxxxPPuvv000000sssss | if (Qv) vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_QPRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + sprintf(hi->mnem, "%s if (%s) vmem(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0x28200028) { + // 00101000001tttttPPi00iii00101000 | vmem(Rt+#Ii):scatter_release + hi->instruction = HEX_INS_V6_VS32B_SRLS_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + sprintf(hi->mnem, "%s vmem(%s+%s):scatter_release %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038ff) == 0x29200028) { + // 00101001001xxxxxPP000iii00101000 | vmem(Rx++#Ii):scatter_release + hi->instruction = HEX_INS_V6_VS32B_SRLS_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + sprintf(hi->mnem, "%s vmem(%s++%s):scatter_release %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fff) == 0x2b200028) { + // 00101011001xxxxxPPu0000000101000 | vmem(Rx++Mu):scatter_release + hi->instruction = HEX_INS_V6_VS32B_SRLS_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s vmem(%s++%s):scatter_release %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2f000100) { + // 00101111000tttttPPu00001000vvvvv | vtmp.h = vgather(Rt,Mu,Vv.h).h + hi->instruction = HEX_INS_V6_VGATHERMH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vv32 + sprintf(hi->mnem, "%s VTMP.h = vgather(%s,%s,%s.h).h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01f80) == 0x2f000500) { + // 00101111000tttttPPu001010ssvvvvv | if (Qs) vtmp.h = vgather(Rt,Mu,Vv.h).h + hi->instruction = HEX_INS_V6_VGATHERMHQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vv32 + sprintf(hi->mnem, "%s if (%s) VTMP.h = vgather(%s,%s,%s.h).h %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2f000200) { + // 00101111000tttttPPu00010000vvvvv | vtmp.h = vgather(Rt,Mu,Vvv.w).h + hi->instruction = HEX_INS_V6_VGATHERMHW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vvv32 + sprintf(hi->mnem, "%s VTMP.h = vgather(%s,%s,%s.w).h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01f80) == 0x2f000600) { + // 00101111000tttttPPu001100ssvvvvv | if (Qs) vtmp.h = vgather(Rt,Mu,Vvv.w).h + hi->instruction = HEX_INS_V6_VGATHERMHWQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vvv32 + sprintf(hi->mnem, "%s if (%s) VTMP.h = vgather(%s,%s,%s.w).h %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_wr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x2f000000) { + // 00101111000tttttPPu00000000vvvvv | vtmp.w = vgather(Rt,Mu,Vv.w).w + hi->instruction = HEX_INS_V6_VGATHERMW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vv32 + sprintf(hi->mnem, "%s VTMP.w = vgather(%s,%s,%s.w).w %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01f80) == 0x2f000400) { + // 00101111000tttttPPu001000ssvvvvv | if (Qs) vtmp.w = vgather(Rt,Mu,Vv.w).w + hi->instruction = HEX_INS_V6_VGATHERMWQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vv32 + sprintf(hi->mnem, "%s if (%s) VTMP.w = vgather(%s,%s,%s.w).w %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x2f200020) { + // 00101111001tttttPPuvvvvv001wwwww | vscatter(Rt,Mu,Vv.h).h = Vw + hi->instruction = HEX_INS_V6_VSCATTERMH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + sprintf(hi->mnem, "%s vscatter(%s,%s,%s.h).h = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x2f2000a0) { + // 00101111001tttttPPuvvvvv101wwwww | vscatter(Rt,Mu,Vv.h).h += Vw + hi->instruction = HEX_INS_V6_VSCATTERMH_ADD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + sprintf(hi->mnem, "%s vscatter(%s,%s,%s.h).h += %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00080) == 0x2f800080) { + // 00101111100tttttPPuvvvvv1sswwwww | if (Qs) vscatter(Rt,Mu,Vv.h).h = Vw + hi->instruction = HEX_INS_V6_VSCATTERMHQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + sprintf(hi->mnem, "%s if (%s) vscatter(%s,%s,%s.h).h = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hex_get_hvx_vr(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x2f200040) { + // 00101111001tttttPPuvvvvv010wwwww | vscatter(Rt,Mu,Vvv.w).h = Vw + hi->instruction = HEX_INS_V6_VSCATTERMHW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vvv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + sprintf(hi->mnem, "%s vscatter(%s,%s,%s.w).h = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x2f2000c0) { + // 00101111001tttttPPuvvvvv110wwwww | vscatter(Rt,Mu,Vvv.w).h += Vw + hi->instruction = HEX_INS_V6_VSCATTERMHW_ADD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vvv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + sprintf(hi->mnem, "%s vscatter(%s,%s,%s.w).h += %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00080) == 0x2fa00000) { + // 00101111101tttttPPuvvvvv0sswwwww | if (Qs) vscatter(Rt,Mu,Vvv.w).h = Vw + hi->instruction = HEX_INS_V6_VSCATTERMHWQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Vvv32 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + sprintf(hi->mnem, "%s if (%s) vscatter(%s,%s,%s.w).h = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_wr(hi->ops[3].op.reg), hex_get_hvx_vr(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x2f200000) { + // 00101111001tttttPPuvvvvv000wwwww | vscatter(Rt,Mu,Vv.w).w = Vw + hi->instruction = HEX_INS_V6_VSCATTERMW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + sprintf(hi->mnem, "%s vscatter(%s,%s,%s.w).w = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x2f200080) { + // 00101111001tttttPPuvvvvv100wwwww | vscatter(Rt,Mu,Vv.w).w += Vw + hi->instruction = HEX_INS_V6_VSCATTERMW_ADD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + sprintf(hi->mnem, "%s vscatter(%s,%s,%s.w).w += %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00080) == 0x2f800000) { + // 00101111100tttttPPuvvvvv0sswwwww | if (Qs) vscatter(Rt,Mu,Vv.w).w = Vw + hi->instruction = HEX_INS_V6_VSCATTERMWQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + sprintf(hi->mnem, "%s if (%s) vscatter(%s,%s,%s.w).w = %s %s", hi->pkt_info.syntax_prefix, hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hex_get_hvx_vr(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0x2c000000) { + // 00101100000tttttPPi00iii00000000 | z = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_ZLD_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + sprintf(hi->mnem, "%s z = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038ff) == 0x2d000000) { + // 00101101000xxxxxPP000iii00000000 | z = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_ZLD_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + sprintf(hi->mnem, "%s z = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fff) == 0x2d000001) { + // 00101101000xxxxxPPu0000000000001 | z = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_ZLD_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s z = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0x2c800000) { + // 00101100100tttttPPivviii00000000 | if (Pv) z = vmem(Rt+#Ii) + hi->instruction = HEX_INS_V6_ZLD_PRED_AI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s if (%s) z = vmem(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020ff) == 0x2d800000) { + // 00101101100xxxxxPP0vviii00000000 | if (Pv) z = vmem(Rx++#Ii) + hi->instruction = HEX_INS_V6_ZLD_PRED_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 2); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s if (%s) z = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe007ff) == 0x2d800001) { + // 00101101100xxxxxPPuvv00000000001 | if (Pv) z = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_ZLD_PRED_PPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s if (%s) z = vmem(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x3: + if ((hi_u32 & 0xffe02060) == 0x3e000000) { + // 00111110000sssssPP0iiiiii00ttttt | memb(Rs+#Ii) += Rt + hi->instruction = HEX_INS_L4_ADD_MEMOPB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memb(%s+##0x%x) += %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e200000) { + // 00111110001sssssPP0iiiiii00ttttt | memh(Rs+#Ii) += Rt + hi->instruction = HEX_INS_L4_ADD_MEMOPH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memh(%s+##0x%x) += %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e400000) { + // 00111110010sssssPP0iiiiii00ttttt | memw(Rs+#Ii) += Rt + hi->instruction = HEX_INS_L4_ADD_MEMOPW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memw(%s+##0x%x) += %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e000040) { + // 00111110000sssssPP0iiiiii10ttttt | memb(Rs+#Ii) &= Rt + hi->instruction = HEX_INS_L4_AND_MEMOPB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memb(%s+##0x%x) &= %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e200040) { + // 00111110001sssssPP0iiiiii10ttttt | memh(Rs+#Ii) &= Rt + hi->instruction = HEX_INS_L4_AND_MEMOPH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memh(%s+##0x%x) &= %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e400040) { + // 00111110010sssssPP0iiiiii10ttttt | memw(Rs+#Ii) &= Rt + hi->instruction = HEX_INS_L4_AND_MEMOPW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memw(%s+##0x%x) &= %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f000000) { + // 00111111000sssssPP0iiiiii00IIIII | memb(Rs+#Ii) += #II + hi->instruction = HEX_INS_L4_IADD_MEMOPB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memb(%s+##0x%x) += #0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f200000) { + // 00111111001sssssPP0iiiiii00IIIII | memh(Rs+#Ii) += #II + hi->instruction = HEX_INS_L4_IADD_MEMOPH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memh(%s+##0x%x) += #0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f400000) { + // 00111111010sssssPP0iiiiii00IIIII | memw(Rs+#Ii) += #II + hi->instruction = HEX_INS_L4_IADD_MEMOPW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memw(%s+##0x%x) += #0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f000040) { + // 00111111000sssssPP0iiiiii10IIIII | memb(Rs+#Ii) = clrbit(#II) + hi->instruction = HEX_INS_L4_IAND_MEMOPB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memb(%s+##0x%x) = clrbit(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f200040) { + // 00111111001sssssPP0iiiiii10IIIII | memh(Rs+#Ii) = clrbit(#II) + hi->instruction = HEX_INS_L4_IAND_MEMOPH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memh(%s+##0x%x) = clrbit(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f400040) { + // 00111111010sssssPP0iiiiii10IIIII | memw(Rs+#Ii) = clrbit(#II) + hi->instruction = HEX_INS_L4_IAND_MEMOPW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memw(%s+##0x%x) = clrbit(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f000060) { + // 00111111000sssssPP0iiiiii11IIIII | memb(Rs+#Ii) = setbit(#II) + hi->instruction = HEX_INS_L4_IOR_MEMOPB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memb(%s+##0x%x) = setbit(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f200060) { + // 00111111001sssssPP0iiiiii11IIIII | memh(Rs+#Ii) = setbit(#II) + hi->instruction = HEX_INS_L4_IOR_MEMOPH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memh(%s+##0x%x) = setbit(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f400060) { + // 00111111010sssssPP0iiiiii11IIIII | memw(Rs+#Ii) = setbit(#II) + hi->instruction = HEX_INS_L4_IOR_MEMOPW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memw(%s+##0x%x) = setbit(#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f000020) { + // 00111111000sssssPP0iiiiii01IIIII | memb(Rs+#Ii) -= #II + hi->instruction = HEX_INS_L4_ISUB_MEMOPB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memb(%s+##0x%x) -= #0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f200020) { + // 00111111001sssssPP0iiiiii01IIIII | memh(Rs+#Ii) -= #II + hi->instruction = HEX_INS_L4_ISUB_MEMOPH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memh(%s+##0x%x) -= #0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3f400020) { + // 00111111010sssssPP0iiiiii01IIIII | memw(Rs+#Ii) -= #II + hi->instruction = HEX_INS_L4_ISUB_MEMOPW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + sprintf(hi->mnem, "%s memw(%s+##0x%x) -= #0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3a000000) { + // 00111010000sssssPPittttti00ddddd | Rd = memb(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_LOADRB_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s %s = memb(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3ac00000) { + // 00111010110sssssPPittttti00ddddd | Rdd = memd(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_LOADRD_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s %s = memd(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3a400000) { + // 00111010010sssssPPittttti00ddddd | Rd = memh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_LOADRH_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s %s = memh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3a800000) { + // 00111010100sssssPPittttti00ddddd | Rd = memw(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_LOADRI_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s %s = memw(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3a200000) { + // 00111010001sssssPPittttti00ddddd | Rd = memub(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_LOADRUB_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s %s = memub(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3a600000) { + // 00111010011sssssPPittttti00ddddd | Rd = memuh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_LOADRUH_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s %s = memuh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e000060) { + // 00111110000sssssPP0iiiiii11ttttt | memb(Rs+#Ii) |= Rt + hi->instruction = HEX_INS_L4_OR_MEMOPB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memb(%s+##0x%x) |= %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e200060) { + // 00111110001sssssPP0iiiiii11ttttt | memh(Rs+#Ii) |= Rt + hi->instruction = HEX_INS_L4_OR_MEMOPH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memh(%s+##0x%x) |= %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e400060) { + // 00111110010sssssPP0iiiiii11ttttt | memw(Rs+#Ii) |= Rt + hi->instruction = HEX_INS_L4_OR_MEMOPW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memw(%s+##0x%x) |= %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x31000000) { + // 00110001000sssssPPitttttivvddddd | if (!Pv) Rd = memb(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRBF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s) %s = memb(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x33000000) { + // 00110011000sssssPPitttttivvddddd | if (!Pv.new) Rd = memb(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRBFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s.new) %s = memb(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x30000000) { + // 00110000000sssssPPitttttivvddddd | if (Pv) Rd = memb(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRBT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s) %s = memb(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x32000000) { + // 00110010000sssssPPitttttivvddddd | if (Pv.new) Rd = memb(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRBTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s.new) %s = memb(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x31c00000) { + // 00110001110sssssPPitttttivvddddd | if (!Pv) Rdd = memd(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRDF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s) %s = memd(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x33c00000) { + // 00110011110sssssPPitttttivvddddd | if (!Pv.new) Rdd = memd(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRDFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s.new) %s = memd(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x30c00000) { + // 00110000110sssssPPitttttivvddddd | if (Pv) Rdd = memd(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRDT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s) %s = memd(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x32c00000) { + // 00110010110sssssPPitttttivvddddd | if (Pv.new) Rdd = memd(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRDTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s.new) %s = memd(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x31400000) { + // 00110001010sssssPPitttttivvddddd | if (!Pv) Rd = memh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRHF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s) %s = memh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x33400000) { + // 00110011010sssssPPitttttivvddddd | if (!Pv.new) Rd = memh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRHFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s.new) %s = memh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x30400000) { + // 00110000010sssssPPitttttivvddddd | if (Pv) Rd = memh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRHT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s) %s = memh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x32400000) { + // 00110010010sssssPPitttttivvddddd | if (Pv.new) Rd = memh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRHTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s.new) %s = memh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x31800000) { + // 00110001100sssssPPitttttivvddddd | if (!Pv) Rd = memw(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRIF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s) %s = memw(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x33800000) { + // 00110011100sssssPPitttttivvddddd | if (!Pv.new) Rd = memw(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRIFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s.new) %s = memw(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x30800000) { + // 00110000100sssssPPitttttivvddddd | if (Pv) Rd = memw(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRIT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s) %s = memw(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x32800000) { + // 00110010100sssssPPitttttivvddddd | if (Pv.new) Rd = memw(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRITNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s.new) %s = memw(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x31200000) { + // 00110001001sssssPPitttttivvddddd | if (!Pv) Rd = memub(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRUBF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s) %s = memub(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x33200000) { + // 00110011001sssssPPitttttivvddddd | if (!Pv.new) Rd = memub(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRUBFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s.new) %s = memub(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x30200000) { + // 00110000001sssssPPitttttivvddddd | if (Pv) Rd = memub(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRUBT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s) %s = memub(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x32200000) { + // 00110010001sssssPPitttttivvddddd | if (Pv.new) Rd = memub(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRUBTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s.new) %s = memub(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x31600000) { + // 00110001011sssssPPitttttivvddddd | if (!Pv) Rd = memuh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRUHF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s) %s = memuh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x33600000) { + // 00110011011sssssPPitttttivvddddd | if (!Pv.new) Rd = memuh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRUHFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (!%s.new) %s = memuh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x30600000) { + // 00110000011sssssPPitttttivvddddd | if (Pv) Rd = memuh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRUHT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s) %s = memuh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x32600000) { + // 00110010011sssssPPitttttivvddddd | if (Pv.new) Rd = memuh(Rs+Rt<<#Ii) + hi->instruction = HEX_INS_L4_PLOADRUHTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + sprintf(hi->mnem, "%s if (%s.new) %s = memuh(%s+%s<<#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->ops[4].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e000020) { + // 00111110000sssssPP0iiiiii01ttttt | memb(Rs+#Ii) -= Rt + hi->instruction = HEX_INS_L4_SUB_MEMOPB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memb(%s+##0x%x) -= %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e200020) { + // 00111110001sssssPP0iiiiii01ttttt | memh(Rs+#Ii) -= Rt + hi->instruction = HEX_INS_L4_SUB_MEMOPH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memh(%s+##0x%x) -= %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02060) == 0x3e400020) { + // 00111110010sssssPP0iiiiii01ttttt | memw(Rs+#Ii) -= Rt + hi->instruction = HEX_INS_L4_SUB_MEMOPW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memw(%s+##0x%x) -= %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x35000000) { + // 00110101000sssssPPiuuuuuivvttttt | if (!Pv) memb(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memb(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x37000000) { + // 00110111000sssssPPiuuuuuivvttttt | if (!Pv.new) memb(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memb(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x35a00000) { + // 00110101101sssssPPiuuuuuivv00ttt | if (!Pv) memb(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memb(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x37a00000) { + // 00110111101sssssPPiuuuuuivv00ttt | if (!Pv.new) memb(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memb(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x34a00000) { + // 00110100101sssssPPiuuuuuivv00ttt | if (Pv) memb(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (%s) memb(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x36a00000) { + // 00110110101sssssPPiuuuuuivv00ttt | if (Pv.new) memb(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memb(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x34000000) { + // 00110100000sssssPPiuuuuuivvttttt | if (Pv) memb(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (%s) memb(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x36000000) { + // 00110110000sssssPPiuuuuuivvttttt | if (Pv.new) memb(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memb(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x35c00000) { + // 00110101110sssssPPiuuuuuivvttttt | if (!Pv) memd(Rs+Ru<<#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + sprintf(hi->mnem, "%s if (!%s) memd(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_double_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x37c00000) { + // 00110111110sssssPPiuuuuuivvttttt | if (!Pv.new) memd(Rs+Ru<<#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + sprintf(hi->mnem, "%s if (!%s.new) memd(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_double_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x34c00000) { + // 00110100110sssssPPiuuuuuivvttttt | if (Pv) memd(Rs+Ru<<#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + sprintf(hi->mnem, "%s if (%s) memd(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_double_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x36c00000) { + // 00110110110sssssPPiuuuuuivvttttt | if (Pv.new) memd(Rs+Ru<<#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + sprintf(hi->mnem, "%s if (%s.new) memd(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_double_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x35600000) { + // 00110101011sssssPPiuuuuuivvttttt | if (!Pv) memh(Rs+Ru<<#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memh(%s+%s<<#0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x37600000) { + // 00110111011sssssPPiuuuuuivvttttt | if (!Pv.new) memh(Rs+Ru<<#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memh(%s+%s<<#0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x34600000) { + // 00110100011sssssPPiuuuuuivvttttt | if (Pv) memh(Rs+Ru<<#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (%s) memh(%s+%s<<#0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x36600000) { + // 00110110011sssssPPiuuuuuivvttttt | if (Pv.new) memh(Rs+Ru<<#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memh(%s+%s<<#0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x35400000) { + // 00110101010sssssPPiuuuuuivvttttt | if (!Pv) memh(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memh(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x37400000) { + // 00110111010sssssPPiuuuuuivvttttt | if (!Pv.new) memh(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memh(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x35a00008) { + // 00110101101sssssPPiuuuuuivv01ttt | if (!Pv) memh(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memh(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x37a00008) { + // 00110111101sssssPPiuuuuuivv01ttt | if (!Pv.new) memh(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memh(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x34a00008) { + // 00110100101sssssPPiuuuuuivv01ttt | if (Pv) memh(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (%s) memh(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x36a00008) { + // 00110110101sssssPPiuuuuuivv01ttt | if (Pv.new) memh(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memh(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x34400000) { + // 00110100010sssssPPiuuuuuivvttttt | if (Pv) memh(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (%s) memh(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x36400000) { + // 00110110010sssssPPiuuuuuivvttttt | if (Pv.new) memh(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memh(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x35800000) { + // 00110101100sssssPPiuuuuuivvttttt | if (!Pv) memw(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memw(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x37800000) { + // 00110111100sssssPPiuuuuuivvttttt | if (!Pv.new) memw(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memw(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x35a00010) { + // 00110101101sssssPPiuuuuuivv10ttt | if (!Pv) memw(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memw(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x37a00010) { + // 00110111101sssssPPiuuuuuivv10ttt | if (!Pv.new) memw(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWFNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memw(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x34a00010) { + // 00110100101sssssPPiuuuuuivv10ttt | if (Pv) memw(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (%s) memw(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00018) == 0x36a00010) { + // 00110110101sssssPPiuuuuuivv10ttt | if (Pv.new) memw(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWTNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memw(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x34800000) { + // 00110100100sssssPPiuuuuuivvttttt | if (Pv) memw(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIT_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (%s) memw(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x36800000) { + // 00110110100sssssPPiuuuuuivvttttt | if (Pv.new) memw(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERITNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memw(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x3c000000) { + // 00111100000sssssPPIiiiiiiIIIIIII | memb(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 6) | (((hi_u32)&0x7f) >> 0)); // II + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x38800000) { + // 00111000100sssssPPIiiiiiivvIIIII | if (!Pv) memb(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRBF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x39800000) { + // 00111001100sssssPPIiiiiiivvIIIII | if (!Pv.new) memb(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRBFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x38000000) { + // 00111000000sssssPPIiiiiiivvIIIII | if (Pv) memb(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRBT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x39000000) { + // 00111001000sssssPPIiiiiiivvIIIII | if (Pv.new) memb(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRBTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) memb(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x3c200000) { + // 00111100001sssssPPIiiiiiiIIIIIII | memh(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 6) | (((hi_u32)&0x7f) >> 0)); // II + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x38a00000) { + // 00111000101sssssPPIiiiiiivvIIIII | if (!Pv) memh(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRHF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x39a00000) { + // 00111001101sssssPPIiiiiiivvIIIII | if (!Pv.new) memh(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRHFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x38200000) { + // 00111000001sssssPPIiiiiiivvIIIII | if (Pv) memh(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRHT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x39200000) { + // 00111001001sssssPPIiiiiiivvIIIII | if (Pv.new) memh(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRHTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) memh(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x3c400000) { + // 00111100010sssssPPIiiiiiiIIIIIII | memw(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 6) | (((hi_u32)&0x7f) >> 0)); // II + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x38c00000) { + // 00111000110sssssPPIiiiiiivvIIIII | if (!Pv) memw(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRIF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x39c00000) { + // 00111001110sssssPPIiiiiiivvIIIII | if (!Pv.new) memw(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRIFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x38400000) { + // 00111000010sssssPPIiiiiiivvIIIII | if (Pv) memw(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRIT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x39400000) { + // 00111001010sssssPPIiiiiiivvIIIII | if (Pv.new) memw(Rs+#Ii) = #II + hi->instruction = HEX_INS_S4_STOREIRITNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) memw(%s+#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3b000000) { + // 00111011000sssssPPiuuuuui00ttttt | memb(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_STORERB_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memb(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00078) == 0x3ba00000) { + // 00111011101sssssPPiuuuuui0000ttt | memb(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_STORERBNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s memb(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3bc00000) { + // 00111011110sssssPPiuuuuui00ttttt | memd(Rs+Ru<<#Ii) = Rtt + hi->instruction = HEX_INS_S4_STORERD_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + sprintf(hi->mnem, "%s memd(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3b600000) { + // 00111011011sssssPPiuuuuui00ttttt | memh(Rs+Ru<<#Ii) = Rt.h + hi->instruction = HEX_INS_S4_STORERF_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memh(%s+%s<<#0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3b400000) { + // 00111011010sssssPPiuuuuui00ttttt | memh(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_STORERH_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memh(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00078) == 0x3ba00008) { + // 00111011101sssssPPiuuuuui0001ttt | memh(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_STORERHNEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s memh(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00060) == 0x3b800000) { + // 00111011100sssssPPiuuuuui00ttttt | memw(Rs+Ru<<#Ii) = Rt + hi->instruction = HEX_INS_S4_STORERI_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + sprintf(hi->mnem, "%s memw(%s+%s<<#0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00078) == 0x3ba00010) { + // 00111011101sssssPPiuuuuui0010ttt | memw(Rs+Ru<<#Ii) = Nt.new + hi->instruction = HEX_INS_S4_STORERINEW_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + sprintf(hi->mnem, "%s memw(%s+%s<<#0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x4: + if ((hi_u32 & 0xf9e00000) == 0x49000000) { + // 01001ii1000iiiiiPPiiiiiiiiiddddd | Rd = memb(gp+#Ii) + hi->instruction = HEX_INS_L2_LOADRBGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + sprintf(hi->mnem, "%s %s = memb(GP+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49c00000) { + // 01001ii1110iiiiiPPiiiiiiiiiddddd | Rdd = memd(gp+#Ii) + hi->instruction = HEX_INS_L2_LOADRDGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(GP+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49400000) { + // 01001ii1010iiiiiPPiiiiiiiiiddddd | Rd = memh(gp+#Ii) + hi->instruction = HEX_INS_L2_LOADRHGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + sprintf(hi->mnem, "%s %s = memh(GP+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49800000) { + // 01001ii1100iiiiiPPiiiiiiiiiddddd | Rd = memw(gp+#Ii) + hi->instruction = HEX_INS_L2_LOADRIGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(GP+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49200000) { + // 01001ii1001iiiiiPPiiiiiiiiiddddd | Rd = memub(gp+#Ii) + hi->instruction = HEX_INS_L2_LOADRUBGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + sprintf(hi->mnem, "%s %s = memub(GP+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49600000) { + // 01001ii1011iiiiiPPiiiiiiiiiddddd | Rd = memuh(gp+#Ii) + hi->instruction = HEX_INS_L2_LOADRUHGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(GP+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x45000000) { + // 01000101000sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRBF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memb(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x47000000) { + // 01000111000sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRBFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memb(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x41000000) { + // 01000001000sssssPP0ttiiiiiiddddd | if (Pt) Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRBT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memb(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x43000000) { + // 01000011000sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRBTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memb(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x45c00000) { + // 01000101110sssssPP0ttiiiiiiddddd | if (!Pt) Rdd = memd(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRDF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memd(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x47c00000) { + // 01000111110sssssPP0ttiiiiiiddddd | if (!Pt.new) Rdd = memd(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRDFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memd(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x41c00000) { + // 01000001110sssssPP0ttiiiiiiddddd | if (Pt) Rdd = memd(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRDT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memd(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x43c00000) { + // 01000011110sssssPP0ttiiiiiiddddd | if (Pt.new) Rdd = memd(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRDTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memd(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x45400000) { + // 01000101010sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRHF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memh(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x47400000) { + // 01000111010sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRHFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memh(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x41400000) { + // 01000001010sssssPP0ttiiiiiiddddd | if (Pt) Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRHT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memh(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x43400000) { + // 01000011010sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRHTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memh(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x45800000) { + // 01000101100sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRIF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memw(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x47800000) { + // 01000111100sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRIFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memw(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x41800000) { + // 01000001100sssssPP0ttiiiiiiddddd | if (Pt) Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRIT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memw(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x43800000) { + // 01000011100sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRITNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memw(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x45200000) { + // 01000101001sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRUBF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memub(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x47200000) { + // 01000111001sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRUBFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memub(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x41200000) { + // 01000001001sssssPP0ttiiiiiiddddd | if (Pt) Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRUBT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memub(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x43200000) { + // 01000011001sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRUBTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memub(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x45600000) { + // 01000101011sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRUHF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memuh(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x47600000) { + // 01000111011sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRUHFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memuh(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x41600000) { + // 01000001011sssssPP0ttiiiiiiddddd | if (Pt) Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRUHT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memuh(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x43600000) { + // 01000011011sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_L2_PLOADRUHTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memuh(%s+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49000000) { + // 01001ii1000iiiiiPPiiiiiiiiiddddd | Rd = memb(#Ii) + hi->instruction = HEX_INS_PS_LOADRBABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + sprintf(hi->mnem, "%s %s = memb(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49c00000) { + // 01001ii1110iiiiiPPiiiiiiiiiddddd | Rdd = memd(#Ii) + hi->instruction = HEX_INS_PS_LOADRDABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s %s = memd(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49400000) { + // 01001ii1010iiiiiPPiiiiiiiiiddddd | Rd = memh(#Ii) + hi->instruction = HEX_INS_PS_LOADRHABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + sprintf(hi->mnem, "%s %s = memh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49800000) { + // 01001ii1100iiiiiPPiiiiiiiiiddddd | Rd = memw(#Ii) + hi->instruction = HEX_INS_PS_LOADRIABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + sprintf(hi->mnem, "%s %s = memw(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49200000) { + // 01001ii1001iiiiiPPiiiiiiiiiddddd | Rd = memub(#Ii) + hi->instruction = HEX_INS_PS_LOADRUBABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + sprintf(hi->mnem, "%s %s = memub(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x49600000) { + // 01001ii1011iiiiiPPiiiiiiiiiddddd | Rd = memuh(#Ii) + hi->instruction = HEX_INS_PS_LOADRUHABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + sprintf(hi->mnem, "%s %s = memuh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48000000) { + // 01001ii0000iiiiiPPitttttiiiiiiii | memb(#Ii) = Rt + hi->instruction = HEX_INS_PS_STORERBABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e01800) == 0x48a00000) { + // 01001ii0101iiiiiPPi00tttiiiiiiii | memb(#Ii) = Nt.new + hi->instruction = HEX_INS_PS_STORERBNEWABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48c00000) { + // 01001ii0110iiiiiPPitttttiiiiiiii | memd(#Ii) = Rtt + hi->instruction = HEX_INS_PS_STORERDABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48600000) { + // 01001ii0011iiiiiPPitttttiiiiiiii | memh(#Ii) = Rt.h + hi->instruction = HEX_INS_PS_STORERFABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48400000) { + // 01001ii0010iiiiiPPitttttiiiiiiii | memh(#Ii) = Rt + hi->instruction = HEX_INS_PS_STORERHABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e01800) == 0x48a00800) { + // 01001ii0101iiiiiPPi01tttiiiiiiii | memh(#Ii) = Nt.new + hi->instruction = HEX_INS_PS_STORERHNEWABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48800000) { + // 01001ii0100iiiiiPPitttttiiiiiiii | memw(#Ii) = Rt + hi->instruction = HEX_INS_PS_STORERIABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e01800) == 0x48a01000) { + // 01001ii0101iiiiiPPi10tttiiiiiiii | memw(#Ii) = Nt.new + hi->instruction = HEX_INS_PS_STORERINEWABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x44000000) { + // 01000100000sssssPPitttttiiiii0vv | if (!Pv) memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memb(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x44a00000) { + // 01000100101sssssPPi00tttiiiii0vv | if (!Pv) memb(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memb(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x40a00000) { + // 01000000101sssssPPi00tttiiiii0vv | if (Pv) memb(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s) memb(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x40000000) { + // 01000000000sssssPPitttttiiiii0vv | if (Pv) memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memb(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x44c00000) { + // 01000100110sssssPPitttttiiiii0vv | if (!Pv) memd(Rs+#Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (!%s) memd(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x40c00000) { + // 01000000110sssssPPitttttiiiii0vv | if (Pv) memd(Rs+#Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (%s) memd(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x44600000) { + // 01000100011sssssPPitttttiiiii0vv | if (!Pv) memh(Rs+#Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memh(%s+##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x40600000) { + // 01000000011sssssPPitttttiiiii0vv | if (Pv) memh(Rs+#Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memh(%s+##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x44400000) { + // 01000100010sssssPPitttttiiiii0vv | if (!Pv) memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memh(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x44a00800) { + // 01000100101sssssPPi01tttiiiii0vv | if (!Pv) memh(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memh(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x40a00800) { + // 01000000101sssssPPi01tttiiiii0vv | if (Pv) memh(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s) memh(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x40400000) { + // 01000000010sssssPPitttttiiiii0vv | if (Pv) memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memh(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x44800000) { + // 01000100100sssssPPitttttiiiii0vv | if (!Pv) memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memw(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x44a01000) { + // 01000100101sssssPPi10tttiiiii0vv | if (!Pv) memw(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memw(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x40a01000) { + // 01000000101sssssPPi10tttiiiii0vv | if (Pv) memw(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s) memw(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x40800000) { + // 01000000100sssssPPitttttiiiii0vv | if (Pv) memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIT_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memw(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48000000) { + // 01001ii0000iiiiiPPitttttiiiiiiii | memb(gp+#Ii) = Rt + hi->instruction = HEX_INS_S2_STORERBGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(GP+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e01800) == 0x48a00000) { + // 01001ii0101iiiiiPPi00tttiiiiiiii | memb(gp+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEWGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(GP+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48c00000) { + // 01001ii0110iiiiiPPitttttiiiiiiii | memd(gp+#Ii) = Rtt + hi->instruction = HEX_INS_S2_STORERDGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(GP+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48600000) { + // 01001ii0011iiiiiPPitttttiiiiiiii | memh(gp+#Ii) = Rt.h + hi->instruction = HEX_INS_S2_STORERFGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(GP+##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48400000) { + // 01001ii0010iiiiiPPitttttiiiiiiii | memh(gp+#Ii) = Rt + hi->instruction = HEX_INS_S2_STORERHGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(GP+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e01800) == 0x48a00800) { + // 01001ii0101iiiiiPPi01tttiiiiiiii | memh(gp+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEWGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(GP+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x48800000) { + // 01001ii0100iiiiiPPitttttiiiiiiii | memw(gp+#Ii) = Rt + hi->instruction = HEX_INS_S2_STORERIGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(GP+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e01800) == 0x48a01000) { + // 01001ii0101iiiiiPPi10tttiiiiiiii | memw(gp+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEWGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(GP+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x46000000) { + // 01000110000sssssPPitttttiiiii0vv | if (!Pv.new) memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memb(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x46a00000) { + // 01000110101sssssPPi00tttiiiii0vv | if (!Pv.new) memb(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memb(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x42a00000) { + // 01000010101sssssPPi00tttiiiii0vv | if (Pv.new) memb(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memb(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x42000000) { + // 01000010000sssssPPitttttiiiii0vv | if (Pv.new) memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memb(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x46c00000) { + // 01000110110sssssPPitttttiiiii0vv | if (!Pv.new) memd(Rs+#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (!%s.new) memd(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x42c00000) { + // 01000010110sssssPPitttttiiiii0vv | if (Pv.new) memd(Rs+#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (%s.new) memd(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x46600000) { + // 01000110011sssssPPitttttiiiii0vv | if (!Pv.new) memh(Rs+#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memh(%s+##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x42600000) { + // 01000010011sssssPPitttttiiiii0vv | if (Pv.new) memh(Rs+#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memh(%s+##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x46400000) { + // 01000110010sssssPPitttttiiiii0vv | if (!Pv.new) memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memh(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x46a00800) { + // 01000110101sssssPPi01tttiiiii0vv | if (!Pv.new) memh(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memh(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x42a00800) { + // 01000010101sssssPPi01tttiiiii0vv | if (Pv.new) memh(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memh(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x42400000) { + // 01000010010sssssPPitttttiiiii0vv | if (Pv.new) memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memh(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x46800000) { + // 01000110100sssssPPitttttiiiii0vv | if (!Pv.new) memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memw(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x46a01000) { + // 01000110101sssssPPi10tttiiiii0vv | if (!Pv.new) memw(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWFNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memw(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01804) == 0x42a01000) { + // 01000010101sssssPPi10tttiiiii0vv | if (Pv.new) memw(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWTNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memw(%s+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00004) == 0x42800000) { + // 01000010100sssssPPitttttiiiii0vv | if (Pv.new) memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERITNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memw(%s+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x5: + if ((hi_u32 & 0xfe000001) == 0x5a000000) { + // 0101101iiiiiiiiiPPiiiiiiiiiiiii0 | call Ii + hi->instruction = HEX_INS_J2_CALL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1ff0000) >> 3) | (((hi_u32)&0x3ffe) >> 1)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 23)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 23); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + sprintf(hi->mnem, "%s call 0x%x %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5d200000) { + // 01011101ii1iiiiiPPi000uuiiiiiii0 | if (!Pu) call Ii + hi->instruction = HEX_INS_J2_CALLF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) call 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0x50a00000) { + // 01010000101sssssPP00000000000000 | callr Rs + hi->instruction = HEX_INS_J2_CALLR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s callr %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x51200000) { + // 01010001001sssssPP0000uu00000000 | if (!Pu) callr Rs + hi->instruction = HEX_INS_J2_CALLRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) callr %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x51000000) { + // 01010001000sssssPP0000uu00000000 | if (Pu) callr Rs + hi->instruction = HEX_INS_J2_CALLRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) callr %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5d000000) { + // 01011101ii0iiiiiPPi000uuiiiiiii0 | if (Pu) call Ii + hi->instruction = HEX_INS_J2_CALLT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) call 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe000001) == 0x58000000) { + // 0101100iiiiiiiiiPPiiiiiiiiiiiii0 | jump Ii + hi->instruction = HEX_INS_J2_JUMP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1ff0000) >> 3) | (((hi_u32)&0x3ffe) >> 1)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 23)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 23); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + sprintf(hi->mnem, "%s jump 0x%x %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5c200000) { + // 01011100ii1iiiiiPPi000uuiiiiiii0 | if (!Pu) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5c200800) { + // 01011100ii1iiiiiPPi010uuiiiiiii0 | if (!Pu.new) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5c201800) { + // 01011100ii1iiiiiPPi110uuiiiiiii0 | if (!Pu.new) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPFNEWPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5c201000) { + // 01011100ii1iiiiiPPi100uuiiiiiii0 | if (!Pu) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPFPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0x52800000) { + // 01010010100sssssPP00000000000000 | jumpr Rs + hi->instruction = HEX_INS_J2_JUMPR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s jumpr %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x53600000) { + // 01010011011sssssPP0000uu00000000 | if (!Pu) jumpr:nt Rs + hi->instruction = HEX_INS_J2_JUMPRF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) jumpr:nt %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x53600800) { + // 01010011011sssssPP0010uu00000000 | if (!Pu.new) jumpr:nt Rs + hi->instruction = HEX_INS_J2_JUMPRFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) jumpr:nt %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x53601800) { + // 01010011011sssssPP0110uu00000000 | if (!Pu.new) jumpr:t Rs + hi->instruction = HEX_INS_J2_JUMPRFNEWPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) jumpr:t %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x53601000) { + // 01010011011sssssPP0100uu00000000 | if (!Pu) jumpr:t Rs + hi->instruction = HEX_INS_J2_JUMPRFPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) jumpr:t %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x53400000) { + // 01010011010sssssPP0000uu00000000 | if (Pu) jumpr:nt Rs + hi->instruction = HEX_INS_J2_JUMPRT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) jumpr:nt %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x53400800) { + // 01010011010sssssPP0010uu00000000 | if (Pu.new) jumpr:nt Rs + hi->instruction = HEX_INS_J2_JUMPRTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) jumpr:nt %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x53401800) { + // 01010011010sssssPP0110uu00000000 | if (Pu.new) jumpr:t Rs + hi->instruction = HEX_INS_J2_JUMPRTNEWPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) jumpr:t %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03cff) == 0x53401000) { + // 01010011010sssssPP0100uu00000000 | if (Pu) jumpr:t Rs + hi->instruction = HEX_INS_J2_JUMPRTPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) jumpr:t %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5c000000) { + // 01011100ii0iiiiiPPi000uuiiiiiii0 | if (Pu) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5c000800) { + // 01011100ii0iiiiiPPi010uuiiiiiii0 | if (Pu.new) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5c001800) { + // 01011100ii0iiiiiPPi110uuiiiiiii0 | if (Pu.new) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPTNEWPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff201c01) == 0x5c001000) { + // 01011100ii0iiiiiPPi100uuiiiiiii0 | if (Pu) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPTPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 16); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e3) == 0x54400000) { + // 0101010001000000PP0iiiii000iii00 | pause(#Ii) + hi->instruction = HEX_INS_J2_PAUSE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 5) | (((hi_u32)&0x1c) >> 2)); // Ii + sprintf(hi->mnem, "%s pause(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e3) == 0x54000000) { + // 0101010000000000PP0iiiii000iii00 | trap0(#Ii) + hi->instruction = HEX_INS_J2_TRAP0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 5) | (((hi_u32)&0x1c) >> 2)); // Ii + sprintf(hi->mnem, "%s trap0(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e3) == 0x54800000) { + // 01010100100xxxxxPP0iiiii000iii00 | trap1(Rx,#Ii) + hi->instruction = HEX_INS_J2_TRAP1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f00) >> 5) | (((hi_u32)&0x1c) >> 2)); // Ii + sprintf(hi->mnem, "%s trap1(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0x52a00000) { + // 01010010101sssssPP00000000000000 | hintjr(Rs) + hi->instruction = HEX_INS_J4_HINTJUMPR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s hintjr(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff20e3) == 0x54800000) { + // 0101010010000000PP0iiiii000iii00 | trap1(#Ii) + hi->instruction = HEX_INS_PS_TRAP1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 5) | (((hi_u32)&0x1c) >> 2)); // Ii + sprintf(hi->mnem, "%s trap1(#0x%x) %s", hi->pkt_info.syntax_prefix, hi->ops[0].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0x56c00000) { + // 01010110110sssssPP00000000000000 | icinva(Rs) + hi->instruction = HEX_INS_Y2_ICINVA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s icinva(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fff) == 0x57c00002) { + // 0101011111000000PP00000000000010 | isync + hi->instruction = HEX_INS_Y2_ISYNC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s isync %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x6: + if ((hi_u32 & 0xffe03fe0) == 0x6a000000) { + // 01101010000sssssPP000000000ddddd | Rd = Cs + hi->instruction = HEX_INS_A2_TFRCRR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Cs32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_ctr_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x62200000) { + // 01100010001sssssPP000000000ddddd | Cd = Rs + hi->instruction = HEX_INS_A2_TFRRCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Cd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_ctr_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x68000000) { + // 01101000000sssssPP000000000ddddd | Rdd = Css + hi->instruction = HEX_INS_A4_TFRCPP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Css32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_ctr_regs64(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x63200000) { + // 01100011001sssssPP000000000ddddd | Cdd = Rss + hi->instruction = HEX_INS_A4_TFRPCP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Cdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_ctr_regs64(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3ffc) == 0x6ba00000) { + // 01101011101000ssPP000000000000dd | Pd = all8(Ps) + hi->instruction = HEX_INS_C2_ALL8; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + sprintf(hi->mnem, "%s %s = all8(%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b000000) { + // 01101011000000ssPP0000tt000000dd | Pd = and(Pt,Ps) + hi->instruction = HEX_INS_C2_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + sprintf(hi->mnem, "%s %s = and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b600000) { + // 01101011011000ssPP0000tt000000dd | Pd = and(Pt,!Ps) + hi->instruction = HEX_INS_C2_ANDN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + sprintf(hi->mnem, "%s %s = and(%s,!%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3ffc) == 0x6b800000) { + // 01101011100000ssPP000000000000dd | Pd = any8(Ps) + hi->instruction = HEX_INS_C2_ANY8; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + sprintf(hi->mnem, "%s %s = any8(%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3ffc) == 0x6bc00000) { + // 01101011110000ssPP000000000000dd | Pd = not(Ps) + hi->instruction = HEX_INS_C2_NOT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + sprintf(hi->mnem, "%s %s = not(%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b200000) { + // 01101011001000ssPP0000tt000000dd | Pd = or(Pt,Ps) + hi->instruction = HEX_INS_C2_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + sprintf(hi->mnem, "%s %s = or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6be00000) { + // 01101011111000ssPP0000tt000000dd | Pd = or(Pt,!Ps) + hi->instruction = HEX_INS_C2_ORN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + sprintf(hi->mnem, "%s %s = or(%s,!%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b400000) { + // 01101011010000ssPP0000tt000000dd | Pd = xor(Ps,Pt) + hi->instruction = HEX_INS_C2_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + sprintf(hi->mnem, "%s %s = xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff2060) == 0x6a490000) { + // 0110101001001001PP0iiiiii00ddddd | Rd = add(pc,#Ii) + hi->instruction = HEX_INS_C4_ADDIPC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + sprintf(hi->mnem, "%s %s = add(PC,##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b100000) { + // 01101011000100ssPP0000ttuu0000dd | Pd = and(Ps,and(Pt,Pu)) + hi->instruction = HEX_INS_C4_AND_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + sprintf(hi->mnem, "%s %s = and(%s,and(%s,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b900000) { + // 01101011100100ssPP0000ttuu0000dd | Pd = and(Ps,and(Pt,!Pu)) + hi->instruction = HEX_INS_C4_AND_ANDN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + sprintf(hi->mnem, "%s %s = and(%s,and(%s,!%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b300000) { + // 01101011001100ssPP0000ttuu0000dd | Pd = and(Ps,or(Pt,Pu)) + hi->instruction = HEX_INS_C4_AND_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + sprintf(hi->mnem, "%s %s = and(%s,or(%s,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6bb00000) { + // 01101011101100ssPP0000ttuu0000dd | Pd = and(Ps,or(Pt,!Pu)) + hi->instruction = HEX_INS_C4_AND_ORN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + sprintf(hi->mnem, "%s %s = and(%s,or(%s,!%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b002090) { + // 01101011000000ssPP1000tt100100dd | Pd = fastcorner9(Ps,Pt) + hi->instruction = HEX_INS_C4_FASTCORNER9; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + sprintf(hi->mnem, "%s %s = fastcorner9(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b102090) { + // 01101011000100ssPP1000tt100100dd | Pd = !fastcorner9(Ps,Pt) + hi->instruction = HEX_INS_C4_FASTCORNER9_NOT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + sprintf(hi->mnem, "%s %s = !fastcorner9(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b500000) { + // 01101011010100ssPP0000ttuu0000dd | Pd = or(Ps,and(Pt,Pu)) + hi->instruction = HEX_INS_C4_OR_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + sprintf(hi->mnem, "%s %s = or(%s,and(%s,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6bd00000) { + // 01101011110100ssPP0000ttuu0000dd | Pd = or(Ps,and(Pt,!Pu)) + hi->instruction = HEX_INS_C4_OR_ANDN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + sprintf(hi->mnem, "%s %s = or(%s,and(%s,!%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b700000) { + // 01101011011100ssPP0000ttuu0000dd | Pd = or(Ps,or(Pt,Pu)) + hi->instruction = HEX_INS_C4_OR_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + sprintf(hi->mnem, "%s %s = or(%s,or(%s,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6bf00000) { + // 01101011111100ssPP0000ttuu0000dd | Pd = or(Ps,or(Pt,!Pu)) + hi->instruction = HEX_INS_C4_OR_ORN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + sprintf(hi->mnem, "%s %s = or(%s,or(%s,!%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x68200000) { + // 01101000001sssssPP000000000ddddd | Rdd = Gss + hi->instruction = HEX_INS_G4_TFRGCPP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Gss32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_guest_regs64(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x6a200000) { + // 01101010001sssssPP000000000ddddd | Rd = Gs + hi->instruction = HEX_INS_G4_TFRGCRR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Gs32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_guest_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x63000000) { + // 01100011000sssssPP000000000ddddd | Gdd = Rss + hi->instruction = HEX_INS_G4_TFRGPCP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Gdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_guest_regs64(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x62000000) { + // 01100010000sssssPP000000000ddddd | Gd = Rs + hi->instruction = HEX_INS_G4_TFRGRCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Gd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_guest_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc01001) == 0x61400000) { + // 0110000101isssssPPi0iiiiiiiiiii0 | if (Rs>=#0) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPRGTEZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 14); + } + sprintf(hi->mnem, "%s if (%s>=#0) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc01001) == 0x61401000) { + // 0110000101isssssPPi1iiiiiiiiiii0 | if (Rs>=#0) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPRGTEZPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 14); + } + sprintf(hi->mnem, "%s if (%s>=#0) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc01001) == 0x61c00000) { + // 0110000111isssssPPi0iiiiiiiiiii0 | if (Rs<=#0) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPRLTEZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 14); + } + sprintf(hi->mnem, "%s if (%s<=#0) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc01001) == 0x61c01000) { + // 0110000111isssssPPi1iiiiiiiiiii0 | if (Rs<=#0) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPRLTEZPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 14); + } + sprintf(hi->mnem, "%s if (%s<=#0) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc01001) == 0x61800000) { + // 0110000110isssssPPi0iiiiiiiiiii0 | if (Rs==#0) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPRNZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 14); + } + sprintf(hi->mnem, "%s if (%s==#0) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc01001) == 0x61801000) { + // 0110000110isssssPPi1iiiiiiiiiii0 | if (Rs==#0) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPRNZPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 14); + } + sprintf(hi->mnem, "%s if (%s==#0) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc01001) == 0x61000000) { + // 0110000100isssssPPi0iiiiiiiiiii0 | if (Rs!=#0) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPRZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 14); + } + sprintf(hi->mnem, "%s if (%s!=#0) jump:nt 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc01001) == 0x61001000) { + // 0110000100isssssPPi1iiiiiiiiiii0 | if (Rs!=#0) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPRZPT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 14); + } + sprintf(hi->mnem, "%s if (%s!=#0) jump:t 0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), addr + (st32)hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02004) == 0x69000000) { + // 01101001000IIIIIPP0iiiiiIIIii0II | loop0(Ii,#II) + hi->instruction = HEX_INS_J2_LOOP0I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_0; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + sprintf(hi->mnem, "%s loop0(0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e7) == 0x60000000) { + // 01100000000sssssPP0iiiii000ii000 | loop0(Ii,Rs) + hi->instruction = HEX_INS_J2_LOOP0R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_0; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s loop0(0x%x,%s) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02004) == 0x69200000) { + // 01101001001IIIIIPP0iiiiiIIIii0II | loop1(Ii,#II) + hi->instruction = HEX_INS_J2_LOOP1I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_1; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + sprintf(hi->mnem, "%s loop1(0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e7) == 0x60200000) { + // 01100000001sssssPP0iiiii000ii000 | loop1(Ii,Rs) + hi->instruction = HEX_INS_J2_LOOP1R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_1; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s loop1(0x%x,%s) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02004) == 0x69a00000) { + // 01101001101IIIIIPP0iiiiiIIIii0II | p3 = sp1loop0(Ii,#II) + hi->instruction = HEX_INS_J2_PLOOP1SI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_0; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + sprintf(hi->mnem, "%s P3 = sp1loop0(0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e7) == 0x60a00000) { + // 01100000101sssssPP0iiiii000ii000 | p3 = sp1loop0(Ii,Rs) + hi->instruction = HEX_INS_J2_PLOOP1SR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_0; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s P3 = sp1loop0(0x%x,%s) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02004) == 0x69c00000) { + // 01101001110IIIIIPP0iiiiiIIIii0II | p3 = sp2loop0(Ii,#II) + hi->instruction = HEX_INS_J2_PLOOP2SI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_0; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + sprintf(hi->mnem, "%s P3 = sp2loop0(0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e7) == 0x60c00000) { + // 01100000110sssssPP0iiiii000ii000 | p3 = sp2loop0(Ii,Rs) + hi->instruction = HEX_INS_J2_PLOOP2SR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_0; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s P3 = sp2loop0(0x%x,%s) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02004) == 0x69e00000) { + // 01101001111IIIIIPP0iiiiiIIIii0II | p3 = sp3loop0(Ii,#II) + hi->instruction = HEX_INS_J2_PLOOP3SI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_0; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + sprintf(hi->mnem, "%s P3 = sP3loop0(0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e7) == 0x60e00000) { + // 01100000111sssssPP0iiiii000ii000 | p3 = sp3loop0(Ii,Rs) + hi->instruction = HEX_INS_J2_PLOOP3SR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_LOOP_0; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffff << 8); + } + hex_op_extend(&(hi->ops[0]), false); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s P3 = sP3loop0(0x%x,%s) %s", hi->pkt_info.syntax_prefix, addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fff) == 0x6c200000) { + // 0110110000100000PP00000000000000 | brkpt + hi->instruction = HEX_INS_Y2_BREAK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s brkpt %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0x64400000) { + // 01100100010sssssPP00000000000000 | wait(Rs) + hi->instruction = HEX_INS_Y2_WAIT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s wait(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0x62400000) { + // 01100010010sssssPP00000000000000 | trace(Rs) + hi->instruction = HEX_INS_Y4_TRACE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s trace(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0x62400020) { + // 01100010010sssssPP00000000100000 | diag(Rs) + hi->instruction = HEX_INS_Y6_DIAG; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s diag(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020ff) == 0x62400040) { + // 01100010010sssssPP0ttttt01000000 | diag0(Rss,Rtt) + hi->instruction = HEX_INS_Y6_DIAG0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s diag0(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020ff) == 0x62400060) { + // 01100010010sssssPP0ttttt01100000 | diag1(Rss,Rtt) + hi->instruction = HEX_INS_Y6_DIAG1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s diag1(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x7: + if ((hi_u32 & 0xffc00000) == 0x76000000) { + // 0111011000isssssPPiiiiiiiiiddddd | Rd = and(Rs,#Ii) + hi->instruction = HEX_INS_A2_ANDIR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x70000000) { + // 01110000000sssssPP000000000ddddd | Rd = aslh(Rs) + hi->instruction = HEX_INS_A2_ASLH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = aslh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x70200000) { + // 01110000001sssssPP000000000ddddd | Rd = asrh(Rs) + hi->instruction = HEX_INS_A2_ASRH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = asrh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff800000) == 0x7c000000) { + // 011111000IIIIIIIPPIiiiiiiiiddddd | Rdd = combine(#Ii,#II) + hi->instruction = HEX_INS_A2_COMBINEII; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[1].op.imm & (1 << 7)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x7f0000) >> 15) | (((hi_u32)&0x2000) >> 13)); // II + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = combine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), signed_imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fff) == 0x7f000000) { + // 0111111100000000PP00000000000000 | nop + hi->instruction = HEX_INS_A2_NOP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s nop %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00000) == 0x76800000) { + // 0111011010isssssPPiiiiiiiiiddddd | Rd = or(Rs,#Ii) + hi->instruction = HEX_INS_A2_ORIR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff802000) == 0x74800000) { + // 011101001uusssssPP0iiiiiiiiddddd | if (!Pu) Rd = add(Rs,#Ii) + hi->instruction = HEX_INS_A2_PADDIF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff802000) == 0x74802000) { + // 011101001uusssssPP1iiiiiiiiddddd | if (!Pu.new) Rd = add(Rs,#Ii) + hi->instruction = HEX_INS_A2_PADDIFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff802000) == 0x74000000) { + // 011101000uusssssPP0iiiiiiiiddddd | if (Pu) Rd = add(Rs,#Ii) + hi->instruction = HEX_INS_A2_PADDIT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff802000) == 0x74002000) { + // 011101000uusssssPP1iiiiiiiiddddd | if (Pu.new) Rd = add(Rs,#Ii) + hi->instruction = HEX_INS_A2_PADDITNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00000) == 0x76400000) { + // 0111011001isssssPPiiiiiiiiiddddd | Rd = sub(#Ii,Rs) + hi->instruction = HEX_INS_A2_SUBRI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[1].op.imm & (1 << 9)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x70a00000) { + // 01110000101sssssPP000000000ddddd | Rd = sxtb(Rs) + hi->instruction = HEX_INS_A2_SXTB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x70e00000) { + // 01110000111sssssPP000000000ddddd | Rd = sxth(Rs) + hi->instruction = HEX_INS_A2_SXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x70600000) { + // 01110000011sssssPP000000000ddddd | Rd = Rs + hi->instruction = HEX_INS_A2_TFR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff200000) == 0x72200000) { + // 01110010ii1xxxxxPPiiiiiiiiiiiiii | Rx.h = #Ii + hi->instruction = HEX_INS_A2_TFRIH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 8) | (((hi_u32)&0x3fff) >> 0)); // Ii + sprintf(hi->mnem, "%s %s.h = #0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff200000) == 0x71200000) { + // 01110001ii1xxxxxPPiiiiiiiiiiiiii | Rx.l = #Ii + hi->instruction = HEX_INS_A2_TFRIL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 8) | (((hi_u32)&0x3fff) >> 0)); // Ii + sprintf(hi->mnem, "%s %s.l = #0x%x %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff200000) == 0x78000000) { + // 01111000ii0iiiiiPPiiiiiiiiiddddd | Rd = #Ii + hi->instruction = HEX_INS_A2_TFRSI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 8) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[1].op.imm & (1 << 15)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 15); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x70c00000) { + // 01110000110sssssPP000000000ddddd | Rd = zxth(Rs) + hi->instruction = HEX_INS_A2_ZXTH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00000) == 0x7c800000) { + // 01111100100IIIIIPPIiiiiiiiiddddd | Rdd = combine(#Ii,#II) + hi->instruction = HEX_INS_A4_COMBINEII; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[1].op.imm & (1 << 7)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 7); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x2000) >> 13)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = combine(%s,##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), signed_imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x73202000) { + // 01110011001sssssPP1iiiiiiiiddddd | Rdd = combine(#Ii,Rs) + hi->instruction = HEX_INS_A4_COMBINEIR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[1].op.imm & (1 << 7)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = combine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x73002000) { + // 01110011000sssssPP1iiiiiiiiddddd | Rdd = combine(Rs,#Ii) + hi->instruction = HEX_INS_A4_COMBINERI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = combine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70002800) { + // 01110000000sssssPP1010uu000ddddd | if (!Pu) Rd = aslh(Rs) + hi->instruction = HEX_INS_A4_PASLHF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) %s = aslh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70002c00) { + // 01110000000sssssPP1011uu000ddddd | if (!Pu.new) Rd = aslh(Rs) + hi->instruction = HEX_INS_A4_PASLHFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) %s = aslh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70002000) { + // 01110000000sssssPP1000uu000ddddd | if (Pu) Rd = aslh(Rs) + hi->instruction = HEX_INS_A4_PASLHT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) %s = aslh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70002400) { + // 01110000000sssssPP1001uu000ddddd | if (Pu.new) Rd = aslh(Rs) + hi->instruction = HEX_INS_A4_PASLHTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) %s = aslh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70202800) { + // 01110000001sssssPP1010uu000ddddd | if (!Pu) Rd = asrh(Rs) + hi->instruction = HEX_INS_A4_PASRHF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) %s = asrh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70202c00) { + // 01110000001sssssPP1011uu000ddddd | if (!Pu.new) Rd = asrh(Rs) + hi->instruction = HEX_INS_A4_PASRHFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) %s = asrh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70202000) { + // 01110000001sssssPP1000uu000ddddd | if (Pu) Rd = asrh(Rs) + hi->instruction = HEX_INS_A4_PASRHT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) %s = asrh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70202400) { + // 01110000001sssssPP1001uu000ddddd | if (Pu.new) Rd = asrh(Rs) + hi->instruction = HEX_INS_A4_PASRHTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) %s = asrh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70a02800) { + // 01110000101sssssPP1010uu000ddddd | if (!Pu) Rd = sxtb(Rs) + hi->instruction = HEX_INS_A4_PSXTBF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70a02c00) { + // 01110000101sssssPP1011uu000ddddd | if (!Pu.new) Rd = sxtb(Rs) + hi->instruction = HEX_INS_A4_PSXTBFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70a02000) { + // 01110000101sssssPP1000uu000ddddd | if (Pu) Rd = sxtb(Rs) + hi->instruction = HEX_INS_A4_PSXTBT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70a02400) { + // 01110000101sssssPP1001uu000ddddd | if (Pu.new) Rd = sxtb(Rs) + hi->instruction = HEX_INS_A4_PSXTBTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) %s = sxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70e02800) { + // 01110000111sssssPP1010uu000ddddd | if (!Pu) Rd = sxth(Rs) + hi->instruction = HEX_INS_A4_PSXTHF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70e02c00) { + // 01110000111sssssPP1011uu000ddddd | if (!Pu.new) Rd = sxth(Rs) + hi->instruction = HEX_INS_A4_PSXTHFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70e02000) { + // 01110000111sssssPP1000uu000ddddd | if (Pu) Rd = sxth(Rs) + hi->instruction = HEX_INS_A4_PSXTHT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70e02400) { + // 01110000111sssssPP1001uu000ddddd | if (Pu.new) Rd = sxth(Rs) + hi->instruction = HEX_INS_A4_PSXTHTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) %s = sxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70802800) { + // 01110000100sssssPP1010uu000ddddd | if (!Pu) Rd = zxtb(Rs) + hi->instruction = HEX_INS_A4_PZXTBF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) %s = zxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70802c00) { + // 01110000100sssssPP1011uu000ddddd | if (!Pu.new) Rd = zxtb(Rs) + hi->instruction = HEX_INS_A4_PZXTBFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) %s = zxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70802000) { + // 01110000100sssssPP1000uu000ddddd | if (Pu) Rd = zxtb(Rs) + hi->instruction = HEX_INS_A4_PZXTBT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) %s = zxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70802400) { + // 01110000100sssssPP1001uu000ddddd | if (Pu.new) Rd = zxtb(Rs) + hi->instruction = HEX_INS_A4_PZXTBTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) %s = zxtb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70c02800) { + // 01110000110sssssPP1010uu000ddddd | if (!Pu) Rd = zxth(Rs) + hi->instruction = HEX_INS_A4_PZXTHF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70c02c00) { + // 01110000110sssssPP1011uu000ddddd | if (!Pu.new) Rd = zxth(Rs) + hi->instruction = HEX_INS_A4_PZXTHFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70c02000) { + // 01110000110sssssPP1000uu000ddddd | if (Pu) Rd = zxth(Rs) + hi->instruction = HEX_INS_A4_PZXTHT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x70c02400) { + // 01110000110sssssPP1001uu000ddddd | if (Pu.new) Rd = zxth(Rs) + hi->instruction = HEX_INS_A4_PZXTHTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) %s = zxth(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x73402000) { + // 01110011010sssssPP1iiiiiiiiddddd | Rd = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_A4_RCMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = cmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0x73602000) { + // 01110011011sssssPP1iiiiiiiiddddd | Rd = !cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_A4_RCMPNEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = !cmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff902000) == 0x7e800000) { + // 011111101uu0iiiiPP0iiiiiiiiddddd | if (!Pu) Rd = #Ii + hi->instruction = HEX_INS_C2_CMOVEIF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf0000) >> 8) | (((hi_u32)&0x1fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff902000) == 0x7e000000) { + // 011111100uu0iiiiPP0iiiiiiiiddddd | if (Pu) Rd = #Ii + hi->instruction = HEX_INS_C2_CMOVEIT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf0000) >> 8) | (((hi_u32)&0x1fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff902000) == 0x7e802000) { + // 011111101uu0iiiiPP1iiiiiiiiddddd | if (!Pu.new) Rd = #Ii + hi->instruction = HEX_INS_C2_CMOVENEWIF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf0000) >> 8) | (((hi_u32)&0x1fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff902000) == 0x7e002000) { + // 011111100uu0iiiiPP1iiiiiiiiddddd | if (Pu.new) Rd = #Ii + hi->instruction = HEX_INS_C2_CMOVENEWIT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf0000) >> 8) | (((hi_u32)&0x1fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc0001c) == 0x75000000) { + // 0111010100isssssPPiiiiiiiii000dd | Pd = cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_C2_CMPEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = cmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc0001c) == 0x75400000) { + // 0111010101isssssPPiiiiiiiii000dd | Pd = cmp.gt(Rs,#Ii) + hi->instruction = HEX_INS_C2_CMPGTI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = cmp.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0001c) == 0x75800000) { + // 01110101100sssssPPiiiiiiiii000dd | Pd = cmp.gtu(Rs,#Ii) + hi->instruction = HEX_INS_C2_CMPGTUI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3fe0) >> 5); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = cmp.gtu(%s,##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfe000000) == 0x7a000000) { + // 0111101uuIIIIIIIPPIiiiiiiiiddddd | Rd = mux(Pu,#Ii,#II) + hi->instruction = HEX_INS_C2_MUXII; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1800000) >> 23); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x7f0000) >> 15) | (((hi_u32)&0x2000) >> 13)); // II + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 7); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s %s = mux(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), signed_imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff802000) == 0x73000000) { + // 011100110uusssssPP0iiiiiiiiddddd | Rd = mux(Pu,Rs,#Ii) + hi->instruction = HEX_INS_C2_MUXIR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s %s = mux(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff802000) == 0x73800000) { + // 011100111uusssssPP0iiiiiiiiddddd | Rd = mux(Pu,#Ii,Rs) + hi->instruction = HEX_INS_C2_MUXRI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = mux(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc0001c) == 0x75400010) { + // 0111010101isssssPPiiiiiiiii100dd | Pd = !cmp.gt(Rs,#Ii) + hi->instruction = HEX_INS_C4_CMPLTEI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = !cmp.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0001c) == 0x75800010) { + // 01110101100sssssPPiiiiiiiii100dd | Pd = !cmp.gtu(Rs,#Ii) + hi->instruction = HEX_INS_C4_CMPLTEUI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3fe0) >> 5); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = !cmp.gtu(%s,##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc0001c) == 0x75000010) { + // 0111010100isssssPPiiiiiiiii100dd | Pd = !cmp.eq(Rs,#Ii) + hi->instruction = HEX_INS_C4_CMPNEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = !cmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x8: + if ((hi_u32 & 0xffe03fe0) == 0x8c800080) { + // 10001100100sssssPP000000100ddddd | Rd = abs(Rs) + hi->instruction = HEX_INS_A2_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = abs(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x808000c0) { + // 10000000100sssssPP000000110ddddd | Rdd = abs(Rss) + hi->instruction = HEX_INS_A2_ABSP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = abs(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c8000a0) { + // 10001100100sssssPP000000101ddddd | Rd = abs(Rs):sat + hi->instruction = HEX_INS_A2_ABSSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = abs(%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x808000a0) { + // 10000000100sssssPP000000101ddddd | Rdd = neg(Rss) + hi->instruction = HEX_INS_A2_NEGP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = neg(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c8000c0) { + // 10001100100sssssPP000000110ddddd | Rd = neg(Rs):sat + hi->instruction = HEX_INS_A2_NEGSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = neg(%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80800080) { + // 10000000100sssssPP000000100ddddd | Rdd = not(Rss) + hi->instruction = HEX_INS_A2_NOTP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = not(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88c00020) { + // 10001000110sssssPP000000001ddddd | Rd = round(Rss):sat + hi->instruction = HEX_INS_A2_ROUNDSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = round(%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88c00000) { + // 10001000110sssssPP000000000ddddd | Rd = sat(Rss) + hi->instruction = HEX_INS_A2_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = sat(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8cc000e0) { + // 10001100110sssssPP000000111ddddd | Rd = satb(Rs) + hi->instruction = HEX_INS_A2_SATB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = satb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8cc00080) { + // 10001100110sssssPP000000100ddddd | Rd = sath(Rs) + hi->instruction = HEX_INS_A2_SATH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sath(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8cc000c0) { + // 10001100110sssssPP000000110ddddd | Rd = satub(Rs) + hi->instruction = HEX_INS_A2_SATUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = satub(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8cc000a0) { + // 10001100110sssssPP000000101ddddd | Rd = satuh(Rs) + hi->instruction = HEX_INS_A2_SATUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = satuh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c8000e0) { + // 10001100100sssssPP000000111ddddd | Rd = swiz(Rs) + hi->instruction = HEX_INS_A2_SWIZ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = swiz(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84400000) { + // 10000100010sssssPP000000000ddddd | Rdd = sxtw(Rs) + hi->instruction = HEX_INS_A2_SXTW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sxtw(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80400080) { + // 10000000010sssssPP000000100ddddd | Rdd = vabsh(Rss) + hi->instruction = HEX_INS_A2_VABSH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vabsh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x804000a0) { + // 10000000010sssssPP000000101ddddd | Rdd = vabsh(Rss):sat + hi->instruction = HEX_INS_A2_VABSHSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vabsh(%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x804000c0) { + // 10000000010sssssPP000000110ddddd | Rdd = vabsw(Rss) + hi->instruction = HEX_INS_A2_VABSW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vabsw(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x804000e0) { + // 10000000010sssssPP000000111ddddd | Rdd = vabsw(Rss):sat + hi->instruction = HEX_INS_A2_VABSWSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vabsw(%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x808000e0) { + // 10000000100sssssPP000000111ddddd | Rdd = vconj(Rss):sat + hi->instruction = HEX_INS_A2_VCONJ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vconj(%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x88c00080) { + // 10001000110sssssPP0iiiii100ddddd | Rdd = bitsplit(Rs,#Ii) + hi->instruction = HEX_INS_A4_BITSPLITI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = bitsplit(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8ce00000) { + // 10001100111sssssPP0iiiii000ddddd | Rd = cround(Rs,#Ii) + hi->instruction = HEX_INS_A4_CROUND_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = cround(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8ce00080) { + // 10001100111sssssPP0iiiii100ddddd | Rd = round(Rs,#Ii) + hi->instruction = HEX_INS_A4_ROUND_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = round(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8ce000c0) { + // 10001100111sssssPP0iiiii110ddddd | Rd = round(Rs,#Ii):sat + hi->instruction = HEX_INS_A4_ROUND_RI_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = round(%s,#0x%x):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x88c000a0) { + // 10001000110sssssPP0iiiii101ddddd | Rd = clip(Rs,#Ii) + hi->instruction = HEX_INS_A7_CLIP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = clip(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x8ce00040) { + // 10001100111sssssPPiiiiii010ddddd | Rdd = cround(Rss,#Ii) + hi->instruction = HEX_INS_A7_CROUNDD_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = cround(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x88c000c0) { + // 10001000110sssssPP0iiiii110ddddd | Rdd = vclip(Rss,#Ii) + hi->instruction = HEX_INS_A7_VCLIP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vclip(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000fc) == 0x85800000) { + // 10000101100sssssPPiiiiii000000dd | Pd = bitsclr(Rs,#Ii) + hi->instruction = HEX_INS_C2_BITSCLRI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = bitsclr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3ce0) == 0x86000000) { + // 1000011000000000PP0000tt000ddddd | Rdd = mask(Pt) + hi->instruction = HEX_INS_C2_MASK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + sprintf(hi->mnem, "%s %s = mask(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3fe0) == 0x89400000) { + // 10001001010000ssPP000000000ddddd | Rd = Ps + hi->instruction = HEX_INS_C2_TFRPR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ffc) == 0x85400000) { + // 10000101010sssssPP000000000000dd | Pd = Rs + hi->instruction = HEX_INS_C2_TFRRP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3ce0) == 0x89000000) { + // 10001001000000ssPP0000tt000ddddd | Rd = vitpack(Ps,Pt) + hi->instruction = HEX_INS_C2_VITPACK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + sprintf(hi->mnem, "%s %s = vitpack(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000fc) == 0x85a00000) { + // 10000101101sssssPPiiiiii000000dd | Pd = !bitsclr(Rs,#Ii) + hi->instruction = HEX_INS_C4_NBITSCLRI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = !bitsclr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e00060) { + // 10000000111sssssPP000000011ddddd | Rdd = convert_d2df(Rss) + hi->instruction = HEX_INS_F2_CONV_D2DF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_D2df(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88400020) { + // 10001000010sssssPP000000001ddddd | Rd = convert_d2sf(Rss) + hi->instruction = HEX_INS_F2_CONV_D2SF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_D2sf(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e00000) { + // 10000000111sssssPP000000000ddddd | Rdd = convert_df2d(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2D; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_df2d(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e000c0) { + // 10000000111sssssPP000000110ddddd | Rdd = convert_df2d(Rss):chop + hi->instruction = HEX_INS_F2_CONV_DF2D_CHOP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_df2d(%s):chop %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88000020) { + // 10001000000sssssPP000000001ddddd | Rd = convert_df2sf(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2SF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_df2sf(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e00020) { + // 10000000111sssssPP000000001ddddd | Rdd = convert_df2ud(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2UD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_df2ud(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e000e0) { + // 10000000111sssssPP000000111ddddd | Rdd = convert_df2ud(Rss):chop + hi->instruction = HEX_INS_F2_CONV_DF2UD_CHOP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_df2ud(%s):chop %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88600020) { + // 10001000011sssssPP000000001ddddd | Rd = convert_df2uw(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2UW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_df2uw(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88a00020) { + // 10001000101sssssPP000000001ddddd | Rd = convert_df2uw(Rss):chop + hi->instruction = HEX_INS_F2_CONV_DF2UW_CHOP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_df2uw(%s):chop %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88800020) { + // 10001000100sssssPP000000001ddddd | Rd = convert_df2w(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2W; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_df2w(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88e00020) { + // 10001000111sssssPP000000001ddddd | Rd = convert_df2w(Rss):chop + hi->instruction = HEX_INS_F2_CONV_DF2W_CHOP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_df2w(%s):chop %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800080) { + // 10000100100sssssPP000000100ddddd | Rdd = convert_sf2d(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2D; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_sf2d(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x848000c0) { + // 10000100100sssssPP000000110ddddd | Rdd = convert_sf2d(Rs):chop + hi->instruction = HEX_INS_F2_CONV_SF2D_CHOP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_sf2d(%s):chop %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800000) { + // 10000100100sssssPP000000000ddddd | Rdd = convert_sf2df(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2DF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_sf2df(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800060) { + // 10000100100sssssPP000000011ddddd | Rdd = convert_sf2ud(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2UD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_sf2ud(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x848000a0) { + // 10000100100sssssPP000000101ddddd | Rdd = convert_sf2ud(Rs):chop + hi->instruction = HEX_INS_F2_CONV_SF2UD_CHOP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_sf2ud(%s):chop %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b600000) { + // 10001011011sssssPP000000000ddddd | Rd = convert_sf2uw(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2UW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_sf2uw(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b600020) { + // 10001011011sssssPP000000001ddddd | Rd = convert_sf2uw(Rs):chop + hi->instruction = HEX_INS_F2_CONV_SF2UW_CHOP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_sf2uw(%s):chop %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b800000) { + // 10001011100sssssPP000000000ddddd | Rd = convert_sf2w(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2W; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_sf2w(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b800020) { + // 10001011100sssssPP000000001ddddd | Rd = convert_sf2w(Rs):chop + hi->instruction = HEX_INS_F2_CONV_SF2W_CHOP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_sf2w(%s):chop %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e00040) { + // 10000000111sssssPP000000010ddddd | Rdd = convert_ud2df(Rss) + hi->instruction = HEX_INS_F2_CONV_UD2DF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_ud2df(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88200020) { + // 10001000001sssssPP000000001ddddd | Rd = convert_ud2sf(Rss) + hi->instruction = HEX_INS_F2_CONV_UD2SF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = convert_ud2sf(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800020) { + // 10000100100sssssPP000000001ddddd | Rdd = convert_uw2df(Rs) + hi->instruction = HEX_INS_F2_CONV_UW2DF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_uw2df(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b200000) { + // 10001011001sssssPP000000000ddddd | Rd = convert_uw2sf(Rs) + hi->instruction = HEX_INS_F2_CONV_UW2SF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_uw2sf(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800040) { + // 10000100100sssssPP000000010ddddd | Rdd = convert_w2df(Rs) + hi->instruction = HEX_INS_F2_CONV_W2DF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_W2df(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b400000) { + // 10001011010sssssPP000000000ddddd | Rd = convert_w2sf(Rs) + hi->instruction = HEX_INS_F2_CONV_W2SF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = convert_W2sf(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x85e00000) { + // 10000101111sssssPP0iiiii000000dd | Pd = sfclass(Rs,#Ii) + hi->instruction = HEX_INS_F2_SFCLASS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = sfclass(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8ba00000) { + // 10001011101sssssPP000000000ddddd | Rd = sffixupr(Rs) + hi->instruction = HEX_INS_F2_SFFIXUPR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sffixupr(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03f80) == 0x8be00000) { + // 10001011111sssssPP0000000eeddddd | Rd,Pe = sfinvsqrta(Rs) + hi->instruction = HEX_INS_F2_SFINVSQRTA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pe4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s,%s = sfinvsqrta(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x80000040) { + // 10000000000sssssPPiiiiii010ddddd | Rdd = asl(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x820000c0) { + // 10000010000sssssPPiiiiii110xxxxx | Rxx += asl(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s += asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82400040) { + // 10000010010sssssPPiiiiii010xxxxx | Rxx &= asl(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s &= asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82000040) { + // 10000010000sssssPPiiiiii010xxxxx | Rxx -= asl(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s -= asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x824000c0) { + // 10000010010sssssPPiiiiii110xxxxx | Rxx |= asl(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s |= asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82800040) { + // 10000010100sssssPPiiiiii010xxxxx | Rxx ^= asl(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_XACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s ^= asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8c000040) { + // 10001100000sssssPP0iiiii010ddddd | Rd = asl(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e0000c0) { + // 10001110000sssssPP0iiiii110xxxxx | Rx += asl(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s += asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400040) { + // 10001110010sssssPP0iiiii010xxxxx | Rx &= asl(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s &= asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000040) { + // 10001110000sssssPP0iiiii010xxxxx | Rx -= asl(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s -= asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e4000c0) { + // 10001110010sssssPP0iiiii110xxxxx | Rx |= asl(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s |= asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8c400040) { + // 10001100010sssssPP0iiiii010ddddd | Rd = asl(Rs,#Ii):sat + hi->instruction = HEX_INS_S2_ASL_I_R_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = asl(%s,#0x%x):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e800040) { + // 10001110100sssssPP0iiiii010xxxxx | Rx ^= asl(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_XACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s ^= asl(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe030e0) == 0x80800040) { + // 10000000100sssssPP00iiii010ddddd | Rdd = vaslh(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_VH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vaslh(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x80400040) { + // 10000000010sssssPP0iiiii010ddddd | Rdd = vaslw(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASL_I_VW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vaslw(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x80000000) { + // 10000000000sssssPPiiiiii000ddddd | Rdd = asr(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82000080) { + // 10000010000sssssPPiiiiii100xxxxx | Rxx += asr(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_P_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s += asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82400000) { + // 10000010010sssssPPiiiiii000xxxxx | Rxx &= asr(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_P_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s &= asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82000000) { + // 10000010000sssssPPiiiiii000xxxxx | Rxx -= asr(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_P_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s -= asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82400080) { + // 10000010010sssssPPiiiiii100xxxxx | Rxx |= asr(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_P_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s |= asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x80c000e0) { + // 10000000110sssssPPiiiiii111ddddd | Rdd = asr(Rss,#Ii):rnd + hi->instruction = HEX_INS_S2_ASR_I_P_RND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = asr(%s,#0x%x):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8c000000) { + // 10001100000sssssPP0iiiii000ddddd | Rd = asr(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000080) { + // 10001110000sssssPP0iiiii100xxxxx | Rx += asr(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_R_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s += asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400000) { + // 10001110010sssssPP0iiiii000xxxxx | Rx &= asr(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_R_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s &= asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000000) { + // 10001110000sssssPP0iiiii000xxxxx | Rx -= asr(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_R_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s -= asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400080) { + // 10001110010sssssPP0iiiii100xxxxx | Rx |= asr(Rs,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_R_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s |= asr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8c400000) { + // 10001100010sssssPP0iiiii000ddddd | Rd = asr(Rs,#Ii):rnd + hi->instruction = HEX_INS_S2_ASR_I_R_RND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = asr(%s,#0x%x):rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x88c00040) { + // 10001000110sssssPP0iiiii010ddddd | Rd = vasrw(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_SVW_TRUN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vasrw(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe030e0) == 0x80800000) { + // 10000000100sssssPP00iiii000ddddd | Rdd = vasrh(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_VH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vasrh(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x80400000) { + // 10000000010sssssPP0iiiii000ddddd | Rdd = vasrw(Rss,#Ii) + hi->instruction = HEX_INS_S2_ASR_I_VW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vasrw(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c4000c0) { + // 10001100010sssssPP000000110ddddd | Rd = brev(Rs) + hi->instruction = HEX_INS_S2_BREV; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = brev(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80c000c0) { + // 10000000110sssssPP000000110ddddd | Rdd = brev(Rss) + hi->instruction = HEX_INS_S2_BREVP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = brev(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c0000a0) { + // 10001100000sssssPP000000101ddddd | Rd = cl0(Rs) + hi->instruction = HEX_INS_S2_CL0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = cl0(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88400040) { + // 10001000010sssssPP000000010ddddd | Rd = cl0(Rss) + hi->instruction = HEX_INS_S2_CL0P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = cl0(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c0000c0) { + // 10001100000sssssPP000000110ddddd | Rd = cl1(Rs) + hi->instruction = HEX_INS_S2_CL1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = cl1(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88400080) { + // 10001000010sssssPP000000100ddddd | Rd = cl1(Rss) + hi->instruction = HEX_INS_S2_CL1P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = cl1(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c000080) { + // 10001100000sssssPP000000100ddddd | Rd = clb(Rs) + hi->instruction = HEX_INS_S2_CLB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = clb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c0000e0) { + // 10001100000sssssPP000000111ddddd | Rd = normamt(Rs) + hi->instruction = HEX_INS_S2_CLBNORM; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = normamt(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88400000) { + // 10001000010sssssPP000000000ddddd | Rd = clb(Rss) + hi->instruction = HEX_INS_S2_CLBP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = clb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8cc00020) { + // 10001100110sssssPP0iiiii001ddddd | Rd = clrbit(Rs,#Ii) + hi->instruction = HEX_INS_S2_CLRBIT_I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = clrbit(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c400080) { + // 10001100010sssssPP000000100ddddd | Rd = ct0(Rs) + hi->instruction = HEX_INS_S2_CT0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = ct0(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88e00040) { + // 10001000111sssssPP000000010ddddd | Rd = ct0(Rss) + hi->instruction = HEX_INS_S2_CT0P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = ct0(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c4000a0) { + // 10001100010sssssPP000000101ddddd | Rd = ct1(Rs) + hi->instruction = HEX_INS_S2_CT1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = ct1(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88e00080) { + // 10001000111sssssPP000000100ddddd | Rd = ct1(Rss) + hi->instruction = HEX_INS_S2_CT1P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = ct1(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80c00080) { + // 10000000110sssssPP000000100ddddd | Rdd = deinterleave(Rss) + hi->instruction = HEX_INS_S2_DEINTERLEAVE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = deinterleave(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff802000) == 0x8d000000) { + // 100011010IIsssssPP0iiiiiIIIddddd | Rd = extractu(Rs,#Ii,#II) + hi->instruction = HEX_INS_S2_EXTRACTU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + sprintf(hi->mnem, "%s %s = extractu(%s,#0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000000) == 0x81000000) { + // 10000001IIIsssssPPiiiiiiIIIddddd | Rdd = extractu(Rss,#Ii,#II) + hi->instruction = HEX_INS_S2_EXTRACTUP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xe00000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + sprintf(hi->mnem, "%s %s = extractu(%s,#0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff802000) == 0x8f000000) { + // 100011110IIsssssPP0iiiiiIIIxxxxx | Rx = insert(Rs,#Ii,#II) + hi->instruction = HEX_INS_S2_INSERT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + sprintf(hi->mnem, "%s %s = insert(%s,#0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000000) == 0x83000000) { + // 10000011IIIsssssPPiiiiiiIIIxxxxx | Rxx = insert(Rss,#Ii,#II) + hi->instruction = HEX_INS_S2_INSERTP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xe00000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + sprintf(hi->mnem, "%s %s = insert(%s,#0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80c000a0) { + // 10000000110sssssPP000000101ddddd | Rdd = interleave(Rss) + hi->instruction = HEX_INS_S2_INTERLEAVE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = interleave(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x80000020) { + // 10000000000sssssPPiiiiii001ddddd | Rdd = lsr(Rss,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x820000a0) { + // 10000010000sssssPPiiiiii101xxxxx | Rxx += lsr(Rss,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s += lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82400020) { + // 10000010010sssssPPiiiiii001xxxxx | Rxx &= lsr(Rss,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s &= lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82000020) { + // 10000010000sssssPPiiiiii001xxxxx | Rxx -= lsr(Rss,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s -= lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x824000a0) { + // 10000010010sssssPPiiiiii101xxxxx | Rxx |= lsr(Rss,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s |= lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82800020) { + // 10000010100sssssPPiiiiii001xxxxx | Rxx ^= lsr(Rss,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_XACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s ^= lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8c000020) { + // 10001100000sssssPP0iiiii001ddddd | Rd = lsr(Rs,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e0000a0) { + // 10001110000sssssPP0iiiii101xxxxx | Rx += lsr(Rs,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s += lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400020) { + // 10001110010sssssPP0iiiii001xxxxx | Rx &= lsr(Rs,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s &= lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000020) { + // 10001110000sssssPP0iiiii001xxxxx | Rx -= lsr(Rs,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s -= lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e4000a0) { + // 10001110010sssssPP0iiiii101xxxxx | Rx |= lsr(Rs,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s |= lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e800020) { + // 10001110100sssssPP0iiiii001xxxxx | Rx ^= lsr(Rs,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_XACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s ^= lsr(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe030e0) == 0x80800020) { + // 10000000100sssssPP00iiii001ddddd | Rdd = vlsrh(Rss,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_VH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vlsrh(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x80400020) { + // 10000000010sssssPP0iiiii001ddddd | Rdd = vlsrw(Rss,#Ii) + hi->instruction = HEX_INS_S2_LSR_I_VW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vlsrw(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff9f2000) == 0x8d002000) { + // 100011010II00000PP1iiiiiIIIddddd | Rd = mask(#Ii,#II) + hi->instruction = HEX_INS_S2_MASK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x600000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + sprintf(hi->mnem, "%s %s = mask(#0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8cc00000) { + // 10001100110sssssPP0iiiii000ddddd | Rd = setbit(Rs,#Ii) + hi->instruction = HEX_INS_S2_SETBIT_I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = setbit(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c800000) { + // 10001100100sssssPP000000000ddddd | Rd = vsathb(Rs) + hi->instruction = HEX_INS_S2_SVSATHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsathb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c800040) { + // 10001100100sssssPP000000010ddddd | Rd = vsathub(Rs) + hi->instruction = HEX_INS_S2_SVSATHUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsathub(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00000) == 0x87000000) { + // 1000011100isssssPPIIIIIIiiixxxxx | Rx = tableidxb(Rs,#Ii,#II):raw + hi->instruction = HEX_INS_S2_TABLEIDXB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 18) | (((hi_u32)&0xe0) >> 5)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s %s = tableidxb(%s,#0x%x,%s):raw %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00000) == 0x87c00000) { + // 1000011111isssssPPIIIIIIiiixxxxx | Rx = tableidxd(Rs,#Ii,#II):raw + hi->instruction = HEX_INS_S2_TABLEIDXD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 18) | (((hi_u32)&0xe0) >> 5)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s %s = tableidxd(%s,#0x%x,%s):raw %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00000) == 0x87400000) { + // 1000011101isssssPPIIIIIIiiixxxxx | Rx = tableidxh(Rs,#Ii,#II):raw + hi->instruction = HEX_INS_S2_TABLEIDXH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 18) | (((hi_u32)&0xe0) >> 5)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s %s = tableidxh(%s,#0x%x,%s):raw %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00000) == 0x87800000) { + // 1000011110isssssPPIIIIIIiiixxxxx | Rx = tableidxw(Rs,#Ii,#II):raw + hi->instruction = HEX_INS_S2_TABLEIDXW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 18) | (((hi_u32)&0xe0) >> 5)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s %s = tableidxw(%s,#0x%x,%s):raw %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8cc00040) { + // 10001100110sssssPP0iiiii010ddddd | Rd = togglebit(Rs,#Ii) + hi->instruction = HEX_INS_S2_TOGGLEBIT_I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = togglebit(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x85000000) { + // 10000101000sssssPP0iiiii000000dd | Pd = tstbit(Rs,#Ii) + hi->instruction = HEX_INS_S2_TSTBIT_I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = tstbit(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88800080) { + // 10001000100sssssPP000000100ddddd | Rd = vrndwh(Rss) + hi->instruction = HEX_INS_S2_VRNDPACKWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vrndwh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x888000c0) { + // 10001000100sssssPP000000110ddddd | Rd = vrndwh(Rss):sat + hi->instruction = HEX_INS_S2_VRNDPACKWHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vrndwh(%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x880000c0) { + // 10001000000sssssPP000000110ddddd | Rd = vsathb(Rss) + hi->instruction = HEX_INS_S2_VSATHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsathb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x800000e0) { + // 10000000000sssssPP000000111ddddd | Rdd = vsathb(Rss) + hi->instruction = HEX_INS_S2_VSATHB_NOPACK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsathb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88000000) { + // 10001000000sssssPP000000000ddddd | Rd = vsathub(Rss) + hi->instruction = HEX_INS_S2_VSATHUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsathub(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x80000080) { + // 10000000000sssssPP000000100ddddd | Rdd = vsathub(Rss) + hi->instruction = HEX_INS_S2_VSATHUB_NOPACK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsathub(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88000040) { + // 10001000000sssssPP000000010ddddd | Rd = vsatwh(Rss) + hi->instruction = HEX_INS_S2_VSATWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsatwh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x800000c0) { + // 10000000000sssssPP000000110ddddd | Rdd = vsatwh(Rss) + hi->instruction = HEX_INS_S2_VSATWH_NOPACK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsatwh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88000080) { + // 10001000000sssssPP000000100ddddd | Rd = vsatwuh(Rss) + hi->instruction = HEX_INS_S2_VSATWUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsatwuh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x800000a0) { + // 10000000000sssssPP000000101ddddd | Rdd = vsatwuh(Rss) + hi->instruction = HEX_INS_S2_VSATWUH_NOPACK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsatwuh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c4000e0) { + // 10001100010sssssPP000000111ddddd | Rd = vsplatb(Rs) + hi->instruction = HEX_INS_S2_VSPLATRB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsplatb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84400040) { + // 10000100010sssssPP000000010ddddd | Rdd = vsplath(Rs) + hi->instruction = HEX_INS_S2_VSPLATRH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsplath(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84000000) { + // 10000100000sssssPP000000000ddddd | Rdd = vsxtbh(Rs) + hi->instruction = HEX_INS_S2_VSXTBH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsxtbh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84000080) { + // 10000100000sssssPP000000100ddddd | Rdd = vsxthw(Rs) + hi->instruction = HEX_INS_S2_VSXTHW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsxthw(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88800040) { + // 10001000100sssssPP000000010ddddd | Rd = vtrunehb(Rss) + hi->instruction = HEX_INS_S2_VTRUNEHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vtrunehb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88800000) { + // 10001000100sssssPP000000000ddddd | Rd = vtrunohb(Rss) + hi->instruction = HEX_INS_S2_VTRUNOHB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vtrunohb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84000040) { + // 10000100000sssssPP000000010ddddd | Rdd = vzxtbh(Rs) + hi->instruction = HEX_INS_S2_VZXTBH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vzxtbh(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x840000c0) { + // 10000100000sssssPP000000110ddddd | Rdd = vzxthw(Rs) + hi->instruction = HEX_INS_S2_VZXTHW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vzxthw(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x8c200000) { + // 10001100001sssssPPiiiiii000ddddd | Rd = add(clb(Rs),#Ii) + hi->instruction = HEX_INS_S4_CLBADDI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(clb(%s),%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x88600040) { + // 10001000011sssssPPiiiiii010ddddd | Rd = add(clb(Rss),#Ii) + hi->instruction = HEX_INS_S4_CLBPADDI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(clb(%s),%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88600000) { + // 10001000011sssssPP000000000ddddd | Rd = normamt(Rss) + hi->instruction = HEX_INS_S4_CLBPNORM; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = normamt(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff802000) == 0x8d800000) { + // 100011011IIsssssPP0iiiiiIIIddddd | Rd = extract(Rs,#Ii,#II) + hi->instruction = HEX_INS_S4_EXTRACT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + sprintf(hi->mnem, "%s %s = extract(%s,#0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000000) == 0x8a000000) { + // 10001010IIIsssssPPiiiiiiIIIddddd | Rdd = extract(Rss,#Ii,#II) + hi->instruction = HEX_INS_S4_EXTRACTP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xe00000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + sprintf(hi->mnem, "%s %s = extract(%s,#0x%x,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0x85200000) { + // 10000101001sssssPP0iiiii000000dd | Pd = !tstbit(Rs,#Ii) + hi->instruction = HEX_INS_S4_NTSTBIT_I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = !tstbit(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe030e0) == 0x88600080) { + // 10001000011sssssPP00iiii100ddddd | Rd = vasrhub(Rss,#Ii):raw + hi->instruction = HEX_INS_S5_ASRHUB_RND_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vasrhub(%s,#0x%x):raw %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe030e0) == 0x886000a0) { + // 10001000011sssssPP00iiii101ddddd | Rd = vasrhub(Rss,#Ii):sat + hi->instruction = HEX_INS_S5_ASRHUB_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vasrhub(%s,#0x%x):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x88600060) { + // 10001000011sssssPP000000011ddddd | Rd = popcount(Rss) + hi->instruction = HEX_INS_S5_POPCOUNTP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = popcount(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe030e0) == 0x80200000) { + // 10000000001sssssPP00iiii000ddddd | Rdd = vasrh(Rss,#Ii):raw + hi->instruction = HEX_INS_S5_VASRHRND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = vasrh(%s,#0x%x):raw %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x80000060) { + // 10000000000sssssPPiiiiii011ddddd | Rdd = rol(Rss,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x820000e0) { + // 10000010000sssssPPiiiiii111xxxxx | Rxx += rol(Rss,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s += rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82400060) { + // 10000010010sssssPPiiiiii011xxxxx | Rxx &= rol(Rss,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s &= rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82000060) { + // 10000010000sssssPPiiiiii011xxxxx | Rxx -= rol(Rss,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s -= rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x824000e0) { + // 10000010010sssssPPiiiiii111xxxxx | Rxx |= rol(Rss,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s |= rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000e0) == 0x82800060) { + // 10000010100sssssPPiiiiii011xxxxx | Rxx ^= rol(Rss,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_XACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s ^= rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8c000060) { + // 10001100000sssssPP0iiiii011ddddd | Rd = rol(Rs,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s = rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e0000e0) { + // 10001110000sssssPP0iiiii111xxxxx | Rx += rol(Rs,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s += rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400060) { + // 10001110010sssssPP0iiiii011xxxxx | Rx &= rol(Rs,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s &= rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000060) { + // 10001110000sssssPP0iiiii011xxxxx | Rx -= rol(Rs,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s -= rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e4000e0) { + // 10001110010sssssPP0iiiii111xxxxx | Rx |= rol(Rs,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s |= rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x8e800060) { + // 10001110100sssssPP0iiiii011xxxxx | Rx ^= rol(Rs,#Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_XACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + sprintf(hi->mnem, "%s %s ^= rol(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x84400080) { + // 10000100010sssssPP000000100ddddd | Rdd = vsplatb(Rs) + hi->instruction = HEX_INS_S6_VSPLATRBP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsplatb(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0x9: + if ((hi_u32 & 0xffe03fe0) == 0x90000000) { + // 10010000000sssssPP000000000ddddd | Rdd = deallocframe(Rs):raw + hi->instruction = HEX_INS_L2_DEALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = deallocframe(%s):raw %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x90800000) { + // 10010ii0100sssssPPiiiiiiiiiyyyyy | Ryy = memb_fifo(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADALIGNB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memb_fifo(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9e800000) { + // 10011110100xxxxxPPu00000000yyyyy | Ryy = memb_fifo(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADALIGNB_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memb_fifo(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x98800000) { + // 10011000100xxxxxPPu0000iiiiyyyyy | Ryy = memb_fifo(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADALIGNB_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memb_fifo(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x98800200) { + // 10011000100xxxxxPPu00010000yyyyy | Ryy = memb_fifo(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADALIGNB_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memb_fifo(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9a800000) { + // 10011010100xxxxxPP00000iiiiyyyyy | Ryy = memb_fifo(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADALIGNB_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memb_fifo(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9c800000) { + // 10011100100xxxxxPPu00000000yyyyy | Ryy = memb_fifo(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADALIGNB_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memb_fifo(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x90400000) { + // 10010ii0010sssssPPiiiiiiiiiyyyyy | Ryy = memh_fifo(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADALIGNH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memh_fifo(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9e400000) { + // 10011110010xxxxxPPu00000000yyyyy | Ryy = memh_fifo(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADALIGNH_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memh_fifo(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x98400000) { + // 10011000010xxxxxPPu0000iiiiyyyyy | Ryy = memh_fifo(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADALIGNH_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memh_fifo(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x98400200) { + // 10011000010xxxxxPPu00010000yyyyy | Ryy = memh_fifo(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADALIGNH_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memh_fifo(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9a400000) { + // 10011010010xxxxxPP00000iiiiyyyyy | Ryy = memh_fifo(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADALIGNH_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memh_fifo(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9c400000) { + // 10011100010xxxxxPPu00000000yyyyy | Ryy = memh_fifo(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADALIGNH_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memh_fifo(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x90200000) { + // 10010ii0001sssssPPiiiiiiiiiddddd | Rd = membh(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADBSW2_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = membh(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9e200000) { + // 10011110001xxxxxPPu00000000ddddd | Rd = membh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADBSW2_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = membh(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x98200000) { + // 10011000001xxxxxPPu0000iiiiddddd | Rd = membh(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBSW2_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = membh(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x98200200) { + // 10011000001xxxxxPPu00010000ddddd | Rd = membh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBSW2_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = membh(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9a200000) { + // 10011010001xxxxxPP00000iiiiddddd | Rd = membh(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADBSW2_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = membh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9c200000) { + // 10011100001xxxxxPPu00000000ddddd | Rd = membh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADBSW2_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = membh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x90e00000) { + // 10010ii0111sssssPPiiiiiiiiiddddd | Rdd = membh(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADBSW4_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 12)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 12); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = membh(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9ee00000) { + // 10011110111xxxxxPPu00000000ddddd | Rdd = membh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADBSW4_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = membh(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x98e00000) { + // 10011000111xxxxxPPu0000iiiiddddd | Rdd = membh(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBSW4_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = membh(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x98e00200) { + // 10011000111xxxxxPPu00010000ddddd | Rdd = membh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBSW4_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = membh(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9ae00000) { + // 10011010111xxxxxPP00000iiiiddddd | Rdd = membh(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADBSW4_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = membh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9ce00000) { + // 10011100111xxxxxPPu00000000ddddd | Rdd = membh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADBSW4_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = membh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x90600000) { + // 10010ii0011sssssPPiiiiiiiiiddddd | Rd = memubh(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADBZW2_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memubh(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9e600000) { + // 10011110011xxxxxPPu00000000ddddd | Rd = memubh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADBZW2_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memubh(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x98600000) { + // 10011000011xxxxxPPu0000iiiiddddd | Rd = memubh(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBZW2_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memubh(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x98600200) { + // 10011000011xxxxxPPu00010000ddddd | Rd = memubh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBZW2_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memubh(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9a600000) { + // 10011010011xxxxxPP00000iiiiddddd | Rd = memubh(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADBZW2_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memubh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9c600000) { + // 10011100011xxxxxPPu00000000ddddd | Rd = memubh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADBZW2_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memubh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x90a00000) { + // 10010ii0101sssssPPiiiiiiiiiddddd | Rdd = memubh(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADBZW4_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 12)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 12); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memubh(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9ea00000) { + // 10011110101xxxxxPPu00000000ddddd | Rdd = memubh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADBZW4_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memubh(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x98a00000) { + // 10011000101xxxxxPPu0000iiiiddddd | Rdd = memubh(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBZW4_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memubh(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x98a00200) { + // 10011000101xxxxxPPu00010000ddddd | Rdd = memubh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBZW4_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memubh(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9aa00000) { + // 10011010101xxxxxPP00000iiiiddddd | Rdd = memubh(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADBZW4_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memubh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9ca00000) { + // 10011100101xxxxxPPu00000000ddddd | Rdd = memubh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADBZW4_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memubh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x91000000) { + // 10010ii1000sssssPPiiiiiiiiiddddd | Rd = memb(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADRB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memb(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f000000) { + // 10011111000xxxxxPPu00000000ddddd | Rd = memb(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRB_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memb(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x99000000) { + // 10011001000xxxxxPPu0000iiiiddddd | Rd = memb(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRB_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memb(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x99000200) { + // 10011001000xxxxxPPu00010000ddddd | Rd = memb(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRB_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memb(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9b000000) { + // 10011011000xxxxxPP00000iiiiddddd | Rd = memb(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADRB_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memb(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d000000) { + // 10011101000xxxxxPPu00000000ddddd | Rd = memb(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRB_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memb(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x91c00000) { + // 10010ii1110sssssPPiiiiiiiiiddddd | Rdd = memd(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADRD_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 13)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 13); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memd(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9fc00000) { + // 10011111110xxxxxPPu00000000ddddd | Rdd = memd(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRD_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memd(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x99c00000) { + // 10011001110xxxxxPPu0000iiiiddddd | Rdd = memd(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRD_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memd(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x99c00200) { + // 10011001110xxxxxPPu00010000ddddd | Rdd = memd(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRD_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memd(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9bc00000) { + // 10011011110xxxxxPP00000iiiiddddd | Rdd = memd(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADRD_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memd(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9dc00000) { + // 10011101110xxxxxPPu00000000ddddd | Rdd = memd(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRD_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memd(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x91400000) { + // 10010ii1010sssssPPiiiiiiiiiddddd | Rd = memh(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADRH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memh(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f400000) { + // 10011111010xxxxxPPu00000000ddddd | Rd = memh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRH_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memh(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x99400000) { + // 10011001010xxxxxPPu0000iiiiddddd | Rd = memh(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRH_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memh(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x99400200) { + // 10011001010xxxxxPPu00010000ddddd | Rd = memh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRH_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memh(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9b400000) { + // 10011011010xxxxxPP00000iiiiddddd | Rd = memh(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADRH_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d400000) { + // 10011101010xxxxxPPu00000000ddddd | Rd = memh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRH_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x91800000) { + // 10010ii1100sssssPPiiiiiiiiiddddd | Rd = memw(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADRI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 12)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 12); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memw(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f800000) { + // 10011111100xxxxxPPu00000000ddddd | Rd = memw(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRI_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memw(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x99800000) { + // 10011001100xxxxxPPu0000iiiiddddd | Rd = memw(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRI_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memw(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x99800200) { + // 10011001100xxxxxPPu00010000ddddd | Rd = memw(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRI_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memw(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9b800000) { + // 10011011100xxxxxPP00000iiiiddddd | Rd = memw(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADRI_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memw(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d800000) { + // 10011101100xxxxxPPu00000000ddddd | Rd = memw(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRI_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memw(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x91200000) { + // 10010ii1001sssssPPiiiiiiiiiddddd | Rd = memub(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADRUB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memub(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f200000) { + // 10011111001xxxxxPPu00000000ddddd | Rd = memub(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRUB_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memub(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x99200000) { + // 10011001001xxxxxPPu0000iiiiddddd | Rd = memub(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRUB_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memub(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x99200200) { + // 10011001001xxxxxPPu00010000ddddd | Rd = memub(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRUB_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memub(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9b200000) { + // 10011011001xxxxxPP00000iiiiddddd | Rd = memub(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADRUB_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memub(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d200000) { + // 10011101001xxxxxPPu00000000ddddd | Rd = memub(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRUB_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memub(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0x91600000) { + // 10010ii1011sssssPPiiiiiiiiiddddd | Rd = memuh(Rs+#Ii) + hi->instruction = HEX_INS_L2_LOADRUH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memuh(%s+%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f600000) { + // 10011111011xxxxxPPu00000000ddddd | Rd = memuh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRUH_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memuh(%s++%s:brev) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01e00) == 0x99600000) { + // 10011001011xxxxxPPu0000iiiiddddd | Rd = memuh(Rx++#Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRUH_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memuh(%s++%s:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_mod_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x99600200) { + // 10011001011xxxxxPPu00010000ddddd | Rd = memuh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRUH_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memuh(%s++I:circ(%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03e00) == 0x9b600000) { + // 10011011011xxxxxPP00000iiiiddddd | Rd = memuh(Rx++#Ii) + hi->instruction = HEX_INS_L2_LOADRUH_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = memuh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d600000) { + // 10011101011xxxxxPPu00000000ddddd | Rd = memuh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRUH_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s %s = memuh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x92000800) { + // 10010010000sssssPP001000000ddddd | Rd = memw_aq(Rs) + hi->instruction = HEX_INS_L2_LOADW_AQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = memw_aq(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x92000000) { + // 10010010000sssssPP000000000ddddd | Rd = memw_locked(Rs) + hi->instruction = HEX_INS_L2_LOADW_LOCKED; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = memw_locked(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b002800) { + // 10011011000xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memb(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRBF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = memb(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b003800) { + // 10011011000xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memb(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRBFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) %s = memb(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b002000) { + // 10011011000xxxxxPP100ttiiiiddddd | if (Pt) Rd = memb(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRBT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = memb(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b003000) { + // 10011011000xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memb(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRBTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) %s = memb(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9bc02800) { + // 10011011110xxxxxPP101ttiiiiddddd | if (!Pt) Rdd = memd(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRDF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 6)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = memd(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9bc03800) { + // 10011011110xxxxxPP111ttiiiiddddd | if (!Pt.new) Rdd = memd(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRDFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 6)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) %s = memd(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9bc02000) { + // 10011011110xxxxxPP100ttiiiiddddd | if (Pt) Rdd = memd(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRDT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 6)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = memd(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9bc03000) { + // 10011011110xxxxxPP110ttiiiiddddd | if (Pt.new) Rdd = memd(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRDTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 6)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) %s = memd(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b402800) { + // 10011011010xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memh(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRHF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = memh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b403800) { + // 10011011010xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memh(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRHFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) %s = memh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b402000) { + // 10011011010xxxxxPP100ttiiiiddddd | if (Pt) Rd = memh(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRHT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = memh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b403000) { + // 10011011010xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memh(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRHTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) %s = memh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b802800) { + // 10011011100xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memw(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRIF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = memw(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b803800) { + // 10011011100xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memw(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRIFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) %s = memw(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b802000) { + // 10011011100xxxxxPP100ttiiiiddddd | if (Pt) Rd = memw(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRIT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = memw(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b803000) { + // 10011011100xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memw(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRITNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) %s = memw(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b202800) { + // 10011011001xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memub(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRUBF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = memub(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b203800) { + // 10011011001xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memub(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRUBFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) %s = memub(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b202000) { + // 10011011001xxxxxPP100ttiiiiddddd | if (Pt) Rd = memub(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRUBT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = memub(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b203000) { + // 10011011001xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memub(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRUBTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) %s = memub(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b602800) { + // 10011011011xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memuh(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRUHF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s) %s = memuh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b603800) { + // 10011011011xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memuh(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRUHFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (!%s.new) %s = memuh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b602000) { + // 10011011011xxxxxPP100ttiiiiddddd | if (Pt) Rd = memuh(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRUHT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s) %s = memuh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x9b603000) { + // 10011011011xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memuh(Rx++#Ii) + hi->instruction = HEX_INS_L2_PLOADRUHTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s if (%s.new) %s = memuh(%s++%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9a801000) { + // 10011010100eeeeePP01IIII0IIyyyyy | Ryy = memb_fifo(Re=#II) + hi->instruction = HEX_INS_L4_LOADALIGNB_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memb_fifo(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9c801000) { + // 10011100100tttttPPi1IIIIiIIyyyyy | Ryy = memb_fifo(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADALIGNB_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memb_fifo(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9a401000) { + // 10011010010eeeeePP01IIII0IIyyyyy | Ryy = memh_fifo(Re=#II) + hi->instruction = HEX_INS_L4_LOADALIGNH_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memh_fifo(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9c401000) { + // 10011100010tttttPPi1IIIIiIIyyyyy | Ryy = memh_fifo(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADALIGNH_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memh_fifo(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9a201000) { + // 10011010001eeeeePP01IIII0IIddddd | Rd = membh(Re=#II) + hi->instruction = HEX_INS_L4_LOADBSW2_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = membh(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9c201000) { + // 10011100001tttttPPi1IIIIiIIddddd | Rd = membh(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADBSW2_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = membh(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9ae01000) { + // 10011010111eeeeePP01IIII0IIddddd | Rdd = membh(Re=#II) + hi->instruction = HEX_INS_L4_LOADBSW4_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = membh(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9ce01000) { + // 10011100111tttttPPi1IIIIiIIddddd | Rdd = membh(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADBSW4_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = membh(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9a601000) { + // 10011010011eeeeePP01IIII0IIddddd | Rd = memubh(Re=#II) + hi->instruction = HEX_INS_L4_LOADBZW2_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memubh(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9c601000) { + // 10011100011tttttPPi1IIIIiIIddddd | Rd = memubh(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADBZW2_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memubh(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9aa01000) { + // 10011010101eeeeePP01IIII0IIddddd | Rdd = memubh(Re=#II) + hi->instruction = HEX_INS_L4_LOADBZW4_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memubh(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9ca01000) { + // 10011100101tttttPPi1IIIIiIIddddd | Rdd = memubh(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADBZW4_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memubh(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x92001800) { + // 10010010000sssssPP011000000ddddd | Rdd = memd_aq(Rs) + hi->instruction = HEX_INS_L4_LOADD_AQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = memd_aq(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x92001000) { + // 10010010000sssssPP010000000ddddd | Rdd = memd_locked(Rs) + hi->instruction = HEX_INS_L4_LOADD_LOCKED; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = memd_locked(%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9b001000) { + // 10011011000eeeeePP01IIII0IIddddd | Rd = memb(Re=#II) + hi->instruction = HEX_INS_L4_LOADRB_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memb(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9d001000) { + // 10011101000tttttPPi1IIIIiIIddddd | Rd = memb(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADRB_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memb(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9bc01000) { + // 10011011110eeeeePP01IIII0IIddddd | Rdd = memd(Re=#II) + hi->instruction = HEX_INS_L4_LOADRD_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memd(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9dc01000) { + // 10011101110tttttPPi1IIIIiIIddddd | Rdd = memd(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADRD_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memd(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9b401000) { + // 10011011010eeeeePP01IIII0IIddddd | Rd = memh(Re=#II) + hi->instruction = HEX_INS_L4_LOADRH_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memh(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9d401000) { + // 10011101010tttttPPi1IIIIiIIddddd | Rd = memh(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADRH_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memh(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9b801000) { + // 10011011100eeeeePP01IIII0IIddddd | Rd = memw(Re=#II) + hi->instruction = HEX_INS_L4_LOADRI_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memw(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9d801000) { + // 10011101100tttttPPi1IIIIiIIddddd | Rd = memw(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADRI_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memw(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9b201000) { + // 10011011001eeeeePP01IIII0IIddddd | Rd = memub(Re=#II) + hi->instruction = HEX_INS_L4_LOADRUB_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memub(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9d201000) { + // 10011101001tttttPPi1IIIIiIIddddd | Rd = memub(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADRUB_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memub(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03080) == 0x9b601000) { + // 10011011011eeeeePP01IIII0IIddddd | Rd = memuh(Re=#II) + hi->instruction = HEX_INS_L4_LOADRUH_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memuh(%s=##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01000) == 0x9d601000) { + // 10011101011tttttPPi1IIIIiIIddddd | Rd = memuh(Rt<<#Ii+#II) + hi->instruction = HEX_INS_L4_LOADRUH_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = memuh(%s<<#0x%x+##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f002880) { + // 10011111000iiiiiPP101tti100ddddd | if (!Pt) Rd = memb(#Ii) + hi->instruction = HEX_INS_L4_PLOADRBF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memb(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f003880) { + // 10011111000iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memb(#Ii) + hi->instruction = HEX_INS_L4_PLOADRBFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memb(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f002080) { + // 10011111000iiiiiPP100tti100ddddd | if (Pt) Rd = memb(#Ii) + hi->instruction = HEX_INS_L4_PLOADRBT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memb(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f003080) { + // 10011111000iiiiiPP110tti100ddddd | if (Pt.new) Rd = memb(#Ii) + hi->instruction = HEX_INS_L4_PLOADRBTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memb(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9fc02880) { + // 10011111110iiiiiPP101tti100ddddd | if (!Pt) Rdd = memd(#Ii) + hi->instruction = HEX_INS_L4_PLOADRDF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memd(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9fc03880) { + // 10011111110iiiiiPP111tti100ddddd | if (!Pt.new) Rdd = memd(#Ii) + hi->instruction = HEX_INS_L4_PLOADRDFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memd(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9fc02080) { + // 10011111110iiiiiPP100tti100ddddd | if (Pt) Rdd = memd(#Ii) + hi->instruction = HEX_INS_L4_PLOADRDT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memd(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9fc03080) { + // 10011111110iiiiiPP110tti100ddddd | if (Pt.new) Rdd = memd(#Ii) + hi->instruction = HEX_INS_L4_PLOADRDTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memd(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f402880) { + // 10011111010iiiiiPP101tti100ddddd | if (!Pt) Rd = memh(#Ii) + hi->instruction = HEX_INS_L4_PLOADRHF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f403880) { + // 10011111010iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memh(#Ii) + hi->instruction = HEX_INS_L4_PLOADRHFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f402080) { + // 10011111010iiiiiPP100tti100ddddd | if (Pt) Rd = memh(#Ii) + hi->instruction = HEX_INS_L4_PLOADRHT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f403080) { + // 10011111010iiiiiPP110tti100ddddd | if (Pt.new) Rd = memh(#Ii) + hi->instruction = HEX_INS_L4_PLOADRHTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f802880) { + // 10011111100iiiiiPP101tti100ddddd | if (!Pt) Rd = memw(#Ii) + hi->instruction = HEX_INS_L4_PLOADRIF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memw(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f803880) { + // 10011111100iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memw(#Ii) + hi->instruction = HEX_INS_L4_PLOADRIFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memw(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f802080) { + // 10011111100iiiiiPP100tti100ddddd | if (Pt) Rd = memw(#Ii) + hi->instruction = HEX_INS_L4_PLOADRIT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memw(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f803080) { + // 10011111100iiiiiPP110tti100ddddd | if (Pt.new) Rd = memw(#Ii) + hi->instruction = HEX_INS_L4_PLOADRITNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memw(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f202880) { + // 10011111001iiiiiPP101tti100ddddd | if (!Pt) Rd = memub(#Ii) + hi->instruction = HEX_INS_L4_PLOADRUBF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memub(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f203880) { + // 10011111001iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memub(#Ii) + hi->instruction = HEX_INS_L4_PLOADRUBFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memub(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f202080) { + // 10011111001iiiiiPP100tti100ddddd | if (Pt) Rd = memub(#Ii) + hi->instruction = HEX_INS_L4_PLOADRUBT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memub(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f203080) { + // 10011111001iiiiiPP110tti100ddddd | if (Pt.new) Rd = memub(#Ii) + hi->instruction = HEX_INS_L4_PLOADRUBTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memub(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f602880) { + // 10011111011iiiiiPP101tti100ddddd | if (!Pt) Rd = memuh(#Ii) + hi->instruction = HEX_INS_L4_PLOADRUHF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s) %s = memuh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f603880) { + // 10011111011iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memuh(#Ii) + hi->instruction = HEX_INS_L4_PLOADRUHFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (!%s.new) %s = memuh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f602080) { + // 10011111011iiiiiPP100tti100ddddd | if (Pt) Rd = memuh(#Ii) + hi->instruction = HEX_INS_L4_PLOADRUHT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s) %s = memuh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038e0) == 0x9f603080) { + // 10011111011iiiiiPP110tti100ddddd | if (Pt.new) Rd = memuh(#Ii) + hi->instruction = HEX_INS_L4_PLOADRUHTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s if (%s.new) %s = memuh(##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fe0) == 0x96000000) { + // 10010110000sssssPP000000000ddddd | Rdd = dealloc_return(Rs):raw + hi->instruction = HEX_INS_L4_RETURN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = dealloc_return(%s):raw %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x96003000) { + // 10010110000sssssPP1100vv000ddddd | if (!Pv) Rdd = dealloc_return(Rs):raw + hi->instruction = HEX_INS_L4_RETURN_F; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) %s = dealloc_return(%s):raw %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x96002800) { + // 10010110000sssssPP1010vv000ddddd | if (!Pv.new) Rdd = dealloc_return(Rs):nt:raw + hi->instruction = HEX_INS_L4_RETURN_FNEW_PNT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) %s = dealloc_return(%s):nt:raw %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x96003800) { + // 10010110000sssssPP1110vv000ddddd | if (!Pv.new) Rdd = dealloc_return(Rs):t:raw + hi->instruction = HEX_INS_L4_RETURN_FNEW_PT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) %s = dealloc_return(%s):t:raw %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x96001000) { + // 10010110000sssssPP0100vv000ddddd | if (Pv) Rdd = dealloc_return(Rs):raw + hi->instruction = HEX_INS_L4_RETURN_T; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) %s = dealloc_return(%s):raw %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x96000800) { + // 10010110000sssssPP0010vv000ddddd | if (Pv.new) Rdd = dealloc_return(Rs):nt:raw + hi->instruction = HEX_INS_L4_RETURN_TNEW_PNT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) %s = dealloc_return(%s):nt:raw %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03ce0) == 0x96001800) { + // 10010110000sssssPP0110vv000ddddd | if (Pv.new) Rdd = dealloc_return(Rs):t:raw + hi->instruction = HEX_INS_L4_RETURN_TNEW_PT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) %s = dealloc_return(%s):t:raw %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0x92000040) { + // 10010010000sssssPPuttttt01000000 | memcpy(Rs,Rt,Mu) + hi->instruction = HEX_INS_L6_MEMCPY; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + sprintf(hi->mnem, "%s memcpy(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0x92000020) { + // 10010010000sssssPP0uuuuu001ddddd | Rd = vextract(Vu,Rs) + hi->instruction = HEX_INS_V6_EXTRACTW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vextract(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0x94000000) { + // 10010100000sssssPP000iiiiiiiiiii | dcfetch(Rs+#Ii) + hi->instruction = HEX_INS_Y2_DCFETCHBO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7ff) >> 0) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s dcfetch(%s+#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xa: + if ((hi_u32 & 0xffe020fc) == 0xa0e0000c) { + // 10100000111sssssPP0000011 | release(Rs):at + hi->instruction = HEX_INS_R6_RELEASE_AT_VI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s release(%s):at %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xa0e0002c) { + // 10100000111sssssPP0001011 | release(Rs):st + hi->instruction = HEX_INS_R6_RELEASE_ST_VI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s release(%s):st %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03800) == 0xa0800000) { + // 10100000100xxxxxPP000iiiiiiiiiii | allocframe(Rx,#Ii):raw + hi->instruction = HEX_INS_S2_ALLOCFRAME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7ff) >> 0) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + sprintf(hi->mnem, "%s allocframe(%s,#0x%x):raw %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab002004) { + // 10101011000xxxxxPP1ttttt0iiii1vv | if (!Pv) memb(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memb(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab002084) { + // 10101011000xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memb(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memb(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba02004) { + // 10101011101xxxxxPP100ttt0iiii1vv | if (!Pv) memb(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memb(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba02084) { + // 10101011101xxxxxPP100ttt1iiii1vv | if (!Pv.new) memb(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memb(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba02000) { + // 10101011101xxxxxPP100ttt0iiii0vv | if (Pv) memb(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s) memb(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba02080) { + // 10101011101xxxxxPP100ttt1iiii0vv | if (Pv.new) memb(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memb(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab002000) { + // 10101011000xxxxxPP1ttttt0iiii0vv | if (Pv) memb(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memb(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab002080) { + // 10101011000xxxxxPP1ttttt1iiii0vv | if (Pv.new) memb(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memb(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xabc02004) { + // 10101011110xxxxxPP1ttttt0iiii1vv | if (!Pv) memd(Rx++#Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (!%s) memd(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xabc02084) { + // 10101011110xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memd(Rx++#Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (!%s.new) memd(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xabc02000) { + // 10101011110xxxxxPP1ttttt0iiii0vv | if (Pv) memd(Rx++#Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (%s) memd(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xabc02080) { + // 10101011110xxxxxPP1ttttt1iiii0vv | if (Pv.new) memd(Rx++#Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (%s.new) memd(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab602004) { + // 10101011011xxxxxPP1ttttt0iiii1vv | if (!Pv) memh(Rx++#Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memh(%s++%s) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab602084) { + // 10101011011xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memh(Rx++#Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memh(%s++%s) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab602000) { + // 10101011011xxxxxPP1ttttt0iiii0vv | if (Pv) memh(Rx++#Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memh(%s++%s) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab602080) { + // 10101011011xxxxxPP1ttttt1iiii0vv | if (Pv.new) memh(Rx++#Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memh(%s++%s) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab402004) { + // 10101011010xxxxxPP1ttttt0iiii1vv | if (!Pv) memh(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memh(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab402084) { + // 10101011010xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memh(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memh(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba02804) { + // 10101011101xxxxxPP101ttt0iiii1vv | if (!Pv) memh(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memh(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba02884) { + // 10101011101xxxxxPP101ttt1iiii1vv | if (!Pv.new) memh(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memh(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba02800) { + // 10101011101xxxxxPP101ttt0iiii0vv | if (Pv) memh(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s) memh(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba02880) { + // 10101011101xxxxxPP101ttt1iiii0vv | if (Pv.new) memh(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memh(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab402000) { + // 10101011010xxxxxPP1ttttt0iiii0vv | if (Pv) memh(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memh(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab402080) { + // 10101011010xxxxxPP1ttttt1iiii0vv | if (Pv.new) memh(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memh(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab802004) { + // 10101011100xxxxxPP1ttttt0iiii1vv | if (!Pv) memw(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memw(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab802084) { + // 10101011100xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memw(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memw(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba03004) { + // 10101011101xxxxxPP110ttt0iiii1vv | if (!Pv) memw(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memw(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba03084) { + // 10101011101xxxxxPP110ttt1iiii1vv | if (!Pv.new) memw(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWFNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memw(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba03000) { + // 10101011101xxxxxPP110ttt0iiii0vv | if (Pv) memw(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s) memw(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03884) == 0xaba03080) { + // 10101011101xxxxxPP110ttt1iiii0vv | if (Pv.new) memw(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWTNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memw(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab802000) { + // 10101011100xxxxxPP1ttttt0iiii0vv | if (Pv) memw(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIT_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memw(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02084) == 0xab802080) { + // 10101011100xxxxxPP1ttttt1iiii0vv | if (Pv.new) memw(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERITNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memw(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0xa1000000) { + // 10100ii1000sssssPPitttttiiiiiiii | memb(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S2_STORERB_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xaf000000) { + // 10101111000xxxxxPPuttttt00000000 | memb(Rx++Mu:brev) = Rt + hi->instruction = HEX_INS_S2_STORERB_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(%s++%s:brev) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00087) == 0xa9000000) { + // 10101001000xxxxxPPuttttt0iiii000 | memb(Rx++#Ii:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERB_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(%s++%s:circ(%s)) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xa9000002) { + // 10101001000xxxxxPPuttttt00000010 | memb(Rx++I:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERB_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(%s++I:circ(%s)) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02087) == 0xab000000) { + // 10101011000xxxxxPP0ttttt0iiii000 | memb(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_STORERB_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xad000000) { + // 10101101000xxxxxPPuttttt00000000 | memb(Rx++Mu) = Rt + hi->instruction = HEX_INS_S2_STORERB_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e01800) == 0xa1a00000) { + // 10100ii1101sssssPPi00tttiiiiiiii | memb(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 10); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(%s+%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0xafa00000) { + // 10101111101xxxxxPPu00ttt00000000 | memb(Rx++Mu:brev) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(%s++%s:brev) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01887) == 0xa9a00000) { + // 10101001101xxxxxPPu00ttt0iiii000 | memb(Rx++#Ii:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(%s++%s:circ(%s)) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0xa9a00002) { + // 10101001101xxxxxPPu00ttt00000010 | memb(Rx++I:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(%s++I:circ(%s)) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03887) == 0xaba00000) { + // 10101011101xxxxxPP000ttt0iiii000 | memb(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 3); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0xada00000) { + // 10101101101xxxxxPPu00ttt00000000 | memb(Rx++Mu) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0xa1c00000) { + // 10100ii1110sssssPPitttttiiiiiiii | memd(Rs+#Ii) = Rtt + hi->instruction = HEX_INS_S2_STORERD_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 13)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 13); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xafc00000) { + // 10101111110xxxxxPPuttttt00000000 | memd(Rx++Mu:brev) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(%s++%s:brev) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00087) == 0xa9c00000) { + // 10101001110xxxxxPPuttttt0iiii000 | memd(Rx++#Ii:circ(Mu)) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 6)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(%s++%s:circ(%s)) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_mod_regs(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xa9c00002) { + // 10101001110xxxxxPPuttttt00000010 | memd(Rx++I:circ(Mu)) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(%s++I:circ(%s)) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02087) == 0xabc00000) { + // 10101011110xxxxxPP0ttttt0iiii000 | memd(Rx++#Ii) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 6)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 6); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xadc00000) { + // 10101101110xxxxxPPuttttt00000000 | memd(Rx++Mu) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0xa1600000) { + // 10100ii1011sssssPPitttttiiiiiiii | memh(Rs+#Ii) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 11)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s+%s) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xaf600000) { + // 10101111011xxxxxPPuttttt00000000 | memh(Rx++Mu:brev) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++%s:brev) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00087) == 0xa9600000) { + // 10101001011xxxxxPPuttttt0iiii000 | memh(Rx++#Ii:circ(Mu)) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++%s:circ(%s)) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xa9600002) { + // 10101001011xxxxxPPuttttt00000010 | memh(Rx++I:circ(Mu)) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++I:circ(%s)) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02087) == 0xab600000) { + // 10101011011xxxxxPP0ttttt0iiii000 | memh(Rx++#Ii) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++%s) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xad600000) { + // 10101101011xxxxxPPuttttt00000000 | memh(Rx++Mu) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++%s) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0xa1400000) { + // 10100ii1010sssssPPitttttiiiiiiii | memh(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S2_STORERH_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 11)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xaf400000) { + // 10101111010xxxxxPPuttttt00000000 | memh(Rx++Mu:brev) = Rt + hi->instruction = HEX_INS_S2_STORERH_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++%s:brev) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00087) == 0xa9400000) { + // 10101001010xxxxxPPuttttt0iiii000 | memh(Rx++#Ii:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERH_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++%s:circ(%s)) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xa9400002) { + // 10101001010xxxxxPPuttttt00000010 | memh(Rx++I:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERH_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++I:circ(%s)) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02087) == 0xab400000) { + // 10101011010xxxxxPP0ttttt0iiii000 | memh(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_STORERH_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xad400000) { + // 10101101010xxxxxPPuttttt00000000 | memh(Rx++Mu) = Rt + hi->instruction = HEX_INS_S2_STORERH_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e01800) == 0xa1a00800) { + // 10100ii1101sssssPPi01tttiiiiiiii | memh(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 11)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 11); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(%s+%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0xafa00800) { + // 10101111101xxxxxPPu01ttt00000000 | memh(Rx++Mu:brev) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(%s++%s:brev) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01887) == 0xa9a00800) { + // 10101001101xxxxxPPu01ttt0iiii000 | memh(Rx++#Ii:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(%s++%s:circ(%s)) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0xa9a00802) { + // 10101001101xxxxxPPu01ttt00000010 | memh(Rx++I:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(%s++I:circ(%s)) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03887) == 0xaba00800) { + // 10101011101xxxxxPP001ttt0iiii000 | memh(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 4); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0xada00800) { + // 10101101101xxxxxPPu01ttt00000000 | memh(Rx++Mu) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e00000) == 0xa1800000) { + // 10100ii1100sssssPPitttttiiiiiiii | memw(Rs+#Ii) = Rt + hi->instruction = HEX_INS_S2_STORERI_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 12)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 12); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(%s+%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xaf800000) { + // 10101111100xxxxxPPuttttt00000000 | memw(Rx++Mu:brev) = Rt + hi->instruction = HEX_INS_S2_STORERI_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(%s++%s:brev) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00087) == 0xa9800000) { + // 10101001100xxxxxPPuttttt0iiii000 | memw(Rx++#Ii:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERI_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(%s++%s:circ(%s)) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xa9800002) { + // 10101001100xxxxxPPuttttt00000010 | memw(Rx++I:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERI_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(%s++I:circ(%s)) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02087) == 0xab800000) { + // 10101011100xxxxxPP0ttttt0iiii000 | memw(Rx++#Ii) = Rt + hi->instruction = HEX_INS_S2_STORERI_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000ff) == 0xad800000) { + // 10101101100xxxxxPPuttttt00000000 | memw(Rx++Mu) = Rt + hi->instruction = HEX_INS_S2_STORERI_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(%s++%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xf9e01800) == 0xa1a01000) { + // 10100ii1101sssssPPi10tttiiiiiiii | memw(Rs+#Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_IO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 12)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 12); + } + hex_op_extend(&(hi->ops[1]), false); // Extension possible + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(%s+%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0xafa01000) { + // 10101111101xxxxxPPu10ttt00000000 | memw(Rx++Mu:brev) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(%s++%s:brev) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01887) == 0xa9a01000) { + // 10101001101xxxxxPPu10ttt0iiii000 | memw(Rx++#Ii:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(%s++%s:circ(%s)) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0xa9a01002) { + // 10101001101xxxxxPPu10ttt00000010 | memw(Rx++I:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(%s++I:circ(%s)) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03887) == 0xaba01000) { + // 10101011101xxxxxPP010ttt0iiii000 | memw(Rx++#Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe018ff) == 0xada01000) { + // 10101101101xxxxxPPu10ttt00000000 | memw(Rx++Mu) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(%s++%s) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xa0a00000) { + // 10100000101sssssPP0ttttt000000dd | memw_locked(Rs,Pd) = Rt + hi->instruction = HEX_INS_S2_STOREW_LOCKED; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw_locked(%s,%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xa0a00008) { + // 10100000101sssssPP0ttttt000010 | memw_rl(Rs):at = Rt + hi->instruction = HEX_INS_S2_STOREW_RL_AT_VI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw_rl(%s):at = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xa0a00028) { + // 10100000101sssssPP0ttttt001010 | memw_rl(Rs):st = Rt + hi->instruction = HEX_INS_S2_STOREW_RL_ST_VI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw_rl(%s):st = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf000084) { + // 10101111000000iiPP0ttttt1iiii1vv | if (!Pv) memb(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memb(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf002084) { + // 10101111000000iiPP1ttttt1iiii1vv | if (!Pv.new) memb(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memb(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa00084) { + // 10101111101000iiPP000ttt1iiii1vv | if (!Pv) memb(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memb(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa02084) { + // 10101111101000iiPP100ttt1iiii1vv | if (!Pv.new) memb(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memb(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa00080) { + // 10101111101000iiPP000ttt1iiii0vv | if (Pv) memb(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s) memb(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa02080) { + // 10101111101000iiPP100ttt1iiii0vv | if (Pv.new) memb(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memb(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf000080) { + // 10101111000000iiPP0ttttt1iiii0vv | if (Pv) memb(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memb(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf002080) { + // 10101111000000iiPP1ttttt1iiii0vv | if (Pv.new) memb(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memb(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xafc00084) { + // 10101111110000iiPP0ttttt1iiii1vv | if (!Pv) memd(#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (!%s) memd(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xafc02084) { + // 10101111110000iiPP1ttttt1iiii1vv | if (!Pv.new) memd(#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (!%s.new) memd(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xafc00080) { + // 10101111110000iiPP0ttttt1iiii0vv | if (Pv) memd(#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (%s) memd(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xafc02080) { + // 10101111110000iiPP1ttttt1iiii0vv | if (Pv.new) memd(#Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s if (%s.new) memd(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf600084) { + // 10101111011000iiPP0ttttt1iiii1vv | if (!Pv) memh(#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memh(##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf602084) { + // 10101111011000iiPP1ttttt1iiii1vv | if (!Pv.new) memh(#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memh(##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf600080) { + // 10101111011000iiPP0ttttt1iiii0vv | if (Pv) memh(#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memh(##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf602080) { + // 10101111011000iiPP1ttttt1iiii0vv | if (Pv.new) memh(#Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memh(##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf400084) { + // 10101111010000iiPP0ttttt1iiii1vv | if (!Pv) memh(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memh(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf402084) { + // 10101111010000iiPP1ttttt1iiii1vv | if (!Pv.new) memh(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memh(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa00884) { + // 10101111101000iiPP001ttt1iiii1vv | if (!Pv) memh(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memh(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa02884) { + // 10101111101000iiPP101ttt1iiii1vv | if (!Pv.new) memh(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memh(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa00880) { + // 10101111101000iiPP001ttt1iiii0vv | if (Pv) memh(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s) memh(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa02880) { + // 10101111101000iiPP101ttt1iiii0vv | if (Pv.new) memh(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memh(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf400080) { + // 10101111010000iiPP0ttttt1iiii0vv | if (Pv) memh(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memh(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf402080) { + // 10101111010000iiPP1ttttt1iiii0vv | if (Pv.new) memh(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memh(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf800084) { + // 10101111100000iiPP0ttttt1iiii1vv | if (!Pv) memw(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) memw(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf802084) { + // 10101111100000iiPP1ttttt1iiii1vv | if (!Pv.new) memw(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) memw(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa01084) { + // 10101111101000iiPP010ttt1iiii1vv | if (!Pv) memw(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWF_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s) memw(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa03084) { + // 10101111101000iiPP110ttt1iiii1vv | if (!Pv.new) memw(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWFNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (!%s.new) memw(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa01080) { + // 10101111101000iiPP010ttt1iiii0vv | if (Pv) memw(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s) memw(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc3884) == 0xafa03080) { + // 10101111101000iiPP110ttt1iiii0vv | if (Pv.new) memw(#Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWTNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s if (%s.new) memw(##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf800080) { + // 10101111100000iiPP0ttttt1iiii0vv | if (Pv) memw(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIT_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) memw(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xfffc2084) == 0xaf802080) { + // 10101111100000iiPP1ttttt1iiii0vv | if (Pv.new) memw(#Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERITNEW_ABS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) memw(##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xa0e00000) { + // 10100000111sssssPP0ttttt000000dd | memd_locked(Rs,Pd) = Rtt + hi->instruction = HEX_INS_S4_STORED_LOCKED; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd_locked(%s,%s) = %s %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xa0e00008) { + // 10100000111sssssPP0ttttt000010 | memd_rl(Rs):at = Rtt + hi->instruction = HEX_INS_S4_STORED_RL_AT_VI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd_rl(%s):at = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xa0e00028) { + // 10100000111sssssPP0ttttt001010 | memd_rl(Rs):st = Rtt + hi->instruction = HEX_INS_S4_STORED_RL_ST_VI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd_rl(%s):st = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0xab000080) { + // 10101011000eeeeePP0ttttt10IIIIII | memb(Re=#II) = Rt + hi->instruction = HEX_INS_S4_STORERB_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(%s=##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00080) == 0xad000080) { + // 10101101000uuuuuPPittttt1iIIIIII | memb(Ru<<#Ii+#II) = Rt + hi->instruction = HEX_INS_S4_STORERB_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memb(%s<<#0x%x+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038c0) == 0xaba00080) { + // 10101011101eeeeePP000ttt10IIIIII | memb(Re=#II) = Nt.new + hi->instruction = HEX_INS_S4_STORERBNEW_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(%s=##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01880) == 0xada00080) { + // 10101101101uuuuuPPi00ttt1iIIIIII | memb(Ru<<#Ii+#II) = Nt.new + hi->instruction = HEX_INS_S4_STORERBNEW_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memb(%s<<#0x%x+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0xabc00080) { + // 10101011110eeeeePP0ttttt10IIIIII | memd(Re=#II) = Rtt + hi->instruction = HEX_INS_S4_STORERD_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(%s=##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00080) == 0xadc00080) { + // 10101101110uuuuuPPittttt1iIIIIII | memd(Ru<<#Ii+#II) = Rtt + hi->instruction = HEX_INS_S4_STORERD_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s memd(%s<<#0x%x+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0xab600080) { + // 10101011011eeeeePP0ttttt10IIIIII | memh(Re=#II) = Rt.h + hi->instruction = HEX_INS_S4_STORERF_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s=##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00080) == 0xad600080) { + // 10101101011uuuuuPPittttt1iIIIIII | memh(Ru<<#Ii+#II) = Rt.h + hi->instruction = HEX_INS_S4_STORERF_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s<<#0x%x+##0x%x) = %s.h %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0xab400080) { + // 10101011010eeeeePP0ttttt10IIIIII | memh(Re=#II) = Rt + hi->instruction = HEX_INS_S4_STORERH_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s=##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00080) == 0xad400080) { + // 10101101010uuuuuPPittttt1iIIIIII | memh(Ru<<#Ii+#II) = Rt + hi->instruction = HEX_INS_S4_STORERH_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memh(%s<<#0x%x+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038c0) == 0xaba00880) { + // 10101011101eeeeePP001ttt10IIIIII | memh(Re=#II) = Nt.new + hi->instruction = HEX_INS_S4_STORERHNEW_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(%s=##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01880) == 0xada00880) { + // 10101101101uuuuuPPi01ttt1iIIIIII | memh(Ru<<#Ii+#II) = Nt.new + hi->instruction = HEX_INS_S4_STORERHNEW_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memh(%s<<#0x%x+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0xab800080) { + // 10101011100eeeeePP0ttttt10IIIIII | memw(Re=#II) = Rt + hi->instruction = HEX_INS_S4_STORERI_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(%s=##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe00080) == 0xad800080) { + // 10101101100uuuuuPPittttt1iIIIIII | memw(Ru<<#Ii+#II) = Rt + hi->instruction = HEX_INS_S4_STORERI_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s memw(%s<<#0x%x+##0x%x) = %s %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe038c0) == 0xaba01080) { + // 10101011101eeeeePP010ttt10IIIIII | memw(Re=#II) = Nt.new + hi->instruction = HEX_INS_S4_STORERINEW_AP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(%s=##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe01880) == 0xada01080) { + // 10101101101uuuuuPPi10ttt1iIIIIII | memw(Ru<<#Ii+#II) = Nt.new + hi->instruction = HEX_INS_S4_STORERINEW_UR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_op_extend(&(hi->ops[2]), false); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + sprintf(hi->mnem, "%s memw(%s<<#0x%x+##0x%x) = %s.new %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fff) == 0xa8000000) { + // 1010100000000000PP00000000000000 | barrier + hi->instruction = HEX_INS_Y2_BARRIER; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s barrier %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0xa0000000) { + // 10100000000sssssPP00000000000000 | dccleana(Rs) + hi->instruction = HEX_INS_Y2_DCCLEANA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s dccleana(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0xa0400000) { + // 10100000010sssssPP00000000000000 | dccleaninva(Rs) + hi->instruction = HEX_INS_Y2_DCCLEANINVA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s dccleaninva(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0xa0200000) { + // 10100000001sssssPP00000000000000 | dcinva(Rs) + hi->instruction = HEX_INS_Y2_DCINVA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s dcinva(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0xa0c00000) { + // 10100000110sssssPP00000000000000 | dczeroa(Rs) + hi->instruction = HEX_INS_Y2_DCZEROA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s dczeroa(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fff) == 0xa8400000) { + // 1010100001000000PP00000000000000 | syncht + hi->instruction = HEX_INS_Y2_SYNCHT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 0; + sprintf(hi->mnem, "%s syncht %s", hi->pkt_info.syntax_prefix, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020ff) == 0xa6000000) { + // 10100110000sssssPP0ttttt00000000 | l2fetch(Rs,Rt) + hi->instruction = HEX_INS_Y4_L2FETCH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s l2fetch(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020ff) == 0xa6800000) { + // 10100110100sssssPP0ttttt00000000 | l2fetch(Rs,Rtt) + hi->instruction = HEX_INS_Y5_L2FETCH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s l2fetch(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020ff) == 0xa6000040) { + // 10100110000sssssPP0ttttt01000000 | dmlink(Rs,Rt) + hi->instruction = HEX_INS_Y6_DMLINK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s dmlink(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fe0) == 0xa8000060) { + // 1010100000000000PP000000011ddddd | Rd = dmpause + hi->instruction = HEX_INS_Y6_DMPAUSE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + sprintf(hi->mnem, "%s %s = dmpause %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fe0) == 0xa8000040) { + // 1010100000000000PP000000010ddddd | Rd = dmpoll + hi->instruction = HEX_INS_Y6_DMPOLL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + sprintf(hi->mnem, "%s %s = dmpoll %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0xa6000080) { + // 10100110000sssssPP00000010000000 | dmresume(Rs) + hi->instruction = HEX_INS_Y6_DMRESUME; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s dmresume(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03fff) == 0xa6000020) { + // 10100110000sssssPP00000000100000 | dmstart(Rs) + hi->instruction = HEX_INS_Y6_DMSTART; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s dmstart(%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffff3fe0) == 0xa8000020) { + // 1010100000000000PP000000001ddddd | Rd = dmwait + hi->instruction = HEX_INS_Y6_DMWAIT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + sprintf(hi->mnem, "%s %s = dmwait %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xb: + if ((hi_u32 & 0xf0000000) == 0xb0000000) { + // 1011iiiiiiisssssPPiiiiiiiiiddddd | Rd = add(Rs,#Ii) + hi->instruction = HEX_INS_A2_ADDI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xfe00000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 15)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 15); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xc: + if ((hi_u32 & 0xffe02080) == 0xc2c00000) { + // 11000010110sssssPP0ttttt0xxddddd | Rdd = add(Rss,Rtt,Px):carry + hi->instruction = HEX_INS_A4_ADDP_C; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Px4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = add(%s,%s,%s):carry %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c000c0) { + // 11000111110sssssPP0ttttt110000dd | Pd = cmpb.eq(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPBEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpb.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c00040) { + // 11000111110sssssPP0ttttt010000dd | Pd = cmpb.gt(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPBGT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpb.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c000e0) { + // 11000111110sssssPP0ttttt111000dd | Pd = cmpb.gtu(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPBGTU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpb.gtu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c00060) { + // 11000111110sssssPP0ttttt011000dd | Pd = cmph.eq(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPHEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmph.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c00080) { + // 11000111110sssssPP0ttttt100000dd | Pd = cmph.gt(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPHGT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmph.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c000a0) { + // 11000111110sssssPP0ttttt101000dd | Pd = cmph.gtu(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPHGTU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmph.gtu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6c00000) { + // 11000110110sssssPP0ttttt000ddddd | Rd = cround(Rs,Rt) + hi->instruction = HEX_INS_A4_CROUND_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cround(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6c00080) { + // 11000110110sssssPP0ttttt100ddddd | Rd = round(Rs,Rt) + hi->instruction = HEX_INS_A4_ROUND_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = round(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6c000c0) { + // 11000110110sssssPP0ttttt110ddddd | Rd = round(Rs,Rt):sat + hi->instruction = HEX_INS_A4_ROUND_RR_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = round(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xc2e00000) { + // 11000010111sssssPP0ttttt0xxddddd | Rdd = sub(Rss,Rtt,Px):carry + hi->instruction = HEX_INS_A4_SUBP_C; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Px4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = sub(%s,%s,%s):carry %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb200020) { + // 11001011001sssssPP0xxxxx001uuuuu | Rxx = vrmaxh(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMAXH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + sprintf(hi->mnem, "%s %s = vrmaxh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb202020) { + // 11001011001sssssPP1xxxxx001uuuuu | Rxx = vrmaxuh(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMAXUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + sprintf(hi->mnem, "%s %s = vrmaxuh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb202040) { + // 11001011001sssssPP1xxxxx010uuuuu | Rxx = vrmaxuw(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMAXUW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + sprintf(hi->mnem, "%s %s = vrmaxuw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb200040) { + // 11001011001sssssPP0xxxxx010uuuuu | Rxx = vrmaxw(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMAXW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + sprintf(hi->mnem, "%s %s = vrmaxw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2000a0) { + // 11001011001sssssPP0xxxxx101uuuuu | Rxx = vrminh(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMINH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + sprintf(hi->mnem, "%s %s = vrminh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2020a0) { + // 11001011001sssssPP1xxxxx101uuuuu | Rxx = vrminuh(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMINUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + sprintf(hi->mnem, "%s %s = vrminuh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2020c0) { + // 11001011001sssssPP1xxxxx110uuuuu | Rxx = vrminuw(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMINUW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + sprintf(hi->mnem, "%s %s = vrminuw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2000c0) { + // 11001011001sssssPP0xxxxx110uuuuu | Rxx = vrminw(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMINW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + sprintf(hi->mnem, "%s %s = vrminw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1400020) { + // 11000001010sssssPP0ttttt001ddddd | Rd = vaddhub(Rss,Rtt):sat + hi->instruction = HEX_INS_A5_VADDHUBS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vaddhub(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6c00040) { + // 11000110110sssssPP0ttttt010ddddd | Rdd = cround(Rss,Rt) + hi->instruction = HEX_INS_A7_CROUNDD_RR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cround(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7800000) { + // 11000111100sssssPP0ttttt000000dd | Pd = bitsclr(Rs,Rt) + hi->instruction = HEX_INS_C2_BITSCLR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = bitsclr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7400000) { + // 11000111010sssssPP0ttttt000000dd | Pd = bitsset(Rs,Rt) + hi->instruction = HEX_INS_C2_BITSSET; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = bitsset(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7a00000) { + // 11000111101sssssPP0ttttt000000dd | Pd = !bitsclr(Rs,Rt) + hi->instruction = HEX_INS_C4_NBITSCLR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = !bitsclr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7600000) { + // 11000111011sssssPP0ttttt000000dd | Pd = !bitsset(Rs,Rt) + hi->instruction = HEX_INS_C4_NBITSSET; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = !bitsset(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7e00060) { + // 11000111111sssssPP0ttttt011000dd | Pd = sfcmp.eq(Rs,Rt) + hi->instruction = HEX_INS_F2_SFCMPEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sfcmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7e00000) { + // 11000111111sssssPP0ttttt000000dd | Pd = sfcmp.ge(Rs,Rt) + hi->instruction = HEX_INS_F2_SFCMPGE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sfcmp.ge(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7e00080) { + // 11000111111sssssPP0ttttt100000dd | Pd = sfcmp.gt(Rs,Rt) + hi->instruction = HEX_INS_F2_SFCMPGT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sfcmp.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7e00020) { + // 11000111111sssssPP0ttttt001000dd | Pd = sfcmp.uo(Rs,Rt) + hi->instruction = HEX_INS_F2_SFCMPUO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sfcmp.uo(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc5000080) { + // 11000101000sssssPP0ttttt100ddddd | Rd = cmpyiwh(Rss,Rt):<<1:rnd:sat + hi->instruction = HEX_INS_M4_CMPYI_WH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpyiwh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc50000a0) { + // 11000101000sssssPP0ttttt101ddddd | Rd = cmpyiwh(Rss,Rt*):<<1:rnd:sat + hi->instruction = HEX_INS_M4_CMPYI_WHC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpyiwh(%s,%s*):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc50000c0) { + // 11000101000sssssPP0ttttt110ddddd | Rd = cmpyrwh(Rss,Rt):<<1:rnd:sat + hi->instruction = HEX_INS_M4_CMPYR_WH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpyrwh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc50000e0) { + // 11000101000sssssPP0ttttt111ddddd | Rd = cmpyrwh(Rss,Rt*):<<1:rnd:sat + hi->instruction = HEX_INS_M4_CMPYR_WHC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpyrwh(%s,%s*):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xca800000) { + // 11001010100sssssPP0ttttt000xxxxx | Rxx ^= xor(Rss,Rtt) + hi->instruction = HEX_INS_M4_XOR_XACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s ^= xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0xc4000000) { + // 11000100000sssssPP0tttttiiiddddd | Rd = addasl(Rt,Rs,#Ii) + hi->instruction = HEX_INS_S2_ADDASL_RRRI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = addasl(%s,%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3800080) { + // 11000011100sssssPP0ttttt100ddddd | Rdd = asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcbc00080) { + // 11001011110sssssPP0ttttt100xxxxx | Rxx += asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb400080) { + // 11001011010sssssPP0ttttt100xxxxx | Rxx &= asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb800080) { + // 11001011100sssssPP0ttttt100xxxxx | Rxx -= asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb000080) { + // 11001011000sssssPP0ttttt100xxxxx | Rxx |= asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb600080) { + // 11001011011sssssPP0ttttt100xxxxx | Rxx ^= asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6400080) { + // 11000110010sssssPP0ttttt100ddddd | Rd = asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xccc00080) { + // 11001100110sssssPP0ttttt100xxxxx | Rx += asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc400080) { + // 11001100010sssssPP0ttttt100xxxxx | Rx &= asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc800080) { + // 11001100100sssssPP0ttttt100xxxxx | Rx -= asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc000080) { + // 11001100000sssssPP0ttttt100xxxxx | Rx |= asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= asl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6000080) { + // 11000110000sssssPP0ttttt100ddddd | Rd = asl(Rs,Rt):sat + hi->instruction = HEX_INS_S2_ASL_R_R_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = asl(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3400080) { + // 11000011010sssssPP0ttttt100ddddd | Rdd = vaslh(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_VH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vaslh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3000080) { + // 11000011000sssssPP0ttttt100ddddd | Rdd = vaslw(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_VW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vaslw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3800000) { + // 11000011100sssssPP0ttttt000ddddd | Rdd = asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcbc00000) { + // 11001011110sssssPP0ttttt000xxxxx | Rxx += asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb400000) { + // 11001011010sssssPP0ttttt000xxxxx | Rxx &= asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb800000) { + // 11001011100sssssPP0ttttt000xxxxx | Rxx -= asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb000000) { + // 11001011000sssssPP0ttttt000xxxxx | Rxx |= asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb600000) { + // 11001011011sssssPP0ttttt000xxxxx | Rxx ^= asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6400000) { + // 11000110010sssssPP0ttttt000ddddd | Rd = asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xccc00000) { + // 11001100110sssssPP0ttttt000xxxxx | Rx += asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc400000) { + // 11001100010sssssPP0ttttt000xxxxx | Rx &= asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc800000) { + // 11001100100sssssPP0ttttt000xxxxx | Rx -= asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc000000) { + // 11001100000sssssPP0ttttt000xxxxx | Rx |= asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= asr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6000000) { + // 11000110000sssssPP0ttttt000ddddd | Rd = asr(Rs,Rt):sat + hi->instruction = HEX_INS_S2_ASR_R_R_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = asr(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc5000040) { + // 11000101000sssssPP0ttttt010ddddd | Rd = vasrw(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_SVW_TRUN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vasrw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3400000) { + // 11000011010sssssPP0ttttt000ddddd | Rdd = vasrh(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_VH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vasrh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3000000) { + // 11000011000sssssPP0ttttt000ddddd | Rdd = vasrw(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_VW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vasrw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1c000c0) { + // 11000001110sssssPP0ttttt110ddddd | Rdd = decbin(Rss,Rtt) + hi->instruction = HEX_INS_S2_CABACDECBIN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = decbin(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6800040) { + // 11000110100sssssPP0ttttt010ddddd | Rd = clrbit(Rs,Rt) + hi->instruction = HEX_INS_S2_CLRBIT_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = clrbit(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc9000000) { + // 11001001000sssssPP0ttttt000ddddd | Rd = extractu(Rs,Rtt) + hi->instruction = HEX_INS_S2_EXTRACTU_RP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = extractu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1000000) { + // 11000001000sssssPP0ttttt000ddddd | Rdd = extractu(Rss,Rtt) + hi->instruction = HEX_INS_S2_EXTRACTUP_RP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = extractu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc8000000) { + // 11001000000sssssPP0ttttt000xxxxx | Rx = insert(Rs,Rtt) + hi->instruction = HEX_INS_S2_INSERT_RP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = insert(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xca000000) { + // 11001010000sssssPP0ttttt000xxxxx | Rxx = insert(Rss,Rtt) + hi->instruction = HEX_INS_S2_INSERTP_RP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = insert(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc18000c0) { + // 11000001100sssssPP0ttttt110ddddd | Rdd = lfs(Rss,Rtt) + hi->instruction = HEX_INS_S2_LFSP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = lfs(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc38000c0) { + // 11000011100sssssPP0ttttt110ddddd | Rdd = lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcbc000c0) { + // 11001011110sssssPP0ttttt110xxxxx | Rxx += lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb4000c0) { + // 11001011010sssssPP0ttttt110xxxxx | Rxx &= lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb8000c0) { + // 11001011100sssssPP0ttttt110xxxxx | Rxx -= lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb0000c0) { + // 11001011000sssssPP0ttttt110xxxxx | Rxx |= lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb6000c0) { + // 11001011011sssssPP0ttttt110xxxxx | Rxx ^= lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc64000c0) { + // 11000110010sssssPP0ttttt110ddddd | Rd = lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xccc000c0) { + // 11001100110sssssPP0ttttt110xxxxx | Rx += lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc4000c0) { + // 11001100010sssssPP0ttttt110xxxxx | Rx &= lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc8000c0) { + // 11001100100sssssPP0ttttt110xxxxx | Rx -= lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc0000c0) { + // 11001100000sssssPP0ttttt110xxxxx | Rx |= lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc34000c0) { + // 11000011010sssssPP0ttttt110ddddd | Rdd = vlslh(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_VH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vlslh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc30000c0) { + // 11000011000sssssPP0ttttt110ddddd | Rdd = vlslw(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_VW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vlslw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3800040) { + // 11000011100sssssPP0ttttt010ddddd | Rdd = lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcbc00040) { + // 11001011110sssssPP0ttttt010xxxxx | Rxx += lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb400040) { + // 11001011010sssssPP0ttttt010xxxxx | Rxx &= lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb800040) { + // 11001011100sssssPP0ttttt010xxxxx | Rxx -= lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb000040) { + // 11001011000sssssPP0ttttt010xxxxx | Rxx |= lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb600040) { + // 11001011011sssssPP0ttttt010xxxxx | Rxx ^= lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6400040) { + // 11000110010sssssPP0ttttt010ddddd | Rd = lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xccc00040) { + // 11001100110sssssPP0ttttt010xxxxx | Rx += lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc400040) { + // 11001100010sssssPP0ttttt010xxxxx | Rx &= lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc800040) { + // 11001100100sssssPP0ttttt010xxxxx | Rx -= lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R_NAC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcc000040) { + // 11001100000sssssPP0ttttt010xxxxx | Rx |= lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= lsr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3400040) { + // 11000011010sssssPP0ttttt010ddddd | Rdd = vlsrh(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_VH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vlsrh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3000040) { + // 11000011000sssssPP0ttttt010ddddd | Rdd = vlsrw(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_VW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vlsrw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6800000) { + // 11000110100sssssPP0ttttt000ddddd | Rd = setbit(Rs,Rt) + hi->instruction = HEX_INS_S2_SETBIT_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = setbit(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1000040) { + // 11000001000sssssPP0ttttt010ddddd | Rdd = shuffeb(Rss,Rtt) + hi->instruction = HEX_INS_S2_SHUFFEB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = shuffeb(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc10000c0) { + // 11000001000sssssPP0ttttt110ddddd | Rdd = shuffeh(Rss,Rtt) + hi->instruction = HEX_INS_S2_SHUFFEH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = shuffeh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1000080) { + // 11000001000sssssPP0ttttt100ddddd | Rdd = shuffob(Rtt,Rss) + hi->instruction = HEX_INS_S2_SHUFFOB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = shuffob(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1800000) { + // 11000001100sssssPP0ttttt000ddddd | Rdd = shuffoh(Rtt,Rss) + hi->instruction = HEX_INS_S2_SHUFFOH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = shuffoh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc6800080) { + // 11000110100sssssPP0ttttt100ddddd | Rd = togglebit(Rs,Rt) + hi->instruction = HEX_INS_S2_TOGGLEBIT_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = togglebit(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7000000) { + // 11000111000sssssPP0ttttt000000dd | Pd = tstbit(Rs,Rt) + hi->instruction = HEX_INS_S2_TSTBIT_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = tstbit(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0xc0000000) { + // 11000000000sssssPP0tttttiiiddddd | Rdd = valignb(Rtt,Rss,#Ii) + hi->instruction = HEX_INS_S2_VALIGNIB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = valignb(%s,%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xc2000000) { + // 11000010000sssssPP0ttttt0uuddddd | Rdd = valignb(Rtt,Rss,Pu) + hi->instruction = HEX_INS_S2_VALIGNRB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + sprintf(hi->mnem, "%s %s = valignb(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3c00040) { + // 11000011110sssssPP0ttttt010ddddd | Rdd = vcnegh(Rss,Rt) + hi->instruction = HEX_INS_S2_VCNEGH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vcnegh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc3c00000) { + // 11000011110sssssPP0ttttt000ddddd | Rdd = vcrotate(Rss,Rt) + hi->instruction = HEX_INS_S2_VCROTATE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vcrotate(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2020e0) { + // 11001011001sssssPP1ttttt111xxxxx | Rxx += vrcnegh(Rss,Rt) + hi->instruction = HEX_INS_S2_VRCNEGH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += vrcnegh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0xc0800000) { + // 11000000100sssssPP0tttttiiiddddd | Rdd = vspliceb(Rss,Rtt,#Ii) + hi->instruction = HEX_INS_S2_VSPLICEIB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = vspliceb(%s,%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xc2800000) { + // 11000010100sssssPP0ttttt0uuddddd | Rdd = vspliceb(Rss,Rtt,Pu) + hi->instruction = HEX_INS_S2_VSPLICERB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + sprintf(hi->mnem, "%s %s = vspliceb(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1800040) { + // 11000001100sssssPP0ttttt010ddddd | Rdd = vtrunewh(Rss,Rtt) + hi->instruction = HEX_INS_S2_VTRUNEWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vtrunewh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1800080) { + // 11000001100sssssPP0ttttt100ddddd | Rdd = vtrunowh(Rss,Rtt) + hi->instruction = HEX_INS_S2_VTRUNOWH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vtrunowh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc9000040) { + // 11001001000sssssPP0ttttt010ddddd | Rd = extract(Rs,Rtt) + hi->instruction = HEX_INS_S4_EXTRACT_RP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = extract(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1c00080) { + // 11000001110sssssPP0ttttt100ddddd | Rdd = extract(Rss,Rtt) + hi->instruction = HEX_INS_S4_EXTRACTP_RP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = extract(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020c0) == 0xc68000c0) { + // 11000110100iiiiiPP0ttttt11iddddd | Rd = lsl(#Ii,Rt) + hi->instruction = HEX_INS_S4_LSLI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x20) >> 5)); // Ii + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffff << 5); + } + if (((st32)hi->ops[1].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[1].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = lsl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), signed_imm, hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xc7200000) { + // 11000111001sssssPP0ttttt000000dd | Pd = !tstbit(Rs,Rt) + hi->instruction = HEX_INS_S4_NTSTBIT_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = !tstbit(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000c0) == 0xc3c000c0) { + // 11000011110sssssPPittttt11iddddd | Rdd = vrcrotate(Rss,Rt,#Ii) + hi->instruction = HEX_INS_S4_VRCROTATE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x20) >> 5)); // Ii + sprintf(hi->mnem, "%s %s = vrcrotate(%s,%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe000c0) == 0xcba00000) { + // 11001011101sssssPPittttt00ixxxxx | Rxx += vrcrotate(Rss,Rt,#Ii) + hi->instruction = HEX_INS_S4_VRCROTATE_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x20) >> 5)); // Ii + sprintf(hi->mnem, "%s %s += vrcrotate(%s,%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1400080) { + // 11000001010sssssPP0ttttt100ddddd | Rdd = vxaddsubh(Rss,Rtt):sat + hi->instruction = HEX_INS_S4_VXADDSUBH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vxaddsubh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1c00000) { + // 11000001110sssssPP0ttttt000ddddd | Rdd = vxaddsubh(Rss,Rtt):rnd:>>1:sat + hi->instruction = HEX_INS_S4_VXADDSUBHR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vxaddsubh(%s,%s):rnd:>>1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1400000) { + // 11000001010sssssPP0ttttt000ddddd | Rdd = vxaddsubw(Rss,Rtt):sat + hi->instruction = HEX_INS_S4_VXADDSUBW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vxaddsubw(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc14000c0) { + // 11000001010sssssPP0ttttt110ddddd | Rdd = vxsubaddh(Rss,Rtt):sat + hi->instruction = HEX_INS_S4_VXSUBADDH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vxsubaddh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1c00040) { + // 11000001110sssssPP0ttttt010ddddd | Rdd = vxsubaddh(Rss,Rtt):rnd:>>1:sat + hi->instruction = HEX_INS_S4_VXSUBADDHR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vxsubaddh(%s,%s):rnd:>>1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1400040) { + // 11000001010sssssPP0ttttt010ddddd | Rdd = vxsubaddw(Rss,Rtt):sat + hi->instruction = HEX_INS_S4_VXSUBADDW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vxsubaddw(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc1800060) { + // 11000001100sssssPP0ttttt011ddddd | Rdd = vtrunehb(Rss,Rtt) + hi->instruction = HEX_INS_S6_VTRUNEHB_PPP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vtrunehb(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xc18000a0) { + // 11000001100sssssPP0ttttt101ddddd | Rdd = vtrunohb(Rss,Rtt) + hi->instruction = HEX_INS_S6_VTRUNOHB_PPP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vtrunohb(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xd: + if ((hi_u32 & 0xffe020e0) == 0xd5400060) { + // 11010101010sssssPP0ttttt011ddddd | Rd = add(Rt.h,Rs.h):<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_HH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.h,%s.h):<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5400040) { + // 11010101010sssssPP0ttttt010ddddd | Rd = add(Rt.h,Rs.l):<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_HL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.h,%s.l):<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5400020) { + // 11010101010sssssPP0ttttt001ddddd | Rd = add(Rt.l,Rs.h):<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_LH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.l,%s.h):<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5400000) { + // 11010101010sssssPP0ttttt000ddddd | Rd = add(Rt.l,Rs.l):<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_LL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.l,%s.l):<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd54000e0) { + // 11010101010sssssPP0ttttt111ddddd | Rd = add(Rt.h,Rs.h):sat:<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_SAT_HH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.h,%s.h):sat:<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd54000c0) { + // 11010101010sssssPP0ttttt110ddddd | Rd = add(Rt.h,Rs.l):sat:<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_SAT_HL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.h,%s.l):sat:<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd54000a0) { + // 11010101010sssssPP0ttttt101ddddd | Rd = add(Rt.l,Rs.h):sat:<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_SAT_LH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.l,%s.h):sat:<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5400080) { + // 11010101010sssssPP0ttttt100ddddd | Rd = add(Rt.l,Rs.l):sat:<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_SAT_LL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.l,%s.l):sat:<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5000040) { + // 11010101000sssssPP0ttttt010ddddd | Rd = add(Rt.l,Rs.h) + hi->instruction = HEX_INS_A2_ADDH_L16_HL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5000000) { + // 11010101000sssssPP0ttttt000ddddd | Rd = add(Rt.l,Rs.l) + hi->instruction = HEX_INS_A2_ADDH_L16_LL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd50000c0) { + // 11010101000sssssPP0ttttt110ddddd | Rd = add(Rt.l,Rs.h):sat + hi->instruction = HEX_INS_A2_ADDH_L16_SAT_HL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.l,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5000080) { + // 11010101000sssssPP0ttttt100ddddd | Rd = add(Rt.l,Rs.l):sat + hi->instruction = HEX_INS_A2_ADDH_L16_SAT_LL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s.l,%s.l):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd30000e0) { + // 11010011000sssssPP0ttttt111ddddd | Rdd = add(Rss,Rtt) + hi->instruction = HEX_INS_A2_ADDP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd36000a0) { + // 11010011011sssssPP0ttttt101ddddd | Rdd = add(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_ADDPSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = add(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd36000e0) { + // 11010011011sssssPP0ttttt111ddddd | Rdd = add(Rss,Rtt):raw:hi + hi->instruction = HEX_INS_A2_ADDSPH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = add(%s,%s):raw:hi %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd36000c0) { + // 11010011011sssssPP0ttttt110ddddd | Rdd = add(Rss,Rtt):raw:lo + hi->instruction = HEX_INS_A2_ADDSPL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = add(%s,%s):raw:lo %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00000) { + // 11010011111sssssPP0ttttt000ddddd | Rdd = and(Rss,Rtt) + hi->instruction = HEX_INS_A2_ANDP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5c00000) { + // 11010101110sssssPP0ttttt000ddddd | Rd = max(Rs,Rt) + hi->instruction = HEX_INS_A2_MAX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = max(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00080) { + // 11010011110sssssPP0ttttt100ddddd | Rdd = max(Rss,Rtt) + hi->instruction = HEX_INS_A2_MAXP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = max(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5c00080) { + // 11010101110sssssPP0ttttt100ddddd | Rd = maxu(Rs,Rt) + hi->instruction = HEX_INS_A2_MAXU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = maxu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c000a0) { + // 11010011110sssssPP0ttttt101ddddd | Rdd = maxu(Rss,Rtt) + hi->instruction = HEX_INS_A2_MAXUP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = maxu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5a00000) { + // 11010101101sssssPP0ttttt000ddddd | Rd = min(Rt,Rs) + hi->instruction = HEX_INS_A2_MIN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = min(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a000c0) { + // 11010011101sssssPP0ttttt110ddddd | Rdd = min(Rtt,Rss) + hi->instruction = HEX_INS_A2_MINP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = min(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5a00080) { + // 11010101101sssssPP0ttttt100ddddd | Rd = minu(Rt,Rs) + hi->instruction = HEX_INS_A2_MINU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = minu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a000e0) { + // 11010011101sssssPP0ttttt111ddddd | Rdd = minu(Rtt,Rss) + hi->instruction = HEX_INS_A2_MINUP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = minu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00040) { + // 11010011111sssssPP0ttttt010ddddd | Rdd = or(Rss,Rtt) + hi->instruction = HEX_INS_A2_ORP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600060) { + // 11010101011sssssPP0ttttt011ddddd | Rd = sub(Rt.h,Rs.h):<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_HH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.h,%s.h):<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600040) { + // 11010101011sssssPP0ttttt010ddddd | Rd = sub(Rt.h,Rs.l):<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_HL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.h,%s.l):<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600020) { + // 11010101011sssssPP0ttttt001ddddd | Rd = sub(Rt.l,Rs.h):<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_LH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.l,%s.h):<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600000) { + // 11010101011sssssPP0ttttt000ddddd | Rd = sub(Rt.l,Rs.l):<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_LL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.l,%s.l):<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd56000e0) { + // 11010101011sssssPP0ttttt111ddddd | Rd = sub(Rt.h,Rs.h):sat:<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_SAT_HH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.h,%s.h):sat:<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd56000c0) { + // 11010101011sssssPP0ttttt110ddddd | Rd = sub(Rt.h,Rs.l):sat:<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_SAT_HL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.h,%s.l):sat:<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd56000a0) { + // 11010101011sssssPP0ttttt101ddddd | Rd = sub(Rt.l,Rs.h):sat:<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_SAT_LH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.l,%s.h):sat:<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600080) { + // 11010101011sssssPP0ttttt100ddddd | Rd = sub(Rt.l,Rs.l):sat:<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_SAT_LL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.l,%s.l):sat:<<16 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5200040) { + // 11010101001sssssPP0ttttt010ddddd | Rd = sub(Rt.l,Rs.h) + hi->instruction = HEX_INS_A2_SUBH_L16_HL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5200000) { + // 11010101001sssssPP0ttttt000ddddd | Rd = sub(Rt.l,Rs.l) + hi->instruction = HEX_INS_A2_SUBH_L16_LL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd52000c0) { + // 11010101001sssssPP0ttttt110ddddd | Rd = sub(Rt.l,Rs.h):sat + hi->instruction = HEX_INS_A2_SUBH_L16_SAT_HL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.l,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5200080) { + // 11010101001sssssPP0ttttt100ddddd | Rd = sub(Rt.l,Rs.l):sat + hi->instruction = HEX_INS_A2_SUBH_L16_SAT_LL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s.l,%s.l):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd32000e0) { + // 11010011001sssssPP0ttttt111ddddd | Rdd = sub(Rtt,Rss) + hi->instruction = HEX_INS_A2_SUBP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = sub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000040) { + // 11010011000sssssPP0ttttt010ddddd | Rdd = vaddh(Rss,Rtt) + hi->instruction = HEX_INS_A2_VADDH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vaddh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000060) { + // 11010011000sssssPP0ttttt011ddddd | Rdd = vaddh(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_VADDHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vaddh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000000) { + // 11010011000sssssPP0ttttt000ddddd | Rdd = vaddub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VADDUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vaddub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000020) { + // 11010011000sssssPP0ttttt001ddddd | Rdd = vaddub(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_VADDUBS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vaddub(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000080) { + // 11010011000sssssPP0ttttt100ddddd | Rdd = vadduh(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_VADDUHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vadduh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd30000a0) { + // 11010011000sssssPP0ttttt101ddddd | Rdd = vaddw(Rss,Rtt) + hi->instruction = HEX_INS_A2_VADDW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vaddw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd30000c0) { + // 11010011000sssssPP0ttttt110ddddd | Rdd = vaddw(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_VADDWS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vaddw(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400040) { + // 11010011010sssssPP0ttttt010ddddd | Rdd = vavgh(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavgh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400080) { + // 11010011010sssssPP0ttttt100ddddd | Rdd = vavgh(Rss,Rtt):crnd + hi->instruction = HEX_INS_A2_VAVGHCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavgh(%s,%s):crnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400060) { + // 11010011010sssssPP0ttttt011ddddd | Rdd = vavgh(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGHR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavgh(%s,%s):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400000) { + // 11010011010sssssPP0ttttt000ddddd | Rdd = vavgub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavgub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400020) { + // 11010011010sssssPP0ttttt001ddddd | Rdd = vavgub(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGUBR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavgub(%s,%s):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd34000a0) { + // 11010011010sssssPP0ttttt101ddddd | Rdd = vavguh(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavguh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd34000c0) { + // 11010011010sssssPP0ttttt110ddddd | Rdd = vavguh(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGUHR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavguh(%s,%s):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600060) { + // 11010011011sssssPP0ttttt011ddddd | Rdd = vavguw(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGUW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavguw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600080) { + // 11010011011sssssPP0ttttt100ddddd | Rdd = vavguw(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGUWR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavguw(%s,%s):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600000) { + // 11010011011sssssPP0ttttt000ddddd | Rdd = vavgw(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavgw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600040) { + // 11010011011sssssPP0ttttt010ddddd | Rdd = vavgw(Rss,Rtt):crnd + hi->instruction = HEX_INS_A2_VAVGWCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavgw(%s,%s):crnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600020) { + // 11010011011sssssPP0ttttt001ddddd | Rdd = vavgw(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGWR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vavgw(%s,%s):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd20000c0) { + // 11010010000sssssPP0ttttt110000dd | Pd = vcmpb.eq(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPBEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpb.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd20000e0) { + // 11010010000sssssPP0ttttt111000dd | Pd = vcmpb.gtu(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPBGTU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpb.gtu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000060) { + // 11010010000sssssPP0ttttt011000dd | Pd = vcmph.eq(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPHEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmph.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000080) { + // 11010010000sssssPP0ttttt100000dd | Pd = vcmph.gt(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPHGT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmph.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd20000a0) { + // 11010010000sssssPP0ttttt101000dd | Pd = vcmph.gtu(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPHGTU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmph.gtu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000000) { + // 11010010000sssssPP0ttttt000000dd | Pd = vcmpw.eq(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPWEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpw.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000020) { + // 11010010000sssssPP0ttttt001000dd | Pd = vcmpw.gt(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPWGT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpw.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000040) { + // 11010010000sssssPP0ttttt010000dd | Pd = vcmpw.gtu(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPWGTU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpw.gtu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c000c0) { + // 11010011110sssssPP0ttttt110ddddd | Rdd = vmaxb(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vmaxb(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00020) { + // 11010011110sssssPP0ttttt001ddddd | Rdd = vmaxh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vmaxh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00000) { + // 11010011110sssssPP0ttttt000ddddd | Rdd = vmaxub(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vmaxub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00040) { + // 11010011110sssssPP0ttttt010ddddd | Rdd = vmaxuh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vmaxuh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a000a0) { + // 11010011101sssssPP0ttttt101ddddd | Rdd = vmaxuw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXUW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vmaxuw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00060) { + // 11010011110sssssPP0ttttt011ddddd | Rdd = vmaxw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vmaxw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c000e0) { + // 11010011110sssssPP0ttttt111ddddd | Rdd = vminb(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vminb(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00020) { + // 11010011101sssssPP0ttttt001ddddd | Rdd = vminh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vminh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00000) { + // 11010011101sssssPP0ttttt000ddddd | Rdd = vminub(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vminub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00040) { + // 11010011101sssssPP0ttttt010ddddd | Rdd = vminuh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vminuh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00080) { + // 11010011101sssssPP0ttttt100ddddd | Rdd = vminuw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINUW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vminuw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00060) { + // 11010011101sssssPP0ttttt011ddddd | Rdd = vminw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vminw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800000) { + // 11010011100sssssPP0ttttt000ddddd | Rdd = vnavgh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VNAVGH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vnavgh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800040) { + // 11010011100sssssPP0ttttt010ddddd | Rdd = vnavgh(Rtt,Rss):crnd:sat + hi->instruction = HEX_INS_A2_VNAVGHCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vnavgh(%s,%s):crnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800020) { + // 11010011100sssssPP0ttttt001ddddd | Rdd = vnavgh(Rtt,Rss):rnd:sat + hi->instruction = HEX_INS_A2_VNAVGHR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vnavgh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800060) { + // 11010011100sssssPP0ttttt011ddddd | Rdd = vnavgw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VNAVGW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vnavgw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd38000c0) { + // 11010011100sssssPP0ttttt110ddddd | Rdd = vnavgw(Rtt,Rss):crnd:sat + hi->instruction = HEX_INS_A2_VNAVGWCR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vnavgw(%s,%s):crnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800080) { + // 11010011100sssssPP0ttttt100ddddd | Rdd = vnavgw(Rtt,Rss):rnd:sat + hi->instruction = HEX_INS_A2_VNAVGWR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vnavgw(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200040) { + // 11010011001sssssPP0ttttt010ddddd | Rdd = vsubh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VSUBH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsubh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200060) { + // 11010011001sssssPP0ttttt011ddddd | Rdd = vsubh(Rtt,Rss):sat + hi->instruction = HEX_INS_A2_VSUBHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsubh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200000) { + // 11010011001sssssPP0ttttt000ddddd | Rdd = vsubub(Rtt,Rss) + hi->instruction = HEX_INS_A2_VSUBUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsubub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200020) { + // 11010011001sssssPP0ttttt001ddddd | Rdd = vsubub(Rtt,Rss):sat + hi->instruction = HEX_INS_A2_VSUBUBS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsubub(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200080) { + // 11010011001sssssPP0ttttt100ddddd | Rdd = vsubuh(Rtt,Rss):sat + hi->instruction = HEX_INS_A2_VSUBUHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsubuh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd32000a0) { + // 11010011001sssssPP0ttttt101ddddd | Rdd = vsubw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VSUBW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsubw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd32000c0) { + // 11010011001sssssPP0ttttt110ddddd | Rdd = vsubw(Rtt,Rss):sat + hi->instruction = HEX_INS_A2_VSUBWS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vsubw(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00080) { + // 11010011111sssssPP0ttttt100ddddd | Rdd = xor(Rss,Rtt) + hi->instruction = HEX_INS_A2_XORP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00020) { + // 11010011111sssssPP0ttttt001ddddd | Rdd = and(Rtt,~Rss) + hi->instruction = HEX_INS_A4_ANDNP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = and(%s,~%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd4200000) { + // 11010100001sssssPP0ttttt000ddddd | Rdd = bitsplit(Rs,Rt) + hi->instruction = HEX_INS_A4_BITSPLIT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = bitsplit(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd20020a0) { + // 11010010000sssssPP1ttttt101000dd | Pd = boundscheck(Rss,Rtt):raw:hi + hi->instruction = HEX_INS_A4_BOUNDSCHECK_HI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = boundscheck(%s,%s):raw:hi %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002080) { + // 11010010000sssssPP1ttttt100000dd | Pd = boundscheck(Rss,Rtt):raw:lo + hi->instruction = HEX_INS_A4_BOUNDSCHECK_LO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = boundscheck(%s,%s):raw:lo %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdd000000) { + // 11011101000sssssPP0iiiiiiii000dd | Pd = cmpb.eq(Rs,#Ii) + hi->instruction = HEX_INS_A4_CMPBEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = cmpb.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdd200000) { + // 11011101001sssssPP0iiiiiiii000dd | Pd = cmpb.gt(Rs,#Ii) + hi->instruction = HEX_INS_A4_CMPBGTI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = cmpb.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0301c) == 0xdd400000) { + // 11011101010sssssPP00iiiiiii000dd | Pd = cmpb.gtu(Rs,#Ii) + hi->instruction = HEX_INS_A4_CMPBGTUI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = cmpb.gtu(%s,##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdd000008) { + // 11011101000sssssPP0iiiiiiii010dd | Pd = cmph.eq(Rs,#Ii) + hi->instruction = HEX_INS_A4_CMPHEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = cmph.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdd200008) { + // 11011101001sssssPP0iiiiiiii010dd | Pd = cmph.gt(Rs,#Ii) + hi->instruction = HEX_INS_A4_CMPHGTI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = cmph.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0301c) == 0xdd400008) { + // 11011101010sssssPP00iiiiiii010dd | Pd = cmph.gtu(Rs,#Ii) + hi->instruction = HEX_INS_A4_CMPHGTUI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = cmph.gtu(%s,##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e000e0) { + // 11010011111sssssPP0ttttt111ddddd | Rd = modwrap(Rs,Rt) + hi->instruction = HEX_INS_A4_MODWRAPU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = modwrap(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00060) { + // 11010011111sssssPP0ttttt011ddddd | Rdd = or(Rtt,~Rss) + hi->instruction = HEX_INS_A4_ORNP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = or(%s,~%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002060) { + // 11010010000sssssPP1ttttt011000dd | Pd = tlbmatch(Rss,Rt) + hi->instruction = HEX_INS_A4_TLBMATCH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = tlbmatch(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002000) { + // 11010010000sssssPP1ttttt000000dd | Pd = any8(vcmpb.eq(Rss,Rtt)) + hi->instruction = HEX_INS_A4_VCMPBEQ_ANY; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = any8(vcmpb.eq(%s,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdc000000) { + // 11011100000sssssPP0iiiiiiii000dd | Pd = vcmpb.eq(Rss,#Ii) + hi->instruction = HEX_INS_A4_VCMPBEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = vcmpb.eq(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002040) { + // 11010010000sssssPP1ttttt010000dd | Pd = vcmpb.gt(Rss,Rtt) + hi->instruction = HEX_INS_A4_VCMPBGT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpb.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdc200000) { + // 11011100001sssssPP0iiiiiiii000dd | Pd = vcmpb.gt(Rss,#Ii) + hi->instruction = HEX_INS_A4_VCMPBGTI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vcmpb.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0301c) == 0xdc400000) { + // 11011100010sssssPP00iiiiiii000dd | Pd = vcmpb.gtu(Rss,#Ii) + hi->instruction = HEX_INS_A4_VCMPBGTUI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = vcmpb.gtu(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdc000008) { + // 11011100000sssssPP0iiiiiiii010dd | Pd = vcmph.eq(Rss,#Ii) + hi->instruction = HEX_INS_A4_VCMPHEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vcmph.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdc200008) { + // 11011100001sssssPP0iiiiiiii010dd | Pd = vcmph.gt(Rss,#Ii) + hi->instruction = HEX_INS_A4_VCMPHGTI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vcmph.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0301c) == 0xdc400008) { + // 11011100010sssssPP00iiiiiii010dd | Pd = vcmph.gtu(Rss,#Ii) + hi->instruction = HEX_INS_A4_VCMPHGTUI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = vcmph.gtu(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdc000010) { + // 11011100000sssssPP0iiiiiiii100dd | Pd = vcmpw.eq(Rss,#Ii) + hi->instruction = HEX_INS_A4_VCMPWEQI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vcmpw.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0201c) == 0xdc200010) { + // 11011100001sssssPP0iiiiiiii100dd | Pd = vcmpw.gt(Rss,#Ii) + hi->instruction = HEX_INS_A4_VCMPWGTI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "#", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "#", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s = vcmpw.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe0301c) == 0xdc400010) { + // 11011100010sssssPP00iiiiiii100dd | Pd = vcmpw.gtu(Rss,#Ii) + hi->instruction = HEX_INS_A4_VCMPWGTUI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = vcmpw.gtu(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002020) { + // 11010010000sssssPP1ttttt001000dd | Pd = !any8(vcmpb.eq(Rss,Rtt)) + hi->instruction = HEX_INS_A6_VCMPBEQ_NOTANY; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = !any8(vcmpb.eq(%s,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2800000) { + // 11010010100sssssPP0ttttt000000dd | Pd = cmp.eq(Rss,Rtt) + hi->instruction = HEX_INS_C2_CMPEQP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2800040) { + // 11010010100sssssPP0ttttt010000dd | Pd = cmp.gt(Rss,Rtt) + hi->instruction = HEX_INS_C2_CMPGTP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmp.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2800080) { + // 11010010100sssssPP0ttttt100000dd | Pd = cmp.gtu(Rss,Rtt) + hi->instruction = HEX_INS_C2_CMPGTUP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmp.gtu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xd1000000) { + // 11010001000sssssPP0ttttt0uuddddd | Rdd = vmux(Pu,Rss,Rtt) + hi->instruction = HEX_INS_C2_VMUX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmux(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe03c1c) == 0xdc800010) { + // 11011100100sssssPP0000iiiii100dd | Pd = dfclass(Rss,#Ii) + hi->instruction = HEX_INS_F2_DFCLASS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3e0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = dfclass(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2e00000) { + // 11010010111sssssPP0ttttt000000dd | Pd = dfcmp.eq(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFCMPEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfcmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2e00040) { + // 11010010111sssssPP0ttttt010000dd | Pd = dfcmp.ge(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFCMPGE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfcmp.ge(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2e00020) { + // 11010010111sssssPP0ttttt001000dd | Pd = dfcmp.gt(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFCMPGT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfcmp.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xd2e00060) { + // 11010010111sssssPP0ttttt011000dd | Pd = dfcmp.uo(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFCMPUO; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfcmp.uo(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffdf0000) == 0xd9400000) { + // 1101100101i00000PPiiiiiiiiiddddd | Rdd = dfmake(#Ii):neg + hi->instruction = HEX_INS_F2_DFIMM_N; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + sprintf(hi->mnem, "%s %s = dfmake(#0x%x):neg %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffdf0000) == 0xd9000000) { + // 1101100100i00000PPiiiiiiiiiddddd | Rdd = dfmake(#Ii):pos + hi->instruction = HEX_INS_F2_DFIMM_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + sprintf(hi->mnem, "%s %s = dfmake(#0x%x):pos %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffdf0000) == 0xd6400000) { + // 1101011001i00000PPiiiiiiiiiddddd | Rd = sfmake(#Ii):neg + hi->instruction = HEX_INS_F2_SFIMM_N; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + sprintf(hi->mnem, "%s %s = sfmake(#0x%x):neg %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffdf0000) == 0xd6000000) { + // 1101011000i00000PPiiiiiiiiiddddd | Rd = sfmake(#Ii):pos + hi->instruction = HEX_INS_F2_SFIMM_P; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + sprintf(hi->mnem, "%s %s = sfmake(#0x%x):pos %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000000) == 0xd8000000) { + // 11011000IiisssssPPidddddiiiIIIII | Rd = add(#Ii,mpyi(Rs,#II)) + hi->instruction = HEX_INS_M4_MPYRI_ADDI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x800000) >> 18) | (((hi_u32)&0x1f) >> 0)); // II + sprintf(hi->mnem, "%s %s = add(##0x%x,mpyi(%s,#0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff800000) == 0xdf800000) { + // 110111111iisssssPPidddddiiiuuuuu | Rd = add(Ru,mpyi(Rs,#Ii)) + hi->instruction = HEX_INS_M4_MPYRI_ADDR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + hex_op_extend(&(hi->ops[3]), false); // Extension possible + sprintf(hi->mnem, "%s %s = add(%s,mpyi(%s,##0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff800000) == 0xdf000000) { + // 110111110iisssssPPidddddiiiuuuuu | Rd = add(Ru,mpyi(#Ii,Rs)) + hi->instruction = HEX_INS_M4_MPYRI_ADDR_U2; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s,mpyi(#0x%x,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff800000) == 0xd7000000) { + // 110101110iisssssPPitttttiiiddddd | Rd = add(#Ii,mpyi(Rs,Rt)) + hi->instruction = HEX_INS_M4_MPYRR_ADDI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = add(##0x%x,mpyi(%s,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd0000000) { + // 11010000000sssssPP0ttttt000ddddd | Rd = parity(Rss,Rtt) + hi->instruction = HEX_INS_S2_PARITYP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = parity(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff800000) == 0xdb000000) { + // 110110110iisssssPPidddddiiiuuuuu | Rd = add(Rs,add(Ru,#Ii)) + hi->instruction = HEX_INS_S4_ADDADDI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s %s = add(%s,add(%s,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000017) == 0xde000004) { + // 11011110iiixxxxxPPiIIIIIiii0i100 | Rx = add(#Ii,asl(Rxin,#II)) + hi->instruction = HEX_INS_S4_ADDI_ASL_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + sprintf(hi->mnem, "%s %s = add(##0x%x,asl(%sin,#0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000017) == 0xde000014) { + // 11011110iiixxxxxPPiIIIIIiii1i100 | Rx = add(#Ii,lsr(Rxin,#II)) + hi->instruction = HEX_INS_S4_ADDI_LSR_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + sprintf(hi->mnem, "%s %s = add(##0x%x,lsr(%sin,#0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000017) == 0xde000000) { + // 11011110iiixxxxxPPiIIIIIiii0i000 | Rx = and(#Ii,asl(Rxin,#II)) + hi->instruction = HEX_INS_S4_ANDI_ASL_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + sprintf(hi->mnem, "%s %s = and(##0x%x,asl(%sin,#0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000017) == 0xde000010) { + // 11011110iiixxxxxPPiIIIIIiii1i000 | Rx = and(#Ii,lsr(Rxin,#II)) + hi->instruction = HEX_INS_S4_ANDI_LSR_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + sprintf(hi->mnem, "%s %s = and(##0x%x,lsr(%sin,#0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00000) == 0xda000000) { + // 1101101000isssssPPiiiiiiiiixxxxx | Rx |= and(Rs,#Ii) + hi->instruction = HEX_INS_S4_OR_ANDI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s |= and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00000) == 0xda400000) { + // 1101101001ixxxxxPPiiiiiiiiiuuuuu | Rx = or(Ru,and(Rxin,#Ii)) + hi->instruction = HEX_INS_S4_OR_ANDIX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[3].op.imm & (1 << 9)) { // signed + hi->ops[3].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[3]), false); // Extension possible + if (((st32)hi->ops[3].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[3].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[3].op.imm); + } + sprintf(hi->mnem, "%s %s = or(%s,and(%sin,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffc00000) == 0xda800000) { + // 1101101010isssssPPiiiiiiiiixxxxx | Rx |= or(Rs,#Ii) + hi->instruction = HEX_INS_S4_OR_ORI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 9); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s |= or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000017) == 0xde000002) { + // 11011110iiixxxxxPPiIIIIIiii0i010 | Rx = or(#Ii,asl(Rxin,#II)) + hi->instruction = HEX_INS_S4_ORI_ASL_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + sprintf(hi->mnem, "%s %s = or(##0x%x,asl(%sin,#0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000017) == 0xde000012) { + // 11011110iiixxxxxPPiIIIIIiii1i010 | Rx = or(#Ii,lsr(Rxin,#II)) + hi->instruction = HEX_INS_S4_ORI_LSR_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + sprintf(hi->mnem, "%s %s = or(##0x%x,lsr(%sin,#0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5e00000) { + // 11010101111sssssPP0ttttt000ddddd | Rd = parity(Rs,Rt) + hi->instruction = HEX_INS_S4_PARITY; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = parity(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff800000) == 0xdb800000) { + // 110110111iisssssPPidddddiiiuuuuu | Rd = add(Rs,sub(#Ii,Ru)) + hi->instruction = HEX_INS_S4_SUBADDI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 5); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + sprintf(hi->mnem, "%s %s = add(%s,sub(%s,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000017) == 0xde000006) { + // 11011110iiixxxxxPPiIIIIIiii0i110 | Rx = sub(#Ii,asl(Rxin,#II)) + hi->instruction = HEX_INS_S4_SUBI_ASL_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + sprintf(hi->mnem, "%s %s = sub(##0x%x,asl(%sin,#0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xff000017) == 0xde000016) { + // 11011110iiixxxxxPPiIIIIIiii1i110 | Rx = sub(#Ii,lsr(Rxin,#II)) + hi->instruction = HEX_INS_S4_SUBI_LSR_RI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_op_extend(&(hi->ops[1]), false); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + sprintf(hi->mnem, "%s %s = sub(##0x%x,lsr(%sin,#0x%x)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hi->ops[3].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5800000) { + // 11010101100sssssPP0ttttt000ddddd | Rd = add(Rs,Rt):sat:deprecated + hi->instruction = HEX_INS_DEP_A2_ADDSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = add(%s,%s):sat:deprecated %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd5800080) { + // 11010101100sssssPP0ttttt100ddddd | Rd = sub(Rt,Rs):sat:deprecated + hi->instruction = HEX_INS_DEP_A2_SUBSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s,%s):sat:deprecated %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xd4000000) { + // 11010100000sssssPP0ttttt000ddddd | Rdd = packhl(Rs,Rt):deprecated + hi->instruction = HEX_INS_DEP_S2_PACKHL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = packhl(%s,%s):deprecated %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xe: + if ((hi_u32 & 0xffe020e0) == 0xe8400020) { + // 11101000010sssssPP0ttttt001ddddd | Rdd = vraddub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VRADDUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vraddub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea400020) { + // 11101010010sssssPP0ttttt001xxxxx | Rxx += vraddub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VRADDUB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vraddub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8400040) { + // 11101000010sssssPP0ttttt010ddddd | Rdd = vrsadub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VRSADUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrsadub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea400040) { + // 11101010010sssssPP0ttttt010xxxxx | Rxx += vrsadub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VRSADUB_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrsadub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xeaa00000) { + // 11101010101sssssPP0ttttt0eexxxxx | Rxx,Pe = vacsh(Rss,Rtt) + hi->instruction = HEX_INS_A5_ACS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pe4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s,%s = vacsh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xeae00000) { + // 11101010111sssssPP0ttttt0eeddddd | Rdd,Pe = vminub(Rtt,Rss) + hi->instruction = HEX_INS_A6_VMINUB_RDP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pe4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s,%s = vminub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000060) { + // 11101000000sssssPP0ttttt011ddddd | Rdd = dfadd(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFADD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfadd(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8200060) { + // 11101000001sssssPP0ttttt011ddddd | Rdd = dfmax(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMAX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfmax(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c00060) { + // 11101000110sssssPP0ttttt011ddddd | Rdd = dfmin(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMIN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfmin(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8400060) { + // 11101000010sssssPP0ttttt011ddddd | Rdd = dfmpyfix(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMPYFIX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfmpyfix(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea800060) { + // 11101010100sssssPP0ttttt011xxxxx | Rxx += dfmpyhh(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMPYHH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += dfmpyhh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea000060) { + // 11101010000sssssPP0ttttt011xxxxx | Rxx += dfmpylh(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMPYLH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += dfmpylh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00060) { + // 11101000101sssssPP0ttttt011ddddd | Rdd = dfmpyll(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMPYLL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfmpyll(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8800060) { + // 11101000100sssssPP0ttttt011ddddd | Rdd = dfsub(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFSUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = dfsub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeb000000) { + // 11101011000sssssPP0ttttt000ddddd | Rd = sfadd(Rs,Rt) + hi->instruction = HEX_INS_F2_SFADD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sfadd(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xebc00020) { + // 11101011110sssssPP0ttttt001ddddd | Rd = sffixupd(Rs,Rt) + hi->instruction = HEX_INS_F2_SFFIXUPD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sffixupd(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xebc00000) { + // 11101011110sssssPP0ttttt000ddddd | Rd = sffixupn(Rs,Rt) + hi->instruction = HEX_INS_F2_SFFIXUPN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sffixupn(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef000080) { + // 11101111000sssssPP0ttttt100xxxxx | Rx += sfmpy(Rs,Rt) + hi->instruction = HEX_INS_F2_SFFMA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += sfmpy(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef0000c0) { + // 11101111000sssssPP0ttttt110xxxxx | Rx += sfmpy(Rs,Rt):lib + hi->instruction = HEX_INS_F2_SFFMA_LIB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += sfmpy(%s,%s):lib %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xef600080) { + // 11101111011sssssPP0ttttt1uuxxxxx | Rx += sfmpy(Rs,Rt,Pu):scale + hi->instruction = HEX_INS_F2_SFFMA_SC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + sprintf(hi->mnem, "%s %s += sfmpy(%s,%s,%s):scale %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef0000a0) { + // 11101111000sssssPP0ttttt101xxxxx | Rx -= sfmpy(Rs,Rt) + hi->instruction = HEX_INS_F2_SFFMS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= sfmpy(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef0000e0) { + // 11101111000sssssPP0ttttt111xxxxx | Rx -= sfmpy(Rs,Rt):lib + hi->instruction = HEX_INS_F2_SFFMS_LIB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= sfmpy(%s,%s):lib %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeb800000) { + // 11101011100sssssPP0ttttt000ddddd | Rd = sfmax(Rs,Rt) + hi->instruction = HEX_INS_F2_SFMAX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sfmax(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeb800020) { + // 11101011100sssssPP0ttttt001ddddd | Rd = sfmin(Rs,Rt) + hi->instruction = HEX_INS_F2_SFMIN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sfmin(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeb400000) { + // 11101011010sssssPP0ttttt000ddddd | Rd = sfmpy(Rs,Rt) + hi->instruction = HEX_INS_F2_SFMPY; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sfmpy(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xebe00080) { + // 11101011111sssssPP0ttttt1eeddddd | Rd,Pe = sfrecipa(Rs,Rt) + hi->instruction = HEX_INS_F2_SFRECIPA; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pe4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s,%s = sfrecipa(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeb000020) { + // 11101011000sssssPP0ttttt001ddddd | Rd = sfsub(Rs,Rt) + hi->instruction = HEX_INS_F2_SFSUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = sfsub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef000020) { + // 11101111000sssssPP0ttttt001xxxxx | Rx += add(Rs,Rt) + hi->instruction = HEX_INS_M2_ACCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0xe2000000) { + // 11100010000sssssPP0iiiiiiiixxxxx | Rx += add(Rs,#Ii) + hi->instruction = HEX_INS_M2_ACCII; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s += add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7000020) { + // 11100111000sssssPP0ttttt001xxxxx | Rxx += cmpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_CMACI_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += cmpyi(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7000040) { + // 11100111000sssssPP0ttttt010xxxxx | Rxx += cmpyr(Rs,Rt) + hi->instruction = HEX_INS_M2_CMACR_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += cmpyr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe70000c0) { + // 11100111000sssssPP0ttttt110xxxxx | Rxx += cmpy(Rs,Rt):sat + hi->instruction = HEX_INS_M2_CMACS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += cmpy(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe78000c0) { + // 11100111100sssssPP0ttttt110xxxxx | Rxx += cmpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_CMACS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += cmpy(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe74000c0) { + // 11100111010sssssPP0ttttt110xxxxx | Rxx += cmpy(Rs,Rt*):sat + hi->instruction = HEX_INS_M2_CMACSC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += cmpy(%s,%s*):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7c000c0) { + // 11100111110sssssPP0ttttt110xxxxx | Rxx += cmpy(Rs,Rt*):<<1:sat + hi->instruction = HEX_INS_M2_CMACSC_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += cmpy(%s,%s*):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe5000020) { + // 11100101000sssssPP0ttttt001ddddd | Rdd = cmpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_CMPYI_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpyi(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe5000040) { + // 11100101000sssssPP0ttttt010ddddd | Rdd = cmpyr(Rs,Rt) + hi->instruction = HEX_INS_M2_CMPYR_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpyr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xed2000c0) { + // 11101101001sssssPP0ttttt110ddddd | Rd = cmpy(Rs,Rt):rnd:sat + hi->instruction = HEX_INS_M2_CMPYRS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpy(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeda000c0) { + // 11101101101sssssPP0ttttt110ddddd | Rd = cmpy(Rs,Rt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_CMPYRS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpy(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xed6000c0) { + // 11101101011sssssPP0ttttt110ddddd | Rd = cmpy(Rs,Rt*):rnd:sat + hi->instruction = HEX_INS_M2_CMPYRSC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpy(%s,%s*):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xede000c0) { + // 11101101111sssssPP0ttttt110ddddd | Rd = cmpy(Rs,Rt*):<<1:rnd:sat + hi->instruction = HEX_INS_M2_CMPYRSC_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpy(%s,%s*):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe50000c0) { + // 11100101000sssssPP0ttttt110ddddd | Rdd = cmpy(Rs,Rt):sat + hi->instruction = HEX_INS_M2_CMPYS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpy(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe58000c0) { + // 11100101100sssssPP0ttttt110ddddd | Rdd = cmpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_CMPYS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpy(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe54000c0) { + // 11100101010sssssPP0ttttt110ddddd | Rdd = cmpy(Rs,Rt*):sat + hi->instruction = HEX_INS_M2_CMPYSC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpy(%s,%s*):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe5c000c0) { + // 11100101110sssssPP0ttttt110ddddd | Rdd = cmpy(Rs,Rt*):<<1:sat + hi->instruction = HEX_INS_M2_CMPYSC_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmpy(%s,%s*):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe70000e0) { + // 11100111000sssssPP0ttttt111xxxxx | Rxx -= cmpy(Rs,Rt):sat + hi->instruction = HEX_INS_M2_CNACS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= cmpy(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe78000e0) { + // 11100111100sssssPP0ttttt111xxxxx | Rxx -= cmpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_CNACS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= cmpy(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe74000e0) { + // 11100111010sssssPP0ttttt111xxxxx | Rxx -= cmpy(Rs,Rt*):sat + hi->instruction = HEX_INS_M2_CNACSC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= cmpy(%s,%s*):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7c000e0) { + // 11100111110sssssPP0ttttt111xxxxx | Rxx -= cmpy(Rs,Rt*):<<1:sat + hi->instruction = HEX_INS_M2_CNACSC_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= cmpy(%s,%s*):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7000000) { + // 11100111000sssssPP0ttttt000xxxxx | Rxx += mpy(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYSS_ACC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7200000) { + // 11100111001sssssPP0ttttt000xxxxx | Rxx -= mpy(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYSS_NAC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xed200020) { + // 11101101001sssssPP0ttttt001ddddd | Rd = mpy(Rs,Rt):rnd + hi->instruction = HEX_INS_M2_DPMPYSS_RND_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s,%s):rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe5000000) { + // 11100101000sssssPP0ttttt000ddddd | Rdd = mpy(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYSS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7400000) { + // 11100111010sssssPP0ttttt000xxxxx | Rxx += mpyu(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYUU_ACC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7600000) { + // 11100111011sssssPP0ttttt000xxxxx | Rxx -= mpyu(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYUU_NAC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe5400000) { + // 11100101010sssssPP0ttttt000ddddd | Rdd = mpyu(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYUU_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeda00080) { + // 11101101101sssssPP0ttttt100ddddd | Rd = mpy(Rs,Rt.h):<<1:rnd:sat + hi->instruction = HEX_INS_M2_HMMPYH_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s,%s.h):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeda00000) { + // 11101101101sssssPP0ttttt000ddddd | Rd = mpy(Rs,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_HMMPYH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s,%s.h):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xede00080) { + // 11101101111sssssPP0ttttt100ddddd | Rd = mpy(Rs,Rt.l):<<1:rnd:sat + hi->instruction = HEX_INS_M2_HMMPYL_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s,%s.l):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeda00020) { + // 11101101101sssssPP0ttttt001ddddd | Rd = mpy(Rs,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_HMMPYL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s,%s.l):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef000000) { + // 11101111000sssssPP0ttttt000xxxxx | Rx += mpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_MACI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyi(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0xe1800000) { + // 11100001100sssssPP0iiiiiiiixxxxx | Rx -= mpyi(Rs,#Ii) + hi->instruction = HEX_INS_M2_MACSIN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s -= mpyi(%s,##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0xe1000000) { + // 11100001000sssssPP0iiiiiiiixxxxx | Rx += mpyi(Rs,#Ii) + hi->instruction = HEX_INS_M2_MACSIP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s += mpyi(%s,##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea2000e0) { + // 11101010001sssssPP0ttttt111xxxxx | Rxx += vmpywoh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMACHS_RS0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpywoh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeaa000e0) { + // 11101010101sssssPP0ttttt111xxxxx | Rxx += vmpywoh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMACHS_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpywoh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea0000e0) { + // 11101010000sssssPP0ttttt111xxxxx | Rxx += vmpywoh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMACHS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpywoh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea8000e0) { + // 11101010100sssssPP0ttttt111xxxxx | Rxx += vmpywoh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMACHS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpywoh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea2000a0) { + // 11101010001sssssPP0ttttt101xxxxx | Rxx += vmpyweh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMACLS_RS0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyweh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeaa000a0) { + // 11101010101sssssPP0ttttt101xxxxx | Rxx += vmpyweh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMACLS_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyweh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea0000a0) { + // 11101010000sssssPP0ttttt101xxxxx | Rxx += vmpyweh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMACLS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyweh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea8000a0) { + // 11101010100sssssPP0ttttt101xxxxx | Rxx += vmpyweh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMACLS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyweh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea6000e0) { + // 11101010011sssssPP0ttttt111xxxxx | Rxx += vmpywouh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMACUHS_RS0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpywouh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeae000e0) { + // 11101010111sssssPP0ttttt111xxxxx | Rxx += vmpywouh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMACUHS_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpywouh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea4000e0) { + // 11101010010sssssPP0ttttt111xxxxx | Rxx += vmpywouh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMACUHS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpywouh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeac000e0) { + // 11101010110sssssPP0ttttt111xxxxx | Rxx += vmpywouh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMACUHS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpywouh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea6000a0) { + // 11101010011sssssPP0ttttt101xxxxx | Rxx += vmpyweuh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMACULS_RS0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyweuh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeae000a0) { + // 11101010111sssssPP0ttttt101xxxxx | Rxx += vmpyweuh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMACULS_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyweuh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea4000a0) { + // 11101010010sssssPP0ttttt101xxxxx | Rxx += vmpyweuh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMACULS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyweuh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeac000a0) { + // 11101010110sssssPP0ttttt101xxxxx | Rxx += vmpyweuh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMACULS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyweuh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe82000e0) { + // 11101000001sssssPP0ttttt111ddddd | Rdd = vmpywoh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMPYH_RS0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpywoh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a000e0) { + // 11101000101sssssPP0ttttt111ddddd | Rdd = vmpywoh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMPYH_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpywoh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe80000e0) { + // 11101000000sssssPP0ttttt111ddddd | Rdd = vmpywoh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMPYH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpywoh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe88000e0) { + // 11101000100sssssPP0ttttt111ddddd | Rdd = vmpywoh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMPYH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpywoh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe82000a0) { + // 11101000001sssssPP0ttttt101ddddd | Rdd = vmpyweh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMPYL_RS0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyweh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a000a0) { + // 11101000101sssssPP0ttttt101ddddd | Rdd = vmpyweh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMPYL_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyweh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe80000a0) { + // 11101000000sssssPP0ttttt101ddddd | Rdd = vmpyweh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMPYL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyweh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe88000a0) { + // 11101000100sssssPP0ttttt101ddddd | Rdd = vmpyweh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMPYL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyweh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe86000e0) { + // 11101000011sssssPP0ttttt111ddddd | Rdd = vmpywouh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMPYUH_RS0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpywouh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e000e0) { + // 11101000111sssssPP0ttttt111ddddd | Rdd = vmpywouh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMPYUH_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpywouh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe84000e0) { + // 11101000010sssssPP0ttttt111ddddd | Rdd = vmpywouh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMPYUH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpywouh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c000e0) { + // 11101000110sssssPP0ttttt111ddddd | Rdd = vmpywouh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMPYUH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpywouh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe86000a0) { + // 11101000011sssssPP0ttttt101ddddd | Rdd = vmpyweuh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMPYUL_RS0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyweuh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e000a0) { + // 11101000111sssssPP0ttttt101ddddd | Rdd = vmpyweuh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMPYUL_RS1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyweuh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe84000a0) { + // 11101000010sssssPP0ttttt101ddddd | Rdd = vmpyweuh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMPYUL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyweuh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c000a0) { + // 11101000110sssssPP0ttttt101ddddd | Rdd = vmpyweuh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMPYUL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyweuh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef800000) { + // 11101111100sssssPP0ttttt000xxxxx | Rx -= mpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_MNACI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyi(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee000060) { + // 11101110000sssssPP0ttttt011xxxxx | Rx += mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPY_ACC_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee800060) { + // 11101110100sssssPP0ttttt011xxxxx | Rx += mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_ACC_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee000040) { + // 11101110000sssssPP0ttttt010xxxxx | Rx += mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPY_ACC_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee800040) { + // 11101110100sssssPP0ttttt010xxxxx | Rx += mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_ACC_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee000020) { + // 11101110000sssssPP0ttttt001xxxxx | Rx += mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPY_ACC_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee800020) { + // 11101110100sssssPP0ttttt001xxxxx | Rx += mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_ACC_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee000000) { + // 11101110000sssssPP0ttttt000xxxxx | Rx += mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPY_ACC_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee800000) { + // 11101110100sssssPP0ttttt000xxxxx | Rx += mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_ACC_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee0000e0) { + // 11101110000sssssPP0ttttt111xxxxx | Rx += mpy(Rs.h,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee8000e0) { + // 11101110100sssssPP0ttttt111xxxxx | Rx += mpy(Rs.h,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.h):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee0000c0) { + // 11101110000sssssPP0ttttt110xxxxx | Rx += mpy(Rs.h,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.l):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee8000c0) { + // 11101110100sssssPP0ttttt110xxxxx | Rx += mpy(Rs.h,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.l):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee0000a0) { + // 11101110000sssssPP0ttttt101xxxxx | Rx += mpy(Rs.l,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee8000a0) { + // 11101110100sssssPP0ttttt101xxxxx | Rx += mpy(Rs.l,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.h):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee000080) { + // 11101110000sssssPP0ttttt100xxxxx | Rx += mpy(Rs.l,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.l):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee800080) { + // 11101110100sssssPP0ttttt100xxxxx | Rx += mpy(Rs.l,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.l):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec000060) { + // 11101100000sssssPP0ttttt011ddddd | Rd = mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPY_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec800060) { + // 11101100100sssssPP0ttttt011ddddd | Rd = mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec000040) { + // 11101100000sssssPP0ttttt010ddddd | Rd = mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPY_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec800040) { + // 11101100100sssssPP0ttttt010ddddd | Rd = mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec000020) { + // 11101100000sssssPP0ttttt001ddddd | Rd = mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPY_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec800020) { + // 11101100100sssssPP0ttttt001ddddd | Rd = mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec000000) { + // 11101100000sssssPP0ttttt000ddddd | Rd = mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPY_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec800000) { + // 11101100100sssssPP0ttttt000ddddd | Rd = mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee200060) { + // 11101110001sssssPP0ttttt011xxxxx | Rx -= mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPY_NAC_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00060) { + // 11101110101sssssPP0ttttt011xxxxx | Rx -= mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_NAC_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee200040) { + // 11101110001sssssPP0ttttt010xxxxx | Rx -= mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPY_NAC_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00040) { + // 11101110101sssssPP0ttttt010xxxxx | Rx -= mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_NAC_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee200020) { + // 11101110001sssssPP0ttttt001xxxxx | Rx -= mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPY_NAC_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00020) { + // 11101110101sssssPP0ttttt001xxxxx | Rx -= mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_NAC_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee200000) { + // 11101110001sssssPP0ttttt000xxxxx | Rx -= mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPY_NAC_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00000) { + // 11101110101sssssPP0ttttt000xxxxx | Rx -= mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_NAC_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee2000e0) { + // 11101110001sssssPP0ttttt111xxxxx | Rx -= mpy(Rs.h,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeea000e0) { + // 11101110101sssssPP0ttttt111xxxxx | Rx -= mpy(Rs.h,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.h):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee2000c0) { + // 11101110001sssssPP0ttttt110xxxxx | Rx -= mpy(Rs.h,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.l):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeea000c0) { + // 11101110101sssssPP0ttttt110xxxxx | Rx -= mpy(Rs.h,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.l):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee2000a0) { + // 11101110001sssssPP0ttttt101xxxxx | Rx -= mpy(Rs.l,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeea000a0) { + // 11101110101sssssPP0ttttt101xxxxx | Rx -= mpy(Rs.l,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.h):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee200080) { + // 11101110001sssssPP0ttttt100xxxxx | Rx -= mpy(Rs.l,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.l):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00080) { + // 11101110101sssssPP0ttttt100xxxxx | Rx -= mpy(Rs.l,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.l):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec200060) { + // 11101100001sssssPP0ttttt011ddddd | Rd = mpy(Rs.h,Rt.h):rnd + hi->instruction = HEX_INS_M2_MPY_RND_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00060) { + // 11101100101sssssPP0ttttt011ddddd | Rd = mpy(Rs.h,Rt.h):<<1:rnd + hi->instruction = HEX_INS_M2_MPY_RND_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):<<1:rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec200040) { + // 11101100001sssssPP0ttttt010ddddd | Rd = mpy(Rs.h,Rt.l):rnd + hi->instruction = HEX_INS_M2_MPY_RND_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00040) { + // 11101100101sssssPP0ttttt010ddddd | Rd = mpy(Rs.h,Rt.l):<<1:rnd + hi->instruction = HEX_INS_M2_MPY_RND_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):<<1:rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec200020) { + // 11101100001sssssPP0ttttt001ddddd | Rd = mpy(Rs.l,Rt.h):rnd + hi->instruction = HEX_INS_M2_MPY_RND_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00020) { + // 11101100101sssssPP0ttttt001ddddd | Rd = mpy(Rs.l,Rt.h):<<1:rnd + hi->instruction = HEX_INS_M2_MPY_RND_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):<<1:rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec200000) { + // 11101100001sssssPP0ttttt000ddddd | Rd = mpy(Rs.l,Rt.l):rnd + hi->instruction = HEX_INS_M2_MPY_RND_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00000) { + // 11101100101sssssPP0ttttt000ddddd | Rd = mpy(Rs.l,Rt.l):<<1:rnd + hi->instruction = HEX_INS_M2_MPY_RND_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):<<1:rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec0000e0) { + // 11101100000sssssPP0ttttt111ddddd | Rd = mpy(Rs.h,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_SAT_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec8000e0) { + // 11101100100sssssPP0ttttt111ddddd | Rd = mpy(Rs.h,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_SAT_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec0000c0) { + // 11101100000sssssPP0ttttt110ddddd | Rd = mpy(Rs.h,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_SAT_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec8000c0) { + // 11101100100sssssPP0ttttt110ddddd | Rd = mpy(Rs.h,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_SAT_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec0000a0) { + // 11101100000sssssPP0ttttt101ddddd | Rd = mpy(Rs.l,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_SAT_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec8000a0) { + // 11101100100sssssPP0ttttt101ddddd | Rd = mpy(Rs.l,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_SAT_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec000080) { + // 11101100000sssssPP0ttttt100ddddd | Rd = mpy(Rs.l,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_SAT_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec800080) { + // 11101100100sssssPP0ttttt100ddddd | Rd = mpy(Rs.l,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_SAT_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec2000e0) { + // 11101100001sssssPP0ttttt111ddddd | Rd = mpy(Rs.h,Rt.h):rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeca000e0) { + // 11101100101sssssPP0ttttt111ddddd | Rd = mpy(Rs.h,Rt.h):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec2000c0) { + // 11101100001sssssPP0ttttt110ddddd | Rd = mpy(Rs.h,Rt.l):rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeca000c0) { + // 11101100101sssssPP0ttttt110ddddd | Rd = mpy(Rs.h,Rt.l):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec2000a0) { + // 11101100001sssssPP0ttttt101ddddd | Rd = mpy(Rs.l,Rt.h):rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeca000a0) { + // 11101100101sssssPP0ttttt101ddddd | Rd = mpy(Rs.l,Rt.h):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec200080) { + // 11101100001sssssPP0ttttt100ddddd | Rd = mpy(Rs.l,Rt.l):rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00080) { + // 11101100101sssssPP0ttttt100ddddd | Rd = mpy(Rs.l,Rt.l):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xed000020) { + // 11101101000sssssPP0ttttt001ddddd | Rd = mpy(Rs,Rt) + hi->instruction = HEX_INS_M2_MPY_UP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeda00040) { + // 11101101101sssssPP0ttttt010ddddd | Rd = mpy(Rs,Rt):<<1 + hi->instruction = HEX_INS_M2_MPY_UP_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s,%s):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xede00000) { + // 11101101111sssssPP0ttttt000ddddd | Rd = mpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_MPY_UP_S1_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6000060) { + // 11100110000sssssPP0ttttt011xxxxx | Rxx += mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_ACC_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6800060) { + // 11100110100sssssPP0ttttt011xxxxx | Rxx += mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_ACC_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6000040) { + // 11100110000sssssPP0ttttt010xxxxx | Rxx += mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_ACC_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6800040) { + // 11100110100sssssPP0ttttt010xxxxx | Rxx += mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_ACC_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6000020) { + // 11100110000sssssPP0ttttt001xxxxx | Rxx += mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_ACC_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6800020) { + // 11100110100sssssPP0ttttt001xxxxx | Rxx += mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_ACC_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6000000) { + // 11100110000sssssPP0ttttt000xxxxx | Rxx += mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_ACC_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6800000) { + // 11100110100sssssPP0ttttt000xxxxx | Rxx += mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_ACC_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4000060) { + // 11100100000sssssPP0ttttt011ddddd | Rdd = mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4800060) { + // 11100100100sssssPP0ttttt011ddddd | Rdd = mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4000040) { + // 11100100000sssssPP0ttttt010ddddd | Rdd = mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4800040) { + // 11100100100sssssPP0ttttt010ddddd | Rdd = mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4000020) { + // 11100100000sssssPP0ttttt001ddddd | Rdd = mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4800020) { + // 11100100100sssssPP0ttttt001ddddd | Rdd = mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4000000) { + // 11100100000sssssPP0ttttt000ddddd | Rdd = mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4800000) { + // 11100100100sssssPP0ttttt000ddddd | Rdd = mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6200060) { + // 11100110001sssssPP0ttttt011xxxxx | Rxx -= mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_NAC_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6a00060) { + // 11100110101sssssPP0ttttt011xxxxx | Rxx -= mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_NAC_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6200040) { + // 11100110001sssssPP0ttttt010xxxxx | Rxx -= mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_NAC_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6a00040) { + // 11100110101sssssPP0ttttt010xxxxx | Rxx -= mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_NAC_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6200020) { + // 11100110001sssssPP0ttttt001xxxxx | Rxx -= mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_NAC_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6a00020) { + // 11100110101sssssPP0ttttt001xxxxx | Rxx -= mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_NAC_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6200000) { + // 11100110001sssssPP0ttttt000xxxxx | Rxx -= mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_NAC_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6a00000) { + // 11100110101sssssPP0ttttt000xxxxx | Rxx -= mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_NAC_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4200060) { + // 11100100001sssssPP0ttttt011ddddd | Rdd = mpy(Rs.h,Rt.h):rnd + hi->instruction = HEX_INS_M2_MPYD_RND_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4a00060) { + // 11100100101sssssPP0ttttt011ddddd | Rdd = mpy(Rs.h,Rt.h):<<1:rnd + hi->instruction = HEX_INS_M2_MPYD_RND_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.h):<<1:rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4200040) { + // 11100100001sssssPP0ttttt010ddddd | Rdd = mpy(Rs.h,Rt.l):rnd + hi->instruction = HEX_INS_M2_MPYD_RND_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4a00040) { + // 11100100101sssssPP0ttttt010ddddd | Rdd = mpy(Rs.h,Rt.l):<<1:rnd + hi->instruction = HEX_INS_M2_MPYD_RND_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.h,%s.l):<<1:rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4200020) { + // 11100100001sssssPP0ttttt001ddddd | Rdd = mpy(Rs.l,Rt.h):rnd + hi->instruction = HEX_INS_M2_MPYD_RND_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4a00020) { + // 11100100101sssssPP0ttttt001ddddd | Rdd = mpy(Rs.l,Rt.h):<<1:rnd + hi->instruction = HEX_INS_M2_MPYD_RND_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.h):<<1:rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4200000) { + // 11100100001sssssPP0ttttt000ddddd | Rdd = mpy(Rs.l,Rt.l):rnd + hi->instruction = HEX_INS_M2_MPYD_RND_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4a00000) { + // 11100100101sssssPP0ttttt000ddddd | Rdd = mpy(Rs.l,Rt.l):<<1:rnd + hi->instruction = HEX_INS_M2_MPYD_RND_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpy(%s.l,%s.l):<<1:rnd %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xed000000) { + // 11101101000sssssPP0ttttt000ddddd | Rd = mpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_MPYI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyi(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0xe0800000) { + // 11100000100sssssPP0iiiiiiiiddddd | Rd = -mpyi(Rs,#Ii) + hi->instruction = HEX_INS_M2_MPYSIN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + sprintf(hi->mnem, "%s %s = -mpyi(%s,#0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0xe0000000) { + // 11100000000sssssPP0iiiiiiiiddddd | Rd = +mpyi(Rs,#Ii) + hi->instruction = HEX_INS_M2_MPYSIP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + hex_op_extend(&(hi->ops[2]), false); // Extension possible + sprintf(hi->mnem, "%s %s = +mpyi(%s,##0x%x) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xed600020) { + // 11101101011sssssPP0ttttt001ddddd | Rd = mpysu(Rs,Rt) + hi->instruction = HEX_INS_M2_MPYSU_UP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpysu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee400060) { + // 11101110010sssssPP0ttttt011xxxxx | Rx += mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_ACC_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeec00060) { + // 11101110110sssssPP0ttttt011xxxxx | Rx += mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_ACC_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee400040) { + // 11101110010sssssPP0ttttt010xxxxx | Rx += mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_ACC_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeec00040) { + // 11101110110sssssPP0ttttt010xxxxx | Rx += mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_ACC_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee400020) { + // 11101110010sssssPP0ttttt001xxxxx | Rx += mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_ACC_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeec00020) { + // 11101110110sssssPP0ttttt001xxxxx | Rx += mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_ACC_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee400000) { + // 11101110010sssssPP0ttttt000xxxxx | Rx += mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_ACC_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeec00000) { + // 11101110110sssssPP0ttttt000xxxxx | Rx += mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_ACC_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec400060) { + // 11101100010sssssPP0ttttt011ddddd | Rd = mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xecc00060) { + // 11101100110sssssPP0ttttt011ddddd | Rd = mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec400040) { + // 11101100010sssssPP0ttttt010ddddd | Rd = mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xecc00040) { + // 11101100110sssssPP0ttttt010ddddd | Rd = mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec400020) { + // 11101100010sssssPP0ttttt001ddddd | Rd = mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xecc00020) { + // 11101100110sssssPP0ttttt001ddddd | Rd = mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xec400000) { + // 11101100010sssssPP0ttttt000ddddd | Rd = mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xecc00000) { + // 11101100110sssssPP0ttttt000ddddd | Rd = mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee600060) { + // 11101110011sssssPP0ttttt011xxxxx | Rx -= mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_NAC_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeee00060) { + // 11101110111sssssPP0ttttt011xxxxx | Rx -= mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_NAC_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee600040) { + // 11101110011sssssPP0ttttt010xxxxx | Rx -= mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_NAC_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeee00040) { + // 11101110111sssssPP0ttttt010xxxxx | Rx -= mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_NAC_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee600020) { + // 11101110011sssssPP0ttttt001xxxxx | Rx -= mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_NAC_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeee00020) { + // 11101110111sssssPP0ttttt001xxxxx | Rx -= mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_NAC_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xee600000) { + // 11101110011sssssPP0ttttt000xxxxx | Rx -= mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_NAC_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeee00000) { + // 11101110111sssssPP0ttttt000xxxxx | Rx -= mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_NAC_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xed400020) { + // 11101101010sssssPP0ttttt001ddddd | Rd = mpyu(Rs,Rt) + hi->instruction = HEX_INS_M2_MPYU_UP; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6400060) { + // 11100110010sssssPP0ttttt011xxxxx | Rxx += mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_ACC_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6c00060) { + // 11100110110sssssPP0ttttt011xxxxx | Rxx += mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_ACC_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6400040) { + // 11100110010sssssPP0ttttt010xxxxx | Rxx += mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_ACC_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6c00040) { + // 11100110110sssssPP0ttttt010xxxxx | Rxx += mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_ACC_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6400020) { + // 11100110010sssssPP0ttttt001xxxxx | Rxx += mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_ACC_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6c00020) { + // 11100110110sssssPP0ttttt001xxxxx | Rxx += mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_ACC_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6400000) { + // 11100110010sssssPP0ttttt000xxxxx | Rxx += mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_ACC_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6c00000) { + // 11100110110sssssPP0ttttt000xxxxx | Rxx += mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_ACC_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpyu(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4400060) { + // 11100100010sssssPP0ttttt011ddddd | Rdd = mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4c00060) { + // 11100100110sssssPP0ttttt011ddddd | Rdd = mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4400040) { + // 11100100010sssssPP0ttttt010ddddd | Rdd = mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4c00040) { + // 11100100110sssssPP0ttttt010ddddd | Rdd = mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4400020) { + // 11100100010sssssPP0ttttt001ddddd | Rdd = mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4c00020) { + // 11100100110sssssPP0ttttt001ddddd | Rdd = mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4400000) { + // 11100100010sssssPP0ttttt000ddddd | Rdd = mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe4c00000) { + // 11100100110sssssPP0ttttt000ddddd | Rdd = mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mpyu(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6600060) { + // 11100110011sssssPP0ttttt011xxxxx | Rxx -= mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_NAC_HH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6e00060) { + // 11100110111sssssPP0ttttt011xxxxx | Rxx -= mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_NAC_HH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.h,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6600040) { + // 11100110011sssssPP0ttttt010xxxxx | Rxx -= mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_NAC_HL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6e00040) { + // 11100110111sssssPP0ttttt010xxxxx | Rxx -= mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_NAC_HL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.h,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6600020) { + // 11100110011sssssPP0ttttt001xxxxx | Rxx -= mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_NAC_LH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6e00020) { + // 11100110111sssssPP0ttttt001xxxxx | Rxx -= mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_NAC_LH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.l,%s.h):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6600000) { + // 11100110011sssssPP0ttttt000xxxxx | Rxx -= mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_NAC_LL_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe6e00000) { + // 11100110111sssssPP0ttttt000xxxxx | Rxx -= mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_NAC_LL_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpyu(%s.l,%s.l):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef800020) { + // 11101111100sssssPP0ttttt001xxxxx | Rx -= add(Rs,Rt) + hi->instruction = HEX_INS_M2_NACCI; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02000) == 0xe2800000) { + // 11100010100sssssPP0iiiiiiiixxxxx | Rx -= add(Rs,#Ii) + hi->instruction = HEX_INS_M2_NACCII; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffff << 7); + } + hex_op_extend(&(hi->ops[2]), false); // Extension possible + if (((st32)hi->ops[2].op.imm) < 0) { + sprintf(signed_imm, "%s%s0x%x", "##", "-", abs((st32)hi->ops[2].op.imm)); // Add a minus sign before hex number + } else { + sprintf(signed_imm, "%s0x%x", "##", (st32)hi->ops[2].op.imm); + } + sprintf(hi->mnem, "%s %s -= add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm, hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef000060) { + // 11101111000sssssPP0ttttt011xxxxx | Rx += sub(Rt,Rs) + hi->instruction = HEX_INS_M2_SUBACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s += sub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8600000) { + // 11101000011sssssPP0ttttt000ddddd | Rdd = vabsdiffh(Rtt,Rss) + hi->instruction = HEX_INS_M2_VABSDIFFH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vabsdiffh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8200000) { + // 11101000001sssssPP0ttttt000ddddd | Rdd = vabsdiffw(Rtt,Rss) + hi->instruction = HEX_INS_M2_VABSDIFFW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vabsdiffw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea400080) { + // 11101010010sssssPP0ttttt100xxxxx | Rxx += vcmpyi(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VCMAC_S0_SAT_I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vcmpyi(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea200080) { + // 11101010001sssssPP0ttttt100xxxxx | Rxx += vcmpyr(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VCMAC_S0_SAT_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vcmpyr(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe84000c0) { + // 11101000010sssssPP0ttttt110ddddd | Rdd = vcmpyi(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VCMPY_S0_SAT_I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpyi(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe82000c0) { + // 11101000001sssssPP0ttttt110ddddd | Rdd = vcmpyr(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VCMPY_S0_SAT_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpyr(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c000c0) { + // 11101000110sssssPP0ttttt110ddddd | Rdd = vcmpyi(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VCMPY_S1_SAT_I; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpyi(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a000c0) { + // 11101000101sssssPP0ttttt110ddddd | Rdd = vcmpyr(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VCMPY_S1_SAT_R; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vcmpyr(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea000080) { + // 11101010000sssssPP0ttttt100xxxxx | Rxx += vdmpy(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VDMACS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vdmpy(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea800080) { + // 11101010100sssssPP0ttttt100xxxxx | Rxx += vdmpy(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VDMACS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vdmpy(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9000000) { + // 11101001000sssssPP0ttttt000ddddd | Rd = vdmpy(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_VDMPYRS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vdmpy(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9800000) { + // 11101001100sssssPP0ttttt000ddddd | Rd = vdmpy(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_VDMPYRS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vdmpy(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000080) { + // 11101000000sssssPP0ttttt100ddddd | Rdd = vdmpy(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VDMPYS_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vdmpy(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8800080) { + // 11101000100sssssPP0ttttt100ddddd | Rdd = vdmpy(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VDMPYS_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vdmpy(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7200020) { + // 11100111001sssssPP0ttttt001xxxxx | Rxx += vmpyh(Rs,Rt) + hi->instruction = HEX_INS_M2_VMAC2; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += vmpyh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea200040) { + // 11101010001sssssPP0ttttt010xxxxx | Rxx += vmpyeh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VMAC2ES; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyeh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea0000c0) { + // 11101010000sssssPP0ttttt110xxxxx | Rxx += vmpyeh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VMAC2ES_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyeh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea8000c0) { + // 11101010100sssssPP0ttttt110xxxxx | Rxx += vmpyeh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VMAC2ES_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vmpyeh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe70000a0) { + // 11100111000sssssPP0ttttt101xxxxx | Rxx += vmpyh(Rs,Rt):sat + hi->instruction = HEX_INS_M2_VMAC2S_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += vmpyh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe78000a0) { + // 11100111100sssssPP0ttttt101xxxxx | Rxx += vmpyh(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_VMAC2S_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += vmpyh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe76000a0) { + // 11100111011sssssPP0ttttt101xxxxx | Rxx += vmpyhsu(Rs,Rt):sat + hi->instruction = HEX_INS_M2_VMAC2SU_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += vmpyhsu(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7e000a0) { + // 11100111111sssssPP0ttttt101xxxxx | Rxx += vmpyhsu(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_VMAC2SU_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += vmpyhsu(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe80000c0) { + // 11101000000sssssPP0ttttt110ddddd | Rdd = vmpyeh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VMPY2ES_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyeh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe88000c0) { + // 11101000100sssssPP0ttttt110ddddd | Rdd = vmpyeh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VMPY2ES_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vmpyeh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe50000a0) { + // 11100101000sssssPP0ttttt101ddddd | Rdd = vmpyh(Rs,Rt):sat + hi->instruction = HEX_INS_M2_VMPY2S_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vmpyh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xed2000e0) { + // 11101101001sssssPP0ttttt111ddddd | Rd = vmpyh(Rs,Rt):rnd:sat + hi->instruction = HEX_INS_M2_VMPY2S_S0PACK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vmpyh(%s,%s):rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe58000a0) { + // 11100101100sssssPP0ttttt101ddddd | Rdd = vmpyh(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_VMPY2S_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vmpyh(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeda000e0) { + // 11101101101sssssPP0ttttt111ddddd | Rd = vmpyh(Rs,Rt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_VMPY2S_S1PACK; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vmpyh(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe50000e0) { + // 11100101000sssssPP0ttttt111ddddd | Rdd = vmpyhsu(Rs,Rt):sat + hi->instruction = HEX_INS_M2_VMPY2SU_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vmpyhsu(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe58000e0) { + // 11100101100sssssPP0ttttt111ddddd | Rdd = vmpyhsu(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_VMPY2SU_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vmpyhsu(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe92000e0) { + // 11101001001sssssPP0ttttt111ddddd | Rd = vraddh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRADDH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vraddh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9000020) { + // 11101001000sssssPP0ttttt001ddddd | Rd = vradduh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRADDUH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vradduh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea000000) { + // 11101010000sssssPP0ttttt000xxxxx | Rxx += vrcmpyi(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRCMACI_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrcmpyi(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea400000) { + // 11101010010sssssPP0ttttt000xxxxx | Rxx += vrcmpyi(Rss,Rtt*) + hi->instruction = HEX_INS_M2_VRCMACI_S0C; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrcmpyi(%s,%s*) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea000020) { + // 11101010000sssssPP0ttttt001xxxxx | Rxx += vrcmpyr(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRCMACR_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrcmpyr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea600020) { + // 11101010011sssssPP0ttttt001xxxxx | Rxx += vrcmpyr(Rss,Rtt*) + hi->instruction = HEX_INS_M2_VRCMACR_S0C; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrcmpyr(%s,%s*) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000000) { + // 11101000000sssssPP0ttttt000ddddd | Rdd = vrcmpyi(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRCMPYI_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrcmpyi(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8400000) { + // 11101000010sssssPP0ttttt000ddddd | Rdd = vrcmpyi(Rss,Rtt*) + hi->instruction = HEX_INS_M2_VRCMPYI_S0C; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrcmpyi(%s,%s*) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000020) { + // 11101000000sssssPP0ttttt001ddddd | Rdd = vrcmpyr(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRCMPYR_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrcmpyr(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8600020) { + // 11101000011sssssPP0ttttt001ddddd | Rdd = vrcmpyr(Rss,Rtt*) + hi->instruction = HEX_INS_M2_VRCMPYR_S0C; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrcmpyr(%s,%s*) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeaa00080) { + // 11101010101sssssPP0ttttt100xxxxx | Rxx += vrcmpys(Rss,Rtt):<<1:sat:raw:hi + hi->instruction = HEX_INS_M2_VRCMPYS_ACC_S1_H; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrcmpys(%s,%s):<<1:sat:raw:hi %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeae00080) { + // 11101010111sssssPP0ttttt100xxxxx | Rxx += vrcmpys(Rss,Rtt):<<1:sat:raw:lo + hi->instruction = HEX_INS_M2_VRCMPYS_ACC_S1_L; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrcmpys(%s,%s):<<1:sat:raw:lo %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00080) { + // 11101000101sssssPP0ttttt100ddddd | Rdd = vrcmpys(Rss,Rtt):<<1:sat:raw:hi + hi->instruction = HEX_INS_M2_VRCMPYS_S1_H; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrcmpys(%s,%s):<<1:sat:raw:hi %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e00080) { + // 11101000111sssssPP0ttttt100ddddd | Rdd = vrcmpys(Rss,Rtt):<<1:sat:raw:lo + hi->instruction = HEX_INS_M2_VRCMPYS_S1_L; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrcmpys(%s,%s):<<1:sat:raw:lo %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9a000c0) { + // 11101001101sssssPP0ttttt110ddddd | Rd = vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:hi + hi->instruction = HEX_INS_M2_VRCMPYS_S1RP_H; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrcmpys(%s,%s):<<1:rnd:sat:raw:hi %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9a000e0) { + // 11101001101sssssPP0ttttt111ddddd | Rd = vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:lo + hi->instruction = HEX_INS_M2_VRCMPYS_S1RP_L; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrcmpys(%s,%s):<<1:rnd:sat:raw:lo %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea000040) { + // 11101010000sssssPP0ttttt010xxxxx | Rxx += vrmpyh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRMAC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrmpyh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000040) { + // 11101000000sssssPP0ttttt010ddddd | Rdd = vrmpyh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRMPY_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrmpyh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef800060) { + // 11101111100sssssPP0ttttt011xxxxx | Rx ^= xor(Rs,Rt) + hi->instruction = HEX_INS_M2_XOR_XACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef400000) { + // 11101111010sssssPP0ttttt000xxxxx | Rx &= and(Rs,Rt) + hi->instruction = HEX_INS_M4_AND_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef200020) { + // 11101111001sssssPP0ttttt001xxxxx | Rx &= and(Rs,~Rt) + hi->instruction = HEX_INS_M4_AND_ANDN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= and(%s,~%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef400020) { + // 11101111010sssssPP0ttttt001xxxxx | Rx &= or(Rs,Rt) + hi->instruction = HEX_INS_M4_AND_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef400040) { + // 11101111010sssssPP0ttttt010xxxxx | Rx &= xor(Rs,Rt) + hi->instruction = HEX_INS_M4_AND_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s &= xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef600000) { + // 11101111011sssssPP0ttttt000xxxxx | Rx += mpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M4_MAC_UP_S1_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += mpy(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe3000000) { + // 11100011000sssssPP0yyyyy000uuuuu | Ry = add(Ru,mpyi(Ryin,Rs)) + hi->instruction = HEX_INS_M4_MPYRR_ADDR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Ry32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ry32in + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = add(%s,mpyi(%sin,%s)) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef600020) { + // 11101111011sssssPP0ttttt001xxxxx | Rx -= mpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M4_NAC_UP_S1_SAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s -= mpy(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef400060) { + // 11101111010sssssPP0ttttt011xxxxx | Rx |= and(Rs,Rt) + hi->instruction = HEX_INS_M4_OR_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef200000) { + // 11101111001sssssPP0ttttt000xxxxx | Rx |= and(Rs,~Rt) + hi->instruction = HEX_INS_M4_OR_ANDN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= and(%s,~%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xefc00000) { + // 11101111110sssssPP0ttttt000xxxxx | Rx |= or(Rs,Rt) + hi->instruction = HEX_INS_M4_OR_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xefc00020) { + // 11101111110sssssPP0ttttt001xxxxx | Rx |= xor(Rs,Rt) + hi->instruction = HEX_INS_M4_OR_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s |= xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe54000e0) { + // 11100101010sssssPP0ttttt111ddddd | Rdd = pmpyw(Rs,Rt) + hi->instruction = HEX_INS_M4_PMPYW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = pmpyw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe72000e0) { + // 11100111001sssssPP0ttttt111xxxxx | Rxx ^= pmpyw(Rs,Rt) + hi->instruction = HEX_INS_M4_PMPYW_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= pmpyw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe5c000e0) { + // 11100101110sssssPP0ttttt111ddddd | Rdd = vpmpyh(Rs,Rt) + hi->instruction = HEX_INS_M4_VPMPYH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vpmpyh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7a000e0) { + // 11100111101sssssPP0ttttt111xxxxx | Rxx ^= vpmpyh(Rs,Rt) + hi->instruction = HEX_INS_M4_VPMPYH_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= vpmpyh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea2000c0) { + // 11101010001sssssPP0ttttt110xxxxx | Rxx += vrmpyweh(Rss,Rtt) + hi->instruction = HEX_INS_M4_VRMPYEH_ACC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrmpyweh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeaa000c0) { + // 11101010101sssssPP0ttttt110xxxxx | Rxx += vrmpyweh(Rss,Rtt):<<1 + hi->instruction = HEX_INS_M4_VRMPYEH_ACC_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrmpyweh(%s,%s):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8400080) { + // 11101000010sssssPP0ttttt100ddddd | Rdd = vrmpyweh(Rss,Rtt) + hi->instruction = HEX_INS_M4_VRMPYEH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrmpyweh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c00080) { + // 11101000110sssssPP0ttttt100ddddd | Rdd = vrmpyweh(Rss,Rtt):<<1 + hi->instruction = HEX_INS_M4_VRMPYEH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrmpyweh(%s,%s):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea6000c0) { + // 11101010011sssssPP0ttttt110xxxxx | Rxx += vrmpywoh(Rss,Rtt) + hi->instruction = HEX_INS_M4_VRMPYOH_ACC_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrmpywoh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeae000c0) { + // 11101010111sssssPP0ttttt110xxxxx | Rxx += vrmpywoh(Rss,Rtt):<<1 + hi->instruction = HEX_INS_M4_VRMPYOH_ACC_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrmpywoh(%s,%s):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8200040) { + // 11101000001sssssPP0ttttt010ddddd | Rdd = vrmpywoh(Rss,Rtt) + hi->instruction = HEX_INS_M4_VRMPYOH_S0; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrmpywoh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00040) { + // 11101000101sssssPP0ttttt010ddddd | Rdd = vrmpywoh(Rss,Rtt):<<1 + hi->instruction = HEX_INS_M4_VRMPYOH_S1; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrmpywoh(%s,%s):<<1 %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xefc00040) { + // 11101111110sssssPP0ttttt010xxxxx | Rx ^= and(Rs,Rt) + hi->instruction = HEX_INS_M4_XOR_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xef200040) { + // 11101111001sssssPP0ttttt010xxxxx | Rx ^= and(Rs,~Rt) + hi->instruction = HEX_INS_M4_XOR_ANDN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= and(%s,~%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xefc00060) { + // 11101111110sssssPP0ttttt011xxxxx | Rx ^= or(Rs,Rt) + hi->instruction = HEX_INS_M4_XOR_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s ^= or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea200020) { + // 11101010001sssssPP0ttttt001xxxxx | Rxx += vdmpybsu(Rss,Rtt):sat + hi->instruction = HEX_INS_M5_VDMACBSU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vdmpybsu(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00020) { + // 11101000101sssssPP0ttttt001ddddd | Rdd = vdmpybsu(Rss,Rtt):sat + hi->instruction = HEX_INS_M5_VDMPYBSU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vdmpybsu(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7c00020) { + // 11100111110sssssPP0ttttt001xxxxx | Rxx += vmpybsu(Rs,Rt) + hi->instruction = HEX_INS_M5_VMACBSU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += vmpybsu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe7800020) { + // 11100111100sssssPP0ttttt001xxxxx | Rxx += vmpybu(Rs,Rt) + hi->instruction = HEX_INS_M5_VMACBUU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s += vmpybu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe5400020) { + // 11100101010sssssPP0ttttt001ddddd | Rdd = vmpybsu(Rs,Rt) + hi->instruction = HEX_INS_M5_VMPYBSU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vmpybsu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe5800020) { + // 11100101100sssssPP0ttttt001ddddd | Rdd = vmpybu(Rs,Rt) + hi->instruction = HEX_INS_M5_VMPYBUU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vmpybu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeac00020) { + // 11101010110sssssPP0ttttt001xxxxx | Rxx += vrmpybsu(Rss,Rtt) + hi->instruction = HEX_INS_M5_VRMACBSU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrmpybsu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea800020) { + // 11101010100sssssPP0ttttt001xxxxx | Rxx += vrmpybu(Rss,Rtt) + hi->instruction = HEX_INS_M5_VRMACBUU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += vrmpybu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c00020) { + // 11101000110sssssPP0ttttt001ddddd | Rdd = vrmpybsu(Rss,Rtt) + hi->instruction = HEX_INS_M5_VRMPYBSU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrmpybsu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8800020) { + // 11101000100sssssPP0ttttt001ddddd | Rdd = vrmpybu(Rss,Rtt) + hi->instruction = HEX_INS_M5_VRMPYBUU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = vrmpybu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e00000) { + // 11101000111sssssPP0ttttt000ddddd | Rdd = vabsdiffb(Rtt,Rss) + hi->instruction = HEX_INS_M6_VABSDIFFB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vabsdiffb(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00000) { + // 11101000101sssssPP0ttttt000ddddd | Rdd = vabsdiffub(Rtt,Rss) + hi->instruction = HEX_INS_M6_VABSDIFFUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + sprintf(hi->mnem, "%s %s = vabsdiffub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8600040) { + // 11101000011sssssPP0ttttt010ddddd | Rdd = cmpyiw(Rss,Rtt) + hi->instruction = HEX_INS_M7_DCMPYIW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyiw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea600040) { + // 11101010011sssssPP0ttttt010xxxxx | Rxx += cmpyiw(Rss,Rtt) + hi->instruction = HEX_INS_M7_DCMPYIW_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += cmpyiw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e00040) { + // 11101000111sssssPP0ttttt010ddddd | Rdd = cmpyiw(Rss,Rtt*) + hi->instruction = HEX_INS_M7_DCMPYIWC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyiw(%s,%s*) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea4000c0) { + // 11101010010sssssPP0ttttt110xxxxx | Rxx += cmpyiw(Rss,Rtt*) + hi->instruction = HEX_INS_M7_DCMPYIWC_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += cmpyiw(%s,%s*) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8800040) { + // 11101000100sssssPP0ttttt010ddddd | Rdd = cmpyrw(Rss,Rtt) + hi->instruction = HEX_INS_M7_DCMPYRW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyrw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xea800040) { + // 11101010100sssssPP0ttttt010xxxxx | Rxx += cmpyrw(Rss,Rtt) + hi->instruction = HEX_INS_M7_DCMPYRW_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += cmpyrw(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c00040) { + // 11101000110sssssPP0ttttt010ddddd | Rdd = cmpyrw(Rss,Rtt*) + hi->instruction = HEX_INS_M7_DCMPYRWC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyrw(%s,%s*) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xeac00040) { + // 11101010110sssssPP0ttttt010xxxxx | Rxx += cmpyrw(Rss,Rtt*) + hi->instruction = HEX_INS_M7_DCMPYRWC_ACC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s += cmpyrw(%s,%s*) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9200000) { + // 11101001001sssssPP0ttttt000ddddd | Rd = cmpyiw(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M7_WCMPYIW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyiw(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9a00000) { + // 11101001101sssssPP0ttttt000ddddd | Rd = cmpyiw(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M7_WCMPYIW_RND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyiw(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9000080) { + // 11101001000sssssPP0ttttt100ddddd | Rd = cmpyiw(Rss,Rtt*):<<1:sat + hi->instruction = HEX_INS_M7_WCMPYIWC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyiw(%s,%s*):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9800080) { + // 11101001100sssssPP0ttttt100ddddd | Rd = cmpyiw(Rss,Rtt*):<<1:rnd:sat + hi->instruction = HEX_INS_M7_WCMPYIWC_RND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyiw(%s,%s*):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9400000) { + // 11101001010sssssPP0ttttt000ddddd | Rd = cmpyrw(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M7_WCMPYRW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyrw(%s,%s):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9c00000) { + // 11101001110sssssPP0ttttt000ddddd | Rd = cmpyrw(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M7_WCMPYRW_RND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyrw(%s,%s):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9600000) { + // 11101001011sssssPP0ttttt000ddddd | Rd = cmpyrw(Rss,Rtt*):<<1:sat + hi->instruction = HEX_INS_M7_WCMPYRWC; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyrw(%s,%s*):<<1:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xe9e00000) { + // 11101001111sssssPP0ttttt000ddddd | Rd = cmpyrw(Rss,Rtt*):<<1:rnd:sat + hi->instruction = HEX_INS_M7_WCMPYRWC_RND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + sprintf(hi->mnem, "%s %s = cmpyrw(%s,%s*):<<1:rnd:sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + case 0xf: + if ((hi_u32 & 0xffe020e0) == 0xf3000000) { + // 11110011000sssssPP0ttttt000ddddd | Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_ADD; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf6400000) { + // 11110110010sssssPP0ttttt000ddddd | Rd = add(Rs,Rt):sat + hi->instruction = HEX_INS_A2_ADDSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = add(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf1000000) { + // 11110001000sssssPP0ttttt000ddddd | Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_AND; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf3800000) { + // 11110011100sssssPP0ttttt000ddddd | Rd = combine(Rt.h,Rs.h) + hi->instruction = HEX_INS_A2_COMBINE_HH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = combine(%s.h,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf3a00000) { + // 11110011101sssssPP0ttttt000ddddd | Rd = combine(Rt.h,Rs.l) + hi->instruction = HEX_INS_A2_COMBINE_HL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = combine(%s.h,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf3c00000) { + // 11110011110sssssPP0ttttt000ddddd | Rd = combine(Rt.l,Rs.h) + hi->instruction = HEX_INS_A2_COMBINE_LH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = combine(%s.l,%s.h) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf3e00000) { + // 11110011111sssssPP0ttttt000ddddd | Rd = combine(Rt.l,Rs.l) + hi->instruction = HEX_INS_A2_COMBINE_LL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = combine(%s.l,%s.l) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf5000000) { + // 11110101000sssssPP0ttttt000ddddd | Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_A2_COMBINEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = combine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf1200000) { + // 11110001001sssssPP0ttttt000ddddd | Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_OR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfb000080) { + // 11111011000sssssPP0ttttt1uuddddd | if (!Pu) Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_PADDF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfb002080) { + // 11111011000sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_PADDFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfb000000) { + // 11111011000sssssPP0ttttt0uuddddd | if (Pu) Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_PADDT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfb002000) { + // 11111011000sssssPP1ttttt0uuddddd | if (Pu.new) Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_PADDTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) %s = add(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9000080) { + // 11111001000sssssPP0ttttt1uuddddd | if (!Pu) Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_PANDF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) %s = and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9002080) { + // 11111001000sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_PANDFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) %s = and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9000000) { + // 11111001000sssssPP0ttttt0uuddddd | if (Pu) Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_PANDT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) %s = and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9002000) { + // 11111001000sssssPP1ttttt0uuddddd | if (Pu.new) Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_PANDTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) %s = and(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9200080) { + // 11111001001sssssPP0ttttt1uuddddd | if (!Pu) Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_PORF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) %s = or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9202080) { + // 11111001001sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_PORFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) %s = or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9200000) { + // 11111001001sssssPP0ttttt0uuddddd | if (Pu) Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_PORT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) %s = or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9202000) { + // 11111001001sssssPP1ttttt0uuddddd | if (Pu.new) Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_PORTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) %s = or(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfb200080) { + // 11111011001sssssPP0ttttt1uuddddd | if (!Pu) Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_PSUBF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s) %s = sub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfb202080) { + // 11111011001sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_PSUBFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (!%s.new) %s = sub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfb200000) { + // 11111011001sssssPP0ttttt0uuddddd | if (Pu) Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_PSUBT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s) %s = sub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfb202000) { + // 11111011001sssssPP1ttttt0uuddddd | if (Pu.new) Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_PSUBTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s if (%s.new) %s = sub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9600080) { + // 11111001011sssssPP0ttttt1uuddddd | if (!Pu) Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_PXORF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) %s = xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9602080) { + // 11111001011sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_PXORFNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) %s = xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9600000) { + // 11111001011sssssPP0ttttt0uuddddd | if (Pu) Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_PXORT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) %s = xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf9602000) { + // 11111001011sssssPP1ttttt0uuddddd | if (Pu.new) Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_PXORTNEW; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) %s = xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf3200000) { + // 11110011001sssssPP0ttttt000ddddd | Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_SUB; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf6c00000) { + // 11110110110sssssPP0ttttt000ddddd | Rd = sub(Rt,Rs):sat + hi->instruction = HEX_INS_A2_SUBSAT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = sub(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf6000000) { + // 11110110000sssssPP0ttttt000ddddd | Rd = vaddh(Rs,Rt) + hi->instruction = HEX_INS_A2_SVADDH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vaddh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf6200000) { + // 11110110001sssssPP0ttttt000ddddd | Rd = vaddh(Rs,Rt):sat + hi->instruction = HEX_INS_A2_SVADDHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vaddh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf6600000) { + // 11110110011sssssPP0ttttt000ddddd | Rd = vadduh(Rs,Rt):sat + hi->instruction = HEX_INS_A2_SVADDUHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vadduh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf7000000) { + // 11110111000sssssPP0ttttt000ddddd | Rd = vavgh(Rs,Rt) + hi->instruction = HEX_INS_A2_SVAVGH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vavgh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf7200000) { + // 11110111001sssssPP0ttttt000ddddd | Rd = vavgh(Rs,Rt):rnd + hi->instruction = HEX_INS_A2_SVAVGHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = vavgh(%s,%s):rnd %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf7600000) { + // 11110111011sssssPP0ttttt000ddddd | Rd = vnavgh(Rt,Rs) + hi->instruction = HEX_INS_A2_SVNAVGH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vnavgh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf6800000) { + // 11110110100sssssPP0ttttt000ddddd | Rd = vsubh(Rt,Rs) + hi->instruction = HEX_INS_A2_SVSUBH; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsubh(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf6a00000) { + // 11110110101sssssPP0ttttt000ddddd | Rd = vsubh(Rt,Rs):sat + hi->instruction = HEX_INS_A2_SVSUBHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsubh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf6e00000) { + // 11110110111sssssPP0ttttt000ddddd | Rd = vsubuh(Rt,Rs):sat + hi->instruction = HEX_INS_A2_SVSUBUHS; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = vsubuh(%s,%s):sat %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf1600000) { + // 11110001011sssssPP0ttttt000ddddd | Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_XOR; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = xor(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf1800000) { + // 11110001100sssssPP0ttttt000ddddd | Rd = and(Rt,~Rs) + hi->instruction = HEX_INS_A4_ANDN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = and(%s,~%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf1a00000) { + // 11110001101sssssPP0ttttt000ddddd | Rd = or(Rt,~Rs) + hi->instruction = HEX_INS_A4_ORN; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + sprintf(hi->mnem, "%s %s = or(%s,~%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf3400000) { + // 11110011010sssssPP0ttttt000ddddd | Rd = cmp.eq(Rs,Rt) + hi->instruction = HEX_INS_A4_RCMPEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf3600000) { + // 11110011011sssssPP0ttttt000ddddd | Rd = !cmp.eq(Rs,Rt) + hi->instruction = HEX_INS_A4_RCMPNEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = !cmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfd000080) { + // 11111101000sssssPP0ttttt1uuddddd | if (!Pu) Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_C2_CCOMBINEWF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s) %s = combine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfd002080) { + // 11111101000sssssPP1ttttt1uuddddd | if (!Pu.new) Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_C2_CCOMBINEWNEWF; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (!%s.new) %s = combine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfd002000) { + // 11111101000sssssPP1ttttt0uuddddd | if (Pu.new) Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_C2_CCOMBINEWNEWT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s.new) %s = combine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xfd000000) { + // 11111101000sssssPP0ttttt0uuddddd | if (Pu) Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_C2_CCOMBINEWT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s if (%s) %s = combine(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xf2000000) { + // 11110010000sssssPP0ttttt000000dd | Pd = cmp.eq(Rs,Rt) + hi->instruction = HEX_INS_C2_CMPEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xf2400000) { + // 11110010010sssssPP0ttttt000000dd | Pd = cmp.gt(Rs,Rt) + hi->instruction = HEX_INS_C2_CMPGT; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmp.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xf2600000) { + // 11110010011sssssPP0ttttt000000dd | Pd = cmp.gtu(Rs,Rt) + hi->instruction = HEX_INS_C2_CMPGTU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = cmp.gtu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe02080) == 0xf4000000) { + // 11110100000sssssPP0ttttt0uuddddd | Rd = mux(Pu,Rs,Rt) + hi->instruction = HEX_INS_C2_MUX; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = mux(%s,%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xf2400010) { + // 11110010010sssssPP0ttttt000100dd | Pd = !cmp.gt(Rs,Rt) + hi->instruction = HEX_INS_C4_CMPLTE; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = !cmp.gt(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xf2600010) { + // 11110010011sssssPP0ttttt000100dd | Pd = !cmp.gtu(Rs,Rt) + hi->instruction = HEX_INS_C4_CMPLTEU; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = !cmp.gtu(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020fc) == 0xf2000010) { + // 11110010000sssssPP0ttttt000100dd | Pd = !cmp.eq(Rs,Rt) + hi->instruction = HEX_INS_C4_CMPNEQ; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = !cmp.eq(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + if ((hi_u32 & 0xffe020e0) == 0xf5800000) { + // 11110101100sssssPP0ttttt000ddddd | Rdd = packhl(Rs,Rt) + hi->instruction = HEX_INS_S2_PACKHL; + hi->pkt_info.parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pkt_info.loop_attr = HEX_NO_LOOP; + hex_set_pkt_info(&(hi->pkt_info)); + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + sprintf(hi->mnem, "%s %s = packhl(%s,%s) %s", hi->pkt_info.syntax_prefix, hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hi->pkt_info.syntax_postfix); + break; + } + break; + } + } + return 4; +} \ No newline at end of file diff --git a/rizin/librz/asm/arch/hexagon/hexagon_insn.h b/rizin/librz/asm/arch/hexagon/hexagon_insn.h new file mode 100644 index 00000000..77630106 --- /dev/null +++ b/rizin/librz/asm/arch/hexagon/hexagon_insn.h @@ -0,0 +1,3510 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + +#ifndef HEXAGON_INSN_H +#define HEXAGON_INSN_H + +enum HEX_INS { + HEX_INS_A2_ABS, + HEX_INS_A2_ABSP, + HEX_INS_A2_ABSSAT, + HEX_INS_A2_ADD, + HEX_INS_A2_ADDH_H16_HH, + HEX_INS_A2_ADDH_H16_HL, + HEX_INS_A2_ADDH_H16_LH, + HEX_INS_A2_ADDH_H16_LL, + HEX_INS_A2_ADDH_H16_SAT_HH, + HEX_INS_A2_ADDH_H16_SAT_HL, + HEX_INS_A2_ADDH_H16_SAT_LH, + HEX_INS_A2_ADDH_H16_SAT_LL, + HEX_INS_A2_ADDH_L16_HL, + HEX_INS_A2_ADDH_L16_LL, + HEX_INS_A2_ADDH_L16_SAT_HL, + HEX_INS_A2_ADDH_L16_SAT_LL, + HEX_INS_A2_ADDI, + HEX_INS_A2_ADDP, + HEX_INS_A2_ADDPSAT, + HEX_INS_A2_ADDSAT, + HEX_INS_A2_ADDSPH, + HEX_INS_A2_ADDSPL, + HEX_INS_A2_AND, + HEX_INS_A2_ANDIR, + HEX_INS_A2_ANDP, + HEX_INS_A2_ASLH, + HEX_INS_A2_ASRH, + HEX_INS_A2_COMBINE_HH, + HEX_INS_A2_COMBINE_HL, + HEX_INS_A2_COMBINE_LH, + HEX_INS_A2_COMBINE_LL, + HEX_INS_A2_COMBINEII, + HEX_INS_A2_COMBINEW, + HEX_INS_A2_MAX, + HEX_INS_A2_MAXP, + HEX_INS_A2_MAXU, + HEX_INS_A2_MAXUP, + HEX_INS_A2_MIN, + HEX_INS_A2_MINP, + HEX_INS_A2_MINU, + HEX_INS_A2_MINUP, + HEX_INS_A2_NEGP, + HEX_INS_A2_NEGSAT, + HEX_INS_A2_NOP, + HEX_INS_A2_NOTP, + HEX_INS_A2_OR, + HEX_INS_A2_ORIR, + HEX_INS_A2_ORP, + HEX_INS_A2_PADDF, + HEX_INS_A2_PADDFNEW, + HEX_INS_A2_PADDIF, + HEX_INS_A2_PADDIFNEW, + HEX_INS_A2_PADDIT, + HEX_INS_A2_PADDITNEW, + HEX_INS_A2_PADDT, + HEX_INS_A2_PADDTNEW, + HEX_INS_A2_PANDF, + HEX_INS_A2_PANDFNEW, + HEX_INS_A2_PANDT, + HEX_INS_A2_PANDTNEW, + HEX_INS_A2_PORF, + HEX_INS_A2_PORFNEW, + HEX_INS_A2_PORT, + HEX_INS_A2_PORTNEW, + HEX_INS_A2_PSUBF, + HEX_INS_A2_PSUBFNEW, + HEX_INS_A2_PSUBT, + HEX_INS_A2_PSUBTNEW, + HEX_INS_A2_PXORF, + HEX_INS_A2_PXORFNEW, + HEX_INS_A2_PXORT, + HEX_INS_A2_PXORTNEW, + HEX_INS_A2_ROUNDSAT, + HEX_INS_A2_SAT, + HEX_INS_A2_SATB, + HEX_INS_A2_SATH, + HEX_INS_A2_SATUB, + HEX_INS_A2_SATUH, + HEX_INS_A2_SUB, + HEX_INS_A2_SUBH_H16_HH, + HEX_INS_A2_SUBH_H16_HL, + HEX_INS_A2_SUBH_H16_LH, + HEX_INS_A2_SUBH_H16_LL, + HEX_INS_A2_SUBH_H16_SAT_HH, + HEX_INS_A2_SUBH_H16_SAT_HL, + HEX_INS_A2_SUBH_H16_SAT_LH, + HEX_INS_A2_SUBH_H16_SAT_LL, + HEX_INS_A2_SUBH_L16_HL, + HEX_INS_A2_SUBH_L16_LL, + HEX_INS_A2_SUBH_L16_SAT_HL, + HEX_INS_A2_SUBH_L16_SAT_LL, + HEX_INS_A2_SUBP, + HEX_INS_A2_SUBRI, + HEX_INS_A2_SUBSAT, + HEX_INS_A2_SVADDH, + HEX_INS_A2_SVADDHS, + HEX_INS_A2_SVADDUHS, + HEX_INS_A2_SVAVGH, + HEX_INS_A2_SVAVGHS, + HEX_INS_A2_SVNAVGH, + HEX_INS_A2_SVSUBH, + HEX_INS_A2_SVSUBHS, + HEX_INS_A2_SVSUBUHS, + HEX_INS_A2_SWIZ, + HEX_INS_A2_SXTB, + HEX_INS_A2_SXTH, + HEX_INS_A2_SXTW, + HEX_INS_A2_TFR, + HEX_INS_A2_TFRCRR, + HEX_INS_A2_TFRIH, + HEX_INS_A2_TFRIL, + HEX_INS_A2_TFRRCR, + HEX_INS_A2_TFRSI, + HEX_INS_A2_VABSH, + HEX_INS_A2_VABSHSAT, + HEX_INS_A2_VABSW, + HEX_INS_A2_VABSWSAT, + HEX_INS_A2_VADDH, + HEX_INS_A2_VADDHS, + HEX_INS_A2_VADDUB, + HEX_INS_A2_VADDUBS, + HEX_INS_A2_VADDUHS, + HEX_INS_A2_VADDW, + HEX_INS_A2_VADDWS, + HEX_INS_A2_VAVGH, + HEX_INS_A2_VAVGHCR, + HEX_INS_A2_VAVGHR, + HEX_INS_A2_VAVGUB, + HEX_INS_A2_VAVGUBR, + HEX_INS_A2_VAVGUH, + HEX_INS_A2_VAVGUHR, + HEX_INS_A2_VAVGUW, + HEX_INS_A2_VAVGUWR, + HEX_INS_A2_VAVGW, + HEX_INS_A2_VAVGWCR, + HEX_INS_A2_VAVGWR, + HEX_INS_A2_VCMPBEQ, + HEX_INS_A2_VCMPBGTU, + HEX_INS_A2_VCMPHEQ, + HEX_INS_A2_VCMPHGT, + HEX_INS_A2_VCMPHGTU, + HEX_INS_A2_VCMPWEQ, + HEX_INS_A2_VCMPWGT, + HEX_INS_A2_VCMPWGTU, + HEX_INS_A2_VCONJ, + HEX_INS_A2_VMAXB, + HEX_INS_A2_VMAXH, + HEX_INS_A2_VMAXUB, + HEX_INS_A2_VMAXUH, + HEX_INS_A2_VMAXUW, + HEX_INS_A2_VMAXW, + HEX_INS_A2_VMINB, + HEX_INS_A2_VMINH, + HEX_INS_A2_VMINUB, + HEX_INS_A2_VMINUH, + HEX_INS_A2_VMINUW, + HEX_INS_A2_VMINW, + HEX_INS_A2_VNAVGH, + HEX_INS_A2_VNAVGHCR, + HEX_INS_A2_VNAVGHR, + HEX_INS_A2_VNAVGW, + HEX_INS_A2_VNAVGWCR, + HEX_INS_A2_VNAVGWR, + HEX_INS_A2_VRADDUB, + HEX_INS_A2_VRADDUB_ACC, + HEX_INS_A2_VRSADUB, + HEX_INS_A2_VRSADUB_ACC, + HEX_INS_A2_VSUBH, + HEX_INS_A2_VSUBHS, + HEX_INS_A2_VSUBUB, + HEX_INS_A2_VSUBUBS, + HEX_INS_A2_VSUBUHS, + HEX_INS_A2_VSUBW, + HEX_INS_A2_VSUBWS, + HEX_INS_A2_XOR, + HEX_INS_A2_XORP, + HEX_INS_A2_ZXTH, + HEX_INS_A4_ADDP_C, + HEX_INS_A4_ANDN, + HEX_INS_A4_ANDNP, + HEX_INS_A4_BITSPLIT, + HEX_INS_A4_BITSPLITI, + HEX_INS_A4_BOUNDSCHECK_HI, + HEX_INS_A4_BOUNDSCHECK_LO, + HEX_INS_A4_CMPBEQ, + HEX_INS_A4_CMPBEQI, + HEX_INS_A4_CMPBGT, + HEX_INS_A4_CMPBGTI, + HEX_INS_A4_CMPBGTU, + HEX_INS_A4_CMPBGTUI, + HEX_INS_A4_CMPHEQ, + HEX_INS_A4_CMPHEQI, + HEX_INS_A4_CMPHGT, + HEX_INS_A4_CMPHGTI, + HEX_INS_A4_CMPHGTU, + HEX_INS_A4_CMPHGTUI, + HEX_INS_A4_COMBINEII, + HEX_INS_A4_COMBINEIR, + HEX_INS_A4_COMBINERI, + HEX_INS_A4_CROUND_RI, + HEX_INS_A4_CROUND_RR, + HEX_INS_A4_EXT, + HEX_INS_A4_MODWRAPU, + HEX_INS_A4_ORN, + HEX_INS_A4_ORNP, + HEX_INS_A4_PASLHF, + HEX_INS_A4_PASLHFNEW, + HEX_INS_A4_PASLHT, + HEX_INS_A4_PASLHTNEW, + HEX_INS_A4_PASRHF, + HEX_INS_A4_PASRHFNEW, + HEX_INS_A4_PASRHT, + HEX_INS_A4_PASRHTNEW, + HEX_INS_A4_PSXTBF, + HEX_INS_A4_PSXTBFNEW, + HEX_INS_A4_PSXTBT, + HEX_INS_A4_PSXTBTNEW, + HEX_INS_A4_PSXTHF, + HEX_INS_A4_PSXTHFNEW, + HEX_INS_A4_PSXTHT, + HEX_INS_A4_PSXTHTNEW, + HEX_INS_A4_PZXTBF, + HEX_INS_A4_PZXTBFNEW, + HEX_INS_A4_PZXTBT, + HEX_INS_A4_PZXTBTNEW, + HEX_INS_A4_PZXTHF, + HEX_INS_A4_PZXTHFNEW, + HEX_INS_A4_PZXTHT, + HEX_INS_A4_PZXTHTNEW, + HEX_INS_A4_RCMPEQ, + HEX_INS_A4_RCMPEQI, + HEX_INS_A4_RCMPNEQ, + HEX_INS_A4_RCMPNEQI, + HEX_INS_A4_ROUND_RI, + HEX_INS_A4_ROUND_RI_SAT, + HEX_INS_A4_ROUND_RR, + HEX_INS_A4_ROUND_RR_SAT, + HEX_INS_A4_SUBP_C, + HEX_INS_A4_TFRCPP, + HEX_INS_A4_TFRPCP, + HEX_INS_A4_TLBMATCH, + HEX_INS_A4_VCMPBEQ_ANY, + HEX_INS_A4_VCMPBEQI, + HEX_INS_A4_VCMPBGT, + HEX_INS_A4_VCMPBGTI, + HEX_INS_A4_VCMPBGTUI, + HEX_INS_A4_VCMPHEQI, + HEX_INS_A4_VCMPHGTI, + HEX_INS_A4_VCMPHGTUI, + HEX_INS_A4_VCMPWEQI, + HEX_INS_A4_VCMPWGTI, + HEX_INS_A4_VCMPWGTUI, + HEX_INS_A4_VRMAXH, + HEX_INS_A4_VRMAXUH, + HEX_INS_A4_VRMAXUW, + HEX_INS_A4_VRMAXW, + HEX_INS_A4_VRMINH, + HEX_INS_A4_VRMINUH, + HEX_INS_A4_VRMINUW, + HEX_INS_A4_VRMINW, + HEX_INS_A5_ACS, + HEX_INS_A5_VADDHUBS, + HEX_INS_A6_VCMPBEQ_NOTANY, + HEX_INS_A6_VMINUB_RDP, + HEX_INS_A7_CLIP, + HEX_INS_A7_CROUNDD_RI, + HEX_INS_A7_CROUNDD_RR, + HEX_INS_A7_VCLIP, + HEX_INS_C2_ALL8, + HEX_INS_C2_AND, + HEX_INS_C2_ANDN, + HEX_INS_C2_ANY8, + HEX_INS_C2_BITSCLR, + HEX_INS_C2_BITSCLRI, + HEX_INS_C2_BITSSET, + HEX_INS_C2_CCOMBINEWF, + HEX_INS_C2_CCOMBINEWNEWF, + HEX_INS_C2_CCOMBINEWNEWT, + HEX_INS_C2_CCOMBINEWT, + HEX_INS_C2_CMOVEIF, + HEX_INS_C2_CMOVEIT, + HEX_INS_C2_CMOVENEWIF, + HEX_INS_C2_CMOVENEWIT, + HEX_INS_C2_CMPEQ, + HEX_INS_C2_CMPEQI, + HEX_INS_C2_CMPEQP, + HEX_INS_C2_CMPGT, + HEX_INS_C2_CMPGTI, + HEX_INS_C2_CMPGTP, + HEX_INS_C2_CMPGTU, + HEX_INS_C2_CMPGTUI, + HEX_INS_C2_CMPGTUP, + HEX_INS_C2_MASK, + HEX_INS_C2_MUX, + HEX_INS_C2_MUXII, + HEX_INS_C2_MUXIR, + HEX_INS_C2_MUXRI, + HEX_INS_C2_NOT, + HEX_INS_C2_OR, + HEX_INS_C2_ORN, + HEX_INS_C2_TFRPR, + HEX_INS_C2_TFRRP, + HEX_INS_C2_VITPACK, + HEX_INS_C2_VMUX, + HEX_INS_C2_XOR, + HEX_INS_C4_ADDIPC, + HEX_INS_C4_AND_AND, + HEX_INS_C4_AND_ANDN, + HEX_INS_C4_AND_OR, + HEX_INS_C4_AND_ORN, + HEX_INS_C4_CMPLTE, + HEX_INS_C4_CMPLTEI, + HEX_INS_C4_CMPLTEU, + HEX_INS_C4_CMPLTEUI, + HEX_INS_C4_CMPNEQ, + HEX_INS_C4_CMPNEQI, + HEX_INS_C4_FASTCORNER9, + HEX_INS_C4_FASTCORNER9_NOT, + HEX_INS_C4_NBITSCLR, + HEX_INS_C4_NBITSCLRI, + HEX_INS_C4_NBITSSET, + HEX_INS_C4_OR_AND, + HEX_INS_C4_OR_ANDN, + HEX_INS_C4_OR_OR, + HEX_INS_C4_OR_ORN, + HEX_INS_F2_CONV_D2DF, + HEX_INS_F2_CONV_D2SF, + HEX_INS_F2_CONV_DF2D, + HEX_INS_F2_CONV_DF2D_CHOP, + HEX_INS_F2_CONV_DF2SF, + HEX_INS_F2_CONV_DF2UD, + HEX_INS_F2_CONV_DF2UD_CHOP, + HEX_INS_F2_CONV_DF2UW, + HEX_INS_F2_CONV_DF2UW_CHOP, + HEX_INS_F2_CONV_DF2W, + HEX_INS_F2_CONV_DF2W_CHOP, + HEX_INS_F2_CONV_SF2D, + HEX_INS_F2_CONV_SF2D_CHOP, + HEX_INS_F2_CONV_SF2DF, + HEX_INS_F2_CONV_SF2UD, + HEX_INS_F2_CONV_SF2UD_CHOP, + HEX_INS_F2_CONV_SF2UW, + HEX_INS_F2_CONV_SF2UW_CHOP, + HEX_INS_F2_CONV_SF2W, + HEX_INS_F2_CONV_SF2W_CHOP, + HEX_INS_F2_CONV_UD2DF, + HEX_INS_F2_CONV_UD2SF, + HEX_INS_F2_CONV_UW2DF, + HEX_INS_F2_CONV_UW2SF, + HEX_INS_F2_CONV_W2DF, + HEX_INS_F2_CONV_W2SF, + HEX_INS_F2_DFADD, + HEX_INS_F2_DFCLASS, + HEX_INS_F2_DFCMPEQ, + HEX_INS_F2_DFCMPGE, + HEX_INS_F2_DFCMPGT, + HEX_INS_F2_DFCMPUO, + HEX_INS_F2_DFIMM_N, + HEX_INS_F2_DFIMM_P, + HEX_INS_F2_DFMAX, + HEX_INS_F2_DFMIN, + HEX_INS_F2_DFMPYFIX, + HEX_INS_F2_DFMPYHH, + HEX_INS_F2_DFMPYLH, + HEX_INS_F2_DFMPYLL, + HEX_INS_F2_DFSUB, + HEX_INS_F2_SFADD, + HEX_INS_F2_SFCLASS, + HEX_INS_F2_SFCMPEQ, + HEX_INS_F2_SFCMPGE, + HEX_INS_F2_SFCMPGT, + HEX_INS_F2_SFCMPUO, + HEX_INS_F2_SFFIXUPD, + HEX_INS_F2_SFFIXUPN, + HEX_INS_F2_SFFIXUPR, + HEX_INS_F2_SFFMA, + HEX_INS_F2_SFFMA_LIB, + HEX_INS_F2_SFFMA_SC, + HEX_INS_F2_SFFMS, + HEX_INS_F2_SFFMS_LIB, + HEX_INS_F2_SFIMM_N, + HEX_INS_F2_SFIMM_P, + HEX_INS_F2_SFINVSQRTA, + HEX_INS_F2_SFMAX, + HEX_INS_F2_SFMIN, + HEX_INS_F2_SFMPY, + HEX_INS_F2_SFRECIPA, + HEX_INS_F2_SFSUB, + HEX_INS_G4_TFRGCPP, + HEX_INS_G4_TFRGCRR, + HEX_INS_G4_TFRGPCP, + HEX_INS_G4_TFRGRCR, + HEX_INS_J2_CALL, + HEX_INS_J2_CALLF, + HEX_INS_J2_CALLR, + HEX_INS_J2_CALLRF, + HEX_INS_J2_CALLRT, + HEX_INS_J2_CALLT, + HEX_INS_J2_JUMP, + HEX_INS_J2_JUMPF, + HEX_INS_J2_JUMPFNEW, + HEX_INS_J2_JUMPFNEWPT, + HEX_INS_J2_JUMPFPT, + HEX_INS_J2_JUMPR, + HEX_INS_J2_JUMPRF, + HEX_INS_J2_JUMPRFNEW, + HEX_INS_J2_JUMPRFNEWPT, + HEX_INS_J2_JUMPRFPT, + HEX_INS_J2_JUMPRGTEZ, + HEX_INS_J2_JUMPRGTEZPT, + HEX_INS_J2_JUMPRLTEZ, + HEX_INS_J2_JUMPRLTEZPT, + HEX_INS_J2_JUMPRNZ, + HEX_INS_J2_JUMPRNZPT, + HEX_INS_J2_JUMPRT, + HEX_INS_J2_JUMPRTNEW, + HEX_INS_J2_JUMPRTNEWPT, + HEX_INS_J2_JUMPRTPT, + HEX_INS_J2_JUMPRZ, + HEX_INS_J2_JUMPRZPT, + HEX_INS_J2_JUMPT, + HEX_INS_J2_JUMPTNEW, + HEX_INS_J2_JUMPTNEWPT, + HEX_INS_J2_JUMPTPT, + HEX_INS_J2_LOOP0I, + HEX_INS_J2_LOOP0R, + HEX_INS_J2_LOOP1I, + HEX_INS_J2_LOOP1R, + HEX_INS_J2_PAUSE, + HEX_INS_J2_PLOOP1SI, + HEX_INS_J2_PLOOP1SR, + HEX_INS_J2_PLOOP2SI, + HEX_INS_J2_PLOOP2SR, + HEX_INS_J2_PLOOP3SI, + HEX_INS_J2_PLOOP3SR, + HEX_INS_J2_TRAP0, + HEX_INS_J2_TRAP1, + HEX_INS_J4_CMPEQ_F_JUMPNV_NT, + HEX_INS_J4_CMPEQ_F_JUMPNV_T, + HEX_INS_J4_CMPEQ_FP0_JUMP_NT, + HEX_INS_J4_CMPEQ_FP0_JUMP_T, + HEX_INS_J4_CMPEQ_FP1_JUMP_NT, + HEX_INS_J4_CMPEQ_FP1_JUMP_T, + HEX_INS_J4_CMPEQ_T_JUMPNV_NT, + HEX_INS_J4_CMPEQ_T_JUMPNV_T, + HEX_INS_J4_CMPEQ_TP0_JUMP_NT, + HEX_INS_J4_CMPEQ_TP0_JUMP_T, + HEX_INS_J4_CMPEQ_TP1_JUMP_NT, + HEX_INS_J4_CMPEQ_TP1_JUMP_T, + HEX_INS_J4_CMPEQI_F_JUMPNV_NT, + HEX_INS_J4_CMPEQI_F_JUMPNV_T, + HEX_INS_J4_CMPEQI_FP0_JUMP_NT, + HEX_INS_J4_CMPEQI_FP0_JUMP_T, + HEX_INS_J4_CMPEQI_FP1_JUMP_NT, + HEX_INS_J4_CMPEQI_FP1_JUMP_T, + HEX_INS_J4_CMPEQI_T_JUMPNV_NT, + HEX_INS_J4_CMPEQI_T_JUMPNV_T, + HEX_INS_J4_CMPEQI_TP0_JUMP_NT, + HEX_INS_J4_CMPEQI_TP0_JUMP_T, + HEX_INS_J4_CMPEQI_TP1_JUMP_NT, + HEX_INS_J4_CMPEQI_TP1_JUMP_T, + HEX_INS_J4_CMPEQN1_F_JUMPNV_NT, + HEX_INS_J4_CMPEQN1_F_JUMPNV_T, + HEX_INS_J4_CMPEQN1_FP0_JUMP_NT, + HEX_INS_J4_CMPEQN1_FP0_JUMP_T, + HEX_INS_J4_CMPEQN1_FP1_JUMP_NT, + HEX_INS_J4_CMPEQN1_FP1_JUMP_T, + HEX_INS_J4_CMPEQN1_T_JUMPNV_NT, + HEX_INS_J4_CMPEQN1_T_JUMPNV_T, + HEX_INS_J4_CMPEQN1_TP0_JUMP_NT, + HEX_INS_J4_CMPEQN1_TP0_JUMP_T, + HEX_INS_J4_CMPEQN1_TP1_JUMP_NT, + HEX_INS_J4_CMPEQN1_TP1_JUMP_T, + HEX_INS_J4_CMPGT_F_JUMPNV_NT, + HEX_INS_J4_CMPGT_F_JUMPNV_T, + HEX_INS_J4_CMPGT_FP0_JUMP_NT, + HEX_INS_J4_CMPGT_FP0_JUMP_T, + HEX_INS_J4_CMPGT_FP1_JUMP_NT, + HEX_INS_J4_CMPGT_FP1_JUMP_T, + HEX_INS_J4_CMPGT_T_JUMPNV_NT, + HEX_INS_J4_CMPGT_T_JUMPNV_T, + HEX_INS_J4_CMPGT_TP0_JUMP_NT, + HEX_INS_J4_CMPGT_TP0_JUMP_T, + HEX_INS_J4_CMPGT_TP1_JUMP_NT, + HEX_INS_J4_CMPGT_TP1_JUMP_T, + HEX_INS_J4_CMPGTI_F_JUMPNV_NT, + HEX_INS_J4_CMPGTI_F_JUMPNV_T, + HEX_INS_J4_CMPGTI_FP0_JUMP_NT, + HEX_INS_J4_CMPGTI_FP0_JUMP_T, + HEX_INS_J4_CMPGTI_FP1_JUMP_NT, + HEX_INS_J4_CMPGTI_FP1_JUMP_T, + HEX_INS_J4_CMPGTI_T_JUMPNV_NT, + HEX_INS_J4_CMPGTI_T_JUMPNV_T, + HEX_INS_J4_CMPGTI_TP0_JUMP_NT, + HEX_INS_J4_CMPGTI_TP0_JUMP_T, + HEX_INS_J4_CMPGTI_TP1_JUMP_NT, + HEX_INS_J4_CMPGTI_TP1_JUMP_T, + HEX_INS_J4_CMPGTN1_F_JUMPNV_NT, + HEX_INS_J4_CMPGTN1_F_JUMPNV_T, + HEX_INS_J4_CMPGTN1_FP0_JUMP_NT, + HEX_INS_J4_CMPGTN1_FP0_JUMP_T, + HEX_INS_J4_CMPGTN1_FP1_JUMP_NT, + HEX_INS_J4_CMPGTN1_FP1_JUMP_T, + HEX_INS_J4_CMPGTN1_T_JUMPNV_NT, + HEX_INS_J4_CMPGTN1_T_JUMPNV_T, + HEX_INS_J4_CMPGTN1_TP0_JUMP_NT, + HEX_INS_J4_CMPGTN1_TP0_JUMP_T, + HEX_INS_J4_CMPGTN1_TP1_JUMP_NT, + HEX_INS_J4_CMPGTN1_TP1_JUMP_T, + HEX_INS_J4_CMPGTU_F_JUMPNV_NT, + HEX_INS_J4_CMPGTU_F_JUMPNV_T, + HEX_INS_J4_CMPGTU_FP0_JUMP_NT, + HEX_INS_J4_CMPGTU_FP0_JUMP_T, + HEX_INS_J4_CMPGTU_FP1_JUMP_NT, + HEX_INS_J4_CMPGTU_FP1_JUMP_T, + HEX_INS_J4_CMPGTU_T_JUMPNV_NT, + HEX_INS_J4_CMPGTU_T_JUMPNV_T, + HEX_INS_J4_CMPGTU_TP0_JUMP_NT, + HEX_INS_J4_CMPGTU_TP0_JUMP_T, + HEX_INS_J4_CMPGTU_TP1_JUMP_NT, + HEX_INS_J4_CMPGTU_TP1_JUMP_T, + HEX_INS_J4_CMPGTUI_F_JUMPNV_NT, + HEX_INS_J4_CMPGTUI_F_JUMPNV_T, + HEX_INS_J4_CMPGTUI_FP0_JUMP_NT, + HEX_INS_J4_CMPGTUI_FP0_JUMP_T, + HEX_INS_J4_CMPGTUI_FP1_JUMP_NT, + HEX_INS_J4_CMPGTUI_FP1_JUMP_T, + HEX_INS_J4_CMPGTUI_T_JUMPNV_NT, + HEX_INS_J4_CMPGTUI_T_JUMPNV_T, + HEX_INS_J4_CMPGTUI_TP0_JUMP_NT, + HEX_INS_J4_CMPGTUI_TP0_JUMP_T, + HEX_INS_J4_CMPGTUI_TP1_JUMP_NT, + HEX_INS_J4_CMPGTUI_TP1_JUMP_T, + HEX_INS_J4_CMPLT_F_JUMPNV_NT, + HEX_INS_J4_CMPLT_F_JUMPNV_T, + HEX_INS_J4_CMPLT_T_JUMPNV_NT, + HEX_INS_J4_CMPLT_T_JUMPNV_T, + HEX_INS_J4_CMPLTU_F_JUMPNV_NT, + HEX_INS_J4_CMPLTU_F_JUMPNV_T, + HEX_INS_J4_CMPLTU_T_JUMPNV_NT, + HEX_INS_J4_CMPLTU_T_JUMPNV_T, + HEX_INS_J4_HINTJUMPR, + HEX_INS_J4_JUMPSETI, + HEX_INS_J4_JUMPSETR, + HEX_INS_J4_TSTBIT0_F_JUMPNV_NT, + HEX_INS_J4_TSTBIT0_F_JUMPNV_T, + HEX_INS_J4_TSTBIT0_FP0_JUMP_NT, + HEX_INS_J4_TSTBIT0_FP0_JUMP_T, + HEX_INS_J4_TSTBIT0_FP1_JUMP_NT, + HEX_INS_J4_TSTBIT0_FP1_JUMP_T, + HEX_INS_J4_TSTBIT0_T_JUMPNV_NT, + HEX_INS_J4_TSTBIT0_T_JUMPNV_T, + HEX_INS_J4_TSTBIT0_TP0_JUMP_NT, + HEX_INS_J4_TSTBIT0_TP0_JUMP_T, + HEX_INS_J4_TSTBIT0_TP1_JUMP_NT, + HEX_INS_J4_TSTBIT0_TP1_JUMP_T, + HEX_INS_L2_DEALLOCFRAME, + HEX_INS_L2_LOADALIGNB_IO, + HEX_INS_L2_LOADALIGNB_PBR, + HEX_INS_L2_LOADALIGNB_PCI, + HEX_INS_L2_LOADALIGNB_PCR, + HEX_INS_L2_LOADALIGNB_PI, + HEX_INS_L2_LOADALIGNB_PR, + HEX_INS_L2_LOADALIGNH_IO, + HEX_INS_L2_LOADALIGNH_PBR, + HEX_INS_L2_LOADALIGNH_PCI, + HEX_INS_L2_LOADALIGNH_PCR, + HEX_INS_L2_LOADALIGNH_PI, + HEX_INS_L2_LOADALIGNH_PR, + HEX_INS_L2_LOADBSW2_IO, + HEX_INS_L2_LOADBSW2_PBR, + HEX_INS_L2_LOADBSW2_PCI, + HEX_INS_L2_LOADBSW2_PCR, + HEX_INS_L2_LOADBSW2_PI, + HEX_INS_L2_LOADBSW2_PR, + HEX_INS_L2_LOADBSW4_IO, + HEX_INS_L2_LOADBSW4_PBR, + HEX_INS_L2_LOADBSW4_PCI, + HEX_INS_L2_LOADBSW4_PCR, + HEX_INS_L2_LOADBSW4_PI, + HEX_INS_L2_LOADBSW4_PR, + HEX_INS_L2_LOADBZW2_IO, + HEX_INS_L2_LOADBZW2_PBR, + HEX_INS_L2_LOADBZW2_PCI, + HEX_INS_L2_LOADBZW2_PCR, + HEX_INS_L2_LOADBZW2_PI, + HEX_INS_L2_LOADBZW2_PR, + HEX_INS_L2_LOADBZW4_IO, + HEX_INS_L2_LOADBZW4_PBR, + HEX_INS_L2_LOADBZW4_PCI, + HEX_INS_L2_LOADBZW4_PCR, + HEX_INS_L2_LOADBZW4_PI, + HEX_INS_L2_LOADBZW4_PR, + HEX_INS_L2_LOADRB_IO, + HEX_INS_L2_LOADRB_PBR, + HEX_INS_L2_LOADRB_PCI, + HEX_INS_L2_LOADRB_PCR, + HEX_INS_L2_LOADRB_PI, + HEX_INS_L2_LOADRB_PR, + HEX_INS_L2_LOADRBGP, + HEX_INS_L2_LOADRD_IO, + HEX_INS_L2_LOADRD_PBR, + HEX_INS_L2_LOADRD_PCI, + HEX_INS_L2_LOADRD_PCR, + HEX_INS_L2_LOADRD_PI, + HEX_INS_L2_LOADRD_PR, + HEX_INS_L2_LOADRDGP, + HEX_INS_L2_LOADRH_IO, + HEX_INS_L2_LOADRH_PBR, + HEX_INS_L2_LOADRH_PCI, + HEX_INS_L2_LOADRH_PCR, + HEX_INS_L2_LOADRH_PI, + HEX_INS_L2_LOADRH_PR, + HEX_INS_L2_LOADRHGP, + HEX_INS_L2_LOADRI_IO, + HEX_INS_L2_LOADRI_PBR, + HEX_INS_L2_LOADRI_PCI, + HEX_INS_L2_LOADRI_PCR, + HEX_INS_L2_LOADRI_PI, + HEX_INS_L2_LOADRI_PR, + HEX_INS_L2_LOADRIGP, + HEX_INS_L2_LOADRUB_IO, + HEX_INS_L2_LOADRUB_PBR, + HEX_INS_L2_LOADRUB_PCI, + HEX_INS_L2_LOADRUB_PCR, + HEX_INS_L2_LOADRUB_PI, + HEX_INS_L2_LOADRUB_PR, + HEX_INS_L2_LOADRUBGP, + HEX_INS_L2_LOADRUH_IO, + HEX_INS_L2_LOADRUH_PBR, + HEX_INS_L2_LOADRUH_PCI, + HEX_INS_L2_LOADRUH_PCR, + HEX_INS_L2_LOADRUH_PI, + HEX_INS_L2_LOADRUH_PR, + HEX_INS_L2_LOADRUHGP, + HEX_INS_L2_LOADW_AQ, + HEX_INS_L2_LOADW_LOCKED, + HEX_INS_L2_PLOADRBF_IO, + HEX_INS_L2_PLOADRBF_PI, + HEX_INS_L2_PLOADRBFNEW_IO, + HEX_INS_L2_PLOADRBFNEW_PI, + HEX_INS_L2_PLOADRBT_IO, + HEX_INS_L2_PLOADRBT_PI, + HEX_INS_L2_PLOADRBTNEW_IO, + HEX_INS_L2_PLOADRBTNEW_PI, + HEX_INS_L2_PLOADRDF_IO, + HEX_INS_L2_PLOADRDF_PI, + HEX_INS_L2_PLOADRDFNEW_IO, + HEX_INS_L2_PLOADRDFNEW_PI, + HEX_INS_L2_PLOADRDT_IO, + HEX_INS_L2_PLOADRDT_PI, + HEX_INS_L2_PLOADRDTNEW_IO, + HEX_INS_L2_PLOADRDTNEW_PI, + HEX_INS_L2_PLOADRHF_IO, + HEX_INS_L2_PLOADRHF_PI, + HEX_INS_L2_PLOADRHFNEW_IO, + HEX_INS_L2_PLOADRHFNEW_PI, + HEX_INS_L2_PLOADRHT_IO, + HEX_INS_L2_PLOADRHT_PI, + HEX_INS_L2_PLOADRHTNEW_IO, + HEX_INS_L2_PLOADRHTNEW_PI, + HEX_INS_L2_PLOADRIF_IO, + HEX_INS_L2_PLOADRIF_PI, + HEX_INS_L2_PLOADRIFNEW_IO, + HEX_INS_L2_PLOADRIFNEW_PI, + HEX_INS_L2_PLOADRIT_IO, + HEX_INS_L2_PLOADRIT_PI, + HEX_INS_L2_PLOADRITNEW_IO, + HEX_INS_L2_PLOADRITNEW_PI, + HEX_INS_L2_PLOADRUBF_IO, + HEX_INS_L2_PLOADRUBF_PI, + HEX_INS_L2_PLOADRUBFNEW_IO, + HEX_INS_L2_PLOADRUBFNEW_PI, + HEX_INS_L2_PLOADRUBT_IO, + HEX_INS_L2_PLOADRUBT_PI, + HEX_INS_L2_PLOADRUBTNEW_IO, + HEX_INS_L2_PLOADRUBTNEW_PI, + HEX_INS_L2_PLOADRUHF_IO, + HEX_INS_L2_PLOADRUHF_PI, + HEX_INS_L2_PLOADRUHFNEW_IO, + HEX_INS_L2_PLOADRUHFNEW_PI, + HEX_INS_L2_PLOADRUHT_IO, + HEX_INS_L2_PLOADRUHT_PI, + HEX_INS_L2_PLOADRUHTNEW_IO, + HEX_INS_L2_PLOADRUHTNEW_PI, + HEX_INS_L4_ADD_MEMOPB_IO, + HEX_INS_L4_ADD_MEMOPH_IO, + HEX_INS_L4_ADD_MEMOPW_IO, + HEX_INS_L4_AND_MEMOPB_IO, + HEX_INS_L4_AND_MEMOPH_IO, + HEX_INS_L4_AND_MEMOPW_IO, + HEX_INS_L4_IADD_MEMOPB_IO, + HEX_INS_L4_IADD_MEMOPH_IO, + HEX_INS_L4_IADD_MEMOPW_IO, + HEX_INS_L4_IAND_MEMOPB_IO, + HEX_INS_L4_IAND_MEMOPH_IO, + HEX_INS_L4_IAND_MEMOPW_IO, + HEX_INS_L4_IOR_MEMOPB_IO, + HEX_INS_L4_IOR_MEMOPH_IO, + HEX_INS_L4_IOR_MEMOPW_IO, + HEX_INS_L4_ISUB_MEMOPB_IO, + HEX_INS_L4_ISUB_MEMOPH_IO, + HEX_INS_L4_ISUB_MEMOPW_IO, + HEX_INS_L4_LOADALIGNB_AP, + HEX_INS_L4_LOADALIGNB_UR, + HEX_INS_L4_LOADALIGNH_AP, + HEX_INS_L4_LOADALIGNH_UR, + HEX_INS_L4_LOADBSW2_AP, + HEX_INS_L4_LOADBSW2_UR, + HEX_INS_L4_LOADBSW4_AP, + HEX_INS_L4_LOADBSW4_UR, + HEX_INS_L4_LOADBZW2_AP, + HEX_INS_L4_LOADBZW2_UR, + HEX_INS_L4_LOADBZW4_AP, + HEX_INS_L4_LOADBZW4_UR, + HEX_INS_L4_LOADD_AQ, + HEX_INS_L4_LOADD_LOCKED, + HEX_INS_L4_LOADRB_AP, + HEX_INS_L4_LOADRB_RR, + HEX_INS_L4_LOADRB_UR, + HEX_INS_L4_LOADRD_AP, + HEX_INS_L4_LOADRD_RR, + HEX_INS_L4_LOADRD_UR, + HEX_INS_L4_LOADRH_AP, + HEX_INS_L4_LOADRH_RR, + HEX_INS_L4_LOADRH_UR, + HEX_INS_L4_LOADRI_AP, + HEX_INS_L4_LOADRI_RR, + HEX_INS_L4_LOADRI_UR, + HEX_INS_L4_LOADRUB_AP, + HEX_INS_L4_LOADRUB_RR, + HEX_INS_L4_LOADRUB_UR, + HEX_INS_L4_LOADRUH_AP, + HEX_INS_L4_LOADRUH_RR, + HEX_INS_L4_LOADRUH_UR, + HEX_INS_L4_OR_MEMOPB_IO, + HEX_INS_L4_OR_MEMOPH_IO, + HEX_INS_L4_OR_MEMOPW_IO, + HEX_INS_L4_PLOADRBF_ABS, + HEX_INS_L4_PLOADRBF_RR, + HEX_INS_L4_PLOADRBFNEW_ABS, + HEX_INS_L4_PLOADRBFNEW_RR, + HEX_INS_L4_PLOADRBT_ABS, + HEX_INS_L4_PLOADRBT_RR, + HEX_INS_L4_PLOADRBTNEW_ABS, + HEX_INS_L4_PLOADRBTNEW_RR, + HEX_INS_L4_PLOADRDF_ABS, + HEX_INS_L4_PLOADRDF_RR, + HEX_INS_L4_PLOADRDFNEW_ABS, + HEX_INS_L4_PLOADRDFNEW_RR, + HEX_INS_L4_PLOADRDT_ABS, + HEX_INS_L4_PLOADRDT_RR, + HEX_INS_L4_PLOADRDTNEW_ABS, + HEX_INS_L4_PLOADRDTNEW_RR, + HEX_INS_L4_PLOADRHF_ABS, + HEX_INS_L4_PLOADRHF_RR, + HEX_INS_L4_PLOADRHFNEW_ABS, + HEX_INS_L4_PLOADRHFNEW_RR, + HEX_INS_L4_PLOADRHT_ABS, + HEX_INS_L4_PLOADRHT_RR, + HEX_INS_L4_PLOADRHTNEW_ABS, + HEX_INS_L4_PLOADRHTNEW_RR, + HEX_INS_L4_PLOADRIF_ABS, + HEX_INS_L4_PLOADRIF_RR, + HEX_INS_L4_PLOADRIFNEW_ABS, + HEX_INS_L4_PLOADRIFNEW_RR, + HEX_INS_L4_PLOADRIT_ABS, + HEX_INS_L4_PLOADRIT_RR, + HEX_INS_L4_PLOADRITNEW_ABS, + HEX_INS_L4_PLOADRITNEW_RR, + HEX_INS_L4_PLOADRUBF_ABS, + HEX_INS_L4_PLOADRUBF_RR, + HEX_INS_L4_PLOADRUBFNEW_ABS, + HEX_INS_L4_PLOADRUBFNEW_RR, + HEX_INS_L4_PLOADRUBT_ABS, + HEX_INS_L4_PLOADRUBT_RR, + HEX_INS_L4_PLOADRUBTNEW_ABS, + HEX_INS_L4_PLOADRUBTNEW_RR, + HEX_INS_L4_PLOADRUHF_ABS, + HEX_INS_L4_PLOADRUHF_RR, + HEX_INS_L4_PLOADRUHFNEW_ABS, + HEX_INS_L4_PLOADRUHFNEW_RR, + HEX_INS_L4_PLOADRUHT_ABS, + HEX_INS_L4_PLOADRUHT_RR, + HEX_INS_L4_PLOADRUHTNEW_ABS, + HEX_INS_L4_PLOADRUHTNEW_RR, + HEX_INS_L4_RETURN, + HEX_INS_L4_RETURN_F, + HEX_INS_L4_RETURN_FNEW_PNT, + HEX_INS_L4_RETURN_FNEW_PT, + HEX_INS_L4_RETURN_T, + HEX_INS_L4_RETURN_TNEW_PNT, + HEX_INS_L4_RETURN_TNEW_PT, + HEX_INS_L4_SUB_MEMOPB_IO, + HEX_INS_L4_SUB_MEMOPH_IO, + HEX_INS_L4_SUB_MEMOPW_IO, + HEX_INS_L6_MEMCPY, + HEX_INS_M2_ACCI, + HEX_INS_M2_ACCII, + HEX_INS_M2_CMACI_S0, + HEX_INS_M2_CMACR_S0, + HEX_INS_M2_CMACS_S0, + HEX_INS_M2_CMACS_S1, + HEX_INS_M2_CMACSC_S0, + HEX_INS_M2_CMACSC_S1, + HEX_INS_M2_CMPYI_S0, + HEX_INS_M2_CMPYR_S0, + HEX_INS_M2_CMPYRS_S0, + HEX_INS_M2_CMPYRS_S1, + HEX_INS_M2_CMPYRSC_S0, + HEX_INS_M2_CMPYRSC_S1, + HEX_INS_M2_CMPYS_S0, + HEX_INS_M2_CMPYS_S1, + HEX_INS_M2_CMPYSC_S0, + HEX_INS_M2_CMPYSC_S1, + HEX_INS_M2_CNACS_S0, + HEX_INS_M2_CNACS_S1, + HEX_INS_M2_CNACSC_S0, + HEX_INS_M2_CNACSC_S1, + HEX_INS_M2_DPMPYSS_ACC_S0, + HEX_INS_M2_DPMPYSS_NAC_S0, + HEX_INS_M2_DPMPYSS_RND_S0, + HEX_INS_M2_DPMPYSS_S0, + HEX_INS_M2_DPMPYUU_ACC_S0, + HEX_INS_M2_DPMPYUU_NAC_S0, + HEX_INS_M2_DPMPYUU_S0, + HEX_INS_M2_HMMPYH_RS1, + HEX_INS_M2_HMMPYH_S1, + HEX_INS_M2_HMMPYL_RS1, + HEX_INS_M2_HMMPYL_S1, + HEX_INS_M2_MACI, + HEX_INS_M2_MACSIN, + HEX_INS_M2_MACSIP, + HEX_INS_M2_MMACHS_RS0, + HEX_INS_M2_MMACHS_RS1, + HEX_INS_M2_MMACHS_S0, + HEX_INS_M2_MMACHS_S1, + HEX_INS_M2_MMACLS_RS0, + HEX_INS_M2_MMACLS_RS1, + HEX_INS_M2_MMACLS_S0, + HEX_INS_M2_MMACLS_S1, + HEX_INS_M2_MMACUHS_RS0, + HEX_INS_M2_MMACUHS_RS1, + HEX_INS_M2_MMACUHS_S0, + HEX_INS_M2_MMACUHS_S1, + HEX_INS_M2_MMACULS_RS0, + HEX_INS_M2_MMACULS_RS1, + HEX_INS_M2_MMACULS_S0, + HEX_INS_M2_MMACULS_S1, + HEX_INS_M2_MMPYH_RS0, + HEX_INS_M2_MMPYH_RS1, + HEX_INS_M2_MMPYH_S0, + HEX_INS_M2_MMPYH_S1, + HEX_INS_M2_MMPYL_RS0, + HEX_INS_M2_MMPYL_RS1, + HEX_INS_M2_MMPYL_S0, + HEX_INS_M2_MMPYL_S1, + HEX_INS_M2_MMPYUH_RS0, + HEX_INS_M2_MMPYUH_RS1, + HEX_INS_M2_MMPYUH_S0, + HEX_INS_M2_MMPYUH_S1, + HEX_INS_M2_MMPYUL_RS0, + HEX_INS_M2_MMPYUL_RS1, + HEX_INS_M2_MMPYUL_S0, + HEX_INS_M2_MMPYUL_S1, + HEX_INS_M2_MNACI, + HEX_INS_M2_MPY_ACC_HH_S0, + HEX_INS_M2_MPY_ACC_HH_S1, + HEX_INS_M2_MPY_ACC_HL_S0, + HEX_INS_M2_MPY_ACC_HL_S1, + HEX_INS_M2_MPY_ACC_LH_S0, + HEX_INS_M2_MPY_ACC_LH_S1, + HEX_INS_M2_MPY_ACC_LL_S0, + HEX_INS_M2_MPY_ACC_LL_S1, + HEX_INS_M2_MPY_ACC_SAT_HH_S0, + HEX_INS_M2_MPY_ACC_SAT_HH_S1, + HEX_INS_M2_MPY_ACC_SAT_HL_S0, + HEX_INS_M2_MPY_ACC_SAT_HL_S1, + HEX_INS_M2_MPY_ACC_SAT_LH_S0, + HEX_INS_M2_MPY_ACC_SAT_LH_S1, + HEX_INS_M2_MPY_ACC_SAT_LL_S0, + HEX_INS_M2_MPY_ACC_SAT_LL_S1, + HEX_INS_M2_MPY_HH_S0, + HEX_INS_M2_MPY_HH_S1, + HEX_INS_M2_MPY_HL_S0, + HEX_INS_M2_MPY_HL_S1, + HEX_INS_M2_MPY_LH_S0, + HEX_INS_M2_MPY_LH_S1, + HEX_INS_M2_MPY_LL_S0, + HEX_INS_M2_MPY_LL_S1, + HEX_INS_M2_MPY_NAC_HH_S0, + HEX_INS_M2_MPY_NAC_HH_S1, + HEX_INS_M2_MPY_NAC_HL_S0, + HEX_INS_M2_MPY_NAC_HL_S1, + HEX_INS_M2_MPY_NAC_LH_S0, + HEX_INS_M2_MPY_NAC_LH_S1, + HEX_INS_M2_MPY_NAC_LL_S0, + HEX_INS_M2_MPY_NAC_LL_S1, + HEX_INS_M2_MPY_NAC_SAT_HH_S0, + HEX_INS_M2_MPY_NAC_SAT_HH_S1, + HEX_INS_M2_MPY_NAC_SAT_HL_S0, + HEX_INS_M2_MPY_NAC_SAT_HL_S1, + HEX_INS_M2_MPY_NAC_SAT_LH_S0, + HEX_INS_M2_MPY_NAC_SAT_LH_S1, + HEX_INS_M2_MPY_NAC_SAT_LL_S0, + HEX_INS_M2_MPY_NAC_SAT_LL_S1, + HEX_INS_M2_MPY_RND_HH_S0, + HEX_INS_M2_MPY_RND_HH_S1, + HEX_INS_M2_MPY_RND_HL_S0, + HEX_INS_M2_MPY_RND_HL_S1, + HEX_INS_M2_MPY_RND_LH_S0, + HEX_INS_M2_MPY_RND_LH_S1, + HEX_INS_M2_MPY_RND_LL_S0, + HEX_INS_M2_MPY_RND_LL_S1, + HEX_INS_M2_MPY_SAT_HH_S0, + HEX_INS_M2_MPY_SAT_HH_S1, + HEX_INS_M2_MPY_SAT_HL_S0, + HEX_INS_M2_MPY_SAT_HL_S1, + HEX_INS_M2_MPY_SAT_LH_S0, + HEX_INS_M2_MPY_SAT_LH_S1, + HEX_INS_M2_MPY_SAT_LL_S0, + HEX_INS_M2_MPY_SAT_LL_S1, + HEX_INS_M2_MPY_SAT_RND_HH_S0, + HEX_INS_M2_MPY_SAT_RND_HH_S1, + HEX_INS_M2_MPY_SAT_RND_HL_S0, + HEX_INS_M2_MPY_SAT_RND_HL_S1, + HEX_INS_M2_MPY_SAT_RND_LH_S0, + HEX_INS_M2_MPY_SAT_RND_LH_S1, + HEX_INS_M2_MPY_SAT_RND_LL_S0, + HEX_INS_M2_MPY_SAT_RND_LL_S1, + HEX_INS_M2_MPY_UP, + HEX_INS_M2_MPY_UP_S1, + HEX_INS_M2_MPY_UP_S1_SAT, + HEX_INS_M2_MPYD_ACC_HH_S0, + HEX_INS_M2_MPYD_ACC_HH_S1, + HEX_INS_M2_MPYD_ACC_HL_S0, + HEX_INS_M2_MPYD_ACC_HL_S1, + HEX_INS_M2_MPYD_ACC_LH_S0, + HEX_INS_M2_MPYD_ACC_LH_S1, + HEX_INS_M2_MPYD_ACC_LL_S0, + HEX_INS_M2_MPYD_ACC_LL_S1, + HEX_INS_M2_MPYD_HH_S0, + HEX_INS_M2_MPYD_HH_S1, + HEX_INS_M2_MPYD_HL_S0, + HEX_INS_M2_MPYD_HL_S1, + HEX_INS_M2_MPYD_LH_S0, + HEX_INS_M2_MPYD_LH_S1, + HEX_INS_M2_MPYD_LL_S0, + HEX_INS_M2_MPYD_LL_S1, + HEX_INS_M2_MPYD_NAC_HH_S0, + HEX_INS_M2_MPYD_NAC_HH_S1, + HEX_INS_M2_MPYD_NAC_HL_S0, + HEX_INS_M2_MPYD_NAC_HL_S1, + HEX_INS_M2_MPYD_NAC_LH_S0, + HEX_INS_M2_MPYD_NAC_LH_S1, + HEX_INS_M2_MPYD_NAC_LL_S0, + HEX_INS_M2_MPYD_NAC_LL_S1, + HEX_INS_M2_MPYD_RND_HH_S0, + HEX_INS_M2_MPYD_RND_HH_S1, + HEX_INS_M2_MPYD_RND_HL_S0, + HEX_INS_M2_MPYD_RND_HL_S1, + HEX_INS_M2_MPYD_RND_LH_S0, + HEX_INS_M2_MPYD_RND_LH_S1, + HEX_INS_M2_MPYD_RND_LL_S0, + HEX_INS_M2_MPYD_RND_LL_S1, + HEX_INS_M2_MPYI, + HEX_INS_M2_MPYSIN, + HEX_INS_M2_MPYSIP, + HEX_INS_M2_MPYSU_UP, + HEX_INS_M2_MPYU_ACC_HH_S0, + HEX_INS_M2_MPYU_ACC_HH_S1, + HEX_INS_M2_MPYU_ACC_HL_S0, + HEX_INS_M2_MPYU_ACC_HL_S1, + HEX_INS_M2_MPYU_ACC_LH_S0, + HEX_INS_M2_MPYU_ACC_LH_S1, + HEX_INS_M2_MPYU_ACC_LL_S0, + HEX_INS_M2_MPYU_ACC_LL_S1, + HEX_INS_M2_MPYU_HH_S0, + HEX_INS_M2_MPYU_HH_S1, + HEX_INS_M2_MPYU_HL_S0, + HEX_INS_M2_MPYU_HL_S1, + HEX_INS_M2_MPYU_LH_S0, + HEX_INS_M2_MPYU_LH_S1, + HEX_INS_M2_MPYU_LL_S0, + HEX_INS_M2_MPYU_LL_S1, + HEX_INS_M2_MPYU_NAC_HH_S0, + HEX_INS_M2_MPYU_NAC_HH_S1, + HEX_INS_M2_MPYU_NAC_HL_S0, + HEX_INS_M2_MPYU_NAC_HL_S1, + HEX_INS_M2_MPYU_NAC_LH_S0, + HEX_INS_M2_MPYU_NAC_LH_S1, + HEX_INS_M2_MPYU_NAC_LL_S0, + HEX_INS_M2_MPYU_NAC_LL_S1, + HEX_INS_M2_MPYU_UP, + HEX_INS_M2_MPYUD_ACC_HH_S0, + HEX_INS_M2_MPYUD_ACC_HH_S1, + HEX_INS_M2_MPYUD_ACC_HL_S0, + HEX_INS_M2_MPYUD_ACC_HL_S1, + HEX_INS_M2_MPYUD_ACC_LH_S0, + HEX_INS_M2_MPYUD_ACC_LH_S1, + HEX_INS_M2_MPYUD_ACC_LL_S0, + HEX_INS_M2_MPYUD_ACC_LL_S1, + HEX_INS_M2_MPYUD_HH_S0, + HEX_INS_M2_MPYUD_HH_S1, + HEX_INS_M2_MPYUD_HL_S0, + HEX_INS_M2_MPYUD_HL_S1, + HEX_INS_M2_MPYUD_LH_S0, + HEX_INS_M2_MPYUD_LH_S1, + HEX_INS_M2_MPYUD_LL_S0, + HEX_INS_M2_MPYUD_LL_S1, + HEX_INS_M2_MPYUD_NAC_HH_S0, + HEX_INS_M2_MPYUD_NAC_HH_S1, + HEX_INS_M2_MPYUD_NAC_HL_S0, + HEX_INS_M2_MPYUD_NAC_HL_S1, + HEX_INS_M2_MPYUD_NAC_LH_S0, + HEX_INS_M2_MPYUD_NAC_LH_S1, + HEX_INS_M2_MPYUD_NAC_LL_S0, + HEX_INS_M2_MPYUD_NAC_LL_S1, + HEX_INS_M2_NACCI, + HEX_INS_M2_NACCII, + HEX_INS_M2_SUBACC, + HEX_INS_M2_VABSDIFFH, + HEX_INS_M2_VABSDIFFW, + HEX_INS_M2_VCMAC_S0_SAT_I, + HEX_INS_M2_VCMAC_S0_SAT_R, + HEX_INS_M2_VCMPY_S0_SAT_I, + HEX_INS_M2_VCMPY_S0_SAT_R, + HEX_INS_M2_VCMPY_S1_SAT_I, + HEX_INS_M2_VCMPY_S1_SAT_R, + HEX_INS_M2_VDMACS_S0, + HEX_INS_M2_VDMACS_S1, + HEX_INS_M2_VDMPYRS_S0, + HEX_INS_M2_VDMPYRS_S1, + HEX_INS_M2_VDMPYS_S0, + HEX_INS_M2_VDMPYS_S1, + HEX_INS_M2_VMAC2, + HEX_INS_M2_VMAC2ES, + HEX_INS_M2_VMAC2ES_S0, + HEX_INS_M2_VMAC2ES_S1, + HEX_INS_M2_VMAC2S_S0, + HEX_INS_M2_VMAC2S_S1, + HEX_INS_M2_VMAC2SU_S0, + HEX_INS_M2_VMAC2SU_S1, + HEX_INS_M2_VMPY2ES_S0, + HEX_INS_M2_VMPY2ES_S1, + HEX_INS_M2_VMPY2S_S0, + HEX_INS_M2_VMPY2S_S0PACK, + HEX_INS_M2_VMPY2S_S1, + HEX_INS_M2_VMPY2S_S1PACK, + HEX_INS_M2_VMPY2SU_S0, + HEX_INS_M2_VMPY2SU_S1, + HEX_INS_M2_VRADDH, + HEX_INS_M2_VRADDUH, + HEX_INS_M2_VRCMACI_S0, + HEX_INS_M2_VRCMACI_S0C, + HEX_INS_M2_VRCMACR_S0, + HEX_INS_M2_VRCMACR_S0C, + HEX_INS_M2_VRCMPYI_S0, + HEX_INS_M2_VRCMPYI_S0C, + HEX_INS_M2_VRCMPYR_S0, + HEX_INS_M2_VRCMPYR_S0C, + HEX_INS_M2_VRCMPYS_ACC_S1_H, + HEX_INS_M2_VRCMPYS_ACC_S1_L, + HEX_INS_M2_VRCMPYS_S1_H, + HEX_INS_M2_VRCMPYS_S1_L, + HEX_INS_M2_VRCMPYS_S1RP_H, + HEX_INS_M2_VRCMPYS_S1RP_L, + HEX_INS_M2_VRMAC_S0, + HEX_INS_M2_VRMPY_S0, + HEX_INS_M2_XOR_XACC, + HEX_INS_M4_AND_AND, + HEX_INS_M4_AND_ANDN, + HEX_INS_M4_AND_OR, + HEX_INS_M4_AND_XOR, + HEX_INS_M4_CMPYI_WH, + HEX_INS_M4_CMPYI_WHC, + HEX_INS_M4_CMPYR_WH, + HEX_INS_M4_CMPYR_WHC, + HEX_INS_M4_MAC_UP_S1_SAT, + HEX_INS_M4_MPYRI_ADDI, + HEX_INS_M4_MPYRI_ADDR, + HEX_INS_M4_MPYRI_ADDR_U2, + HEX_INS_M4_MPYRR_ADDI, + HEX_INS_M4_MPYRR_ADDR, + HEX_INS_M4_NAC_UP_S1_SAT, + HEX_INS_M4_OR_AND, + HEX_INS_M4_OR_ANDN, + HEX_INS_M4_OR_OR, + HEX_INS_M4_OR_XOR, + HEX_INS_M4_PMPYW, + HEX_INS_M4_PMPYW_ACC, + HEX_INS_M4_VPMPYH, + HEX_INS_M4_VPMPYH_ACC, + HEX_INS_M4_VRMPYEH_ACC_S0, + HEX_INS_M4_VRMPYEH_ACC_S1, + HEX_INS_M4_VRMPYEH_S0, + HEX_INS_M4_VRMPYEH_S1, + HEX_INS_M4_VRMPYOH_ACC_S0, + HEX_INS_M4_VRMPYOH_ACC_S1, + HEX_INS_M4_VRMPYOH_S0, + HEX_INS_M4_VRMPYOH_S1, + HEX_INS_M4_XOR_AND, + HEX_INS_M4_XOR_ANDN, + HEX_INS_M4_XOR_OR, + HEX_INS_M4_XOR_XACC, + HEX_INS_M5_VDMACBSU, + HEX_INS_M5_VDMPYBSU, + HEX_INS_M5_VMACBSU, + HEX_INS_M5_VMACBUU, + HEX_INS_M5_VMPYBSU, + HEX_INS_M5_VMPYBUU, + HEX_INS_M5_VRMACBSU, + HEX_INS_M5_VRMACBUU, + HEX_INS_M5_VRMPYBSU, + HEX_INS_M5_VRMPYBUU, + HEX_INS_M6_VABSDIFFB, + HEX_INS_M6_VABSDIFFUB, + HEX_INS_M7_DCMPYIW, + HEX_INS_M7_DCMPYIW_ACC, + HEX_INS_M7_DCMPYIWC, + HEX_INS_M7_DCMPYIWC_ACC, + HEX_INS_M7_DCMPYRW, + HEX_INS_M7_DCMPYRW_ACC, + HEX_INS_M7_DCMPYRWC, + HEX_INS_M7_DCMPYRWC_ACC, + HEX_INS_M7_WCMPYIW, + HEX_INS_M7_WCMPYIW_RND, + HEX_INS_M7_WCMPYIWC, + HEX_INS_M7_WCMPYIWC_RND, + HEX_INS_M7_WCMPYRW, + HEX_INS_M7_WCMPYRW_RND, + HEX_INS_M7_WCMPYRWC, + HEX_INS_M7_WCMPYRWC_RND, + HEX_INS_PS_LOADRBABS, + HEX_INS_PS_LOADRDABS, + HEX_INS_PS_LOADRHABS, + HEX_INS_PS_LOADRIABS, + HEX_INS_PS_LOADRUBABS, + HEX_INS_PS_LOADRUHABS, + HEX_INS_PS_STORERBABS, + HEX_INS_PS_STORERBNEWABS, + HEX_INS_PS_STORERDABS, + HEX_INS_PS_STORERFABS, + HEX_INS_PS_STORERHABS, + HEX_INS_PS_STORERHNEWABS, + HEX_INS_PS_STORERIABS, + HEX_INS_PS_STORERINEWABS, + HEX_INS_PS_TRAP1, + HEX_INS_R6_RELEASE_AT_VI, + HEX_INS_R6_RELEASE_ST_VI, + HEX_INS_S2_ADDASL_RRRI, + HEX_INS_S2_ALLOCFRAME, + HEX_INS_S2_ASL_I_P, + HEX_INS_S2_ASL_I_P_ACC, + HEX_INS_S2_ASL_I_P_AND, + HEX_INS_S2_ASL_I_P_NAC, + HEX_INS_S2_ASL_I_P_OR, + HEX_INS_S2_ASL_I_P_XACC, + HEX_INS_S2_ASL_I_R, + HEX_INS_S2_ASL_I_R_ACC, + HEX_INS_S2_ASL_I_R_AND, + HEX_INS_S2_ASL_I_R_NAC, + HEX_INS_S2_ASL_I_R_OR, + HEX_INS_S2_ASL_I_R_SAT, + HEX_INS_S2_ASL_I_R_XACC, + HEX_INS_S2_ASL_I_VH, + HEX_INS_S2_ASL_I_VW, + HEX_INS_S2_ASL_R_P, + HEX_INS_S2_ASL_R_P_ACC, + HEX_INS_S2_ASL_R_P_AND, + HEX_INS_S2_ASL_R_P_NAC, + HEX_INS_S2_ASL_R_P_OR, + HEX_INS_S2_ASL_R_P_XOR, + HEX_INS_S2_ASL_R_R, + HEX_INS_S2_ASL_R_R_ACC, + HEX_INS_S2_ASL_R_R_AND, + HEX_INS_S2_ASL_R_R_NAC, + HEX_INS_S2_ASL_R_R_OR, + HEX_INS_S2_ASL_R_R_SAT, + HEX_INS_S2_ASL_R_VH, + HEX_INS_S2_ASL_R_VW, + HEX_INS_S2_ASR_I_P, + HEX_INS_S2_ASR_I_P_ACC, + HEX_INS_S2_ASR_I_P_AND, + HEX_INS_S2_ASR_I_P_NAC, + HEX_INS_S2_ASR_I_P_OR, + HEX_INS_S2_ASR_I_P_RND, + HEX_INS_S2_ASR_I_R, + HEX_INS_S2_ASR_I_R_ACC, + HEX_INS_S2_ASR_I_R_AND, + HEX_INS_S2_ASR_I_R_NAC, + HEX_INS_S2_ASR_I_R_OR, + HEX_INS_S2_ASR_I_R_RND, + HEX_INS_S2_ASR_I_SVW_TRUN, + HEX_INS_S2_ASR_I_VH, + HEX_INS_S2_ASR_I_VW, + HEX_INS_S2_ASR_R_P, + HEX_INS_S2_ASR_R_P_ACC, + HEX_INS_S2_ASR_R_P_AND, + HEX_INS_S2_ASR_R_P_NAC, + HEX_INS_S2_ASR_R_P_OR, + HEX_INS_S2_ASR_R_P_XOR, + HEX_INS_S2_ASR_R_R, + HEX_INS_S2_ASR_R_R_ACC, + HEX_INS_S2_ASR_R_R_AND, + HEX_INS_S2_ASR_R_R_NAC, + HEX_INS_S2_ASR_R_R_OR, + HEX_INS_S2_ASR_R_R_SAT, + HEX_INS_S2_ASR_R_SVW_TRUN, + HEX_INS_S2_ASR_R_VH, + HEX_INS_S2_ASR_R_VW, + HEX_INS_S2_BREV, + HEX_INS_S2_BREVP, + HEX_INS_S2_CABACDECBIN, + HEX_INS_S2_CL0, + HEX_INS_S2_CL0P, + HEX_INS_S2_CL1, + HEX_INS_S2_CL1P, + HEX_INS_S2_CLB, + HEX_INS_S2_CLBNORM, + HEX_INS_S2_CLBP, + HEX_INS_S2_CLRBIT_I, + HEX_INS_S2_CLRBIT_R, + HEX_INS_S2_CT0, + HEX_INS_S2_CT0P, + HEX_INS_S2_CT1, + HEX_INS_S2_CT1P, + HEX_INS_S2_DEINTERLEAVE, + HEX_INS_S2_EXTRACTU, + HEX_INS_S2_EXTRACTU_RP, + HEX_INS_S2_EXTRACTUP, + HEX_INS_S2_EXTRACTUP_RP, + HEX_INS_S2_INSERT, + HEX_INS_S2_INSERT_RP, + HEX_INS_S2_INSERTP, + HEX_INS_S2_INSERTP_RP, + HEX_INS_S2_INTERLEAVE, + HEX_INS_S2_LFSP, + HEX_INS_S2_LSL_R_P, + HEX_INS_S2_LSL_R_P_ACC, + HEX_INS_S2_LSL_R_P_AND, + HEX_INS_S2_LSL_R_P_NAC, + HEX_INS_S2_LSL_R_P_OR, + HEX_INS_S2_LSL_R_P_XOR, + HEX_INS_S2_LSL_R_R, + HEX_INS_S2_LSL_R_R_ACC, + HEX_INS_S2_LSL_R_R_AND, + HEX_INS_S2_LSL_R_R_NAC, + HEX_INS_S2_LSL_R_R_OR, + HEX_INS_S2_LSL_R_VH, + HEX_INS_S2_LSL_R_VW, + HEX_INS_S2_LSR_I_P, + HEX_INS_S2_LSR_I_P_ACC, + HEX_INS_S2_LSR_I_P_AND, + HEX_INS_S2_LSR_I_P_NAC, + HEX_INS_S2_LSR_I_P_OR, + HEX_INS_S2_LSR_I_P_XACC, + HEX_INS_S2_LSR_I_R, + HEX_INS_S2_LSR_I_R_ACC, + HEX_INS_S2_LSR_I_R_AND, + HEX_INS_S2_LSR_I_R_NAC, + HEX_INS_S2_LSR_I_R_OR, + HEX_INS_S2_LSR_I_R_XACC, + HEX_INS_S2_LSR_I_VH, + HEX_INS_S2_LSR_I_VW, + HEX_INS_S2_LSR_R_P, + HEX_INS_S2_LSR_R_P_ACC, + HEX_INS_S2_LSR_R_P_AND, + HEX_INS_S2_LSR_R_P_NAC, + HEX_INS_S2_LSR_R_P_OR, + HEX_INS_S2_LSR_R_P_XOR, + HEX_INS_S2_LSR_R_R, + HEX_INS_S2_LSR_R_R_ACC, + HEX_INS_S2_LSR_R_R_AND, + HEX_INS_S2_LSR_R_R_NAC, + HEX_INS_S2_LSR_R_R_OR, + HEX_INS_S2_LSR_R_VH, + HEX_INS_S2_LSR_R_VW, + HEX_INS_S2_MASK, + HEX_INS_S2_PACKHL, + HEX_INS_S2_PARITYP, + HEX_INS_S2_PSTORERBF_IO, + HEX_INS_S2_PSTORERBF_PI, + HEX_INS_S2_PSTORERBFNEW_PI, + HEX_INS_S2_PSTORERBNEWF_IO, + HEX_INS_S2_PSTORERBNEWF_PI, + HEX_INS_S2_PSTORERBNEWFNEW_PI, + HEX_INS_S2_PSTORERBNEWT_IO, + HEX_INS_S2_PSTORERBNEWT_PI, + HEX_INS_S2_PSTORERBNEWTNEW_PI, + HEX_INS_S2_PSTORERBT_IO, + HEX_INS_S2_PSTORERBT_PI, + HEX_INS_S2_PSTORERBTNEW_PI, + HEX_INS_S2_PSTORERDF_IO, + HEX_INS_S2_PSTORERDF_PI, + HEX_INS_S2_PSTORERDFNEW_PI, + HEX_INS_S2_PSTORERDT_IO, + HEX_INS_S2_PSTORERDT_PI, + HEX_INS_S2_PSTORERDTNEW_PI, + HEX_INS_S2_PSTORERFF_IO, + HEX_INS_S2_PSTORERFF_PI, + HEX_INS_S2_PSTORERFFNEW_PI, + HEX_INS_S2_PSTORERFT_IO, + HEX_INS_S2_PSTORERFT_PI, + HEX_INS_S2_PSTORERFTNEW_PI, + HEX_INS_S2_PSTORERHF_IO, + HEX_INS_S2_PSTORERHF_PI, + HEX_INS_S2_PSTORERHFNEW_PI, + HEX_INS_S2_PSTORERHNEWF_IO, + HEX_INS_S2_PSTORERHNEWF_PI, + HEX_INS_S2_PSTORERHNEWFNEW_PI, + HEX_INS_S2_PSTORERHNEWT_IO, + HEX_INS_S2_PSTORERHNEWT_PI, + HEX_INS_S2_PSTORERHNEWTNEW_PI, + HEX_INS_S2_PSTORERHT_IO, + HEX_INS_S2_PSTORERHT_PI, + HEX_INS_S2_PSTORERHTNEW_PI, + HEX_INS_S2_PSTORERIF_IO, + HEX_INS_S2_PSTORERIF_PI, + HEX_INS_S2_PSTORERIFNEW_PI, + HEX_INS_S2_PSTORERINEWF_IO, + HEX_INS_S2_PSTORERINEWF_PI, + HEX_INS_S2_PSTORERINEWFNEW_PI, + HEX_INS_S2_PSTORERINEWT_IO, + HEX_INS_S2_PSTORERINEWT_PI, + HEX_INS_S2_PSTORERINEWTNEW_PI, + HEX_INS_S2_PSTORERIT_IO, + HEX_INS_S2_PSTORERIT_PI, + HEX_INS_S2_PSTORERITNEW_PI, + HEX_INS_S2_SETBIT_I, + HEX_INS_S2_SETBIT_R, + HEX_INS_S2_SHUFFEB, + HEX_INS_S2_SHUFFEH, + HEX_INS_S2_SHUFFOB, + HEX_INS_S2_SHUFFOH, + HEX_INS_S2_STORERB_IO, + HEX_INS_S2_STORERB_PBR, + HEX_INS_S2_STORERB_PCI, + HEX_INS_S2_STORERB_PCR, + HEX_INS_S2_STORERB_PI, + HEX_INS_S2_STORERB_PR, + HEX_INS_S2_STORERBGP, + HEX_INS_S2_STORERBNEW_IO, + HEX_INS_S2_STORERBNEW_PBR, + HEX_INS_S2_STORERBNEW_PCI, + HEX_INS_S2_STORERBNEW_PCR, + HEX_INS_S2_STORERBNEW_PI, + HEX_INS_S2_STORERBNEW_PR, + HEX_INS_S2_STORERBNEWGP, + HEX_INS_S2_STORERD_IO, + HEX_INS_S2_STORERD_PBR, + HEX_INS_S2_STORERD_PCI, + HEX_INS_S2_STORERD_PCR, + HEX_INS_S2_STORERD_PI, + HEX_INS_S2_STORERD_PR, + HEX_INS_S2_STORERDGP, + HEX_INS_S2_STORERF_IO, + HEX_INS_S2_STORERF_PBR, + HEX_INS_S2_STORERF_PCI, + HEX_INS_S2_STORERF_PCR, + HEX_INS_S2_STORERF_PI, + HEX_INS_S2_STORERF_PR, + HEX_INS_S2_STORERFGP, + HEX_INS_S2_STORERH_IO, + HEX_INS_S2_STORERH_PBR, + HEX_INS_S2_STORERH_PCI, + HEX_INS_S2_STORERH_PCR, + HEX_INS_S2_STORERH_PI, + HEX_INS_S2_STORERH_PR, + HEX_INS_S2_STORERHGP, + HEX_INS_S2_STORERHNEW_IO, + HEX_INS_S2_STORERHNEW_PBR, + HEX_INS_S2_STORERHNEW_PCI, + HEX_INS_S2_STORERHNEW_PCR, + HEX_INS_S2_STORERHNEW_PI, + HEX_INS_S2_STORERHNEW_PR, + HEX_INS_S2_STORERHNEWGP, + HEX_INS_S2_STORERI_IO, + HEX_INS_S2_STORERI_PBR, + HEX_INS_S2_STORERI_PCI, + HEX_INS_S2_STORERI_PCR, + HEX_INS_S2_STORERI_PI, + HEX_INS_S2_STORERI_PR, + HEX_INS_S2_STORERIGP, + HEX_INS_S2_STORERINEW_IO, + HEX_INS_S2_STORERINEW_PBR, + HEX_INS_S2_STORERINEW_PCI, + HEX_INS_S2_STORERINEW_PCR, + HEX_INS_S2_STORERINEW_PI, + HEX_INS_S2_STORERINEW_PR, + HEX_INS_S2_STORERINEWGP, + HEX_INS_S2_STOREW_LOCKED, + HEX_INS_S2_STOREW_RL_AT_VI, + HEX_INS_S2_STOREW_RL_ST_VI, + HEX_INS_S2_SVSATHB, + HEX_INS_S2_SVSATHUB, + HEX_INS_S2_TABLEIDXB, + HEX_INS_S2_TABLEIDXD, + HEX_INS_S2_TABLEIDXH, + HEX_INS_S2_TABLEIDXW, + HEX_INS_S2_TOGGLEBIT_I, + HEX_INS_S2_TOGGLEBIT_R, + HEX_INS_S2_TSTBIT_I, + HEX_INS_S2_TSTBIT_R, + HEX_INS_S2_VALIGNIB, + HEX_INS_S2_VALIGNRB, + HEX_INS_S2_VCNEGH, + HEX_INS_S2_VCROTATE, + HEX_INS_S2_VRCNEGH, + HEX_INS_S2_VRNDPACKWH, + HEX_INS_S2_VRNDPACKWHS, + HEX_INS_S2_VSATHB, + HEX_INS_S2_VSATHB_NOPACK, + HEX_INS_S2_VSATHUB, + HEX_INS_S2_VSATHUB_NOPACK, + HEX_INS_S2_VSATWH, + HEX_INS_S2_VSATWH_NOPACK, + HEX_INS_S2_VSATWUH, + HEX_INS_S2_VSATWUH_NOPACK, + HEX_INS_S2_VSPLATRB, + HEX_INS_S2_VSPLATRH, + HEX_INS_S2_VSPLICEIB, + HEX_INS_S2_VSPLICERB, + HEX_INS_S2_VSXTBH, + HEX_INS_S2_VSXTHW, + HEX_INS_S2_VTRUNEHB, + HEX_INS_S2_VTRUNEWH, + HEX_INS_S2_VTRUNOHB, + HEX_INS_S2_VTRUNOWH, + HEX_INS_S2_VZXTBH, + HEX_INS_S2_VZXTHW, + HEX_INS_S4_ADDADDI, + HEX_INS_S4_ADDI_ASL_RI, + HEX_INS_S4_ADDI_LSR_RI, + HEX_INS_S4_ANDI_ASL_RI, + HEX_INS_S4_ANDI_LSR_RI, + HEX_INS_S4_CLBADDI, + HEX_INS_S4_CLBPADDI, + HEX_INS_S4_CLBPNORM, + HEX_INS_S4_EXTRACT, + HEX_INS_S4_EXTRACT_RP, + HEX_INS_S4_EXTRACTP, + HEX_INS_S4_EXTRACTP_RP, + HEX_INS_S4_LSLI, + HEX_INS_S4_NTSTBIT_I, + HEX_INS_S4_NTSTBIT_R, + HEX_INS_S4_OR_ANDI, + HEX_INS_S4_OR_ANDIX, + HEX_INS_S4_OR_ORI, + HEX_INS_S4_ORI_ASL_RI, + HEX_INS_S4_ORI_LSR_RI, + HEX_INS_S4_PARITY, + HEX_INS_S4_PSTORERBF_ABS, + HEX_INS_S4_PSTORERBF_RR, + HEX_INS_S4_PSTORERBFNEW_ABS, + HEX_INS_S4_PSTORERBFNEW_IO, + HEX_INS_S4_PSTORERBFNEW_RR, + HEX_INS_S4_PSTORERBNEWF_ABS, + HEX_INS_S4_PSTORERBNEWF_RR, + HEX_INS_S4_PSTORERBNEWFNEW_ABS, + HEX_INS_S4_PSTORERBNEWFNEW_IO, + HEX_INS_S4_PSTORERBNEWFNEW_RR, + HEX_INS_S4_PSTORERBNEWT_ABS, + HEX_INS_S4_PSTORERBNEWT_RR, + HEX_INS_S4_PSTORERBNEWTNEW_ABS, + HEX_INS_S4_PSTORERBNEWTNEW_IO, + HEX_INS_S4_PSTORERBNEWTNEW_RR, + HEX_INS_S4_PSTORERBT_ABS, + HEX_INS_S4_PSTORERBT_RR, + HEX_INS_S4_PSTORERBTNEW_ABS, + HEX_INS_S4_PSTORERBTNEW_IO, + HEX_INS_S4_PSTORERBTNEW_RR, + HEX_INS_S4_PSTORERDF_ABS, + HEX_INS_S4_PSTORERDF_RR, + HEX_INS_S4_PSTORERDFNEW_ABS, + HEX_INS_S4_PSTORERDFNEW_IO, + HEX_INS_S4_PSTORERDFNEW_RR, + HEX_INS_S4_PSTORERDT_ABS, + HEX_INS_S4_PSTORERDT_RR, + HEX_INS_S4_PSTORERDTNEW_ABS, + HEX_INS_S4_PSTORERDTNEW_IO, + HEX_INS_S4_PSTORERDTNEW_RR, + HEX_INS_S4_PSTORERFF_ABS, + HEX_INS_S4_PSTORERFF_RR, + HEX_INS_S4_PSTORERFFNEW_ABS, + HEX_INS_S4_PSTORERFFNEW_IO, + HEX_INS_S4_PSTORERFFNEW_RR, + HEX_INS_S4_PSTORERFT_ABS, + HEX_INS_S4_PSTORERFT_RR, + HEX_INS_S4_PSTORERFTNEW_ABS, + HEX_INS_S4_PSTORERFTNEW_IO, + HEX_INS_S4_PSTORERFTNEW_RR, + HEX_INS_S4_PSTORERHF_ABS, + HEX_INS_S4_PSTORERHF_RR, + HEX_INS_S4_PSTORERHFNEW_ABS, + HEX_INS_S4_PSTORERHFNEW_IO, + HEX_INS_S4_PSTORERHFNEW_RR, + HEX_INS_S4_PSTORERHNEWF_ABS, + HEX_INS_S4_PSTORERHNEWF_RR, + HEX_INS_S4_PSTORERHNEWFNEW_ABS, + HEX_INS_S4_PSTORERHNEWFNEW_IO, + HEX_INS_S4_PSTORERHNEWFNEW_RR, + HEX_INS_S4_PSTORERHNEWT_ABS, + HEX_INS_S4_PSTORERHNEWT_RR, + HEX_INS_S4_PSTORERHNEWTNEW_ABS, + HEX_INS_S4_PSTORERHNEWTNEW_IO, + HEX_INS_S4_PSTORERHNEWTNEW_RR, + HEX_INS_S4_PSTORERHT_ABS, + HEX_INS_S4_PSTORERHT_RR, + HEX_INS_S4_PSTORERHTNEW_ABS, + HEX_INS_S4_PSTORERHTNEW_IO, + HEX_INS_S4_PSTORERHTNEW_RR, + HEX_INS_S4_PSTORERIF_ABS, + HEX_INS_S4_PSTORERIF_RR, + HEX_INS_S4_PSTORERIFNEW_ABS, + HEX_INS_S4_PSTORERIFNEW_IO, + HEX_INS_S4_PSTORERIFNEW_RR, + HEX_INS_S4_PSTORERINEWF_ABS, + HEX_INS_S4_PSTORERINEWF_RR, + HEX_INS_S4_PSTORERINEWFNEW_ABS, + HEX_INS_S4_PSTORERINEWFNEW_IO, + HEX_INS_S4_PSTORERINEWFNEW_RR, + HEX_INS_S4_PSTORERINEWT_ABS, + HEX_INS_S4_PSTORERINEWT_RR, + HEX_INS_S4_PSTORERINEWTNEW_ABS, + HEX_INS_S4_PSTORERINEWTNEW_IO, + HEX_INS_S4_PSTORERINEWTNEW_RR, + HEX_INS_S4_PSTORERIT_ABS, + HEX_INS_S4_PSTORERIT_RR, + HEX_INS_S4_PSTORERITNEW_ABS, + HEX_INS_S4_PSTORERITNEW_IO, + HEX_INS_S4_PSTORERITNEW_RR, + HEX_INS_S4_STORED_LOCKED, + HEX_INS_S4_STORED_RL_AT_VI, + HEX_INS_S4_STORED_RL_ST_VI, + HEX_INS_S4_STOREIRB_IO, + HEX_INS_S4_STOREIRBF_IO, + HEX_INS_S4_STOREIRBFNEW_IO, + HEX_INS_S4_STOREIRBT_IO, + HEX_INS_S4_STOREIRBTNEW_IO, + HEX_INS_S4_STOREIRH_IO, + HEX_INS_S4_STOREIRHF_IO, + HEX_INS_S4_STOREIRHFNEW_IO, + HEX_INS_S4_STOREIRHT_IO, + HEX_INS_S4_STOREIRHTNEW_IO, + HEX_INS_S4_STOREIRI_IO, + HEX_INS_S4_STOREIRIF_IO, + HEX_INS_S4_STOREIRIFNEW_IO, + HEX_INS_S4_STOREIRIT_IO, + HEX_INS_S4_STOREIRITNEW_IO, + HEX_INS_S4_STORERB_AP, + HEX_INS_S4_STORERB_RR, + HEX_INS_S4_STORERB_UR, + HEX_INS_S4_STORERBNEW_AP, + HEX_INS_S4_STORERBNEW_RR, + HEX_INS_S4_STORERBNEW_UR, + HEX_INS_S4_STORERD_AP, + HEX_INS_S4_STORERD_RR, + HEX_INS_S4_STORERD_UR, + HEX_INS_S4_STORERF_AP, + HEX_INS_S4_STORERF_RR, + HEX_INS_S4_STORERF_UR, + HEX_INS_S4_STORERH_AP, + HEX_INS_S4_STORERH_RR, + HEX_INS_S4_STORERH_UR, + HEX_INS_S4_STORERHNEW_AP, + HEX_INS_S4_STORERHNEW_RR, + HEX_INS_S4_STORERHNEW_UR, + HEX_INS_S4_STORERI_AP, + HEX_INS_S4_STORERI_RR, + HEX_INS_S4_STORERI_UR, + HEX_INS_S4_STORERINEW_AP, + HEX_INS_S4_STORERINEW_RR, + HEX_INS_S4_STORERINEW_UR, + HEX_INS_S4_SUBADDI, + HEX_INS_S4_SUBI_ASL_RI, + HEX_INS_S4_SUBI_LSR_RI, + HEX_INS_S4_VRCROTATE, + HEX_INS_S4_VRCROTATE_ACC, + HEX_INS_S4_VXADDSUBH, + HEX_INS_S4_VXADDSUBHR, + HEX_INS_S4_VXADDSUBW, + HEX_INS_S4_VXSUBADDH, + HEX_INS_S4_VXSUBADDHR, + HEX_INS_S4_VXSUBADDW, + HEX_INS_S5_ASRHUB_RND_SAT, + HEX_INS_S5_ASRHUB_SAT, + HEX_INS_S5_POPCOUNTP, + HEX_INS_S5_VASRHRND, + HEX_INS_S6_ROL_I_P, + HEX_INS_S6_ROL_I_P_ACC, + HEX_INS_S6_ROL_I_P_AND, + HEX_INS_S6_ROL_I_P_NAC, + HEX_INS_S6_ROL_I_P_OR, + HEX_INS_S6_ROL_I_P_XACC, + HEX_INS_S6_ROL_I_R, + HEX_INS_S6_ROL_I_R_ACC, + HEX_INS_S6_ROL_I_R_AND, + HEX_INS_S6_ROL_I_R_NAC, + HEX_INS_S6_ROL_I_R_OR, + HEX_INS_S6_ROL_I_R_XACC, + HEX_INS_S6_VSPLATRBP, + HEX_INS_S6_VTRUNEHB_PPP, + HEX_INS_S6_VTRUNOHB_PPP, + HEX_INS_V6_EXTRACTW, + HEX_INS_V6_LVSPLATB, + HEX_INS_V6_LVSPLATH, + HEX_INS_V6_LVSPLATW, + HEX_INS_V6_PRED_AND, + HEX_INS_V6_PRED_AND_N, + HEX_INS_V6_PRED_NOT, + HEX_INS_V6_PRED_OR, + HEX_INS_V6_PRED_OR_N, + HEX_INS_V6_PRED_SCALAR2, + HEX_INS_V6_PRED_SCALAR2V2, + HEX_INS_V6_PRED_XOR, + HEX_INS_V6_SHUFFEQH, + HEX_INS_V6_SHUFFEQW, + HEX_INS_V6_V6MPYHUBS10, + HEX_INS_V6_V6MPYHUBS10_VXX, + HEX_INS_V6_V6MPYVUBS10, + HEX_INS_V6_V6MPYVUBS10_VXX, + HEX_INS_V6_VL32UB_AI, + HEX_INS_V6_VL32UB_PI, + HEX_INS_V6_VL32UB_PPU, + HEX_INS_V6_VL32B_AI, + HEX_INS_V6_VL32B_CUR_AI, + HEX_INS_V6_VL32B_CUR_NPRED_AI, + HEX_INS_V6_VL32B_CUR_NPRED_PI, + HEX_INS_V6_VL32B_CUR_NPRED_PPU, + HEX_INS_V6_VL32B_CUR_PI, + HEX_INS_V6_VL32B_CUR_PPU, + HEX_INS_V6_VL32B_CUR_PRED_AI, + HEX_INS_V6_VL32B_CUR_PRED_PI, + HEX_INS_V6_VL32B_CUR_PRED_PPU, + HEX_INS_V6_VL32B_NPRED_AI, + HEX_INS_V6_VL32B_NPRED_PI, + HEX_INS_V6_VL32B_NPRED_PPU, + HEX_INS_V6_VL32B_NT_AI, + HEX_INS_V6_VL32B_NT_CUR_AI, + HEX_INS_V6_VL32B_NT_CUR_NPRED_AI, + HEX_INS_V6_VL32B_NT_CUR_NPRED_PI, + HEX_INS_V6_VL32B_NT_CUR_NPRED_PPU, + HEX_INS_V6_VL32B_NT_CUR_PI, + HEX_INS_V6_VL32B_NT_CUR_PPU, + HEX_INS_V6_VL32B_NT_CUR_PRED_AI, + HEX_INS_V6_VL32B_NT_CUR_PRED_PI, + HEX_INS_V6_VL32B_NT_CUR_PRED_PPU, + HEX_INS_V6_VL32B_NT_NPRED_AI, + HEX_INS_V6_VL32B_NT_NPRED_PI, + HEX_INS_V6_VL32B_NT_NPRED_PPU, + HEX_INS_V6_VL32B_NT_PI, + HEX_INS_V6_VL32B_NT_PPU, + HEX_INS_V6_VL32B_NT_PRED_AI, + HEX_INS_V6_VL32B_NT_PRED_PI, + HEX_INS_V6_VL32B_NT_PRED_PPU, + HEX_INS_V6_VL32B_NT_TMP_AI, + HEX_INS_V6_VL32B_NT_TMP_NPRED_AI, + HEX_INS_V6_VL32B_NT_TMP_NPRED_PI, + HEX_INS_V6_VL32B_NT_TMP_NPRED_PPU, + HEX_INS_V6_VL32B_NT_TMP_PI, + HEX_INS_V6_VL32B_NT_TMP_PPU, + HEX_INS_V6_VL32B_NT_TMP_PRED_AI, + HEX_INS_V6_VL32B_NT_TMP_PRED_PI, + HEX_INS_V6_VL32B_NT_TMP_PRED_PPU, + HEX_INS_V6_VL32B_PI, + HEX_INS_V6_VL32B_PPU, + HEX_INS_V6_VL32B_PRED_AI, + HEX_INS_V6_VL32B_PRED_PI, + HEX_INS_V6_VL32B_PRED_PPU, + HEX_INS_V6_VL32B_TMP_AI, + HEX_INS_V6_VL32B_TMP_NPRED_AI, + HEX_INS_V6_VL32B_TMP_NPRED_PI, + HEX_INS_V6_VL32B_TMP_NPRED_PPU, + HEX_INS_V6_VL32B_TMP_PI, + HEX_INS_V6_VL32B_TMP_PPU, + HEX_INS_V6_VL32B_TMP_PRED_AI, + HEX_INS_V6_VL32B_TMP_PRED_PI, + HEX_INS_V6_VL32B_TMP_PRED_PPU, + HEX_INS_V6_VS32UB_AI, + HEX_INS_V6_VS32UB_NPRED_AI, + HEX_INS_V6_VS32UB_NPRED_PI, + HEX_INS_V6_VS32UB_NPRED_PPU, + HEX_INS_V6_VS32UB_PI, + HEX_INS_V6_VS32UB_PPU, + HEX_INS_V6_VS32UB_PRED_AI, + HEX_INS_V6_VS32UB_PRED_PI, + HEX_INS_V6_VS32UB_PRED_PPU, + HEX_INS_V6_VS32B_AI, + HEX_INS_V6_VS32B_NEW_AI, + HEX_INS_V6_VS32B_NEW_NPRED_AI, + HEX_INS_V6_VS32B_NEW_NPRED_PI, + HEX_INS_V6_VS32B_NEW_NPRED_PPU, + HEX_INS_V6_VS32B_NEW_PI, + HEX_INS_V6_VS32B_NEW_PPU, + HEX_INS_V6_VS32B_NEW_PRED_AI, + HEX_INS_V6_VS32B_NEW_PRED_PI, + HEX_INS_V6_VS32B_NEW_PRED_PPU, + HEX_INS_V6_VS32B_NPRED_AI, + HEX_INS_V6_VS32B_NPRED_PI, + HEX_INS_V6_VS32B_NPRED_PPU, + HEX_INS_V6_VS32B_NQPRED_AI, + HEX_INS_V6_VS32B_NQPRED_PI, + HEX_INS_V6_VS32B_NQPRED_PPU, + HEX_INS_V6_VS32B_NT_AI, + HEX_INS_V6_VS32B_NT_NEW_AI, + HEX_INS_V6_VS32B_NT_NEW_NPRED_AI, + HEX_INS_V6_VS32B_NT_NEW_NPRED_PI, + HEX_INS_V6_VS32B_NT_NEW_NPRED_PPU, + HEX_INS_V6_VS32B_NT_NEW_PI, + HEX_INS_V6_VS32B_NT_NEW_PPU, + HEX_INS_V6_VS32B_NT_NEW_PRED_AI, + HEX_INS_V6_VS32B_NT_NEW_PRED_PI, + HEX_INS_V6_VS32B_NT_NEW_PRED_PPU, + HEX_INS_V6_VS32B_NT_NPRED_AI, + HEX_INS_V6_VS32B_NT_NPRED_PI, + HEX_INS_V6_VS32B_NT_NPRED_PPU, + HEX_INS_V6_VS32B_NT_NQPRED_AI, + HEX_INS_V6_VS32B_NT_NQPRED_PI, + HEX_INS_V6_VS32B_NT_NQPRED_PPU, + HEX_INS_V6_VS32B_NT_PI, + HEX_INS_V6_VS32B_NT_PPU, + HEX_INS_V6_VS32B_NT_PRED_AI, + HEX_INS_V6_VS32B_NT_PRED_PI, + HEX_INS_V6_VS32B_NT_PRED_PPU, + HEX_INS_V6_VS32B_NT_QPRED_AI, + HEX_INS_V6_VS32B_NT_QPRED_PI, + HEX_INS_V6_VS32B_NT_QPRED_PPU, + HEX_INS_V6_VS32B_PI, + HEX_INS_V6_VS32B_PPU, + HEX_INS_V6_VS32B_PRED_AI, + HEX_INS_V6_VS32B_PRED_PI, + HEX_INS_V6_VS32B_PRED_PPU, + HEX_INS_V6_VS32B_QPRED_AI, + HEX_INS_V6_VS32B_QPRED_PI, + HEX_INS_V6_VS32B_QPRED_PPU, + HEX_INS_V6_VS32B_SRLS_AI, + HEX_INS_V6_VS32B_SRLS_PI, + HEX_INS_V6_VS32B_SRLS_PPU, + HEX_INS_V6_VABSB, + HEX_INS_V6_VABSB_SAT, + HEX_INS_V6_VABSDIFFH, + HEX_INS_V6_VABSDIFFUB, + HEX_INS_V6_VABSDIFFUH, + HEX_INS_V6_VABSDIFFW, + HEX_INS_V6_VABSH, + HEX_INS_V6_VABSH_SAT, + HEX_INS_V6_VABSW, + HEX_INS_V6_VABSW_SAT, + HEX_INS_V6_VADDB, + HEX_INS_V6_VADDB_DV, + HEX_INS_V6_VADDBNQ, + HEX_INS_V6_VADDBQ, + HEX_INS_V6_VADDBSAT, + HEX_INS_V6_VADDBSAT_DV, + HEX_INS_V6_VADDCARRY, + HEX_INS_V6_VADDCARRYO, + HEX_INS_V6_VADDCARRYSAT, + HEX_INS_V6_VADDCLBH, + HEX_INS_V6_VADDCLBW, + HEX_INS_V6_VADDH, + HEX_INS_V6_VADDH_DV, + HEX_INS_V6_VADDHNQ, + HEX_INS_V6_VADDHQ, + HEX_INS_V6_VADDHSAT, + HEX_INS_V6_VADDHSAT_DV, + HEX_INS_V6_VADDHW, + HEX_INS_V6_VADDHW_ACC, + HEX_INS_V6_VADDUBH, + HEX_INS_V6_VADDUBH_ACC, + HEX_INS_V6_VADDUBSAT, + HEX_INS_V6_VADDUBSAT_DV, + HEX_INS_V6_VADDUBUBB_SAT, + HEX_INS_V6_VADDUHSAT, + HEX_INS_V6_VADDUHSAT_DV, + HEX_INS_V6_VADDUHW, + HEX_INS_V6_VADDUHW_ACC, + HEX_INS_V6_VADDUWSAT, + HEX_INS_V6_VADDUWSAT_DV, + HEX_INS_V6_VADDW, + HEX_INS_V6_VADDW_DV, + HEX_INS_V6_VADDWNQ, + HEX_INS_V6_VADDWQ, + HEX_INS_V6_VADDWSAT, + HEX_INS_V6_VADDWSAT_DV, + HEX_INS_V6_VALIGNB, + HEX_INS_V6_VALIGNBI, + HEX_INS_V6_VAND, + HEX_INS_V6_VANDNQRT, + HEX_INS_V6_VANDNQRT_ACC, + HEX_INS_V6_VANDQRT, + HEX_INS_V6_VANDQRT_ACC, + HEX_INS_V6_VANDVNQV, + HEX_INS_V6_VANDVQV, + HEX_INS_V6_VANDVRT, + HEX_INS_V6_VANDVRT_ACC, + HEX_INS_V6_VASLH, + HEX_INS_V6_VASLH_ACC, + HEX_INS_V6_VASLHV, + HEX_INS_V6_VASLW, + HEX_INS_V6_VASLW_ACC, + HEX_INS_V6_VASLWV, + HEX_INS_V6_VASR_INTO, + HEX_INS_V6_VASRH, + HEX_INS_V6_VASRH_ACC, + HEX_INS_V6_VASRHBRNDSAT, + HEX_INS_V6_VASRHBSAT, + HEX_INS_V6_VASRHUBRNDSAT, + HEX_INS_V6_VASRHUBSAT, + HEX_INS_V6_VASRHV, + HEX_INS_V6_VASRUHUBRNDSAT, + HEX_INS_V6_VASRUHUBSAT, + HEX_INS_V6_VASRUWUHRNDSAT, + HEX_INS_V6_VASRUWUHSAT, + HEX_INS_V6_VASRW, + HEX_INS_V6_VASRW_ACC, + HEX_INS_V6_VASRWH, + HEX_INS_V6_VASRWHRNDSAT, + HEX_INS_V6_VASRWHSAT, + HEX_INS_V6_VASRWUHRNDSAT, + HEX_INS_V6_VASRWUHSAT, + HEX_INS_V6_VASRWV, + HEX_INS_V6_VASSIGN, + HEX_INS_V6_VAVGB, + HEX_INS_V6_VAVGBRND, + HEX_INS_V6_VAVGH, + HEX_INS_V6_VAVGHRND, + HEX_INS_V6_VAVGUB, + HEX_INS_V6_VAVGUBRND, + HEX_INS_V6_VAVGUH, + HEX_INS_V6_VAVGUHRND, + HEX_INS_V6_VAVGUW, + HEX_INS_V6_VAVGUWRND, + HEX_INS_V6_VAVGW, + HEX_INS_V6_VAVGWRND, + HEX_INS_V6_VCCOMBINE, + HEX_INS_V6_VCL0H, + HEX_INS_V6_VCL0W, + HEX_INS_V6_VCMOV, + HEX_INS_V6_VCOMBINE, + HEX_INS_V6_VDEAL, + HEX_INS_V6_VDEALB, + HEX_INS_V6_VDEALB4W, + HEX_INS_V6_VDEALH, + HEX_INS_V6_VDEALVDD, + HEX_INS_V6_VDELTA, + HEX_INS_V6_VDMPYBUS, + HEX_INS_V6_VDMPYBUS_ACC, + HEX_INS_V6_VDMPYBUS_DV, + HEX_INS_V6_VDMPYBUS_DV_ACC, + HEX_INS_V6_VDMPYHB, + HEX_INS_V6_VDMPYHB_ACC, + HEX_INS_V6_VDMPYHB_DV, + HEX_INS_V6_VDMPYHB_DV_ACC, + HEX_INS_V6_VDMPYHISAT, + HEX_INS_V6_VDMPYHISAT_ACC, + HEX_INS_V6_VDMPYHSAT, + HEX_INS_V6_VDMPYHSAT_ACC, + HEX_INS_V6_VDMPYHSUISAT, + HEX_INS_V6_VDMPYHSUISAT_ACC, + HEX_INS_V6_VDMPYHSUSAT, + HEX_INS_V6_VDMPYHSUSAT_ACC, + HEX_INS_V6_VDMPYHVSAT, + HEX_INS_V6_VDMPYHVSAT_ACC, + HEX_INS_V6_VDSADUH, + HEX_INS_V6_VDSADUH_ACC, + HEX_INS_V6_VEQB, + HEX_INS_V6_VEQB_AND, + HEX_INS_V6_VEQB_OR, + HEX_INS_V6_VEQB_XOR, + HEX_INS_V6_VEQH, + HEX_INS_V6_VEQH_AND, + HEX_INS_V6_VEQH_OR, + HEX_INS_V6_VEQH_XOR, + HEX_INS_V6_VEQW, + HEX_INS_V6_VEQW_AND, + HEX_INS_V6_VEQW_OR, + HEX_INS_V6_VEQW_XOR, + HEX_INS_V6_VGATHERMH, + HEX_INS_V6_VGATHERMHQ, + HEX_INS_V6_VGATHERMHW, + HEX_INS_V6_VGATHERMHWQ, + HEX_INS_V6_VGATHERMW, + HEX_INS_V6_VGATHERMWQ, + HEX_INS_V6_VGTB, + HEX_INS_V6_VGTB_AND, + HEX_INS_V6_VGTB_OR, + HEX_INS_V6_VGTB_XOR, + HEX_INS_V6_VGTH, + HEX_INS_V6_VGTH_AND, + HEX_INS_V6_VGTH_OR, + HEX_INS_V6_VGTH_XOR, + HEX_INS_V6_VGTUB, + HEX_INS_V6_VGTUB_AND, + HEX_INS_V6_VGTUB_OR, + HEX_INS_V6_VGTUB_XOR, + HEX_INS_V6_VGTUH, + HEX_INS_V6_VGTUH_AND, + HEX_INS_V6_VGTUH_OR, + HEX_INS_V6_VGTUH_XOR, + HEX_INS_V6_VGTUW, + HEX_INS_V6_VGTUW_AND, + HEX_INS_V6_VGTUW_OR, + HEX_INS_V6_VGTUW_XOR, + HEX_INS_V6_VGTW, + HEX_INS_V6_VGTW_AND, + HEX_INS_V6_VGTW_OR, + HEX_INS_V6_VGTW_XOR, + HEX_INS_V6_VHIST, + HEX_INS_V6_VHISTQ, + HEX_INS_V6_VINSERTWR, + HEX_INS_V6_VLALIGNB, + HEX_INS_V6_VLALIGNBI, + HEX_INS_V6_VLSRB, + HEX_INS_V6_VLSRH, + HEX_INS_V6_VLSRHV, + HEX_INS_V6_VLSRW, + HEX_INS_V6_VLSRWV, + HEX_INS_V6_VLUT4, + HEX_INS_V6_VLUTVVB, + HEX_INS_V6_VLUTVVB_NM, + HEX_INS_V6_VLUTVVB_ORACC, + HEX_INS_V6_VLUTVVB_ORACCI, + HEX_INS_V6_VLUTVVBI, + HEX_INS_V6_VLUTVWH, + HEX_INS_V6_VLUTVWH_NM, + HEX_INS_V6_VLUTVWH_ORACC, + HEX_INS_V6_VLUTVWH_ORACCI, + HEX_INS_V6_VLUTVWHI, + HEX_INS_V6_VMAXB, + HEX_INS_V6_VMAXH, + HEX_INS_V6_VMAXUB, + HEX_INS_V6_VMAXUH, + HEX_INS_V6_VMAXW, + HEX_INS_V6_VMINB, + HEX_INS_V6_VMINH, + HEX_INS_V6_VMINUB, + HEX_INS_V6_VMINUH, + HEX_INS_V6_VMINW, + HEX_INS_V6_VMPABUS, + HEX_INS_V6_VMPABUS_ACC, + HEX_INS_V6_VMPABUSV, + HEX_INS_V6_VMPABUU, + HEX_INS_V6_VMPABUU_ACC, + HEX_INS_V6_VMPABUUV, + HEX_INS_V6_VMPAHB, + HEX_INS_V6_VMPAHB_ACC, + HEX_INS_V6_VMPAHHSAT, + HEX_INS_V6_VMPAUHB, + HEX_INS_V6_VMPAUHB_ACC, + HEX_INS_V6_VMPAUHUHSAT, + HEX_INS_V6_VMPSUHUHSAT, + HEX_INS_V6_VMPYBUS, + HEX_INS_V6_VMPYBUS_ACC, + HEX_INS_V6_VMPYBUSV, + HEX_INS_V6_VMPYBUSV_ACC, + HEX_INS_V6_VMPYBV, + HEX_INS_V6_VMPYBV_ACC, + HEX_INS_V6_VMPYEWUH, + HEX_INS_V6_VMPYEWUH_64, + HEX_INS_V6_VMPYH, + HEX_INS_V6_VMPYH_ACC, + HEX_INS_V6_VMPYHSAT_ACC, + HEX_INS_V6_VMPYHSRS, + HEX_INS_V6_VMPYHSS, + HEX_INS_V6_VMPYHUS, + HEX_INS_V6_VMPYHUS_ACC, + HEX_INS_V6_VMPYHV, + HEX_INS_V6_VMPYHV_ACC, + HEX_INS_V6_VMPYHVSRS, + HEX_INS_V6_VMPYIEOH, + HEX_INS_V6_VMPYIEWH_ACC, + HEX_INS_V6_VMPYIEWUH, + HEX_INS_V6_VMPYIEWUH_ACC, + HEX_INS_V6_VMPYIH, + HEX_INS_V6_VMPYIH_ACC, + HEX_INS_V6_VMPYIHB, + HEX_INS_V6_VMPYIHB_ACC, + HEX_INS_V6_VMPYIOWH, + HEX_INS_V6_VMPYIWB, + HEX_INS_V6_VMPYIWB_ACC, + HEX_INS_V6_VMPYIWH, + HEX_INS_V6_VMPYIWH_ACC, + HEX_INS_V6_VMPYIWUB, + HEX_INS_V6_VMPYIWUB_ACC, + HEX_INS_V6_VMPYOWH, + HEX_INS_V6_VMPYOWH_64_ACC, + HEX_INS_V6_VMPYOWH_RND, + HEX_INS_V6_VMPYOWH_RND_SACC, + HEX_INS_V6_VMPYOWH_SACC, + HEX_INS_V6_VMPYUB, + HEX_INS_V6_VMPYUB_ACC, + HEX_INS_V6_VMPYUBV, + HEX_INS_V6_VMPYUBV_ACC, + HEX_INS_V6_VMPYUH, + HEX_INS_V6_VMPYUH_ACC, + HEX_INS_V6_VMPYUHE, + HEX_INS_V6_VMPYUHE_ACC, + HEX_INS_V6_VMPYUHV, + HEX_INS_V6_VMPYUHV_ACC, + HEX_INS_V6_VMUX, + HEX_INS_V6_VNAVGB, + HEX_INS_V6_VNAVGH, + HEX_INS_V6_VNAVGUB, + HEX_INS_V6_VNAVGW, + HEX_INS_V6_VNCCOMBINE, + HEX_INS_V6_VNCMOV, + HEX_INS_V6_VNORMAMTH, + HEX_INS_V6_VNORMAMTW, + HEX_INS_V6_VNOT, + HEX_INS_V6_VOR, + HEX_INS_V6_VPACKEB, + HEX_INS_V6_VPACKEH, + HEX_INS_V6_VPACKHB_SAT, + HEX_INS_V6_VPACKHUB_SAT, + HEX_INS_V6_VPACKOB, + HEX_INS_V6_VPACKOH, + HEX_INS_V6_VPACKWH_SAT, + HEX_INS_V6_VPACKWUH_SAT, + HEX_INS_V6_VPOPCOUNTH, + HEX_INS_V6_VPREFIXQB, + HEX_INS_V6_VPREFIXQH, + HEX_INS_V6_VPREFIXQW, + HEX_INS_V6_VRDELTA, + HEX_INS_V6_VRMPYBUB_RTT, + HEX_INS_V6_VRMPYBUB_RTT_ACC, + HEX_INS_V6_VRMPYBUS, + HEX_INS_V6_VRMPYBUS_ACC, + HEX_INS_V6_VRMPYBUSI, + HEX_INS_V6_VRMPYBUSI_ACC, + HEX_INS_V6_VRMPYBUSV, + HEX_INS_V6_VRMPYBUSV_ACC, + HEX_INS_V6_VRMPYBV, + HEX_INS_V6_VRMPYBV_ACC, + HEX_INS_V6_VRMPYUB, + HEX_INS_V6_VRMPYUB_ACC, + HEX_INS_V6_VRMPYUB_RTT, + HEX_INS_V6_VRMPYUB_RTT_ACC, + HEX_INS_V6_VRMPYUBI, + HEX_INS_V6_VRMPYUBI_ACC, + HEX_INS_V6_VRMPYUBV, + HEX_INS_V6_VRMPYUBV_ACC, + HEX_INS_V6_VRMPYZBB_RT, + HEX_INS_V6_VRMPYZBB_RT_ACC, + HEX_INS_V6_VRMPYZBB_RX, + HEX_INS_V6_VRMPYZBB_RX_ACC, + HEX_INS_V6_VRMPYZBUB_RT, + HEX_INS_V6_VRMPYZBUB_RT_ACC, + HEX_INS_V6_VRMPYZBUB_RX, + HEX_INS_V6_VRMPYZBUB_RX_ACC, + HEX_INS_V6_VRMPYZCB_RT, + HEX_INS_V6_VRMPYZCB_RT_ACC, + HEX_INS_V6_VRMPYZCB_RX, + HEX_INS_V6_VRMPYZCB_RX_ACC, + HEX_INS_V6_VRMPYZCBS_RT, + HEX_INS_V6_VRMPYZCBS_RT_ACC, + HEX_INS_V6_VRMPYZCBS_RX, + HEX_INS_V6_VRMPYZCBS_RX_ACC, + HEX_INS_V6_VRMPYZNB_RT, + HEX_INS_V6_VRMPYZNB_RT_ACC, + HEX_INS_V6_VRMPYZNB_RX, + HEX_INS_V6_VRMPYZNB_RX_ACC, + HEX_INS_V6_VROR, + HEX_INS_V6_VROTR, + HEX_INS_V6_VROUNDHB, + HEX_INS_V6_VROUNDHUB, + HEX_INS_V6_VROUNDUHUB, + HEX_INS_V6_VROUNDUWUH, + HEX_INS_V6_VROUNDWH, + HEX_INS_V6_VROUNDWUH, + HEX_INS_V6_VRSADUBI, + HEX_INS_V6_VRSADUBI_ACC, + HEX_INS_V6_VSATDW, + HEX_INS_V6_VSATHUB, + HEX_INS_V6_VSATUWUH, + HEX_INS_V6_VSATWH, + HEX_INS_V6_VSB, + HEX_INS_V6_VSCATTERMH, + HEX_INS_V6_VSCATTERMH_ADD, + HEX_INS_V6_VSCATTERMHQ, + HEX_INS_V6_VSCATTERMHW, + HEX_INS_V6_VSCATTERMHW_ADD, + HEX_INS_V6_VSCATTERMHWQ, + HEX_INS_V6_VSCATTERMW, + HEX_INS_V6_VSCATTERMW_ADD, + HEX_INS_V6_VSCATTERMWQ, + HEX_INS_V6_VSH, + HEX_INS_V6_VSHUFEH, + HEX_INS_V6_VSHUFF, + HEX_INS_V6_VSHUFFB, + HEX_INS_V6_VSHUFFEB, + HEX_INS_V6_VSHUFFH, + HEX_INS_V6_VSHUFFOB, + HEX_INS_V6_VSHUFFVDD, + HEX_INS_V6_VSHUFOEB, + HEX_INS_V6_VSHUFOEH, + HEX_INS_V6_VSHUFOH, + HEX_INS_V6_VSUBB, + HEX_INS_V6_VSUBB_DV, + HEX_INS_V6_VSUBBNQ, + HEX_INS_V6_VSUBBQ, + HEX_INS_V6_VSUBBSAT, + HEX_INS_V6_VSUBBSAT_DV, + HEX_INS_V6_VSUBCARRY, + HEX_INS_V6_VSUBCARRYO, + HEX_INS_V6_VSUBH, + HEX_INS_V6_VSUBH_DV, + HEX_INS_V6_VSUBHNQ, + HEX_INS_V6_VSUBHQ, + HEX_INS_V6_VSUBHSAT, + HEX_INS_V6_VSUBHSAT_DV, + HEX_INS_V6_VSUBHW, + HEX_INS_V6_VSUBUBH, + HEX_INS_V6_VSUBUBSAT, + HEX_INS_V6_VSUBUBSAT_DV, + HEX_INS_V6_VSUBUBUBB_SAT, + HEX_INS_V6_VSUBUHSAT, + HEX_INS_V6_VSUBUHSAT_DV, + HEX_INS_V6_VSUBUHW, + HEX_INS_V6_VSUBUWSAT, + HEX_INS_V6_VSUBUWSAT_DV, + HEX_INS_V6_VSUBW, + HEX_INS_V6_VSUBW_DV, + HEX_INS_V6_VSUBWNQ, + HEX_INS_V6_VSUBWQ, + HEX_INS_V6_VSUBWSAT, + HEX_INS_V6_VSUBWSAT_DV, + HEX_INS_V6_VSWAP, + HEX_INS_V6_VTMPYB, + HEX_INS_V6_VTMPYB_ACC, + HEX_INS_V6_VTMPYBUS, + HEX_INS_V6_VTMPYBUS_ACC, + HEX_INS_V6_VTMPYHB, + HEX_INS_V6_VTMPYHB_ACC, + HEX_INS_V6_VUNPACKB, + HEX_INS_V6_VUNPACKH, + HEX_INS_V6_VUNPACKOB, + HEX_INS_V6_VUNPACKOH, + HEX_INS_V6_VUNPACKUB, + HEX_INS_V6_VUNPACKUH, + HEX_INS_V6_VWHIST128, + HEX_INS_V6_VWHIST128M, + HEX_INS_V6_VWHIST128Q, + HEX_INS_V6_VWHIST128QM, + HEX_INS_V6_VWHIST256, + HEX_INS_V6_VWHIST256_SAT, + HEX_INS_V6_VWHIST256Q, + HEX_INS_V6_VWHIST256Q_SAT, + HEX_INS_V6_VXOR, + HEX_INS_V6_VZB, + HEX_INS_V6_VZH, + HEX_INS_V6_ZLD_AI, + HEX_INS_V6_ZLD_PI, + HEX_INS_V6_ZLD_PPU, + HEX_INS_V6_ZLD_PRED_AI, + HEX_INS_V6_ZLD_PRED_PI, + HEX_INS_V6_ZLD_PRED_PPU, + HEX_INS_V6_ZEXTRACT, + HEX_INS_Y2_BARRIER, + HEX_INS_Y2_BREAK, + HEX_INS_Y2_DCCLEANA, + HEX_INS_Y2_DCCLEANINVA, + HEX_INS_Y2_DCFETCHBO, + HEX_INS_Y2_DCINVA, + HEX_INS_Y2_DCZEROA, + HEX_INS_Y2_ICINVA, + HEX_INS_Y2_ISYNC, + HEX_INS_Y2_SYNCHT, + HEX_INS_Y2_WAIT, + HEX_INS_Y4_L2FETCH, + HEX_INS_Y4_TRACE, + HEX_INS_Y5_L2FETCH, + HEX_INS_Y6_DIAG, + HEX_INS_Y6_DIAG0, + HEX_INS_Y6_DIAG1, + HEX_INS_Y6_DMLINK, + HEX_INS_Y6_DMPAUSE, + HEX_INS_Y6_DMPOLL, + HEX_INS_Y6_DMRESUME, + HEX_INS_Y6_DMSTART, + HEX_INS_Y6_DMWAIT, + HEX_INS_DEP_A2_ADDSAT, + HEX_INS_DEP_A2_SUBSAT, + HEX_INS_DEP_S2_PACKHL, + HEX_INS_INVALID_DECODE, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ADDSP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ADDSP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ADDSP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_TFR, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_TFR, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_TFR, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_TFR, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI1_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI1_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREWI1, +}; + +#endif \ No newline at end of file diff --git a/rizin/librz/asm/p/asm_hexagon.c b/rizin/librz/asm/p/asm_hexagon.c new file mode 100644 index 00000000..125665b7 --- /dev/null +++ b/rizin/librz/asm/p/asm_hexagon.c @@ -0,0 +1,40 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + +#include +#include +#include +#include +#include "hexagon.h" +#include "hexagon_insn.h" + +static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int l) { + HexInsn hi = { 0 }; + ut32 data = rz_read_le32(buf); + op->size = hexagon_disasm_instruction(data, &hi, (ut32)a->pc); + rz_strbuf_set(&op->buf_asm, hi.mnem); + return op->size; +} + +RzAsmPlugin rz_asm_plugin_hexagon = { + .name = "hexagon", + .arch = "hexagon", + .author = "xvilka", + .license = "LGPL3", + .bits = 32, + .desc = "Qualcomm Hexagon (QDSP6) V6", + .disassemble = &disassemble, +}; + +#ifndef RZ_PLUGIN_INCORE +RZ_API RzLibStruct rizin_plugin = { + .type = RZ_LIB_TYPE_ASM, + .data = &rz_asm_plugin_hexagon +}; +#endif diff --git a/rizin/test/db/analysis/hexagon b/rizin/test/db/analysis/hexagon new file mode 100644 index 00000000..1239bb45 --- /dev/null +++ b/rizin/test/db/analysis/hexagon @@ -0,0 +1,19 @@ +NAME=hexagon jumps +FILE=bins/elf/analysis/hexagon-hello-loop +CMDS=< 0x00005128 jump 0x5128 +c 0x00005134 -> 0x00005138 jump 0x5138 +C 0x00005138 -> 0x000050e0 call sym.pHello +C 0x0000513c -> 0x000050f8 call sym.pWorld +c 0x00005140 -> 0x00005144 jump 0x5144 +c 0x00005150 -> 0x00005128 jump 0x5128 +call sym.pHello +call sym.pWorld +EOF +RUN diff --git a/rizin/test/db/asm/hexagon b/rizin/test/db/asm/hexagon new file mode 100644 index 00000000..d0358908 --- /dev/null +++ b/rizin/test/db/asm/hexagon @@ -0,0 +1,32 @@ +d "/ immext(##0x0)" 00400000 0x0 +d "/ immext(##0x40)" 01400000 0x0 +d "/ immext(##0xffffffc0)" ff7fff0f 0x0 + +d "[ R0 = ##0x101" 20e00078 +d "[ R5 = add(clb(R31),#-0x1)" 05ff3f8c +d "[ R4 = add(R19,##0x33)" 64c613b0 + +d "[ nop" 00c0007f 0x10000000 +d "/ R31 = add(R0,##0x2)" 5f4000b0 + +d "[ P0 = tstbit(R6,#0); if (!P0.new) jump:t 0x14" 04e3c611 0xc +d "[ P0 = tstbit(R6,#0); if (!P0.new) jump:t 0x8" fce3f611 0x10 + +d "[ R7 = ##0x4 ; R0 = #-1" 003a4728 0x0 +d "[ R1:0 = memd(R29+#0x40) ; if (P0) dealloc_return" 441f403e +d "[ R7:6 = memd(R29+#0x40) ; if (!P0) dealloc_return" 451f433e +d "[ R23:22 = combine(#0,#0x2) ; R17:16 = memd(R29+#0x40)" 443e475c +d "[ if (!P0.new) R23 = #0 ; jumpr R31" c03f5f5a + +d "[ G9:8 = R9:8" 08c00863 +d "[ GELR = R31" 00c01f62 + +d "/ R11:10 = memb_fifo(R12++M0:brev)" 0a408c9e +d "[ R15:14 = memb_fifo(R7=##0x3)" 6ed0879a +dB "[ C21:20 = R19:18" 14c03263 +d "[ C17:16 = R19:18" 10c03263 +d "[ C19:18 = R31:30" 12c03e63 + +dB "HVX MISSING" 4160d719 + +d "[ loop0(0x6c,#0x10)" 88c00069 0x68 diff --git a/setup.py b/setup.py new file mode 100644 index 00000000..185f7c08 --- /dev/null +++ b/setup.py @@ -0,0 +1,7 @@ +# SPDX-FileCopyrightText: 2021 Rot127 +# +# SPDX-License-Identifier: LGPL-3.0-only + +from setuptools import setup, find_packages + +setup(name="rz-hexagon", version="1.0", packages=find_packages()) diff --git a/test-bins/main.o b/test-bins/main.o new file mode 100644 index 00000000..3a16f0f8 Binary files /dev/null and b/test-bins/main.o differ