From 496dbf46a16d0d3f71de830aba0abda12e8757f4 Mon Sep 17 00:00:00 2001
From: Robbin Ehn <rehn@rivosinc.com>
Date: Tue, 14 Jan 2025 05:34:44 +0100
Subject: [PATCH] Middle of work 7 tested

---
 src/hotspot/cpu/riscv/assembler_riscv.hpp | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp
index 07712d7e6040e..46160ca7d9f32 100644
--- a/src/hotspot/cpu/riscv/assembler_riscv.hpp
+++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp
@@ -1169,27 +1169,27 @@ enum operand_size { int8, int16, int32, uint32, int64 };
   }
 
   void fclass_s(Register Rd, FloatRegister Rs1) {
-    fp_base(Rd, Rs1, 0b00000, 0b001, 0b00, 0b11110);
+    fp_base(Rd, Rs1, 0b00000, 0b001, 0b00, 0b11100);
   }
 
   void fclass_d(Register Rd, FloatRegister Rs1) {
-    fp_base(Rd, Rs1, 0b00000, 0b001, 0b01, 0b11110);
+    fp_base(Rd, Rs1, 0b00000, 0b001, 0b01, 0b11100);
   }
 
   void fmv_x_w(Register Rd, FloatRegister Rs1) {
-    fp_base(Rd, Rs1, 0b00000, 0b000, 0b00, 0b11110);
+    fp_base(Rd, Rs1, 0b00000, 0b000, 0b00, 0b11100);
   }
 
   void fmv_x_d(Register Rd, FloatRegister Rs1) {
-    fp_base(Rd, Rs1, 0b00000, 0b000, 0b01, 0b11110);
+    fp_base(Rd, Rs1, 0b00000, 0b000, 0b01, 0b11100);
   }
 
   void fclass_h(Register Rd, FloatRegister Rs1) {
-    fp_base(Rd, Rs1, 0b00000, 0b001, 0b10, 0b11110);
+    fp_base(Rd, Rs1, 0b00000, 0b001, 0b10, 0b11100);
   }
 
   void fmv_x_h(Register Rd, FloatRegister Rs1) {
-    fp_base(Rd, Rs1, 0b00000, 0b000, 0b10, 0b11110);
+    fp_base(Rd, Rs1, 0b00000, 0b000, 0b10, 0b11100);
   }
 
  private: