diff --git a/test/hotspot/gtest/riscv/test_assembler_riscv.cpp b/test/hotspot/gtest/riscv/test_assembler_riscv.cpp
new file mode 100644
index 0000000000000..7709898b0ae97
--- /dev/null
+++ b/test/hotspot/gtest/riscv/test_assembler_riscv.cpp
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2020, Red Hat Inc. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ */
+
+#include "precompiled.hpp"
+
+#if (defined(RISCV) || defined(RISCV64)) && !defined(ZERO)
+
+#include "asm/assembler.inline.hpp"
+#include "asm/macroAssembler.hpp"
+#include "memory/resourceArea.hpp"
+#include "unittest.hpp"
+
+typedef uint64_t (*zicond_eq)(int64_t cmp1, int64_t cmp2, int64_t dst, int64_t src);
+
+class CmovTester {
+ public:
+  template <typename FUNC>
+  static void test(FUNC &f) {
+    BufferBlob* bb = BufferBlob::create("riscvTest", 500000);
+    CodeBuffer code(bb);
+    MacroAssembler _masm(&code);
+    f(_masm);
+    BufferBlob::free(bb);
+  }
+};
+  
+static void cmov_eq_true(MacroAssembler& _masm) {
+  #define __ _masm.
+  address entry = __ pc();
+  __ cmov_eq(c_rarg0, c_rarg1, c_rarg2, c_rarg3);
+  __ mv(c_rarg0, c_rarg2);
+  __ ret();
+  #undef __
+  uint64_t ret = ((zicond_eq)entry)(88, 88, 66, 77);
+  ASSERT_EQ(ret, 77ul);
+}
+
+static void cmov_eq_false(MacroAssembler& _masm) {
+  #define __ _masm.
+  address entry = __ pc();
+  __ cmov_eq(c_rarg0, c_rarg1, c_rarg2, c_rarg3);
+  __ mv(c_rarg0, c_rarg2);
+  __ ret();
+  #undef __
+  uint64_t ret = ((zicond_eq)entry)(88, 87, 66, 77);
+  ASSERT_EQ(ret, 66ul);
+}
+
+TEST_VM(Instruction, Cmov) {
+  CmovTester::test(cmov_eq_true);
+  CmovTester::test(cmov_eq_false);
+}
+#endif  // RISCV