From 9474b77aaf47cfb1c8ef0dc2228bad5fdcc25373 Mon Sep 17 00:00:00 2001
From: Robbin Ehn <rehn@rivosinc.com>
Date: Wed, 15 Nov 2023 11:20:55 +0000
Subject: [PATCH] tier1

---
 src/hotspot/cpu/riscv/macroAssembler_riscv.cpp | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
index 7cf074f1648aa..57ca35229024e 100644
--- a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
+++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
@@ -4387,7 +4387,6 @@ void MacroAssembler::shadd(Register Rd, Register Rs1, Register Rs2, Register tmp
 void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
   // TODO refactor masm + asm
   // This code is not nice, we can do much better if refactored.
-  assert(bits == 8 || bits == 16 || bits == 32, "must be");
   if (bits == 32) {
     if (UseZba) {
       zext_w(dst, src);
@@ -4435,7 +4434,6 @@ void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
 void MacroAssembler::sign_extend(Register dst, Register src, int bits) {
   // TODO refactor masm + asm
   // This code is not nice, we can do much better if refactored.
-  assert(bits == 8 || bits == 16 || bits == 32, "must be");
   if (bits == 32) {
     sext_w(dst, src);
     return;