From eefcd2698957878a5baf38660ab5ccb38ae8641f Mon Sep 17 00:00:00 2001
From: Robbin Ehn <rehn@rivosinc.com>
Date: Fri, 22 Dec 2023 15:04:23 +0100
Subject: [PATCH] fixed lmul

---
 src/hotspot/cpu/riscv/stubGenerator_riscv.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp b/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
index 5f998ffa2bd1e..4c9696c6d69a8 100644
--- a/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
+++ b/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
@@ -3936,7 +3936,7 @@ class StubGenerator: public StubCodeGenerator {
       // ma: mask agnostic (don't care about those lanes)
       // x0 is not written, we known the number of vector elements.
 
-      if (vset_sew == Assembler::e32 && MaxVectorSize == 16) {
+      if (vset_sew == Assembler::e64 && MaxVectorSize == 16) {
         __ vsetivli(x0, 4, vset_sew, Assembler::m2, Assembler::ma, Assembler::ta);
       } else {
         __ vsetivli(x0, 4, vset_sew, Assembler::m1, Assembler::ma, Assembler::ta);