diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp
index e92b3b521d00a..c5af5edfa1133 100644
--- a/src/hotspot/cpu/riscv/assembler_riscv.hpp
+++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp
@@ -537,9 +537,9 @@ class Assembler : public AbstractAssembler {
   }
 
   INSN(lb,  0b0000011, 0b000);
-  INSN(_lbu, 0b0000011, 0b100); // Zcb
-  INSN(_lh,  0b0000011, 0b001); // Zcb
-  INSN(_lhu, 0b0000011, 0b101); // Zcb
+  INSN(_lbu, 0b0000011, 0b100);
+  INSN(_lh,  0b0000011, 0b001);
+  INSN(_lhu, 0b0000011, 0b101);
   INSN(_lw, 0b0000011, 0b010);
   INSN(lwu, 0b0000011, 0b110);
   INSN(_ld, 0b0000011, 0b011);
@@ -2959,7 +2959,7 @@ enum Nf {
     }
   }
 
-  // Format CU, c.[sz]ext.*, c.no
+  // Format CU, c.[sz]ext.*, c.not
   template <uint8_t InstructionType>
   void c_u_if(Register Rs1) {
     assert_cond(do_compress_zcb(Rs1));
@@ -3094,7 +3094,6 @@ enum Nf {
   // Prerequisites: Zcb, Zbb
   // Format CS
   void c_zext_h(Register Rs1) {
-    //assert(instruction_premitted<VM_Version::rv_ext_Zbb, VM_Version::rv_ext_Zcb>(Rs1), "invalid");
     c_u_if<0b010>(Rs1);
   }
 
diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
index 3e5be3886a428..38fa34324ad3a 100644
--- a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
+++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
@@ -493,8 +493,7 @@ class MacroAssembler: public Assembler {
   }
 
   inline void zext_b(Register Rd, Register Rs) {
-    if (do_compress_zcb(Rd, Rs) &&
-        (Rd == Rs)) {
+    if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
       c_zext_b(Rd);
     } else {
       andi(Rd, Rs, 0xFF);