config.json

{
    "DESIGN_NAME": "tt_um_clash_mac",
    "VERILOG_FILES": [
      "dir::src/Clash_TinyTapeout_EthernetMac_TopEntity_topEntity_trueDualPortBlockRamWrapper.v",
      "dir::src/Clash_TinyTapeout_EthernetMac_TopEntity_topEntity_resetSynchronizer.v",
      "dir::src/Clash_TinyTapeout_EthernetMac_TopEntity_topEntity_resetSynchronizer_0.v",
      "dir::src/Clash_TinyTapeout_EthernetMac_TopEntity_topEntity_asyncFIFOSynchronizer.v",
      "dir::src/topEntity.v",
      "dir::src/project.v"
    ],
    "FP_PDN_CHECK_NODES": false,
    "FP_PDN_VOFFSET": 66.32,
    "FP_PDN_CFG": "pdn_cfg.tcl",
    "MAGIC_LEF_WRITE_USE_GDS": true,
    "MAGIC_WRITE_LEF_PINONLY": true,

    "//": "don't use power rings or met5",
    "FP_PDN_MULTILAYER": false,
    "RT_MAX_LAYER": "met4",

    "ROUTING_CORES": 8,
    "PL_TARGET_DENSITY_PCT": 82,
    "SYNTH_STRATEGY": "AREA 1",
    "GRT_ALLOW_CONGESTION" : true,
    "PL_RESIZER_MAX_SLEW_MARGIN" : 20.0,
    "GLB_RESIZER_MAX_SLEW_MARGIN" : 20.0,
    "FP_MACRO_HORIZONTAL_HALO": 6,
    "FP_MACRO_VERTICAL_HALO": 6,

    "RUN_CTS": true,
    "CLOCK_PERIOD": 40,
    "CLOCK_PORT": ["ethRxClk", "ethTxClk"],
    "CLOCK_NET": ["ethRxClk", "ethTxClk"],
    "FALLBACK_SDC_FILE": "dir::src/project.sdc",
    "FP_SIZING": "absolute",

    "DIE_AREA": [0.0, 0.0, 508.76, 225.76],
    "FP_DEF_TEMPLATE": "dir::tt/def/tt_block_3x2_pg.def",
    "//": "reduce wasted space",
    "TOP_MARGIN_MULT": 1,
    "BOTTOM_MARGIN_MULT": 1,
    "LEFT_MARGIN_MULT": 6,
    "RIGHT_MARGIN_MULT": 6,
    "ERROR_ON_SYNTH_CHECKS": false
  }